diff options
| author | Marek Vasut | 2015-08-11 00:54:12 +0200 |
|---|---|---|
| committer | Marek Vasut | 2015-08-23 11:56:19 +0200 |
| commit | 7e4d2fa2ed2ddf80121372db0282315dc9850a1b (patch) | |
| tree | 1e30c098faa00668af88faafed150d8c1d1ce518 /arch/arm/mach-socfpga | |
| parent | a8535c306c68eb050ad0835845ea87a856b192f1 (diff) | |
arm: socfpga: Fix delay in clock manager
This code claims it needs to wait 7us, yet it uses get_timer() function
which operates with millisecond granularity. Use timer_get_us() instead,
which operates with microsecond granularity.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch/arm/mach-socfpga')
| -rw-r--r-- | arch/arm/mach-socfpga/clock_manager.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 1341df4361d..aa716366ea3 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -90,7 +90,7 @@ static void cm_write_with_phase(uint32_t value, void cm_basic_init(const struct cm_config * const cfg) { - uint32_t start, timeout; + unsigned long end; /* Start by being paranoid and gate all sw managed clocks */ @@ -159,12 +159,10 @@ void cm_basic_init(const struct cm_config * const cfg) writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); /* - * Time starts here - * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1) + * Time starts here. Must wait 7 us from + * BGPWRDN_SET(0) to VCO_ENABLE_SET(1). */ - start = get_timer(0); - /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */ - timeout = 7; + end = timer_get_us() + 7; /* main mpu */ writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); @@ -204,7 +202,7 @@ void cm_basic_init(const struct cm_config * const cfg) writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk); /* 7 us must have elapsed before we can enable the VCO */ - while (get_timer(start) < timeout) + while (timer_get_us() < end) ; /* Enable vco */ |