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authorMarek Vasut2019-11-20 22:36:24 +0100
committerMarek Vasut2019-11-25 13:12:56 +0100
commita1a9843a29672be49a5bbb3a07fea8dbc88369ba (patch)
tree623f8c55db030e78616a97ae9c136a8f3f8ddb9f /arch/arm
parent533832c6a47b5f7463f3b1d20337d2746f568b24 (diff)
ARM: socfpga: Unreset NAND in SPL on Gen5
In case the SPL on Gen5 loads U-Boot from NAND, unreset the NAND IP explicitly in the platform code as the denali-spl driver is not aware of DM at all. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-socfpga/spl_gen5.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 47e63709ad8..408e4093754 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -138,6 +138,13 @@ void board_init_f(ulong dummy)
if (ret)
debug("Reset init failed: %d\n", ret);
+#ifdef CONFIG_SPL_NAND_DENALI
+ struct socfpga_reset_manager *reset_manager_base =
+ (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
+
+ clrbits_le32(&reset_manager_base->per_mod_reset, BIT(4));
+#endif
+
/* enable console uart printing */
preloader_console_init();