diff options
| author | Marcus Comstedt | 2019-08-11 14:45:29 +0200 |
|---|---|---|
| committer | Andes | 2019-09-03 09:30:41 +0800 |
| commit | f6cb427fdc1d2c4236f0a9bc97068c30ca228282 (patch) | |
| tree | 09eb9cfd8d9c586a6b8143a1f7816676168413e5 /arch/riscv | |
| parent | 71bdfcb21d755435a8e99f0ff66b853a3759f4b7 (diff) | |
riscv: update fix_rela_dyn
The addend is now added for RELOC_TYPE relocs. Also, changed the loop
structure so that all the R_RISCV_RELATIVE relocs are not required to
be at the beginning of the list.
Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
Cc: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/start.S | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index b15209d6231..0a2ce6d6913 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -269,7 +269,7 @@ fix_rela_dyn: /* * skip first reserved entry: address, type, addend */ - bne t1, t2, 7f + j 10f 6: LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ @@ -280,9 +280,7 @@ fix_rela_dyn: add t5, t5, t6 /* t5 <-- location to fix up in RAM */ add t3, t3, t6 /* t3 <-- location to fix up in RAM */ SREG t5, 0(t3) -7: - addi t1, t1, (REGBYTES*3) - ble t1, t2, 6b + j 10f 8: la t4, __dyn_sym_start @@ -299,13 +297,15 @@ fix_rela_dyn: li t5, SYM_SIZE mul t0, t0, t5 add s5, t4, t0 + LREG t0, -(REGBYTES)(t1) /* t0 <-- addend */ LREG t5, REGBYTES(s5) + add t5, t5, t0 add t5, t5, t6 /* t5 <-- location to fix up in RAM */ add t3, t3, t6 /* t3 <-- location to fix up in RAM */ SREG t5, 0(t3) 10: addi t1, t1, (REGBYTES*3) - ble t1, t2, 9b + ble t1, t2, 6b /* * trap update |