diff options
| author | Rick Chen | 2019-04-30 13:49:35 +0800 |
|---|---|---|
| committer | Andes | 2019-05-09 16:46:46 +0800 |
| commit | f9281b8905d50d1f284df92f53534ffb8d2558a8 (patch) | |
| tree | 83505bfad6d301945a8e3e4d740fc0c8e3712a83 /arch/riscv | |
| parent | e7e47f6391d13bd7e6d5dd705c548d0260a88c55 (diff) | |
riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled
This patch will fix prior_stage_fdt_address write failure problem, when
AE350 boots from flash.
When AE350 boots from flash, prior_stage_fdt_address will be flash
address, we shall avoid it to be written.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/cpu.c | 2 | ||||
| -rw-r--r-- | arch/riscv/cpu/start.S | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 0cfd7d61a78..e9a8b437ed0 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -15,7 +15,9 @@ * The variables here must be stored in the data section since they are used * before the bss section is available. */ +#ifdef CONFIG_OF_PRIOR_STAGE phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); +#endif #ifndef CONFIG_XIP u32 hart_lottery __attribute__((section(".data"))) = 0; diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 3402d09a054..60ac8c621e4 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -111,8 +111,10 @@ call_board_init_f_0: bnez tp, secondary_hart_loop #endif +#ifdef CONFIG_OF_PRIOR_STAGE la t0, prior_stage_fdt_address SREG s1, 0(t0) +#endif jal board_init_f_init_reserve |