diff options
| author | Peng Fan | 2019-05-09 08:33:55 +0000 |
|---|---|---|
| committer | Stefano Babic | 2019-06-11 10:43:00 +0200 |
| commit | 16529ff255a37df29133ebffc62e59793cbf6d86 (patch) | |
| tree | 9fc2750a10cb7114c7d9c0b643870c19bafd9c5a /arch | |
| parent | 75eba1832103e85c7e79c7f71b4deaaadcd6bcef (diff) | |
imx: define ARCH_MXC for i.MX8/8M/7ULP
Without this definition, fsl_esdhc will access reserved registers
on i.MX chips, so define ARCH_MXC to fix it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-imx8/imx-regs.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-imx8m/imx-regs.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 2 |
3 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h index af0fb5154b6..6333ff4686f 100644 --- a/arch/arm/include/asm/arch-imx8/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8/imx-regs.h @@ -6,6 +6,8 @@ #ifndef __ASM_ARCH_IMX8_REGS_H__ #define __ASM_ARCH_IMX8_REGS_H__ +#define ARCH_MXC + #define LPUART_BASE 0x5A060000 #define GPT1_BASE_ADDR 0x5D140000 diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 3facd5450c0..68666a535b9 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -6,6 +6,8 @@ #ifndef __ASM_ARCH_IMX8M_REGS_H__ #define __ASM_ARCH_IMX8M_REGS_H__ +#define ARCH_MXC + #include <asm/mach-imx/regs-lcdif.h> #define ROM_VERSION_A0 0x800 diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index bf9f39aca23..63b02de0878 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -8,6 +8,8 @@ #include <linux/sizes.h> +#define ARCH_MXC + #define CAAM_SEC_SRAM_BASE (0x26000000) #define CAAM_SEC_SRAM_SIZE (SZ_32K) #define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1) |