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authorYanhong Wang2023-06-15 17:36:51 +0800
committerLeo Yu-Chi Liang2023-07-12 13:21:40 +0800
commit38d900b409199df02a1a26dfcb464d4d2b6e27d2 (patch)
treed808b9a2b1549c24b71d1683331e6803d47f169d /arch
parent99f3a43d1cbc9abe14839734bb35444c1633f836 (diff)
ram: starfive: Read memory size information from EEPROM
StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of DDR capacity includes 2G/4G/8G, a DT can not support multiple capacities, so the capacity size information is recorded to EEPROM, when DDR initialization required capacity size information is read from EEPROM. If there is no information in EEPROM, it is initialized with the default size defined in DT. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/riscv/cpu/jh7110/spl.c32
1 files changed, 31 insertions, 1 deletions
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 104f0fe9497..72adcefa0e9 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -3,19 +3,49 @@
* Copyright (C) 2022 StarFive Technology Co., Ltd.
* Author: Yanhong Wang<yanhong.wang@starfivetech.com>
*/
-
+#include <common.h>
+#include <asm/arch/eeprom.h>
#include <asm/csr.h>
#include <asm/sections.h>
#include <dm.h>
+#include <linux/sizes.h>
#include <log.h>
+#include <init.h>
#define CSR_U74_FEATURE_DISABLE 0x7c1
#define L2_LIM_MEM_END 0x81FFFFFUL
+DECLARE_GLOBAL_DATA_PTR;
+
+static bool check_ddr_size(phys_size_t size)
+{
+ switch (size) {
+ case SZ_2:
+ case SZ_4:
+ case SZ_8:
+ case SZ_16:
+ return true;
+ default:
+ return false;
+ }
+}
+
int spl_soc_init(void)
{
int ret;
struct udevice *dev;
+ phys_size_t size;
+
+ ret = fdtdec_setup_mem_size_base();
+ if (ret)
+ return ret;
+
+ /* Read the definition of the DDR size from eeprom, and if not,
+ * use the definition in DT
+ */
+ size = (get_ddr_size_from_eeprom() >> 16) & 0xFF;
+ if (check_ddr_size(size))
+ gd->ram_size = size << 30;
/* DDR init */
ret = uclass_get_device(UCLASS_RAM, 0, &dev);