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authorBin Meng2016-02-02 05:58:09 -0800
committerBin Meng2016-02-05 12:47:24 +0800
commit5c884420a5752163ce738701701ae1874d8f466d (patch)
tree272d9681f2206e68daffef295da7370e8b9b973c /arch
parentd8277a87d0993492b2c09dcd9ccf1ce652d03b9c (diff)
x86: Drop pci_type1.c and DEFINE_PCI_DEVICE_TABLE
Now that we have converted all x86 codes to DM PCI, drop pci_type1.c which is only built for legacy PCI. Also per checkpatch.pl warning, DEFINE_PCI_DEVICE_TABLE is now deprecated so drop that too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/include/asm/pci.h7
-rw-r--r--arch/x86/lib/Makefile3
-rw-r--r--arch/x86/lib/pci_type1.c50
3 files changed, 0 insertions, 60 deletions
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index 46b992ef448..f93c840244a 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -18,13 +18,6 @@
#ifndef __ASSEMBLY__
-#define DEFINE_PCI_DEVICE_TABLE(_table) \
- const struct pci_device_id _table[]
-
-struct pci_controller;
-
-void pci_setup_type1(struct pci_controller *hose);
-
int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
ulong *valuep, enum pci_size_t size);
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 50bc69a659f..4fc19365eb7 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -22,9 +22,6 @@ obj-y += cmd_mtrr.o
obj-y += northbridge-uclass.o
obj-$(CONFIG_I8259_PIC) += i8259.o
obj-$(CONFIG_I8254_TIMER) += i8254.o
-ifndef CONFIG_DM_PCI
-obj-$(CONFIG_PCI) += pci_type1.o
-endif
obj-y += pirq_routing.o
obj-y += relocate.o
obj-y += physmem.o
diff --git a/arch/x86/lib/pci_type1.c b/arch/x86/lib/pci_type1.c
deleted file mode 100644
index a251adcacd4..00000000000
--- a/arch/x86/lib/pci_type1.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Support for type PCI configuration cycles.
- * based on pci_indirect.c
- */
-#include <common.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <asm/pci.h>
-
-#define cfg_read(val, addr, op) (*val = op((int)(addr)))
-#define cfg_write(val, addr, op) op((val), (int)(addr))
-
-#define TYPE1_PCI_OP(rw, size, type, op, mask) \
-static int \
-type1_##rw##_config_##size(struct pci_controller *hose, \
- pci_dev_t dev, int offset, type val) \
-{ \
- outl(dev | (offset & 0xfc) | PCI_CFG_EN, (int)hose->cfg_addr); \
- cfg_##rw(val, hose->cfg_data + (offset & mask), op); \
- return 0; \
-}
-
-TYPE1_PCI_OP(read, byte, u8 *, inb, 3)
-TYPE1_PCI_OP(read, word, u16 *, inw, 2)
-TYPE1_PCI_OP(read, dword, u32 *, inl, 0)
-
-TYPE1_PCI_OP(write, byte, u8, outb, 3)
-TYPE1_PCI_OP(write, word, u16, outw, 2)
-TYPE1_PCI_OP(write, dword, u32, outl, 0)
-
-void pci_setup_type1(struct pci_controller *hose)
-{
- pci_set_ops(hose,
- type1_read_config_byte,
- type1_read_config_word,
- type1_read_config_dword,
- type1_write_config_byte,
- type1_write_config_word,
- type1_write_config_dword);
-
- hose->cfg_addr = (unsigned int *)PCI_REG_ADDR;
- hose->cfg_data = (unsigned char *)PCI_REG_DATA;
-}