diff options
| author | Michael Walle | 2021-10-13 18:14:07 +0200 |
|---|---|---|
| committer | Priyanka Jain | 2021-11-09 17:18:23 +0530 |
| commit | fbddc2701d2e0faea8193c7bfc1d2c810f0f73a6 (patch) | |
| tree | 9628b98ea8ea9ff637b3f5a7e554ba9da852e856 /arch | |
| parent | f02f2f93a543d96c09bf5ce159c90f608202218b (diff) | |
arm: dts: ls1028a: move the SPI and eSDHC controller nodes into /soc
While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/fsl-ls1028a.dtsi | 116 |
1 files changed, 58 insertions, 58 deletions
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 6d80b328168..ecafa67d087 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -266,64 +266,6 @@ status = "disabled"; }; - dspi0: dspi@2100000 { - compatible = "fsl,vf610-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dspi"; - clocks = <&clockgen 4 0>; - num-cs = <5>; - litte-endian; - status = "disabled"; - }; - - dspi1: dspi@2110000 { - compatible = "fsl,vf610-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2110000 0x0 0x10000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dspi"; - clocks = <&clockgen 4 0>; - num-cs = <5>; - little-endian; - status = "disabled"; - }; - - dspi2: dspi@2120000 { - compatible = "fsl,vf610-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2120000 0x0 0x10000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dspi"; - clocks = <&clockgen 4 0>; - num-cs = <5>; - little-endian; - status = "disabled"; - }; - - esdhc0: esdhc@2140000 { - compatible = "fsl,esdhc"; - reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - big-endian; - bus-width = <4>; - status = "disabled"; - }; - - esdhc1: esdhc@2150000 { - compatible = "fsl,esdhc"; - reg = <0x0 0x2150000 0x0 0x10000>; - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - big-endian; - non-removable; - bus-width = <4>; - status = "disabled"; - }; - gpio0: gpio@2300000 { compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; reg = <0x0 0x2300000 0x0 0x10000>; @@ -484,5 +426,63 @@ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + litte-endian; + status = "disabled"; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + little-endian; + status = "disabled"; + }; + + dspi2: dspi@2120000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2120000 0x0 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + little-endian; + status = "disabled"; + }; + + esdhc0: esdhc@2140000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + big-endian; + bus-width = <4>; + status = "disabled"; + }; + + esdhc1: esdhc@2150000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2150000 0x0 0x10000>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + big-endian; + non-removable; + bus-width = <4>; + status = "disabled"; + }; }; }; |