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authorTony Dinh2021-07-29 20:02:43 -0700
committerStefan Roese2021-08-11 08:42:26 +0200
commit293a8de6fa0fdc70f6de6d7fb8d70d46e342e42c (patch)
tree8dd00729e7ddca06639148f84610801e75f7ff82 /board/Seagate
parent296c32b243888af0846afd829bdcdf8157763b4e (diff)
arm: kirkwood: GoFlex Home: Use Ethernet PHY name and address from device tree
In DM Ethernet, the old "egiga0" name is no longer valid, so replace these with Ethernet PHY names from device tree. Also, read Ethernet PHY address from device tree. Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/Seagate')
-rw-r--r--board/Seagate/goflexhome/goflexhome.c57
1 files changed, 45 insertions, 12 deletions
diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c
index af8cab7bdc7..52be64fb8c2 100644
--- a/board/Seagate/goflexhome/goflexhome.c
+++ b/board/Seagate/goflexhome/goflexhome.c
@@ -1,5 +1,9 @@
// SPDX-License-Identifier: GPL-2.0+
/*
+ * Copyright (C) 2021
+ * Tony Dinh <mibodhi@gmail.com>
+ * Suriyan Ramasami <suriyan.r@gmail.com>
+ *
* Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
*
* Based on dockstar.c originally written by
@@ -107,36 +111,65 @@ int board_init(void)
return 0;
}
+static int fdt_get_phy_addr(const char *path)
+{
+ const void *fdt = gd->fdt_blob;
+ const u32 *reg;
+ const u32 *val;
+ int node, phandle, addr;
+
+ /* Find the node by its full path */
+ node = fdt_path_offset(fdt, path);
+ if (node >= 0) {
+ /* Look up phy-handle */
+ val = fdt_getprop(fdt, node, "phy-handle", NULL);
+ if (val) {
+ phandle = fdt32_to_cpu(*val);
+ if (!phandle)
+ return -1;
+ /* Follow it to its node */
+ node = fdt_node_offset_by_phandle(fdt, phandle);
+ if (node) {
+ /* Look up reg */
+ reg = fdt_getprop(fdt, node, "reg", NULL);
+ if (reg) {
+ addr = fdt32_to_cpu(*reg);
+ return addr;
+ }
+ }
+ }
+ }
+ return -1;
+}
+
#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
{
u16 reg;
- u16 devadr;
- char *name = "egiga0";
+ int phyaddr;
+ char *name = "ethernet-controller@72000";
+ char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
if (miiphy_set_current_dev(name))
return;
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
- printf("Err..%s could not read PHY dev address\n",
- __func__);
+ phyaddr = fdt_get_phy_addr(eth0_path);
+ if (phyaddr < 0)
return;
- }
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+ miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+ miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
/* reset the phy */
- miiphy_reset(name, devadr);
+ miiphy_reset(name, phyaddr);
printf("88E1116 Initialized on %s\n", name);
}