board: ns2: Add support for Broadcom Northstar 2

Add support for the Broadcom Northstar2 SoC and SVK (bcm958712k).  The
BCM5871X is a series of quad-core 64-bit 2GHz ARMv8 Cortex-A57
processors targeting a broad range of networking applications.

Signed-off-by: Jon Mason <jon.mason@broadcom.com>

4 files changed, 86 insertions, 0 deletions

diff --git a/board/broadcom/bcm958712k/MAINTAINERS b/board/broadcom/bcm958712k/MAINTAINERS
new file mode 100644
index 00000000000..024fb1447d2
--- /dev/null
+++ b/board/broadcom/bcm958712k/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM958712K BOARD
+M:	Jon Mason <jon.mason@broadcom.com>
+S:	Maintained
+F:	board/broadcom/bcmns2/
+F:	include/configs/bcm_northstar2.h
+F:	configs/bcm958712k_defconfig
diff --git a/board/broadcom/bcmns2/Kconfig b/board/broadcom/bcmns2/Kconfig
new file mode 100644
index 00000000000..3ac67249c4d
--- /dev/null
+++ b/board/broadcom/bcmns2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BCMNS2
+
+config SYS_BOARD
+	default "bcmns2"
+
+config SYS_VENDOR
+	default "broadcom"
+
+config SYS_SOC
+	default "ns2"
+
+config SYS_CONFIG_NAME
+	default "bcm_northstar2"
+
+endif
diff --git a/board/broadcom/bcmns2/Makefile b/board/broadcom/bcmns2/Makefile
new file mode 100644
index 00000000000..f6ddd800b17
--- /dev/null
+++ b/board/broadcom/bcmns2/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Broadcom Ltd.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= northstar2.o
diff --git a/board/broadcom/bcmns2/northstar2.c b/board/broadcom/bcmns2/northstar2.c
new file mode 100644
index 00000000000..a64431d35e5
--- /dev/null
+++ b/board/broadcom/bcmns2/northstar2.c
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2016 Broadcom Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region ns2_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0xff80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = ns2_mem_map;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+				    PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
+void reset_cpu(ulong addr)
+{
+	psci_system_reset();
+}