* Patch by André Schwarz, 8 Dec 2003:

  fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM):
  - TX and RX deskriptors must be quad-word aligned
  - does not work with only one TX deskriptor
  - standard reset method does not work

* Patch by Masami Komiya, 08 Dec 2003:
  add RTL8139 ethernet driver

* Patches by Ed Okerson, 07 Dec 2003:
  - fix ethernet for the AU1x00 processors in little-endian mode.
  - extend memsetup.S for the AU1x00 processors in BE and LE modes

1 files changed, 315 insertions, 71 deletions

diff --git a/board/dbau1x00/memsetup.S b/board/dbau1x00/memsetup.S
index 6c61e6fac35..d2a17a01b07 100644
--- a/board/dbau1x00/memsetup.S
+++ b/board/dbau1x00/memsetup.S
@@ -4,114 +4,358 @@
 #include <version.h>
 #include <asm/regdef.h>
 #include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+#define AU1500_SYS_ADDR		0xB1900000
+#define sys_endian		0x0038
+#define CP0_Config0		$16
+#define MEM_1MS			((396000000/1000000) * 1000)
+
+	.text
+	.set noreorder
+	.set mips32
 
 	.globl	memsetup
 memsetup:
+	/*
+	 * Step 1) Establish CPU endian mode.
+	 * Db1500-specific:
+	 * Switch S1.1 Off(bit7 reads 1) is Little Endian
+	 * Switch S1.1 On (bit7 reads 0) is Big Endian
+	 */
+	li	t0, MEM_STCFG1
+	li	t1, 0x00000080
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME1
+	li	t1, 0x22080a20
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR1
+	li	t1, 0x10c03f00
+	sw	t1, 0(t0)
+
+	li	t0, 0xAE000008
+	lw	t1,0(t0)
+	andi	t1,t1,0x80
+	beq	zero,t1,big_endian
+	nop
+little_endian:
+
+	/* Change Au1 core to little endian */
+	li	t0, AU1500_SYS_ADDR
+	li	t1, 1
+	sw	t1, sys_endian(t0)
+	mfc0	t2, CP0_CONFIG
+	mtc0	t2, CP0_CONFIG
+	nop
+	nop
+
+	/* Big Endian is default so nothing to do but fall through */
+
+big_endian:
+
+	/*
+	 * Step 2) Establish Status Register
+	 * (set BEV, clear ERL, clear EXL, clear IE)
+	 */
+	li	t1, 0x00400000
+	mtc0	t1, CP0_STATUS
+
+	/*
+	 * Step 3) Establish CP0 Config0
+	 * (set OD, set K0=3)
+	 */
+	li	t1, 0x00080003
+	mtc0	t1, CP0_CONFIG
+
+	/*
+	 * Step 4) Disable Watchpoint facilities
+	 */
+	li t1, 0x00000000
+	mtc0	t1, CP0_WATCHLO
+	mtc0	t1, CP0_IWATCHLO
+	/*
+	 * Step 5) Disable the performance counters
+	 */
+	mtc0	zero, CP0_PERFORMANCE
+	nop
+
+	/*
+	 * Step 6) Establish EJTAG Debug register
+	 */
+	mtc0	zero, CP0_DEBUG
+	nop
+
+	/*
+	 * Step 7) Establish Cause
+	 * (set IV bit)
+	 */
+	li	t1, 0x00800000
+	mtc0	t1, CP0_CAUSE
+
+	/* Establish Wired (and Random) */
+	mtc0	zero, CP0_WIRED
+	nop
+
 	/* First setup pll:s to make serial work ok */
 	/* We have a 12 MHz crystal */
-	li              t0, SYS_CPUPLL
-	li              t1, 0x21 /* 396 MHz */
-	sw              t1, 0(t0)
+	li	t0, SYS_CPUPLL
+	li	t1, 0x21  /* 396 MHz */
+	sw	t1, 0(t0)
 	sync
 	nop
+	nop
 
+	/* wait 1mS for clocks to settle */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
 	/* Setup AUX PLL */
-	li              t0, SYS_AUXPLL
-	li              t1, 8 /* 96 MHz */
-	sw              t1, 0(t0) /* aux pll */
+	li	t0, SYS_AUXPLL
+	li	t1, 0x20 /* 96 MHz */
+	sw	t1, 0(t0) /* aux pll */
 	sync
 
-/* SDCS 0,1 SDRAM */
-	li		t0, MEM_SDMODE0
-	li		t1, 0x005522AA
-	sw		t1, 0(t0)
+	/*  Static memory controller */
 
-	li              t0, MEM_SDMODE1
-	li		t1, 0x005522AA
-	sw		t1, 0(t0)
+	/* RCE0 AMD 29LV640M MirrorBit Flash */
+	li	t0, MEM_STCFG0
+	li	t1, 0x00000013
+	sw	t1, 0(t0)
 
-	li              t0, MEM_SDADDR0
-	li		t1, 0x001003F8
-	sw		t1, 0(t0)
+	li	t0, MEM_STTIME0
+	li	t1, 0x040181D7
+	sw	t1, 0(t0)
 
+	li	t0, MEM_STADDR0
+	li	t1, 0x11E03F80
+	sw	t1, 0(t0)
 
-	li              t0, MEM_SDADDR1
-	li		t1, 0x001023F8
-	sw		t1, 0(t0)
-	sync
+	/* RCE1 CPLD Board Logic */
+	li	t0, MEM_STCFG1
+	li	t1, 0x00000080
+	sw	t1, 0(t0)
 
-	li              t0, MEM_SDREFCFG
-	li		t1, 0x64000C24 /* Disable */
-	sw		t1, 0(t0)
-	sync
+	li	t0, MEM_STTIME1
+	li	t1, 0x22080a20
+	sw	t1, 0(t0)
 
-	li              t0, MEM_SDPRECMD
-	sw		zero, 0(t0)
-	sync
+	li	t0, MEM_STADDR1
+	li	t1, 0x10c03f00
+	sw	t1, 0(t0)
+
+	/* RCE2 CPLD Board Logic */
+	li	t0, MEM_STCFG2
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME2
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR2
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	/* RCE3 PCMCIA 250ns */
+	li	t0, MEM_STCFG3
+	li	t1, 0x00000002
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME3
+	li	t1, 0x280E3E07
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR3
+	li	t1, 0x10000000
+	sw	t1, 0(t0)
 
-	li              t0, MEM_SDAUTOREF
-	sw		zero, 0(t0)
-	sync
-	sw		zero, 0(t0)
 	sync
 
-	li              t0, MEM_SDREFCFG
-	li		t1, 0x66000C24 /* Enable */
-	sw		t1, 0(t0)
+	/* Set peripherals to a known state */
+	li	t0, IC0_CFG0CLR
+	li	t1, 0xFFFFFFFF
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG0CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG1CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG2CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_SRCSET
+	sw	t1, 0(t0)
+
+	li	t0, IC0_ASSIGNSET
+	sw	t1, 0(t0)
+
+	li	t0, IC0_WAKECLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_RISINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_FALLINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_TESTBIT
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
 	sync
 
-	li              t0, MEM_SDWRMD0
-	li		t1, 0x00000033
-	sw		t1, 0(t0)
+	li	t0, IC1_CFG0CLR
+	li	t1, 0xFFFFFFFF
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG0CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG1CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG2CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_SRCSET
+	sw	t1, 0(t0)
+
+	li	t0, IC1_ASSIGNSET
+	sw	t1, 0(t0)
+
+	li	t0, IC1_WAKECLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_RISINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_FALLINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_TESTBIT
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
 	sync
 
-	li              t0, MEM_SDWRMD1
-	li		t1, 0x00000033
-	sw		t1, 0(t0)
+	li	t0, SYS_FREQCTRL0
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_FREQCTRL1
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_CLKSRC
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_PININPUTEN
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
 	sync
 
-	/*  Static memory controller */
+	li	t0, 0xB1100100
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
 
-	/* RCE0 AMD 29LV640M MirrorBit Flash */
-	li              t0, MEM_STCFG0
-	li		t1, 0x00000003
-	sw		t1, 0(t0)
+	li	t0, 0xB1400100
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
 
-	li		t0, MEM_STTIME0
-	li		t1, 0x22080b20
-	sw		t1, 0(t0)
 
-	li		t0, MEM_STADDR0
-	li		t1, 0x11E03F80
-	sw		t1, 0(t0)
+	li	t0, SYS_WAKEMSK
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
 
-	/* RCE1 CPLD Board Logic */
-	li		t0, MEM_STCFG1
-	li		t1, 0x00000080
-	sw		t1, 0(t0)
+	li	t0, SYS_WAKESRC
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
 
-	li		t0, MEM_STTIME1
-	li		t1, 0x22080a20
-	sw		t1, 0(t0)
+	/* wait 1mS before setup */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
 
-	li		t0, MEM_STADDR1
-	li		t1, 0x10c03f00
-	sw		t1, 0(t0)
+/* SDCS 0,1 SDRAM */
+	li	t0, MEM_SDMODE0
+	li	t1, 0x005522AA
+	sw	t1, 0(t0)
 
-	/* RCE3 PCMCIA 250ns */
-	li		t0, MEM_STCFG3
-	li		t1, 0x00000002
-	sw		t1, 0(t0)
+	li	t0, MEM_SDMODE1
+	li	t1, 0x005522AA
+	sw	t1, 0(t0)
 
+	li	t0, MEM_SDMODE2
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR0
+	li	t1, 0x001003F8
+	sw	t1, 0(t0)
+
+
+	li	t0, MEM_SDADDR1
+	li	t1, 0x001023F8
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR2
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	sync
+
+	li	t0, MEM_SDREFCFG
+	li	t1, 0x64000C24 /* Disable */
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDPRECMD
+	sw	zero, 0(t0)
+	sync
+
+	li	t0, MEM_SDAUTOREF
+	sw	zero, 0(t0)
+	sync
+	sw	zero, 0(t0)
+	sync
+
+	li	t0, MEM_SDREFCFG
+	li	t1, 0x66000C24 /* Enable */
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD0
+	li	t1, 0x00000033
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD1
+	li	t1, 0x00000033
+	sw	t1, 0(t0)
+	sync
+
+	/* wait 1mS after setup */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
 
-	li		t0, MEM_STTIME3
-	li		t1, 0x280E3E07
-	sw		t1, 0(t0)
+	li	t0, SYS_PINFUNC
+	li	t1, 0x00008080
+	sw	t1, 0(t0)
 
-	li		t0, MEM_STADDR3
-	li		t1, 0x10000000
-	sw		t1, 0(t0)
+	li	t0, SYS_TRIOUTCLR
+	li	t1, 0x00001FFF
+	sw	t1, 0(t0)
 
+	li	t0, SYS_OUTPUTCLR
+	li	t1, 0x00008000
+	sw	t1, 0(t0)
 	sync
 
 	j	ra