diff options
| author | Adam Ford | 2017-08-08 09:00:27 -0500 |
|---|---|---|
| committer | Tom Rini | 2017-08-11 11:34:10 -0400 |
| commit | f07515578be131a71773f836b761cf135527c2dc (patch) | |
| tree | af00ce4243b7ec4ca6bd024573a0769f999d755d /board/logicpd | |
| parent | 40c8d26a4dd94db490eeaeb2d028591e6fe40465 (diff) | |
OMAP3: omap3logic: Fix DDR Pin Mux
The 512 MB DDR version of SOM's use CS0 and CS1. CS1 is not correctly
setup in the pin muxing. This causes erratic behavior on suspend/resume
This fix has been tested on both 256 and 512 MB DDR versions.
Signed-off-by: Adam Ford <aford173@gmail.com>
Diffstat (limited to 'board/logicpd')
| -rw-r--r-- | board/logicpd/omap3som/omap3logic.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 7990dd25130..f8b9f687fb1 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -320,7 +320,7 @@ void set_muxconf_regs(void) MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)); /*SDRC_CKE1*/ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ |