OMAP3: mvblx: Initial support for mvBlueLYNX-X

Add support for the MATRIX VISION mvBlueLYNX-X, an OMAP3-based
intelligent camera.

Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

7 files changed, 1263 insertions, 0 deletions

diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile
new file mode 100644
index 00000000000..01cb5171569
--- /dev/null
+++ b/board/matrix_vision/mvblx/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += mvblx.o fpga.o
+COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o
+COBJS	:= $(COBJS-y)
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+CFLAGS += -Werror
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/matrix_vision/mvblx/config.mk b/board/matrix_vision/mvblx/config.mk
new file mode 100644
index 00000000000..cf055db623b
--- /dev/null
+++ b/board/matrix_vision/mvblx/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/matrix_vision/mvblx/fpga.c b/board/matrix_vision/mvblx/fpga.c
new file mode 100644
index 00000000000..dacc13845dc
--- /dev/null
+++ b/board/matrix_vision/mvblx/fpga.c
@@ -0,0 +1,219 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2011
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ * Michael Jones, Matrix Vision GmbH, michael.jones@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include <asm/gpio.h>
+#include "fpga.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...)      printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+	fpga_null_fn,   /* Altera_pre_fn */
+	fpga_config_fn,
+	fpga_status_fn,
+	fpga_done_fn,
+	fpga_wr_fn,
+	fpga_null_fn,
+	fpga_null_fn,
+};
+
+Altera_desc cyclone2 = {
+	Altera_CYC2,
+	fast_passive_parallel,
+	Altera_EP3C5_SIZE,
+	(void *) &altera_fns,
+	NULL,
+	0
+};
+
+#define GPIO_RESET		43
+#define GPIO_DCLK		65
+#define GPIO_nSTATUS	157
+#define GPIO_CONF_DONE	158
+#define GPIO_nCONFIG	159
+#define GPIO_DATA0		54
+#define GPIO_DATA1		55
+#define GPIO_DATA2		56
+#define GPIO_DATA3		57
+#define GPIO_DATA4		58
+#define GPIO_DATA5		60
+#define GPIO_DATA6		61
+#define GPIO_DATA7		62
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* return FPGA_SUCCESS on success, else FPGA_FAIL
+ */
+int mvblx_init_fpga(void)
+{
+	fpga_debug("Initializing FPGA interface\n");
+	fpga_init();
+	fpga_add(fpga_altera, &cyclone2);
+
+	if (gpio_request(GPIO_DCLK, "dclk") ||
+			gpio_request(GPIO_nSTATUS, "nStatus") ||
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+			gpio_request(GPIO_CONF_DONE, "conf_done") ||
+#endif
+			gpio_request(GPIO_nCONFIG, "nConfig") ||
+			gpio_request(GPIO_DATA0, "data0") ||
+			gpio_request(GPIO_DATA1, "data1") ||
+			gpio_request(GPIO_DATA2, "data2") ||
+			gpio_request(GPIO_DATA3, "data3") ||
+			gpio_request(GPIO_DATA4, "data4") ||
+			gpio_request(GPIO_DATA5, "data5") ||
+			gpio_request(GPIO_DATA6, "data6") ||
+			gpio_request(GPIO_DATA7, "data7")) {
+		printf("%s: error requesting GPIOs.", __func__);
+		return FPGA_FAIL;
+	}
+
+	/* set up outputs */
+	gpio_direction_output(GPIO_DCLK,  0);
+	gpio_direction_output(GPIO_nCONFIG, 0);
+	gpio_direction_output(GPIO_DATA0, 0);
+	gpio_direction_output(GPIO_DATA1, 0);
+	gpio_direction_output(GPIO_DATA2, 0);
+	gpio_direction_output(GPIO_DATA3, 0);
+	gpio_direction_output(GPIO_DATA4, 0);
+	gpio_direction_output(GPIO_DATA5, 0);
+	gpio_direction_output(GPIO_DATA6, 0);
+	gpio_direction_output(GPIO_DATA7, 0);
+
+	/* NB omap_free_gpio() resets to an input, so we can't
+	 * free ie. nCONFIG, or else the FPGA would reset
+	 * Q: presumably gpio_free() has the same effect?
+	 */
+
+	/* set up inputs */
+	gpio_direction_input(GPIO_nSTATUS);
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+	gpio_direction_input(GPIO_CONF_DONE);
+#endif
+
+	fpga_config_fn(0, 1, 0);
+	udelay(60);
+
+	return FPGA_SUCCESS;
+}
+
+int fpga_null_fn(int cookie)
+{
+	return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+	fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert);
+	if (flush) {
+		gpio_set_value(GPIO_nCONFIG, !assert);
+		udelay(1);
+		gpio_set_value(GPIO_nCONFIG, assert);
+	}
+
+	return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+	int result = 0;
+
+	/* since revA of BLX, we will not get this signal. */
+	udelay(10);
+#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+	fpga_debug("not waiting for CONF_DONE.");
+	result = 1;
+#else
+	fpga_debug("CONF_DONE check ... ");
+	if (gpio_get_value(GPIO_CONF_DONE))  {
+		fpga_debug("high\n");
+		result = 1;
+	} else
+		fpga_debug("low\n");
+	gpio_free(GPIO_CONF_DONE);
+#endif
+
+	return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+	int result = 0;
+	fpga_debug("STATUS check ... ");
+
+	result = gpio_get_value(GPIO_nSTATUS);
+
+	if (result < 0)
+		fpga_debug("error\n");
+	else if (result > 0)
+		fpga_debug("high\n");
+	else
+		fpga_debug("low\n");
+
+	return result;
+}
+
+static inline int _write_fpga(u8 byte)
+{
+	gpio_set_value(GPIO_DATA0, byte & 0x01);
+	gpio_set_value(GPIO_DATA1, (byte >> 1) & 0x01);
+	gpio_set_value(GPIO_DATA2, (byte >> 2) & 0x01);
+	gpio_set_value(GPIO_DATA3, (byte >> 3) & 0x01);
+	gpio_set_value(GPIO_DATA4, (byte >> 4) & 0x01);
+	gpio_set_value(GPIO_DATA5, (byte >> 5) & 0x01);
+	gpio_set_value(GPIO_DATA6, (byte >> 6) & 0x01);
+	gpio_set_value(GPIO_DATA7, (byte >> 7) & 0x01);
+
+	/* clock */
+	gpio_set_value(GPIO_DCLK, 1);
+	udelay(1);
+	gpio_set_value(GPIO_DCLK, 0);
+	udelay(1);
+
+	return 0;
+}
+
+int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
+{
+	unsigned char *data = (unsigned char *) buf;
+	int i;
+
+	fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+	for (i = 0; i < len; i++)
+		_write_fpga(data[i]);
+	fpga_debug("-%s\n", __func__);
+
+	return FPGA_SUCCESS;
+}
diff --git a/board/matrix_vision/mvblx/fpga.h b/board/matrix_vision/mvblx/fpga.h
new file mode 100644
index 00000000000..3d427bf5733
--- /dev/null
+++ b/board/matrix_vision/mvblx/fpga.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvblx_init_fpga(void);
+
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);
diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c
new file mode 100644
index 00000000000..74b5b19be22
--- /dev/null
+++ b/board/matrix_vision/mvblx/mvblx.c
@@ -0,0 +1,169 @@
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from Beagle and Overo
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "mvblx.h"
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void);
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init();	/* in SRAM or SDRAM, finish GPMC */
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	printf("mvBlueLYNX-X\n");
+	if (get_cpu_family() == CPU_OMAP36XX)
+		setenv("mpurate", "1000");
+	else
+		setenv("mpurate", "600");
+
+	twl4030_power_init();
+
+#if defined(CONFIG_CMD_NET)
+	setup_net_chip();
+#endif /* CONFIG_CMD_NET */
+
+	mvblx_init_fpga();
+
+	mac_read_from_eeprom();
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_MVBLX();
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	omap_mmc_init(1);
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET)
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ *		Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+	/* Configure GPMC registers */
+	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1);
+	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2);
+	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3);
+	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4);
+	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5);
+	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6);
+	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7);
+
+	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+		&ctrl_base->gpmc_nadv_ale);
+
+	/* Make GPIO 139 as output pin */
+	writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe);
+
+	/* Now send a pulse on the GPIO pin */
+	writel(GPIO11, &gpio5_base->setdataout);
+	udelay(1);
+	writel(GPIO11, &gpio5_base->cleardataout);
+	udelay(1);
+	writel(GPIO11, &gpio5_base->setdataout);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
+
+int overwrite_console(void)
+{
+	/* return TRUE if console should be overwritten */
+	return 0;
+}
+
+#endif /* CONFIG_CMD_NET */
diff --git a/board/matrix_vision/mvblx/mvblx.h b/board/matrix_vision/mvblx/mvblx.h
new file mode 100644
index 00000000000..cda5b0bd01c
--- /dev/null
+++ b/board/matrix_vision/mvblx/mvblx.h
@@ -0,0 +1,362 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MVBLX_H_
+#define _MVBLX_H_
+
+#include <asm/arch/sys_proto.h>
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"OMAP3 mvBlueLYNX-X camera",
+	"no NAND",
+};
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_MVBLX() \
+ /*SDRC*/\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) /*GPMC_A1*/\
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) /*GPMC_A2*/\
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) /*GPMC_A3*/\
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) /*GPMC_A4*/\
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) /*GPMC_A5*/\
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) /*GPMC_A6*/\
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) /*GPMC_A7*/\
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M4)) /*GPIO_41*/\
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M4)) /*GPIO_42*/\
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M4)) /*GPIO_43*/\
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) /*GPMC_D0*/\
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) /*GPMC_D1*/\
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) /*GPMC_D2*/\
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) /*GPMC_D3*/\
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) /*GPMC_D4*/\
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) /*GPMC_D5*/\
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) /*GPMC_D6*/\
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) /*GPMC_D7*/\
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) /*GPMC_D8*/\
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) /*GPMC_D9*/\
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) /*GPMC_D10*/\
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) /*GPMC_D11*/\
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) /*GPMC_D12*/\
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) /*GPMC_D13*/\
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) /*GPMC_D14*/\
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) /*GPMC_D15*/\
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
+	MUX_VAL(CP(GPMC_NCS3),		(IEN  | PTU | EN  | M4)) /*GPIO54*/\
+	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M4)) /*GPIO55*/\
+	MUX_VAL(CP(GPMC_NCS5),		(IEN  | PTU | EN  | M4)) /*GPIO56*/\
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTU | EN  | M4)) /*GPIO57*/\
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M4)) /*GPIO58*/\
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IEN  | PTU | EN  | M4)) /*GPIO60*/\
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M4)) /*GPIO61*/\
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTU | EN  | M4)) /*GPIO62*/\
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IDIS  | PTU | EN  | M4)) /*GPIO65*/\
+ /*DSS*/\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M4)) /*not_used*/\
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M4)) /*not_used*/\
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M4)) /*not_used*/\
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M4)) /*not_used*/\
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M4)) /*not_used*/\
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M4)) /*not_used*/\
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
+ /*CAMERA*/\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card 1*/\
+	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+	MUX_VAL(CP(MMC1_DAT4),		(IDIS  | PTU | DIS  | M4)) /*GPIO_?*/\
+	MUX_VAL(CP(MMC1_DAT5),		(IDIS  | PTU | DIS  | M4)) /*GPIO_?*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IDIS  | PTU | DIS  | M4)) /*GPIO_?*/\
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | DIS  | M7)) /*GPIO_129 disabled*/\
+ /*Expansion card 2 */\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | DIS  | M0)) /*MMC2_CLK*/\
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | DIS  | M0)) /*MMC2_CMD*/\
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT0*/\
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT1*/\
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT2*/\
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT3*/\
+	MUX_VAL(CP(MMC2_DAT4),		(IDIS  | PTU | DIS  | M4)) /*GPIO_136*/\
+	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137*/\
+	MUX_VAL(CP(MMC2_DAT6),		(IDIS  | PTU | DIS  | M4)) /*GPIO_138*/\
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M1)) /*UART2_CTS*/\
+	MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+	MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+	MUX_VAL(CP(MCBSP3_FSX),		(IDIS | PTD | DIS | M1)) /*UART2_RX*/\
+ /*Modem Interface */\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+	MUX_VAL(CP(UART1_CTS),		(IEN | PTU | EN | M4)) /*GPIO_150*/ \
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+	MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+	MUX_VAL(CP(MCBSP1_FSR),		(IEN | PTU | EN  | M4)) /*GPIO_157*/\
+	MUX_VAL(CP(MCBSP1_DX),		(IEN | PTU | DIS | M4)) /*GPIO_158 1-wire */\
+	MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
+	MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+	MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /*Serial Interface*/\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) /*I2C2_SCL*/\
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) /*I2C2_SDA*/\
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
+	MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
+	MUX_VAL(CP(MCSPI1_CLK),		(IDIS  | PTU | DIS  | M4)) /*GPIO_171*/\
+	MUX_VAL(CP(MCSPI1_SIMO),	(IDIS  | PTU | DIS  | M4)) /*GPIO_172*/\
+	MUX_VAL(CP(MCSPI1_SOMI),	(IDIS  | PTU | DIS  | M4)) /*GPIO_173*/\
+	MUX_VAL(CP(MCSPI1_CS0),		(IDIS  | PTD | DIS  | M4)) /*GPIO_174*/\
+	MUX_VAL(CP(MCSPI1_CS3),		(IDIS  | PTU | DIS | M4)) /*GPIO_177*/\
+ /* USB EHCI (port 2) not used */\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) /*McSPI2_CLK*/\
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI2_SIMO*/\
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI2_SOMI*/\
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI2_CS0*/\
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M0)) /*McSPI2_CS1*/\
+ /*Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+	MUX_VAL(CP(SYS_BOOT0),		(IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
+	MUX_VAL(CP(SYS_BOOT1),		(IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M0)) /*GPIO_4*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ \
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+	MUX_VAL(CP(SYS_CLKOUT1),	(IDIS  | PTD | DIS | M4)) /*GPIO_10*/\
+	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTD | DIS  | M0)) /*SYS_CLKOUT2*/\
+ /* USB EHCI (port 1) */\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M3)) /*HSUSB1_STP*/\
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+	MUX_VAL(CP(ETK_D10_ES2),	(IEN | PTU | EN | M4)) /*GPIO_24*/\
+	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M4)) /*GPIO_25*/\
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | DIS | M4)) /*GPIO_26*/\
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | DIS | M4)) /*GPIO_27*/\
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | DIS | M4)) /*GPIO_28*/\
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | DIS | M4)) /*GPIO_29*/\
+ /*Die to Die */\
+	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
+	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
+	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
+	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
+	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
+	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
+	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
+	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
+	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
+	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
+	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
+	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
+	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
+	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
+	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
+	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
+	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
+	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
+	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
+	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
+	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
+	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
+	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
+	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
+	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
+	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
+	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
+	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
+	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
+	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
+	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
+	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
+	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
+	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
+
+#endif
diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c
new file mode 100644
index 00000000000..945a36dfe66
--- /dev/null
+++ b/board/matrix_vision/mvblx/sys_eeprom.c
@@ -0,0 +1,395 @@
+/*
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ * York Sun (yorksun@freescale.com)
+ * Haiying Wang (haiying.wang@freescale.com)
+ * Timur Tabi (timur@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+
+/* #define DEBUG */
+
+/*
+ * static eeprom: EEPROM layout
+ */
+static struct __attribute__ ((__packed__)) eeprom {
+	u8 id[16];		/* 0x01 - 0x0F Type e.g. 100wG-5111 */
+	u8 sn[10];		/* 0x10 - 0x19 Serial Number */
+	u8 date[6];		/* 0x1A - 0x1F Build Date */
+	u8 mac[6];		/* 0x20 - 0x25 MAC address  */
+	u8 reserved[10];/* 0x26 - 0x2f reserved */
+	u32 crc;        /* x+1         CRC32 checksum */
+} e;
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read;
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+static void show_eeprom(void)
+{
+	unsigned int crc;
+	char safe_string[16];
+
+#ifdef DEBUG
+	int i;
+#endif
+	u8 *p;
+
+	/* ID */
+	strncpy(safe_string, (char *)e.id, sizeof(e.id));
+	safe_string[sizeof(e.id)-1] = 0;
+	printf("ID: mvBlueLYNX-X%s\n", safe_string);
+
+	/* Serial number */
+	strncpy(safe_string, (char *)e.sn, sizeof(e.sn));
+	safe_string[sizeof(e.sn)-1] = 0;
+	printf("SN: %s\n", safe_string);
+
+	/* Build date, BCD date values, as YYMMDDhhmmss */
+	printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
+		e.date[0], e.date[1], e.date[2],
+		e.date[3] & 0x7F, e.date[4], e.date[5],
+		e.date[3] & 0x80 ? "PM" : "");
+
+	/* Show MAC address  */
+	p = e.mac;
+	printf("Eth: %02x:%02x:%02x:%02x:%02x:%02x\n",
+		p[0], p[1], p[2], p[3],	p[4], p[5]);
+
+	crc = crc32(0, (void *)&e, sizeof(e) - 4);
+
+	if (crc == be32_to_cpu(e.crc))
+		printf("CRC: %08x\n", be32_to_cpu(e.crc));
+	else
+		printf("CRC: %08x (should be %08x)\n", be32_to_cpu(e.crc), crc);
+
+#ifdef DEBUG
+	printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
+	for (i = 0; i < sizeof(e); i++) {
+		if ((i % 16) == 0)
+			printf("%02X: ", i);
+		printf("%02X ", ((u8 *)&e)[i]);
+		if (((i % 16) == 15) || (i == sizeof(e) - 1))
+			printf("\n");
+	}
+#endif
+}
+
+/**
+ * read_eeprom - read the EEPROM into memory
+ */
+static int read_eeprom(void)
+{
+	int ret;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	unsigned int bus;
+#endif
+
+	if (has_been_read)
+		return 0;
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	bus = i2c_get_bus_num();
+	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+	ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+		(uchar *)&e, sizeof(e));
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	i2c_set_bus_num(bus);
+#endif
+
+#ifdef DEBUG
+	show_eeprom();
+#endif
+
+	has_been_read = (ret == 0) ? 1 : 0;
+
+	return ret;
+}
+
+/**
+ *  update_crc - update the CRC
+ *
+ *  This function should be called after each update to the EEPROM structure,
+ *  to make sure the CRC is always correct.
+ */
+static void update_crc(void)
+{
+	u32 crc;
+
+	crc = crc32(0, (void *)&e, sizeof(e) - 4);
+	e.crc = cpu_to_be32(crc);
+}
+
+/**
+ * prog_eeprom - write the EEPROM from memory
+ */
+static int prog_eeprom(void)
+{
+	int ret = 0;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	unsigned int bus;
+#endif
+
+	update_crc();
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	bus = i2c_get_bus_num();
+	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+	ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+		(uchar *)&e, sizeof(e));
+
+	if (!ret) {
+		/* Verify the write by reading back the EEPROM and comparing */
+		struct eeprom e2;
+#ifdef DEBUG
+		printf("%s verifying...\n", __func__);
+#endif
+		ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+			(uchar *)&e2, sizeof(e2));
+
+		if (!ret && memcmp(&e, &e2, sizeof(e)))
+			ret = -1;
+	}
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	i2c_set_bus_num(bus);
+#endif
+
+	if (ret) {
+		printf("Programming failed.\n");
+		has_been_read = 0;
+		return -1;
+	}
+
+	printf("Programming passed.\n");
+	return 0;
+}
+
+/**
+ * h2i - converts hex character into a number
+ *
+ * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
+ * the integer equivalent.
+ */
+static inline u8 h2i(char p)
+{
+	if ((p >= '0') && (p <= '9'))
+		return p - '0';
+
+	if ((p >= 'A') && (p <= 'F'))
+		return (p - 'A') + 10;
+
+	if ((p >= 'a') && (p <= 'f'))
+		return (p - 'a') + 10;
+
+	return 0;
+}
+
+/**
+ * set_date - stores the build date into the EEPROM
+ *
+ * This function takes a pointer to a string in the format "YYMMDDhhmmss"
+ * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
+ * and stores it in the build date field of the EEPROM local copy.
+ */
+static void set_date(const char *string)
+{
+	unsigned int i;
+
+	if (strlen(string) != 12) {
+		printf("Usage: mac date YYMMDDhhmmss\n");
+		return;
+	}
+
+	for (i = 0; i < 6; i++)
+		e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
+
+	update_crc();
+}
+
+/**
+ * set_mac_address - stores a MAC address into the EEPROM
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
+ * stores it in the MAC address field in the EEPROM local copy.
+ */
+static void set_mac_address(const char *string)
+{
+	char *p = (char *) string;
+	unsigned int i;
+
+	for (i = 0; *p && (i < 6); i++) {
+		e.mac[i] = simple_strtoul(p, &p, 16);
+		if (*p == ':')
+			p++;
+	}
+
+	update_crc();
+}
+
+int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char cmd;
+
+	if (argc == 1) {
+		show_eeprom();
+		return 0;
+	}
+
+	cmd = argv[1][0];
+
+	if (cmd == 'r') {
+#ifdef DEBUG
+		printf("%s read\n", __func__);
+#endif
+		read_eeprom();
+		return 0;
+	}
+
+	if (argc == 2) {
+		switch (cmd) {
+		case 's':	/* save */
+#ifdef DEBUG
+			printf("%s save\n", __func__);
+#endif
+			prog_eeprom();
+			break;
+		default:
+			return cmd_usage(cmdtp);
+		}
+
+		return 0;
+	}
+
+	/* We know we have at least one parameter  */
+
+	switch (cmd) {
+	case 'n':	/* serial number */
+#ifdef DEBUG
+		printf("%s serial number\n", __func__);
+#endif
+		memset(e.sn, 0, sizeof(e.sn));
+		strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
+		update_crc();
+		break;
+	case 'd':	/* date BCD format YYMMDDhhmmss */
+		set_date(argv[2]);
+		break;
+	case 'e':	/* errata */
+		printf("mac errata not implemented\n");
+		break;
+	case 'i':	/* id */
+		memset(e.id, 0, sizeof(e.id));
+		strncpy((char *)e.id, argv[2], sizeof(e.id) - 1);
+		update_crc();
+		break;
+	case 'p':	/* ports */
+		printf("mac ports not implemented (always 1 port)\n");
+		break;
+	case '0' ... '9':
+		/* we only have "mac 0" but any digit can be used here */
+		set_mac_address(argv[2]);
+		break;
+	case 'h':	/* help */
+	default:
+		return cmd_usage(cmdtp);
+	}
+
+	return 0;
+}
+
+int mac_read_from_eeprom(void)
+{
+	u32 crc, crc_offset = offsetof(struct eeprom, crc);
+	u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
+
+	if (read_eeprom()) {
+		printf("EEPROM Read failed.\n");
+		return -1;
+	}
+
+	crc = crc32(0, (void *)&e, crc_offset);
+	crcp = (void *)&e + crc_offset;
+	if (crc != be32_to_cpu(*crcp)) {
+		printf("EEPROM CRC mismatch (%08x != %08x)\n", crc,
+			be32_to_cpu(e.crc));
+		return -1;
+	}
+
+	if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) &&
+		memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
+		char ethaddr[9];
+
+		sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+			e.mac[0],
+			e.mac[1],
+			e.mac[2],
+			e.mac[3],
+			e.mac[4],
+			e.mac[5]);
+		/* Only initialize environment variables that are blank
+		 * (i.e. have not yet been set)
+		 */
+		if (!getenv("ethaddr"))
+			setenv("ethaddr", ethaddr);
+	}
+
+	if (memcmp(&e.sn, "\0\0\0\0\0\0\0\0\0\0", 10) &&
+		memcmp(&e.sn, "\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF", 10)) {
+		char serial_num[12];
+
+		strncpy(serial_num, (char *)e.sn, sizeof(e.sn) - 1);
+		/* Only initialize environment variables that are blank
+		 * (i.e. have not yet been set)
+		 */
+		if (!getenv("serial#"))
+			setenv("serial#", serial_num);
+	}
+
+	/* TODO should I calculate CRC here? */
+	return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	char *serial = getenv("serial#");
+
+	if (serial && (strlen(serial) > 3)) {
+		/* use the numerical part of the serial number LXnnnnnn */
+		serialnr->high = 0;
+		serialnr->low = simple_strtoul(serial + 2, NULL, 10);
+	} else {
+		serialnr->high = 0;
+		serialnr->low = 0;
+	}
+}
+#endif