diff options
| author | Murali Karicheri | 2019-02-21 12:02:04 -0500 |
|---|---|---|
| committer | Tom Rini | 2019-04-12 08:05:46 -0400 |
| commit | f748ec9d328b95cc246c960c1cd6c6478b57e788 (patch) | |
| tree | 79a042ac18eefd5464ec7dc7ed5394901c10071d /board/ti | |
| parent | 55d5cb17282e1e5a15309975e0259a9438308197 (diff) | |
ARM: k2g: add a workaround to reset the phy
This patch adds a workaround to reset the phy one time during boot
using GPIO0 pin 10 to make sure, the Phy latches the configuration
from the input pins correctly.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'board/ti')
| -rw-r--r-- | board/ti/ks2_evm/board_k2g.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 39a782e4796..6d0fc21c67a 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -315,6 +315,21 @@ int embedded_dtb_select(void) BIT(9)); setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET, BIT(9)); + } else if (board_is_k2g_ice()) { + /* GBE Phy workaround. For Phy to latch the input + * configuration, a GPIO reset is asserted at the + * Phy reset pin to latch configuration correctly after SoC + * reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE + * board. Just do a low to high transition. + */ + clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET, + BIT(10)); + setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET, + BIT(10)); + /* Delay just to get a transition to high */ + udelay(100); + setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET, + BIT(10)); } return 0; |