diff options
| author | Peng Fan | 2020-12-25 16:16:34 +0800 |
|---|---|---|
| committer | Stefano Babic | 2021-01-23 11:30:30 +0100 |
| commit | 48b90f86c583183e2f4d80b2747ebff612c4173f (patch) | |
| tree | 85dc6b26e8cc8efb87b4ec29dfa46f72321fcd32 /board | |
| parent | 184aa6504143b452132e28cd3ebecc7b941cdfa1 (diff) | |
imx: imx8mp_evk: enable eth support
Add board code to configure the network interface
Add net defconfig
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/imx8mp_evk/imx8mp_evk.c | 65 |
1 files changed, 64 insertions, 1 deletions
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index 034a349236e..330b47fa5f9 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -7,9 +7,13 @@ #include <env.h> #include <errno.h> #include <init.h> +#include <miiphy.h> +#include <netdev.h> +#include <linux/delay.h> #include <asm/mach-imx/iomux-v3.h> #include <asm-generic/gpio.h> #include <asm/arch/imx8mp_pins.h> +#include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/mach-imx/gpio.h> @@ -40,10 +44,69 @@ int board_early_init_f(void) return 0; } -int board_init(void) +static void setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Enable RGMII TX clk output */ + setbits_le32(&gpr->gpr[1], BIT(22)); +} + +#define EQOS_RST_PAD IMX_GPIO_NR(4, 22) +static iomux_v3_cfg_t const eqos_rst_pads[] = { + MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_eqos(void) { + imx_iomux_v3_setup_multiple_pads(eqos_rst_pads, + ARRAY_SIZE(eqos_rst_pads)); + + gpio_request(EQOS_RST_PAD, "eqos_rst"); + gpio_direction_output(EQOS_RST_PAD, 0); + mdelay(15); + gpio_direction_output(EQOS_RST_PAD, 1); + mdelay(100); +} + +static int setup_eqos(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + setup_iomux_eqos(); + + /* set INTF as RGMII, enable RGMII TXC clock */ + clrsetbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); + setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); + + return set_clk_eqos(ENET_125MHZ); +} + +#if CONFIG_IS_ENABLED(NET) +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); return 0; } +#endif + +int board_init(void) +{ + int ret = 0; + + if (CONFIG_IS_ENABLED(FEC_MXC)) { + setup_fec(); + + if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) + ret = setup_eqos(); + } + + return ret; +} int board_late_init(void) { |