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authorMichael Walle2021-03-26 19:40:59 +0100
committerPriyanka Jain2021-04-15 14:22:22 +0530
commit9b3843f8f76fa7812eff503253b47b4b0d69b933 (patch)
tree1437026ce07083fb41c2e6d4238f47e340a852b3 /board
parent6d1ab4a10e3051def7c5d7b522042b84a122f0a1 (diff)
board: sl28: add config to enable console output on SER0
Sometimes it is desireable to have the console output on the first serial line. Introduce a configuration option for it (in the board scope). Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'board')
-rw-r--r--board/kontron/sl28/Kconfig10
-rw-r--r--board/kontron/sl28/Makefile2
-rw-r--r--board/kontron/sl28/common.c11
3 files changed, 22 insertions, 1 deletions
diff --git a/board/kontron/sl28/Kconfig b/board/kontron/sl28/Kconfig
index 4078ef186b5..abcacc3185f 100644
--- a/board/kontron/sl28/Kconfig
+++ b/board/kontron/sl28/Kconfig
@@ -48,4 +48,14 @@ config SL28_BL32_ENTRY_ADDR
endif
+config SL28_ENABLE_SER0_CONSOLE
+ bool "Enable console output on SER0"
+ select DM_SERIAL
+ select SPL_DM_SERIAL
+ select FSL_LPUART
+ help
+ By default the console output of this board is on the second serial
+ line (SER1). Sometimes it is desirable to enable output on the first
+ serial line (SER0). For example, if you have a carrier which only
+ supports the first serial port.
endif
diff --git a/board/kontron/sl28/Makefile b/board/kontron/sl28/Makefile
index 147ef9872b8..5d220f07447 100644
--- a/board/kontron/sl28/Makefile
+++ b/board/kontron/sl28/Makefile
@@ -4,7 +4,7 @@ ifndef CONFIG_SPL_BUILD
obj-y += sl28.o cmds.o
endif
-obj-y += ddr.o
+obj-y += common.o ddr.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
diff --git a/board/kontron/sl28/common.c b/board/kontron/sl28/common.c
new file mode 100644
index 00000000000..33c6843c3f7
--- /dev/null
+++ b/board/kontron/sl28/common.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_lpuart_clk(void)
+{
+ return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
+}