diff options
author | Peter Robinson | 2020-04-20 20:27:36 +0100 |
---|---|---|
committer | Kever Yang | 2020-05-31 22:22:07 +0800 |
commit | 9fb8e24804ea65a0edead7d7d606da016a71fdd8 (patch) | |
tree | 7b19b476eab494d46a30ba02b6fa4b50c3d6db24 /board | |
parent | 7390fb9999c0f42d227b78898f1fe48c936c9b63 (diff) |
rockchip: Add initial support for the Pinebook Pro laptop from Pine64.
Specification:
- Rockchip RK3399
- 4GB Dual-Channel LPDDR4
- eMMC socket
- mSD card slot
- 128Mbit (16Mb) SPI Flash
- AP6256 for 11AC WiFi + BT5
- 14 inch 1920*1080 eDP MiPi display
- Camera
- USB 3.0, 2.0 ports
- Type-C port with alt-mode display (DP 1.2) and 15W charge
- DC 5V/3A
- optional PCIe slot for NVMe SSD drive
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'board')
-rw-r--r-- | board/pine64/pinebook-pro-rk3399/Kconfig | 15 | ||||
-rw-r--r-- | board/pine64/pinebook-pro-rk3399/MAINTAINERS | 8 | ||||
-rw-r--r-- | board/pine64/pinebook-pro-rk3399/Makefile | 1 | ||||
-rw-r--r-- | board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c | 75 |
4 files changed, 99 insertions, 0 deletions
diff --git a/board/pine64/pinebook-pro-rk3399/Kconfig b/board/pine64/pinebook-pro-rk3399/Kconfig new file mode 100644 index 00000000000..3bb7ca448e4 --- /dev/null +++ b/board/pine64/pinebook-pro-rk3399/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PINEBOOK_PRO_RK3399 + +config SYS_BOARD + default "pinebook-pro-rk3399" + +config SYS_VENDOR + default "pine64" + +config SYS_CONFIG_NAME + default "pinebook-pro-rk3399" + +config BOARD_SPECIFIC_OPTIONS + def_bool y + +endif diff --git a/board/pine64/pinebook-pro-rk3399/MAINTAINERS b/board/pine64/pinebook-pro-rk3399/MAINTAINERS new file mode 100644 index 00000000000..227c1c0bea9 --- /dev/null +++ b/board/pine64/pinebook-pro-rk3399/MAINTAINERS @@ -0,0 +1,8 @@ +PINEBOOK_PRO +M: Peter Robinson <pbrobinson@gmail.com> +S: Maintained +F: board/pine64/rk3399-pinebook-pro/ +F: include/configs/rk3399-pinebook-pro.h +F: arch/arm/dts/rk3399-pinebook-pro.dts +F: arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +F: configs/pinebook-pro-rk3399_defconfig diff --git a/board/pine64/pinebook-pro-rk3399/Makefile b/board/pine64/pinebook-pro-rk3399/Makefile new file mode 100644 index 00000000000..2f692a12a67 --- /dev/null +++ b/board/pine64/pinebook-pro-rk3399/Makefile @@ -0,0 +1 @@ +obj-y += pinebook-pro-rk3399.o diff --git a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c new file mode 100644 index 00000000000..516292aaa59 --- /dev/null +++ b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) Copyright 2020 Peter Robinson <pbrobinson at gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/misc.h> +#include <power/regulator.h> + +#define GRF_IO_VSEL_BT565_SHIFT 0 +#define PMUGRF_CON0_VSEL_SHIFT 8 + +#ifndef CONFIG_SPL_BUILD +int board_early_init_f(void) +{ + struct udevice *regulator; + int ret; + + ret = regulator_get_by_platname("vcc5v0_usb", ®ulator); + if (ret) { + pr_debug("%s vcc5v0_usb init fail! ret %d\n", __func__, ret); + goto out; + } + + ret = regulator_set_enable(regulator, true); + if (ret) + pr_debug("%s vcc5v0-host-en-gpio set fail! ret %d\n", __func__, ret); + +out: + return 0; +} +#endif + +#ifdef CONFIG_MISC_INIT_R +static void setup_iodomain(void) +{ + struct rk3399_grf_regs *grf = + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + struct rk3399_pmugrf_regs *pmugrf = + syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + + /* BT565 is in 1.8v domain */ + rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); + + /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ + rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); +} + +int misc_init_r(void) +{ + const u32 cpuid_offset = 0x7; + const u32 cpuid_length = 0x10; + u8 cpuid[cpuid_length]; + int ret; + + setup_iodomain(); + + ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); + if (ret) + return ret; + + ret = rockchip_cpuid_set(cpuid, cpuid_length); + if (ret) + return ret; + + return ret; +} +#endif |