diff options
| author | Marek Vasut | 2020-03-06 21:52:21 +0100 |
|---|---|---|
| committer | Marek Vasut | 2020-04-13 13:49:51 +0200 |
| commit | 8876f89640d3386822025f42b60b1ff9dd679123 (patch) | |
| tree | 58f679e97501edd5592174adefd467e1ebd645cf /configs/socfpga_secu1_defconfig | |
| parent | 995972ddbbcc5fccd324ab384bca9af90e710755 (diff) | |
ARM: socfpga: Enable DM RTC bootcount on ABB SECU1
Add and enable RTC-backed boot counter on ABB SECU1 platform.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'configs/socfpga_secu1_defconfig')
| -rw-r--r-- | configs/socfpga_secu1_defconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index 230959ec865..fcb38f1a410 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -48,6 +48,9 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SPL_DM_SEQ_ALIAS=y # CONFIG_SPL_BLK is not set +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_DM_BOOTCOUNT=y +CONFIG_DM_BOOTCOUNT_RTC=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y @@ -76,6 +79,8 @@ CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_DM_RTC=y +CONFIG_RTC_M41T62=y CONFIG_SPI=y CONFIG_SPI_MEM=y CONFIG_DESIGNWARE_SPI=y |