diff options
| author | Stefan Roese | 2006-11-22 13:20:50 +0100 |
|---|---|---|
| committer | Stefan Roese | 2006-11-22 13:20:50 +0100 |
| commit | 2053283304eeddf250d109e6791eb6fa4cad14f7 (patch) | |
| tree | 2a9152c1e640f91b4e2a3ee06ef42572c28aaa42 /cpu | |
| parent | 4ef6251403f637841000e0fef9e832aa01339822 (diff) | |
[PATCH] PPC4xx start.S: Fix for processor errata
Fixed cpu/ppc4xx/start.S for 440EPx Errata: further corrects PPC440EPx
errata 1.12: 440_33 by moving patch up in code.
Signed-off-by: Jeff Mann <mannj@embeddedplanet.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/ppc4xx/start.S | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 3fe13daaf38..8e000d30924 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -204,6 +204,18 @@ _start_440: mfspr r1,mcsr mtspr mcsr,r1 #endif + + /*----------------------------------------------------------------*/ + /* CCR0 init */ + /*----------------------------------------------------------------*/ + /* Disable store gathering & broadcast, guarantee inst/data + * cache block touch, force load/store alignment + * (see errata 1.12: 440_33) + */ + lis r1,0x0030 /* store gathering & broadcast disable */ + ori r1,r1,0x6000 /* cache touch */ + mtspr ccr0,r1 + /*----------------------------------------------------------------*/ /* Initialize debug */ /*----------------------------------------------------------------*/ @@ -225,17 +237,6 @@ _start_440: mtspr dbsr,r1 /* Clear all valid bits */ skip_debug_init: - /*----------------------------------------------------------------*/ - /* CCR0 init */ - /*----------------------------------------------------------------*/ - /* Disable store gathering & broadcast, guarantee inst/data - * cache block touch, force load/store alignment - * (see errata 1.12: 440_33) - */ - lis r1,0x0030 /* store gathering & broadcast disable */ - ori r1,r1,0x6000 /* cache touch */ - mtspr ccr0,r1 - #if defined (CONFIG_440SPE) /*----------------------------------------------------------------+ | Initialize Core Configuration Reg1. |