diff options
| author | Sughosh Ganu | 2019-12-28 23:58:28 +0530 |
|---|---|---|
| committer | Heinrich Schuchardt | 2020-01-07 18:08:21 +0100 |
| commit | 82ebf0f6a01c79aa4059bdaf3ddc6522adcc56b5 (patch) | |
| tree | 4fee0893369bae15098e5962fc3f045e6bdf35f1 /drivers/clk/clk_stm32mp1.c | |
| parent | a2487684003b0bc380955e1a38cdd71da3ca4366 (diff) | |
clk: stm32mp1: Add a clock entry for RNG1 device
Add an entry for allowing clock enablement for the random number
generator peripheral, RNG1.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'drivers/clk/clk_stm32mp1.c')
| -rw-r--r-- | drivers/clk/clk_stm32mp1.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 3718970dc7c..da66bde41b5 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -563,6 +563,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL), |