diff options
| author | York Sun | 2016-04-04 11:41:26 -0700 |
|---|---|---|
| committer | York Sun | 2016-04-06 10:26:46 -0700 |
| commit | 3c1d218a1d3048fb576677c47eab43049d0b7778 (patch) | |
| tree | fac5c6482522cef5563f368ee2777f4ed274759e /drivers/crypto | |
| parent | 2a5558399828e24fce9e948288a88cd28887875e (diff) | |
armv8: LS2080A: Consolidate LS2080A and LS2085A
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'drivers/crypto')
| -rw-r--r-- | drivers/crypto/fsl/jr.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 3fc418a8c42..8bc517dadcf 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -545,12 +545,12 @@ int sec_init(void) /* * Modifying CAAM Read/Write Attributes - * For LS2080A and LS2085A + * For LS2080A * For AXI Write - Cacheable, Write Back, Write allocate * For AXI Read - Cacheable, Read allocate - * Only For LS2080a and LS2085a, to solve CAAM coherency issues + * Only For LS2080a, to solve CAAM coherency issues */ -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT); mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT); #else |