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authorAshok Reddy Soma2021-07-09 05:53:40 -0600
committerMichal Simek2021-07-26 09:18:45 +0200
commitaffcba728b90428f38e6ea6b945935146c8f3dcb (patch)
tree7b2f927dc91c33b75e93cde543af832322f365de /drivers/mmc
parent8e34aa00e971b41764d03b335941f5bf14f605ac (diff)
mmc: zynq_sdhci: Allow configuring zero Tap values
Allow configuring ITAP and OTAP values with zero to avoid failures in some cases (one of them is SD boot mode). Legacy, SDR12 modes require to program the ITAP and OTAP values as zero, whereas for SDR50 and SDR104 modes ITAP value is zero. In SD boot mode firmware configures the SD ITAP and OTAP values and in this case u-boot has to re-configure required tap values(including zero) based on the operating mode. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/zynq_sdhci.c16
1 files changed, 4 insertions, 12 deletions
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 5bad5cb9e7a..f65a87a4e14 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -198,9 +198,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
* ZynqMP does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
@@ -253,9 +251,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
* ZynqMP does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
@@ -307,9 +303,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
* Versal does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
@@ -370,9 +364,7 @@ static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
* Versal does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {