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authorKunihiko Hayashi2021-07-06 19:01:08 +0900
committerTom Rini2021-07-14 16:48:07 -0400
commitb0415d826fce8e04d0c2f09876a479301ccb6405 (patch)
tree4fc8bf662fd18b29796627f15d3479b5fbf27fc5 /drivers/phy
parent34707b32edad37427327a5358433d0591a07dcc1 (diff)
phy: socionext: Add UniPhier PCIe PHY driver
Add PCIe PHY driver support for Pro5, LD20 and PXs3 SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Diffstat (limited to 'drivers/phy')
-rw-r--r--drivers/phy/socionext/Kconfig12
-rw-r--r--drivers/phy/socionext/Makefile6
-rw-r--r--drivers/phy/socionext/phy-uniphier-pcie.c59
3 files changed, 77 insertions, 0 deletions
diff --git a/drivers/phy/socionext/Kconfig b/drivers/phy/socionext/Kconfig
new file mode 100644
index 00000000000..bcd579e98ec
--- /dev/null
+++ b/drivers/phy/socionext/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# PHY drivers for Socionext platforms.
+#
+
+config PHY_UNIPHIER_PCIE
+ bool "UniPhier PCIe PHY driver"
+ depends on PHY && ARCH_UNIPHIER
+ imply REGMAP
+ help
+ Enable this to support PHY implemented in PCIe controller
+ on UniPhier SoCs.
diff --git a/drivers/phy/socionext/Makefile b/drivers/phy/socionext/Makefile
new file mode 100644
index 00000000000..5484360b70f
--- /dev/null
+++ b/drivers/phy/socionext/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the phy drivers.
+#
+
+obj-$(CONFIG_PHY_UNIPHIER_PCIE) += phy-uniphier-pcie.o
diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c
new file mode 100644
index 00000000000..d352c4ca3a9
--- /dev/null
+++ b/drivers/phy/socionext/phy-uniphier-pcie.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * phy_uniphier_pcie.c - Socionext UniPhier PCIe PHY driver
+ * Copyright 2019-2021 Socionext, Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <regmap.h>
+#include <syscon.h>
+
+/* SG */
+#define SG_USBPCIESEL 0x590
+#define SG_USBPCIESEL_PCIE BIT(0)
+
+struct uniphier_pciephy_priv {
+ int dummy;
+};
+
+static int uniphier_pciephy_init(struct phy *phy)
+{
+ return 0;
+}
+
+static int uniphier_pciephy_probe(struct udevice *dev)
+{
+ struct regmap *regmap;
+
+ regmap = syscon_regmap_lookup_by_phandle(dev,
+ "socionext,syscon");
+ if (!IS_ERR(regmap))
+ regmap_update_bits(regmap, SG_USBPCIESEL,
+ SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE);
+
+ return 0;
+}
+
+static struct phy_ops uniphier_pciephy_ops = {
+ .init = uniphier_pciephy_init,
+};
+
+static const struct udevice_id uniphier_pciephy_ids[] = {
+ { .compatible = "socionext,uniphier-pro5-pcie-phy" },
+ { .compatible = "socionext,uniphier-ld20-pcie-phy" },
+ { .compatible = "socionext,uniphier-pxs3-pcie-phy" },
+ { }
+};
+
+U_BOOT_DRIVER(uniphier_pcie_phy) = {
+ .name = "uniphier-pcie-phy",
+ .id = UCLASS_PHY,
+ .of_match = uniphier_pciephy_ids,
+ .ops = &uniphier_pciephy_ops,
+ .probe = uniphier_pciephy_probe,
+ .priv_auto = sizeof(struct uniphier_pciephy_priv),
+};