diff options
author | Igor Prusov | 2023-11-09 20:10:04 +0300 |
---|---|---|
committer | Tom Rini | 2023-11-16 18:59:58 -0500 |
commit | 13248d66aeea02afc120ba83075e1af32cefd592 (patch) | |
tree | 3b74811fd4b0b28ed73e696af95965c97e162ce0 /drivers/phy | |
parent | 35425507b3253bb1e08110f67e130e7c9c272cf7 (diff) |
treewide: use linux/time.h for time conversion defines
Now that we have time conversion defines from in time.h there is no need
for each driver to define their own version.
Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com> #at91
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> #qcom geni
Reviewed-by: Stefan Bosch <stefan_b@posteo.net> #nanopi2
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Diffstat (limited to 'drivers/phy')
-rw-r--r-- | drivers/phy/meson-axg-mipi-dphy.c | 3 | ||||
-rw-r--r-- | drivers/phy/phy-core-mipi-dphy.c | 3 | ||||
-rw-r--r-- | drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c | 3 |
3 files changed, 3 insertions, 6 deletions
diff --git a/drivers/phy/meson-axg-mipi-dphy.c b/drivers/phy/meson-axg-mipi-dphy.c index cf2a1cd14c7..a69b6c97594 100644 --- a/drivers/phy/meson-axg-mipi-dphy.c +++ b/drivers/phy/meson-axg-mipi-dphy.c @@ -25,6 +25,7 @@ #include <linux/bitops.h> #include <linux/compat.h> #include <linux/bitfield.h> +#include <linux/time.h> /* [31] soft reset for the phy. * 1: reset. 0: dessert the reset. @@ -170,8 +171,6 @@ #define MIPI_DSI_TEST_CTRL0 0x3c #define MIPI_DSI_TEST_CTRL1 0x40 -#define NSEC_PER_MSEC 1000000L - struct phy_meson_axg_mipi_dphy_priv { struct regmap *regmap; #if CONFIG_IS_ENABLED(CLK) diff --git a/drivers/phy/phy-core-mipi-dphy.c b/drivers/phy/phy-core-mipi-dphy.c index ba5f6486126..bb61816add2 100644 --- a/drivers/phy/phy-core-mipi-dphy.c +++ b/drivers/phy/phy-core-mipi-dphy.c @@ -6,11 +6,10 @@ #include <common.h> #include <div64.h> +#include <linux/time.h> #include <phy-mipi-dphy.h> -#define PSEC_PER_SEC 1000000000000LL - /* * Minimum D-PHY timings based on MIPI D-PHY specification. Derived * from the valid ranges specified in Section 6.9, Table 14, Page 41 diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c index 9ed7af0d6ef..5be76e05339 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c @@ -15,6 +15,7 @@ #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/math64.h> +#include <linux/time.h> #include <phy-mipi-dphy.h> #include <reset.h> @@ -186,8 +187,6 @@ #define DSI_PHY_STATUS 0xb0 #define PHY_LOCK BIT(0) -#define PSEC_PER_SEC 1000000000000LL - #define msleep(a) udelay(a * 1000) enum phy_max_rate { |