diff options
| author | Haiying Wang | 2011-02-11 01:25:30 -0600 |
|---|---|---|
| committer | Kumar Gala | 2011-04-05 10:18:39 -0500 |
| commit | a52d2f816dac9cf516b4c795d44ce42cbe6aacb3 (patch) | |
| tree | 1537649316d30b38f942321e83be20f6f47df84f /drivers/qe | |
| parent | c1fc2d4fc282fb59f42c82fd0b5e8255497093b5 (diff) | |
powerpc/85xx: Add P1021 specific QE and UEC support
P1021 has some QE pins which need to be set in pmuxcr register before
using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and
UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to
be released after MII access because QE12 pin is muxed with LBCTL signal.
Also added relevant QE support defines unique to P1021.
The P1021 QE is shared on P1012, P1016, and P1025.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'drivers/qe')
| -rw-r--r-- | drivers/qe/uec.c | 37 |
1 files changed, 36 insertions, 1 deletions
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 282ab237516..811e3fc3156 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2011 Freescale Semiconductor, Inc. * * Dave Liu <daveliu@freescale.com> * @@ -588,9 +588,27 @@ static void phy_change(struct eth_device *dev) { uec_private_t *uec = (uec_private_t *)dev->priv; +#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ + defined(CONFIG_P1021) || defined(CONFIG_P1025) + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* QE9 and QE12 need to be set for enabling QE MII managment signals */ + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); +#endif + /* Update the link, speed, duplex */ uec->mii_info->phyinfo->read_status(uec->mii_info); +#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ + defined(CONFIG_P1021) || defined(CONFIG_P1025) + /* + * QE12 is muxed with LBCTL, it needs to be released for enabling + * LBCTL signal for LBC usage. + */ + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); +#endif + /* Adjust the interface according to speed */ adjust_link(dev); } @@ -1198,10 +1216,21 @@ static int uec_init(struct eth_device* dev, bd_t *bd) uec_private_t *uec; int err, i; struct phy_info *curphy; +#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ + defined(CONFIG_P1021) || defined(CONFIG_P1025) + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif uec = (uec_private_t *)dev->priv; if (uec->the_first_run == 0) { +#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ + defined(CONFIG_P1021) || defined(CONFIG_P1025) + /* QE9 and QE12 need to be set for enabling QE MII managment signals */ + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); +#endif + err = init_phy(dev); if (err) { printf("%s: Cannot initialize PHY, aborting.\n", @@ -1228,6 +1257,12 @@ static int uec_init(struct eth_device* dev, bd_t *bd) udelay(100000); } while (1); +#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ + defined(CONFIG_P1021) || defined(CONFIG_P1025) + /* QE12 needs to be released for enabling LBCTL signal*/ + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); +#endif + if (err || i <= 0) printf("warning: %s: timeout on PHY link\n", dev->name); |