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authorBin Meng2023-10-11 21:15:49 +0800
committerTom Rini2023-11-27 16:18:59 -0500
commite5c19ce47c7063553b26443560179307416e26f9 (patch)
tree53fed59bf5c61d003706a5585b835209c9ebb9f9 /drivers/ufs
parent07a64f0a347a4befb01dbdf912f8451f30f71abc (diff)
ufs: Allow mmio registers on the PCI bus
Check if the UFS controller is on the PCI bus, and get its register base address accordingly. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Diffstat (limited to 'drivers/ufs')
-rw-r--r--drivers/ufs/ufs.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c
index 96801866d33..fb2a607ef11 100644
--- a/drivers/ufs/ufs.c
+++ b/drivers/ufs/ufs.c
@@ -1914,6 +1914,7 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops)
struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev);
struct scsi_plat *scsi_plat;
struct udevice *scsi_dev;
+ void __iomem *mmio_base;
int err;
device_find_first_child(ufs_dev, &scsi_dev);
@@ -1927,7 +1928,14 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops)
hba->dev = ufs_dev;
hba->ops = hba_ops;
- hba->mmio_base = dev_read_addr_ptr(ufs_dev);
+
+ if (device_is_on_pci_bus(ufs_dev)) {
+ mmio_base = dm_pci_map_bar(ufs_dev, PCI_BASE_ADDRESS_0, 0, 0,
+ PCI_REGION_TYPE, PCI_REGION_MEM);
+ } else {
+ mmio_base = dev_read_addr_ptr(ufs_dev);
+ }
+ hba->mmio_base = mmio_base;
/* Set descriptor lengths to specification defaults */
ufshcd_def_desc_sizes(hba);