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authorBernhard Messerklinger2018-02-15 08:59:53 +0100
committerTom Rini2018-02-23 10:40:50 -0500
commit664758c3dd1cf9c892ce98112e629cb032ac64aa (patch)
tree691f1c0252f2ac697744c53b1c729af8a9b2d26d /drivers
parent4be9f1f25d331a717a12ce7ac560b8534a4e2e7c (diff)
pci: Fix decode regions for memory banks
Since memory banks may not be located behind each other we need to add them separately. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pci/pci-uclass.c17
1 files changed, 16 insertions, 1 deletions
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 5a24eb6428f..ad43e8a27cc 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -815,7 +815,6 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node,
ofnode node)
{
int pci_addr_cells, addr_cells, size_cells;
- phys_addr_t base = 0, size;
int cells_per_record;
const u32 *prop;
int len;
@@ -874,6 +873,21 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node,
}
/* Add a region for our local memory */
+#ifdef CONFIG_NR_DRAM_BANKS
+ bd_t *bd = gd->bd;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+ if (bd->bi_dram[i].size) {
+ pci_set_region(hose->regions + hose->region_count++,
+ bd->bi_dram[i].start,
+ bd->bi_dram[i].start,
+ bd->bi_dram[i].size,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+ }
+ }
+#else
+ phys_addr_t base = 0, size;
+
size = gd->ram_size;
#ifdef CONFIG_SYS_SDRAM_BASE
base = CONFIG_SYS_SDRAM_BASE;
@@ -882,6 +896,7 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node,
size = gd->pci_ram_top - base;
pci_set_region(hose->regions + hose->region_count++, base, base,
size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+#endif
return 0;
}