rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

1 files changed, 112 insertions, 112 deletions

diff --git a/include/configs/sc3.h b/include/configs/sc3.h
index 88a24b87973..44135dfac54 100644
--- a/include/configs/sc3.h
+++ b/include/configs/sc3.h
@@ -128,7 +128,7 @@
 #undef CONFIG_BOOTCOMMAND
 
 #define CONFIG_SILENT_CONSOLE	1	/* enable silent startup */
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
 #if 1	/* feel free to disable for development */
 #define CONFIG_AUTOBOOT_KEYED		/* Enable password protection	*/
@@ -160,7 +160,7 @@
 #undef CONFIG_ISP1161_PRESENT
 
 #undef CONFIG_LOADS_ECHO   /* no echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_NET_MULTI
 /* #define CONFIG_EEPRO100_SROM_WRITE */
@@ -205,42 +205,42 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP	1		/* undef to save memory		*/
-#define CFG_PROMPT	"SC3> "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_LONGHELP	1		/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"SC3> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
 /*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
  * The Linux BASE_BAUD define should match this configuration.
  *    baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  * set Linux BASE_BAUD to 403200.
  *
  * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to
  * (see 405GP datasheet for descritpion)
  */
-#undef	CFG_EXT_SERIAL_CLOCK		/* external serial clock */
-#undef	CFG_405_UART_ERRATA_59		/* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD		921600	/* internal clock */
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK		/* external serial clock */
+#undef	CONFIG_SYS_405_UART_ERRATA_59		/* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		921600	/* internal clock */
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
-#define CFG_LOAD_ADDR		0x1000000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x1000000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
 /*-----------------------------------------------------------------------
  * IIC stuff
@@ -253,11 +253,11 @@
 #define I2C_ACTIVE 0
 #define I2C_TRISTATE 0
 
-#define CFG_I2C_SPEED		100000	/* use the standard 100kHz speed */
-#define CFG_I2C_SLAVE		0x7F		/* mask valid bits */
+#define CONFIG_SYS_I2C_SPEED		100000	/* use the standard 100kHz speed */
+#define CONFIG_SYS_I2C_SLAVE		0x7F		/* mask valid bits */
 
 #define CONFIG_RTC_DS1337
-#define CFG_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -275,14 +275,14 @@
 /* If you want to see, whats connected to your PCI bus */
 /* #define CONFIG_PCI_SCAN_SHOW */
 
-#define CFG_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * External peripheral base address
@@ -306,103 +306,103 @@
 
 #define	CONFIG_ATAPI
 #define	CONFIG_DOS_PARTITION
-#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define	CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
 #ifndef IDE_USES_ISA_EMULATION
 
 /* New and faster access */
-#define	CFG_ATA_BASE_ADDR		0x7A000000	/* start of ISA IO emulation */
+#define	CONFIG_SYS_ATA_BASE_ADDR		0x7A000000	/* start of ISA IO emulation */
 
 /* How many IDE busses are available */
-#define	CFG_IDE_MAXBUS		1
+#define	CONFIG_SYS_IDE_MAXBUS		1
 
 /* What IDE ports are available */
-#define	CFG_ATA_IDE0_OFFSET	0x000		/* first is available */
-#undef	CFG_ATA_IDE1_OFFSET			/* second not available */
+#define	CONFIG_SYS_ATA_IDE0_OFFSET	0x000		/* first is available */
+#undef	CONFIG_SYS_ATA_IDE1_OFFSET			/* second not available */
 
 /* access to the data port is calculated:
-   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
 
 /* access to the registers is calculated:
-   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
-#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */
+#define	CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
 
 /* access to the alternate register is calculated:
-   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
-#define CFG_ATA_ALT_OFFSET	0x008		/* Offset for alternate registers	*/
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x008		/* Offset for alternate registers	*/
 
 #else /* IDE_USES_ISA_EMULATION */
 
-#define	CFG_ATA_BASE_ADDR		0x79000000	/* start of ISA IO emulation */
+#define	CONFIG_SYS_ATA_BASE_ADDR		0x79000000	/* start of ISA IO emulation */
 
 /* How many IDE busses are available */
-#define	CFG_IDE_MAXBUS		1
+#define	CONFIG_SYS_IDE_MAXBUS		1
 
 /* What IDE ports are available */
-#define	CFG_ATA_IDE0_OFFSET	0x01F0	/* first is available */
-#undef	CFG_ATA_IDE1_OFFSET				/* second not available */
+#define	CONFIG_SYS_ATA_IDE0_OFFSET	0x01F0	/* first is available */
+#undef	CONFIG_SYS_ATA_IDE1_OFFSET				/* second not available */
 
 /* access to the data port is calculated:
-   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
 
 /* access to the registers is calculated:
-   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
-#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */
+#define	CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
 
 /* access to the alternate register is calculated:
-   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
-#define CFG_ATA_ALT_OFFSET	0x03F0		/* Offset for alternate registers	*/
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x03F0		/* Offset for alternate registers	*/
 
 #endif /* IDE_USES_ISA_EMULATION */
 
 #endif
 
 /*
-#define	CFG_KEY_REG_BASE_ADDR	0xF0100000
-#define	CFG_IR_REG_BASE_ADDR	0xF0200000
-#define	CFG_FPGA_REG_BASE_ADDR	0xF0300000
+#define	CONFIG_SYS_KEY_REG_BASE_ADDR	0xF0100000
+#define	CONFIG_SYS_IR_REG_BASE_ADDR	0xF0200000
+#define	CONFIG_SYS_FPGA_REG_BASE_ADDR	0xF0300000
 */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  *
- * CFG_FLASH_BASE   -> start address of internal flash
- * CFG_MONITOR_BASE -> start of u-boot
+ * CONFIG_SYS_FLASH_BASE   -> start address of internal flash
+ * CONFIG_SYS_MONITOR_BASE -> start of u-boot
  */
 #ifndef __ASSEMBLER__
 extern unsigned long offsetOfBigFlash;
 extern unsigned long offsetOfEnvironment;
 #endif
 
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFE00000
-#define CFG_MONITOR_BASE	0xFFFC0000     /* placed last 256k */
-#define CFG_MONITOR_LEN		(224 * 1024)	/* Reserve 224 KiB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 KiB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFE00000
+#define CONFIG_SYS_MONITOR_BASE	0xFFFC0000     /* placed last 256k */
+#define CONFIG_SYS_MONITOR_LEN		(224 * 1024)	/* Reserve 224 KiB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 KiB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MiB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization ## FIXME: lookup in datasheet
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_CFI			/* flash is CFI compat.	*/
+#define CONFIG_SYS_FLASH_CFI			/* flash is CFI compat.	*/
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver*/
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-#define CFG_WRITE_SWAPPED_DATA		/* swap Databytes between reading/writing */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_WRITE_SWAPPED_DATA		/* swap Databytes between reading/writing */
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #ifdef CONFIG_ENV_IS_IN_FLASH
@@ -421,9 +421,9 @@ extern unsigned long offsetOfEnvironment;
 /*
  * NAND-FLASH stuff
  */
-#define CFG_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define NAND_MAX_CHIPS		1
-#define CFG_NAND_BASE		0x77D00000
+#define CONFIG_SYS_NAND_BASE		0x77D00000
 
 
 #define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
@@ -439,55 +439,55 @@ extern unsigned long offsetOfEnvironment;
  *
  */
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE
 #define FLASH_BASE1_PRELIM	0
 
 /*-----------------------------------------------------------------------
  * Some informations about the internal SRAM (OCM=On Chip Memory)
  *
- * CFG_OCM_DATA_ADDR -> location
- * CFG_OCM_DATA_SIZE -> size
+ * CONFIG_SYS_OCM_DATA_ADDR -> location
+ * CONFIG_SYS_OCM_DATA_SIZE -> size
 */
 
-#define CFG_TEMP_STACK_OCM	1
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM):
  * - we are using the internal 4k SRAM, so we don't need data cache mapping
- * - internal SRAM (OCM=On Chip Memory) is placed to CFG_OCM_DATA_ADDR
+ * - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR
  * - Stackpointer will be located to
- *   (CFG_INIT_RAM_ADDR&0xFFFF0000) | (CFG_INIT_SP_OFFSET&0x0000FFFF)
+ *   (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF)
  *   in cpu/ppc4xx/start.S
  */
 
-#undef CFG_INIT_DCACHE_CS
+#undef CONFIG_SYS_INIT_DCACHE_CS
 /* Where the internal SRAM starts */
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR
 /* Where the internal SRAM ends (only offset) */
-#define CFG_INIT_RAM_END	0x0F00
+#define CONFIG_SYS_INIT_RAM_END	0x0F00
 
 /*
 
- CFG_INIT_RAM_ADDR ------> ------------ lower address
+ CONFIG_SYS_INIT_RAM_ADDR ------> ------------ lower address
 			   |	      |
 			   |  ^       |
 			   |  |       |
 			   |  | Stack |
- CFG_GBL_DATA_OFFSET ----> ------------
+ CONFIG_SYS_GBL_DATA_OFFSET ----> ------------
 			   |	      |
 			   | 64 Bytes |
 			   |	      |
- CFG_INIT_RAM_END  ------> ------------ higher address
+ CONFIG_SYS_INIT_RAM_END  ------> ------------ higher address
   (offset only)
 
 */
 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_SIZE     64
-#define CFG_GBL_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_SIZE     64
+#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 /* Initial value of the stack pointern in internal SRAM */
-#define CFG_INIT_SP_OFFSET    CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Internal Definitions
@@ -504,31 +504,31 @@ extern unsigned long offsetOfEnvironment;
 /* This chip select accesses the boot device */
 /* It depends on boot select switch if this device is 16 or 8 bit */
 
-#undef CFG_EBC_PB0AP
-#undef CFG_EBC_PB0CR
+#undef CONFIG_SYS_EBC_PB0AP
+#undef CONFIG_SYS_EBC_PB0CR
 
-#undef CFG_EBC_PB1AP
-#undef CFG_EBC_PB1CR
+#undef CONFIG_SYS_EBC_PB1AP
+#undef CONFIG_SYS_EBC_PB1CR
 
-#undef CFG_EBC_PB2AP
-#undef CFG_EBC_PB2CR
+#undef CONFIG_SYS_EBC_PB2AP
+#undef CONFIG_SYS_EBC_PB2CR
 
-#undef CFG_EBC_PB3AP
-#undef CFG_EBC_PB3CR
+#undef CONFIG_SYS_EBC_PB3AP
+#undef CONFIG_SYS_EBC_PB3CR
 
-#undef CFG_EBC_PB4AP
-#undef CFG_EBC_PB4CR
+#undef CONFIG_SYS_EBC_PB4AP
+#undef CONFIG_SYS_EBC_PB4CR
 
-#undef CFG_EBC_PB5AP
-#undef CFG_EBC_PB5CR
+#undef CONFIG_SYS_EBC_PB5AP
+#undef CONFIG_SYS_EBC_PB5CR
 
-#undef CFG_EBC_PB6AP
-#undef CFG_EBC_PB6CR
+#undef CONFIG_SYS_EBC_PB6AP
+#undef CONFIG_SYS_EBC_PB6CR
 
-#undef CFG_EBC_PB7AP
-#undef CFG_EBC_PB7CR
+#undef CONFIG_SYS_EBC_PB7AP
+#undef CONFIG_SYS_EBC_PB7CR
 
-#define CFG_EBC_CFG    0xb84ef000
+#define CONFIG_SYS_EBC_CFG    0xb84ef000
 
 #define CONFIG_SDRAM_BANK0	/* use the standard SDRAM initialization */
 #undef CONFIG_SPD_EEPROM
@@ -543,15 +543,15 @@ extern unsigned long offsetOfEnvironment;
  * External peripheral base address
  ***********************************************************************/
 
-#define CFG_ISA_MEM_BASE_ADDRESS 0x78000000
+#define CONFIG_SYS_ISA_MEM_BASE_ADDRESS 0x78000000
 /*
  Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu.
  Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die
  das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen
  auf ISA- und PCI-Zyklen)
  */
-#define CFG_ISA_IO_BASE_ADDRESS  0xE8000000
-/*#define CFG_ISA_IO_BASE_ADDRESS  0x79000000 */
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS  0xE8000000
+/*#define CONFIG_SYS_ISA_IO_BASE_ADDRESS  0x79000000 */
 
 /************************************************************
  * Video support