diff options
| author | Thierry Reding | 2019-03-15 16:32:33 +0100 |
|---|---|---|
| committer | Tom Rini | 2019-04-23 17:57:23 -0400 |
| commit | aec4298ccb337106fd0115b91d846a022fdf301d (patch) | |
| tree | cdafe7302277ab1454ae4f840efc52c23c0afc3c /include/pci.h | |
| parent | d94d9aa675b2d8a50b8b66b07f3210d291f7eaff (diff) | |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS
If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added
as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale
with the number of DRAM banks, otherwise we will end up with too little
space in the hose->regions array to store all system memory regions.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/pci.h')
| -rw-r--r-- | include/pci.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/include/pci.h b/include/pci.h index 5fb212cab1a..9668503f093 100644 --- a/include/pci.h +++ b/include/pci.h @@ -545,7 +545,11 @@ extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *); -#define MAX_PCI_REGIONS 7 +#ifdef CONFIG_NR_DRAM_BANKS +#define MAX_PCI_REGIONS (CONFIG_NR_DRAM_BANKS + 7) +#else +#define MAX_PCI_REGIONS 7 +#endif #define INDIRECT_TYPE_NO_PCIE_LINK 1 |