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authorTakahiro Kuwano2023-12-22 14:46:01 +0900
committerJagan Teki2024-01-29 19:34:17 +0530
commit9901312e09af0bf51e35628cd8547637c103ed6c (patch)
tree839d3ffe060c8761f5500560b18c28870c726121 /include
parent9768d7c7ecad722bdfdad72fa10a0e8a788c7a31 (diff)
mtd: spi-nor-core: Use CLPEF(0x82) as alternative to CLSR(0x30) for S25 and S28
Infineon(Cypress) S28Hx-T family does not support legacy CLSR(0x30) opcode. Instead, it supports CLPEF(0x82) which has the same functionality as CLSR. spansion_sr_ready() is for multi-die package parts including S28HS02GT, so we need to use CLPEF instead of CLSR. This change does not affect to S25x02GT which uses spansion_sr_ready() as S25Hx-T family also supports CLPEF(0x82) as well as CLSR(0x30). Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/mtd/spi-nor.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index ebe38306a1d..8a94e120372 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -180,6 +180,7 @@
/* For Cypress flash. */
#define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
#define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
+#define SPINOR_OP_CYPRESS_CLPEF 0x82 /* Clear P/E err flag */
#define SPINOR_REG_CYPRESS_ARCFN 0x00000006
#define SPINOR_REG_CYPRESS_STR1V 0x00800000
#define SPINOR_REG_CYPRESS_CFR1V 0x00800002