diff options
| author | Aaron Williams | 2020-06-30 12:08:56 +0200 |
|---|---|---|
| committer | Daniel Schwierzeck | 2020-07-18 15:47:50 +0200 |
| commit | 0dc4ab9c43ff6a235b4c0c5295a1a9747ea684c9 (patch) | |
| tree | 27c647c9fbc99170c2761f28d434e8431f668304 /scripts | |
| parent | 59aea37abf6bf6d5119a9e2f0237b26bf820b285 (diff) | |
mips: octeon: Initial minimal support for the Marvell Octeon SoC
This patch adds very basic support for the Octeon III SoCs. Only
CFI parallel NOR flash and UART is supported for now.
Please note that the basic Octeon port does not include the DDR3/4
initialization yet. This will be added in some follow-up patches
later. To still use U-Boot on with this port, the L2 cache (4MiB on
Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the
prompt on such boards.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'scripts')
| -rw-r--r-- | scripts/config_whitelist.txt | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 1602b05f077..2ec7642583d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -228,7 +228,6 @@ CONFIG_CPLD_BR_PRELIM CONFIG_CPLD_OR_PRELIM CONFIG_CPM2 CONFIG_CPU_ARMV8 -CONFIG_CPU_CAVIUM_OCTEON CONFIG_CPU_FREQ_HZ CONFIG_CPU_HAS_LLSC CONFIG_CPU_HAS_PREFETCH |