diff options
27 files changed, 393 insertions, 1050 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7265e554257..a4d95c8306b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -840,10 +840,7 @@ dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb dtb-$(CONFIG_MX6SX) += \ imx6sx-sabreauto.dtb \ imx6sx-sdb.dtb \ - imx6sx-softing-vining-2000.dtb \ - imx6sx-udoo-neo-basic.dtb \ - imx6sx-udoo-neo-extended.dtb \ - imx6sx-udoo-neo-full.dtb + imx6sx-softing-vining-2000.dtb dtb-$(CONFIG_MX6UL) += \ imx6ul-geam.dtb \ diff --git a/arch/arm/dts/imx6sx-udoo-neo-basic-u-boot.dtsi b/arch/arm/dts/imx6sx-udoo-neo-basic-u-boot.dtsi index b5e1f2b9a16..7f5a6424bac 100644 --- a/arch/arm/dts/imx6sx-udoo-neo-basic-u-boot.dtsi +++ b/arch/arm/dts/imx6sx-udoo-neo-basic-u-boot.dtsi @@ -1,5 +1,13 @@ // SPDX-License-Identifier: GPL-2.0+ +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; +}; + &soc { bootph-all; }; @@ -15,3 +23,7 @@ &uart1 { bootph-all; }; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx6sx-udoo-neo-basic.dts b/arch/arm/dts/imx6sx-udoo-neo-basic.dts deleted file mode 100644 index 205ea26484e..00000000000 --- a/arch/arm/dts/imx6sx-udoo-neo-basic.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -/dts-v1/; - -#include "imx6sx-udoo-neo.dtsi" - -/ { - model = "UDOO Neo Basic"; - compatible = "udoo,neobasic", "fsl,imx6sx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; -}; - -&fec1 { - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; diff --git a/arch/arm/dts/imx6sx-udoo-neo-extended.dts b/arch/arm/dts/imx6sx-udoo-neo-extended.dts deleted file mode 100644 index 5817b498539..00000000000 --- a/arch/arm/dts/imx6sx-udoo-neo-extended.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -/dts-v1/; - -#include "imx6sx-udoo-neo.dtsi" - -/ { - model = "UDOO Neo Extended"; - compatible = "udoo,neoextended", "fsl,imx6sx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&i2c4 { /* Onboard Motion sensors */ - status = "okay"; -}; - -&uart3 { /* Bluetooth */ - status = "okay"; -}; diff --git a/arch/arm/dts/imx6sx-udoo-neo-full.dts b/arch/arm/dts/imx6sx-udoo-neo-full.dts deleted file mode 100644 index 96f4d89848a..00000000000 --- a/arch/arm/dts/imx6sx-udoo-neo-full.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -/dts-v1/; - -#include "imx6sx-udoo-neo.dtsi" - -/ { - model = "UDOO Neo Full"; - compatible = "udoo,neofull", "fsl,imx6sx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&fec1 { - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&i2c4 { /* Onboard Motion sensors */ - status = "okay"; -}; - -&uart3 { /* Bluetooth */ - status = "okay"; -}; diff --git a/arch/arm/dts/imx6sx-udoo-neo.dtsi b/arch/arm/dts/imx6sx-udoo-neo.dtsi deleted file mode 100644 index c84ea1fac5e..00000000000 --- a/arch/arm/dts/imx6sx-udoo-neo.dtsi +++ /dev/null @@ -1,482 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -#include "imx6sx.dtsi" - -/ { - compatible = "fsl,imx6sx"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - red { - label = "udoo-neo:red:mmc"; - gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - - orange { - label = "udoo-neo:orange:user"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; - - reg_sdio_pwr: regulator-sdio-pwr { - compatible = "regulator-fixed"; - gpio = <&gpio6 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-name = "SDIO_PWR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_otg1_reg>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_otg2_reg>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan: regulator-wlan { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-reset-duration = <10>; - phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <100000>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { /* Brick snap in sensors connector */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <100000>; - status = "okay"; - - hdmi-transmitter@70 { - compatible = "nxp,tda998x"; - reg = <0x70>; - interrupts-extended = <&gpio3 27 IRQ_TYPE_LEVEL_LOW>; - - ports { - port { - hdmi: endpoint { - remote-endpoint = <&lcdc>; - }; - }; - }; - }; -}; - -&i2c4 { /* Onboard Motion sensors */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clock-frequency = <100000>; - status = "disabled"; -}; - -&lcdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - status = "okay"; - - port { - lcdc: endpoint { - remote-endpoint = <&hdmi>; - }; - }; -}; - -&iomuxc { - pinctrl_bt_reg: btreggrp { - fsl,pins = - <MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x15059>; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = - <MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0xa0b1>, - <MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1>, - <MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1>, - <MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1>, - <MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1>, - <MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1>, - - <MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x3081>, - <MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x3081>, - <MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081>, - <MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081>, - <MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081>, - <MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x3081>, - - <MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91>; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = - <MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1>, - <MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1>; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = - <MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1>, - <MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1>; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = - <MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1>, - <MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1>; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = - <MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x4001b8b1>, - <MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x4001b8b1>; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 - MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 - MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 - MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 - MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 - MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 - MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 - MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 - MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 - MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 - MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 - MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 - MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 - MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 - MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 - MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 - MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 - MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 - MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 - MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 - MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 - MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 - MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 - MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 - MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 - MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 - MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = - <MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1>, - <MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1>; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = - <MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1>, - <MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1>; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = - <MX6SX_PAD_SD3_DATA4__UART3_DCE_RX 0x13059>, - <MX6SX_PAD_SD3_DATA5__UART3_DCE_TX 0x13059>, - <MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x13059>, - <MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x13059>; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = - <MX6SX_PAD_SD4_DATA4__UART5_DCE_RX 0x1b0b1>, - <MX6SX_PAD_SD4_DATA5__UART5_DCE_TX 0x1b0b1>; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = - <MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x1b0b1>, - <MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x1b0b1>, - <MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x1b0b1>, - <MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x1b0b1>, - <MX6SX_PAD_CSI_DATA04__UART6_DCE_RX 0x1b0b1>, - <MX6SX_PAD_CSI_DATA05__UART6_DCE_TX 0x1b0b1>, - <MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS 0x1b0b1>, - <MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS 0x1b0b1>; - }; - - pinctrl_otg1_reg: otg1grp { - fsl,pins = - <MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0>; - }; - - pinctrl_otg2_reg: otg2grp { - fsl,pins = - <MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x10b0>; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = - <MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059>, - <MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x10b0>; - }; - - pinctrl_usb_otg2: usbot2ggrp { - fsl,pins = - <MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x10b0>; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = - <MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059>, - <MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059>, - <MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059>, - <MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059>, - <MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059>, - <MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059>, - <MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059>; /* CD */ - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = - <MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x15059>, - <MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x13059>, - <MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17069>, - <MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17069>, - <MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17069>, - <MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17069>, - <MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17069>, - <MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10069>, - <MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x10059>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* Cortex-M4 serial */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "disabled"; -}; - -&uart3 { /* Bluetooth - only on Extended/Full versions */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "disabled"; - - bluetooth { - compatible = "ti,wl1831-st"; - enable-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_reg>; - max-speed = <921600>; - }; -}; - -/* Arduino serial */ -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "disabled"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - uart-has-rtscts; - status = "disabled"; -}; - -&usbotg1 { /* J2 micro USB port */ - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - status = "okay"; -}; - -&usbotg2 { /* J3 host USB port */ - vbus-supply = <®_usb_otg2_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg2>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_sdio_pwr>; - bus-width = <4>; - cd-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&usdhc3 { /* Wi-Fi */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - non-removable; - vmmc-supply = <®_wlan>; - cap-power-off-card; - wakeup-source; - keep-power-in-suspend; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1831"; - reg = <2>; - interrupt-parent = <&gpio2>; - interrupts = <16 IRQ_TYPE_EDGE_RISING>; - ref-clock-frequency = <38400000>; - tcxo-clock-frequency = <26000000>; - }; -}; diff --git a/arch/arm/dts/imx93-u-boot.dtsi b/arch/arm/dts/imx93-u-boot.dtsi index 289aba17584..b2b3d57318f 100644 --- a/arch/arm/dts/imx93-u-boot.dtsi +++ b/arch/arm/dts/imx93-u-boot.dtsi @@ -9,6 +9,14 @@ }; }; +&A55_0 { + clocks = <&clk IMX93_CLK_ARM_PLL>; +}; + +&A55_1 { + clocks = <&clk IMX93_CLK_ARM_PLL>; +}; + &binman { u-boot-spl-ddr { align = <4>; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 7800553ae8d..bee9d5f4877 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -636,6 +636,7 @@ config TARGET_UDOO_NEO select DM_THERMAL select SUPPORT_SPL imply CMD_DM + imply OF_UPSTREAM config TARGET_SOFTING_VINING_2000 bool "Softing VIN|ING 2000" diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 2b0cb2361c4..b85fd806cba 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -20,7 +20,6 @@ #include <linux/errno.h> #include <asm/gpio.h> #include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/sata.h> #include <asm/mach-imx/spi.h> #include <asm/mach-imx/boot_mode.h> @@ -56,10 +55,6 @@ DECLARE_GLOBAL_DATA_PTR; #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - #define RGB_PAD_CTRL PAD_CTL_DSE_120ohm #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ @@ -72,53 +67,11 @@ DECLARE_GLOBAL_DATA_PTR; #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) -/* Prevent compiler error if gpio number 08 or 09 is used */ -#define not_octal(gp) ((((0x##gp >> 4) & 0xf) * 10) + ((0x##gp & 0xf))) - -#define _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \ - sda_pad, sda_bank, sda_gp, pad_ctrl, join_io) { \ - .scl = { \ - .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##scl_pad##__##i2cnum##_SCL,\ - pad_ctrl), \ - .gpio_mode = NEW_PAD_CTRL( \ - cpu##_PAD_##scl_pad##__GPIO##scl_bank##join_io##scl_gp,\ - pad_ctrl), \ - .gp = IMX_GPIO_NR(scl_bank, not_octal(scl_gp)) \ - }, \ - .sda = { \ - .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##sda_pad##__##i2cnum##_SDA,\ - pad_ctrl), \ - .gpio_mode = NEW_PAD_CTRL( \ - cpu##_PAD_##sda_pad##__GPIO##sda_bank##join_io##sda_gp,\ - pad_ctrl), \ - .gp = IMX_GPIO_NR(sda_bank, not_octal(sda_gp)) \ - } \ -} - -#define I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \ - sda_pad, sda_bank, sda_gp, pad_ctrl) \ - _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \ - sda_pad, sda_bank, sda_gp, pad_ctrl, _IO) - #if defined(CONFIG_MX6QDL) -#define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp, \ - sda_pad, sda_bank, sda_gp, pad_ctrl) \ - I2C_PADS_INFO_CPU(MX6Q, i2cnum, scl_pad, scl_bank, scl_gp, \ - sda_pad, sda_bank, sda_gp, pad_ctrl), \ - I2C_PADS_INFO_CPU(MX6DL, i2cnum, scl_pad, scl_bank, scl_gp, \ - sda_pad, sda_bank, sda_gp, pad_ctrl) -#define I2C_PADS_INFO_ENTRY_SPACING 2 - #define IOMUX_PAD_CTRL(name, pad_ctrl) \ NEW_PAD_CTRL(MX6Q_PAD_##name, pad_ctrl), \ NEW_PAD_CTRL(MX6DL_PAD_##name, pad_ctrl) #else -#define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp, \ - sda_pad, sda_bank, sda_gp, pad_ctrl) \ - I2C_PADS_INFO_CPU(MX6, i2cnum, scl_pad, scl_bank, scl_gp, \ - sda_pad, sda_bank, sda_gp, pad_ctrl) -#define I2C_PADS_INFO_ENTRY_SPACING 1 - #define IOMUX_PAD_CTRL(name, pad_ctrl) NEW_PAD_CTRL(MX6_PAD_##name, pad_ctrl) #endif @@ -139,18 +92,6 @@ static iomux_v3_cfg_t const uart2_pads[] = { IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL), }; -static struct i2c_pads_info i2c_pads[] = { - /* I2C1, SGTL5000 */ - I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL), - /* I2C2 Camera, MIPI */ - I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13, - I2C_PAD_CTRL), - /* I2C3, J15 - RGB connector */ - I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL), -}; - -#define I2C_BUS_CNT 3 - static iomux_v3_cfg_t const usdhc2_pads[] = { IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL), IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL), @@ -420,9 +361,11 @@ static void do_enable_hdmi(struct display_info_t const *dev) static int detect_i2c(struct display_info_t const *dev) { - return ((0 == i2c_set_bus_num(dev->bus)) - && - (0 == i2c_probe(dev->addr))); + struct udevice *udev = NULL; + int ret; + + ret = i2c_get_chip_for_busnum(dev->bus, dev->addr, 1, &udev); + return ret ? 0 : 1; } static void enable_lvds(struct display_info_t const *dev) @@ -831,15 +774,7 @@ int overwrite_console(void) int board_init(void) { struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - struct i2c_pads_info *p = i2c_pads; - int i; - int stride = 1; -#if defined(CONFIG_MX6QDL) - stride = 2; - if (!is_mx6dq() && !is_mx6dqp()) - p += 1; -#endif clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_OTG_ID_MASK, IOMUXC_GPR1_OTG_ID_GPIO1); @@ -853,10 +788,6 @@ int board_init(void) setup_spi(); #endif SETUP_IOMUX_PADS(usdhc2_pads); - for (i = 0; i < I2C_BUS_CNT; i++) { - setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, p); - p += stride; - } #ifdef CONFIG_SATA setup_sata(); diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c index 896350140d6..cf3368c253b 100644 --- a/board/embest/mx6boards/mx6boards.c +++ b/board/embest/mx6boards/mx6boards.c @@ -25,7 +25,6 @@ #include <asm/gpio.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/spi.h> #include <asm/mach-imx/video.h> #include <i2c.h> @@ -61,10 +60,6 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) @@ -148,57 +143,6 @@ static void setup_spi(void) } #endif -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gp = IMX_GPIO_NR(5, 27) - }, - .sda = { - .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gp = IMX_GPIO_NR(5, 26) - } -}; - -struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gp = IMX_GPIO_NR(4, 13) - } -}; - -struct i2c_pads_info i2c_pad_info3 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gp = IMX_GPIO_NR(1, 5) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gp = IMX_GPIO_NR(1, 6) - } -}; - iomux_v3_cfg_t const tft_pads_riot[] = { /* LCD_PWR_EN */ MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -258,8 +202,11 @@ static void do_enable_hdmi(struct display_info_t const *dev) static int detect_i2c(struct display_info_t const *dev) { - return (0 == i2c_set_bus_num(dev->bus)) && - (0 == i2c_probe(dev->addr)); + struct udevice *udev = NULL; + int ret; + + ret = i2c_get_chip_for_busnum(dev->bus, dev->addr, 1, &udev); + return ret ? 0 : 1; } struct display_info_t const displays[] = {{ @@ -400,12 +347,7 @@ int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */ - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - /* i2c2 : HDMI EDID */ - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - /* i2c3 : LVDS, Expansion connector */ - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); + #ifdef CONFIG_MXC_SPI setup_spi(); #endif diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c index b435b721e53..4cf214bf17c 100644 --- a/board/udoo/neo/neo.c +++ b/board/udoo/neo/neo.c @@ -57,9 +57,6 @@ enum { #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST) -#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm) - #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) @@ -113,10 +110,6 @@ static iomux_v3_cfg_t const phy_control_pads[] = { MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), }; -static iomux_v3_cfg_t const wdog_b_pad = { - MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - static iomux_v3_cfg_t const peri_3v3_pads[] = { MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), }; @@ -143,20 +136,28 @@ static int setup_fec(void) return enable_fec_anatop_clock(0, ENET_25MHZ); } +static char *board_string(int type) +{ + switch (type) { + case UDOO_NEO_TYPE_BASIC: + return "BASIC"; + case UDOO_NEO_TYPE_BASIC_KS: + return "BASICKS"; + case UDOO_NEO_TYPE_FULL: + return "FULL"; + case UDOO_NEO_TYPE_EXTENDED: + return "EXTENDED"; + } + return "UNDEFINED"; +} + int board_init(void) { + int *board_type = (int *)OCRAM_START; + /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - /* - * Because kernel set WDOG_B mux before pad with the commone pinctrl - * framwork now and wdog reset will be triggered once set WDOG_B mux - * with default pad setting, we set pad setting here to workaround this. - * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set - * as GPIO mux firstly here to workaround it. - */ - imx_iomux_v3_setup_pad(wdog_b_pad); - /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, ARRAY_SIZE(peri_3v3_pads)); @@ -165,6 +166,8 @@ int board_init(void) gpio_request(IMX_GPIO_NR(4, 16), "ncp692"); gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); + printf("Board: UDOO Neo %s\n", board_string(*board_type)); + setup_fec(); return 0; @@ -195,30 +198,6 @@ int board_mmc_init(struct bd_info *bis) return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); } -static char *board_string(int type) -{ - switch (type) { - case UDOO_NEO_TYPE_BASIC: - return "BASIC"; - case UDOO_NEO_TYPE_BASIC_KS: - return "BASICKS"; - case UDOO_NEO_TYPE_FULL: - return "FULL"; - case UDOO_NEO_TYPE_EXTENDED: - return "EXTENDED"; - } - return "UNDEFINED"; -} - -/* Override the default implementation, DT model is not accurate */ -int checkboard(void) -{ - int *board_type = (int *)OCRAM_START; - - printf("Board: UDOO Neo %s\n", board_string(*board_type)); - return 0; -} - int board_late_init(void) { int *board_type = (int *)OCRAM_START; diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index 12d96b674ca..f295ecfe4b7 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -90,6 +90,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_CONS_INDEX=4 +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index 8325aaa1c9d..198fec2cb2c 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -10,9 +10,6 @@ CONFIG_ENV_SECT_SIZE=0x2000 CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q.cfg" CONFIG_MX6Q=y CONFIG_TARGET_EMBESTMX6BOARDS=y -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-marsboard" CONFIG_DISTRO_DEFAULTS=y @@ -37,7 +34,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y @@ -50,6 +47,7 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index ae9d1fa2447..bb830c429d0 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -10,9 +10,6 @@ CONFIG_ENV_OFFSET=0xC0000 CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q.cfg" CONFIG_MX6Q=y CONFIG_TARGET_NITROGEN6X=y -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DDR_MB=1024 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabrelite" @@ -55,7 +52,7 @@ CONFIG_DWC_AHSATA=y CONFIG_LBA48=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -68,6 +65,8 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index 3ce26da1e77..7060d3cf961 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -11,9 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x2000 CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6dl2g.cfg" CONFIG_MX6DL=y CONFIG_TARGET_NITROGEN6X=y -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DDR_MB=2048 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" @@ -61,7 +58,7 @@ CONFIG_NETCONSOLE=y CONFIG_BOUNCE_BUFFER=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -74,6 +71,8 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index 6a0f48a73c6..c2566c96aba 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -11,9 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x2000 CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6dl.cfg" CONFIG_MX6DL=y CONFIG_TARGET_NITROGEN6X=y -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DDR_MB=1024 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" @@ -61,7 +58,7 @@ CONFIG_NETCONSOLE=y CONFIG_BOUNCE_BUFFER=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -74,6 +71,8 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 991311e7b6b..07800eff08a 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -11,9 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x2000 CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q2g.cfg" CONFIG_MX6Q=y CONFIG_TARGET_NITROGEN6X=y -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DDR_MB=2048 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-nitrogen6x" @@ -64,7 +61,7 @@ CONFIG_DWC_AHSATA=y CONFIG_LBA48=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -77,6 +74,8 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index 72085fce630..c5e6ce52858 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -11,9 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x2000 CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q.cfg" CONFIG_MX6Q=y CONFIG_TARGET_NITROGEN6X=y -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DDR_MB=1024 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-nitrogen6x" @@ -64,7 +61,7 @@ CONFIG_DWC_AHSATA=y CONFIG_LBA48=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -77,6 +74,8 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index b31182c1e34..e91c19d30e9 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -11,9 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x2000 CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6s1g.cfg" CONFIG_MX6S=y CONFIG_TARGET_NITROGEN6X=y -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DDR_MB=1024 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" @@ -61,7 +58,7 @@ CONFIG_NETCONSOLE=y CONFIG_BOUNCE_BUFFER=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -74,6 +71,8 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index 4928f9c4495..b8b410c2cfe 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -11,9 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x2000 CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6s.cfg" CONFIG_MX6S=y CONFIG_TARGET_NITROGEN6X=y -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DDR_MB=512 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" @@ -61,7 +58,7 @@ CONFIG_NETCONSOLE=y CONFIG_BOUNCE_BUFFER=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -74,6 +71,8 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 1b303e738bb..a1e806be421 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -12,9 +12,6 @@ CONFIG_ENV_OFFSET=0x60000 CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6s1g.cfg" CONFIG_MX6S=y CONFIG_TARGET_EMBESTMX6BOARDS=y -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-riotboard" CONFIG_SPL_TEXT_BASE=0x00908000 @@ -53,7 +50,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y @@ -67,6 +64,7 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig index 4986b4c2626..0c76b005557 100644 --- a/configs/udoo_neo_defconfig +++ b/configs/udoo_neo_defconfig @@ -11,7 +11,7 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_MX6SX=y CONFIG_TARGET_UDOO_NEO=y CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx6sx-udoo-neo-basic" +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6sx-udoo-neo-basic" CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SYS_MONITOR_LEN=409600 CONFIG_SPL_MMC=y @@ -19,9 +19,13 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set +CONFIG_LTO=y +CONFIG_HAS_BOARD_SIZE_LIMIT=y +CONFIG_BOARD_SIZE_LIMIT=523264 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" CONFIG_SYS_PBSIZE=532 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y @@ -61,5 +65,8 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_ANATOP=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_IMX_WATCHDOG=y diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index ba9923d8f6f..df9f0285e1e 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -128,6 +128,10 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6)); clk_dm(IMX6QDL_CLK_I2C2, imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8)); + clk_dm(IMX6QDL_CLK_I2C3, + imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10)); + clk_dm(IMX6QDL_CLK_PWM1, + imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16)); clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2("enet", "ipg", base + 0x6c, 10)); clk_dm(IMX6QDL_CLK_ENET_REF, diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 70e2e53bdea..e538f047b31 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -14,108 +14,137 @@ #include "clk.h" -static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", }; -static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; -static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; -static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; -static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", }; -static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; +static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", }; +static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; +static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; +static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; +static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", }; +static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; -static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", - "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; +static const char * const imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", + "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", + "audio_pll1_out", "sys_pll3_out", }; -static const char *imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", - "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", }; +static const char * const imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", + "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", + "audio_pll1_out", "video_pll1_out", }; #ifndef CONFIG_SPL_BUILD -static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", - "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; +static const char * const imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", + "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", + "video_pll1_out", "sys_pll3_out", }; -static const char *imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", - "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", }; +static const char * const imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", + "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", + "video_pll1_out", "clk_ext4", }; -static const char *imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4", "video_pll1_out", }; +static const char * const imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "video_pll1_out", }; -static const char *imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m", - "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", }; +static const char * const imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", + "sys_pll2_200m", "sys_pll2_500m", "video_pll1_out", + "audio_pll2_out", }; #endif -static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", - "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", }; +static const char * const imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", + "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll1_out", }; -static const char *imx8mm_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m", - "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; +static const char * const imx8mm_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; -static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", - "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; +static const char * const imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_out", "sys_pll1_100m", }; -static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", - "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; +static const char * const imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_out", "sys_pll1_100m", }; -static const char *imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; -static const char *imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; -static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; -static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; #if CONFIG_IS_ENABLED(PCIE_DW_IMX) -static const char *imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m", - "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", }; +static const char * const imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m", + "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m", + "sys_pll2_333m", "sys_pll3_out", }; -static const char *imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll2_500m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4", "sys_pll1_400m", }; +static const char * const imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll2_500m", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "sys_pll1_400m", }; -static const char *imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out", - "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", }; +static const char * const imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m", + "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m", + "sys_pll1_160m", "sys_pll1_200m", }; #endif #ifndef CONFIG_SPL_BUILD -static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; +static const char * const imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext1", + "sys_pll1_80m", "video_pll1_out", }; -static const char *imx8mm_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; +static const char * const imx8mm_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext1", + "sys_pll1_80m", "video_pll1_out", }; -static const char *imx8mm_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; +static const char * const imx8mm_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext2", + "sys_pll1_80m", "video_pll1_out", }; -static const char *imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; +static const char * const imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext2", + "sys_pll1_80m", "video_pll1_out", }; #endif -static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out", - "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; +static const char * const imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", + "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", + "sys_pll1_80m", "sys_pll2_166m", }; -static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", - "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", }; +static const char * const imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_clk", "sys_pll1_100m", }; #if CONFIG_IS_ENABLED(NXP_FSPI) -static const char *imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m", - "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", }; +static const char * const imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", + "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", + "sys_pll3_out", "sys_pll1_100m", }; #endif -static const char *imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", - "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; +static const char * const imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; -static const char *imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", - "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; +static const char * const imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; #if CONFIG_IS_ENABLED(DM_SPI) -static const char *imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", - "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; +static const char * const imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; -static const char *imx8mm_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", - "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; +static const char * const imx8mm_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; -static const char *imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", - "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; +static const char * const imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; #endif static int imx8mm_clk_probe(struct udevice *dev) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index ed9e16d7c18..8911e342f18 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -16,110 +16,132 @@ static u32 share_count_nand; -static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", }; -static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; -static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; -static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; -static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", }; -static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; +static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", }; +static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; +static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; +static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; +static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", }; +static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; -static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", - "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; +static const char * const imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", + "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", + "audio_pll1_out", "sys_pll3_out", }; -static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", - "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", }; +static const char * const imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", + "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", + "audio_pll1_out", "video_pll_out", }; -static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", - "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", }; +static const char * const imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", + "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", + "video_pll_out", "sys_pll3_out", }; #ifndef CONFIG_SPL_BUILD -static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", - "sys_pll1_160m", "audio_pll1_out", "video_pll_out", "clk_ext4", }; +static const char * const imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", + "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", + "video_pll_out", "clk_ext4", }; -static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4", "video_pll_out", }; +static const char * const imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "video_pll_out", }; -static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m", - "sys_pll2_500m", "audio_pll1_out", "video_pll_out", "audio_pll2_out", }; +static const char * const imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", + "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", + "video_pll_out", "audio_pll2_out", }; #endif -static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", - "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", }; +static const char * const imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", + "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll1_out", }; static const char * const imx8mn_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", - "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", - "clk_ext4", "audio_pll2_out", }; + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; -static const char *imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", - "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; +static const char * const imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_out", "sys_pll1_100m", }; -static const char *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", - "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; +static const char * const imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_out", "sys_pll1_100m", }; #if CONFIG_IS_ENABLED(DM_SPI) -static const char *imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", - "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", - "sys_pll2_250m", "audio_pll2_out", }; +static const char * const imx8mn_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; -static const char *imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", - "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", - "sys_pll2_250m", "audio_pll2_out", }; +static const char * const imx8mn_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; -static const char *imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", - "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", - "sys_pll2_250m", "audio_pll2_out", }; +static const char * const imx8mn_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; #endif -static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", + "audio_pll2_out", "sys_pll1_133m", }; -static const char *imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", + "audio_pll2_out", "sys_pll1_133m", }; -static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", + "audio_pll2_out", "sys_pll1_133m", }; -static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", + "audio_pll2_out", "sys_pll1_133m", }; #ifndef CONFIG_SPL_BUILD -static const char *imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; +static const char * const imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext1", + "sys_pll1_80m", "video_pll_out", }; -static const char *imx8mn_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; +static const char * const imx8mn_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext1", + "sys_pll1_80m", "video_pll_out", }; -static const char *imx8mn_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; +static const char * const imx8mn_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext2", + "sys_pll1_80m", "video_pll_out", }; -static const char *imx8mn_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; +static const char * const imx8mn_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext2", + "sys_pll1_80m", "video_pll_out", }; #endif -static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "m7_alt_pll", - "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; +static const char * const imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", + "m7_alt_pll", "sys_pll2_125m", "sys_pll3_out", + "sys_pll1_80m", "sys_pll2_166m", }; -static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", - "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", }; +static const char * const imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_clk", "sys_pll1_100m", }; -static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m", - "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", }; +static const char * const imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", + "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", + "sys_pll3_out", "sys_pll1_100m", }; -static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", +static const char * const imx8mn_nand_sels[] = {"clock-osc-24m", "sys_pll2_500m", "audio_pll1_out", "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll_out", }; static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", - "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", - "clk_ext3", "audio_pll2_out", }; + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", - "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", - "clk_ext3", "audio_pll2_out", }; + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; static int imx8mn_clk_probe(struct udevice *dev) { + struct clk osc_24m_clk; void __iomem *base; + int ret; base = (void *)ANATOP_BASE_ADDR; @@ -238,6 +260,11 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1)); + ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk); + if (ret) + return ret; + clk_dm(IMX8MN_CLK_24M, dev_get_clk_ptr(osc_24m_clk.dev)); + base = dev_read_addr_ptr(dev); if (!base) return -EINVAL; diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 1f498b6ba4e..6b18483c814 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -14,178 +14,178 @@ #include "clk.h" -static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", }; -static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; -static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; -static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; -static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", }; -static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; +static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", }; +static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; +static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; +static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; +static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", }; +static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; -static const char *imx8mp_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", - "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", - "audio_pll1_out", "sys_pll3_out", }; +static const char * const imx8mp_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", + "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", + "audio_pll1_out", "sys_pll3_out", }; -static const char *imx8mp_hsio_axi_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", - "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", - "clk_ext4", "audio_pll2_out", }; +static const char * const imx8mp_hsio_axi_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; -static const char *imx8mp_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m", "sys_pll1_800m", - "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "sys_pll1_100m",}; +static const char * const imx8mp_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m", "sys_pll1_800m", + "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "sys_pll1_100m",}; -static const char *imx8mp_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", - "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", - "video_pll1_out", "sys_pll3_out", }; +static const char * const imx8mp_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", + "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", + "video_pll1_out", "sys_pll3_out", }; -static const char *imx8mp_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", - "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", - "sys_pll2_250m", "audio_pll1_out", }; +static const char * const imx8mp_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", + "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll1_out", }; -static const char *imx8mp_noc_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out", - "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; +static const char * const imx8mp_noc_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; -static const char *imx8mp_noc_io_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out", - "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; +static const char * const imx8mp_noc_io_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; -static const char *imx8mp_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", - "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", - "audio_pll1_out", "video_pll1_out", }; +static const char * const imx8mp_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", + "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", + "audio_pll1_out", "video_pll1_out", }; -static const char *imx8mp_dram_alt_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll1_100m", - "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out", - "audio_pll1_out", "sys_pll1_266m", }; +static const char * const imx8mp_dram_alt_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll1_100m", + "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out", + "audio_pll1_out", "sys_pll1_266m", }; -static const char *imx8mp_dram_apb_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", - "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", - "sys_pll2_250m", "audio_pll2_out", }; +static const char * const imx8mp_dram_apb_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; static const char * const imx8mp_pcie_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", }; -static const char *imx8mp_i2c5_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", - "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mp_i2c5_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; -static const char *imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", - "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; -static const char *imx8mp_enet_qos_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", - "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", - "video_pll1_out", "clk_ext4", }; +static const char * const imx8mp_enet_qos_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", + "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", + "video_pll1_out", "clk_ext4", }; -static const char *imx8mp_enet_qos_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", - "clk_ext1", "clk_ext2", "clk_ext3", - "clk_ext4", "video_pll1_out", }; +static const char * const imx8mp_enet_qos_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "video_pll1_out", }; -static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", - "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", - "audio_pll2_out", "sys_pll1_100m", }; +static const char * const imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_out", "sys_pll1_100m", }; -static const char *imx8mp_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", - "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", - "audio_pll2_out", "sys_pll1_100m", }; +static const char * const imx8mp_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_out", "sys_pll1_100m", }; -static const char *imx8mp_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", - "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mp_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; -static const char *imx8mp_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", - "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mp_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; -static const char *imx8mp_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", - "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mp_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; -static const char *imx8mp_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", - "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mp_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; -static const char *imx8mp_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", - "sys_pll2_100m", "sys_pll3_out", "clk_ext2", - "clk_ext4", "audio_pll2_out", }; +static const char * const imx8mp_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; -static const char *imx8mp_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", - "sys_pll2_100m", "sys_pll3_out", "clk_ext2", - "clk_ext3", "audio_pll2_out", }; - -static const char *imx8mp_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", - "sys_pll2_100m", "sys_pll3_out", "clk_ext2", - "clk_ext4", "audio_pll2_out", }; +static const char * const imx8mp_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; -static const char *imx8mp_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", - "sys_pll2_100m", "sys_pll3_out", "clk_ext2", - "clk_ext3", "audio_pll2_out", }; +static const char * const imx8mp_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; -static const char *imx8mp_usb_core_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", - "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", +static const char * const imx8mp_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; -static const char *imx8mp_usb_phy_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", - "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", - "clk_ext3", "audio_pll2_out", }; +static const char * const imx8mp_usb_core_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char * const imx8mp_usb_phy_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; -static const char *imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", - "sys_pll2_100m", "sys_pll1_800m", - "sys_pll2_500m", "clk_ext4", "audio_pll2_out" }; +static const char * const imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll1_800m", + "sys_pll2_500m", "clk_ext4", "audio_pll2_out" }; -static const char *imx8mp_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", - "sys_pll1_40m", "sys_pll3_out", "clk_ext1", - "sys_pll1_80m", "video_pll1_out", }; +static const char * const imx8mp_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext1", + "sys_pll1_80m", "video_pll1_out", }; -static const char *imx8mp_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", - "sys_pll1_40m", "sys_pll3_out", "clk_ext1", - "sys_pll1_80m", "video_pll1_out", }; +static const char * const imx8mp_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext1", + "sys_pll1_80m", "video_pll1_out", }; -static const char *imx8mp_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", - "sys_pll1_40m", "sys_pll3_out", "clk_ext2", - "sys_pll1_80m", "video_pll1_out", }; +static const char * const imx8mp_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext2", + "sys_pll1_80m", "video_pll1_out", }; -static const char *imx8mp_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", - "sys_pll1_40m", "sys_pll3_out", "clk_ext2", - "sys_pll1_80m", "video_pll1_out", }; +static const char * const imx8mp_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext2", + "sys_pll1_80m", "video_pll1_out", }; -static const char *imx8mp_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mp_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char *imx8mp_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mp_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char *imx8mp_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mp_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char *imx8mp_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", - "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", - "sys_pll1_80m", "sys_pll2_166m" }; +static const char * const imx8mp_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", + "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", + "sys_pll1_80m", "sys_pll2_166m" }; -static const char *imx8mp_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", - "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", - "sys_pll3_out", "sys_pll1_100m", }; +static const char * const imx8mp_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", + "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", + "sys_pll3_out", "sys_pll1_100m", }; -static const char *imx8mp_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", - "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", - "audio_pll2_out", "sys_pll1_100m", }; +static const char * const imx8mp_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_out", "sys_pll1_100m", }; -static const char *imx8mp_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", - "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", - "video_pll1_out", "clk_ext4", }; +static const char * const imx8mp_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", + "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", + "video_pll1_out", "clk_ext4", }; -static const char *imx8mp_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", - "clk_ext1", "clk_ext2", "clk_ext3", - "clk_ext4", "video_pll1_out", }; +static const char * const imx8mp_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "video_pll1_out", }; -static const char *imx8mp_enet_phy_ref_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", - "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; +static const char * const imx8mp_enet_phy_ref_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", + "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; -static const char *imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; +static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; static int imx8mp_clk_probe(struct udevice *dev) { diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index c9c599d0762..c03d11dcdae 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -11,8 +11,6 @@ #include "mx6_common.h" -#define CFG_MXC_UART_BASE UART2_BASE - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_SYS_FSL_USDHC_NUM 2 |