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-rw-r--r--drivers/clk/qcom/clock-apq8016.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index 9de0ad5ed32..e6647f7c41d 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -103,20 +103,20 @@ static const struct bcr_regs uart2_regs = {
};
/* UART: 115200 */
-static int clk_init_uart(struct msm_clk_priv *priv)
+int apq8016_clk_init_uart(phys_addr_t base)
{
/* Enable AHB clock */
- clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
+ clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk);
/* 7372800 uart block clock @ GPLL0 */
- clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
+ clk_rcg_set_rate_mnd(base, &uart2_regs, 1, 144, 15625,
CFG_CLK_SRC_GPLL0, 16);
/* Vote for gpll0 clock */
- clk_enable_gpll0(priv->base, &gpll0_vote_clk);
+ clk_enable_gpll0(base, &gpll0_vote_clk);
/* Enable core clk */
- clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
+ clk_enable_cbc(base + BLSP1_UART2_APPS_CBCR);
return 0;
}
@@ -133,7 +133,7 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate)
return clk_init_sdc(priv, 1, rate);
break;
case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */
- return clk_init_uart(priv);
+ return apq8016_clk_init_uart(priv->base);
break;
default:
return 0;