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-rw-r--r--arch/arm/cpu/arm926ejs/spear/spl.c2
-rw-r--r--arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c2
-rw-r--r--arch/arm/cpu/armv8/spl_data.c4
3 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c
index 08b98a2d068..b5b9945a87f 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -22,7 +22,7 @@
* The BSS cannot be used for this purpose because it will be zeroed after
* having stored the pointer, so force the location to the data section.
*/
-u32 bootrom_stash_sp __attribute__((section(".data")));
+u32 bootrom_stash_sp __section(".data");
static void ddr_clock_init(void)
{
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
index 4a4b3c6f232..28a79452074 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -13,7 +13,7 @@
#include <fsl_immap.h>
#include "fsl_epu.h"
-#define __secure __attribute__((section("._secure.text")))
+#define __secure __section("._secure.text")
#define CCSR_GICD_CTLR 0x1000
#define CCSR_GICC_CTLR 0x2000
diff --git a/arch/arm/cpu/armv8/spl_data.c b/arch/arm/cpu/armv8/spl_data.c
index 8fd986a67a2..8f1231c86eb 100644
--- a/arch/arm/cpu/armv8/spl_data.c
+++ b/arch/arm/cpu/armv8/spl_data.c
@@ -6,8 +6,8 @@
#include <common.h>
#include <spl.h>
-char __data_save_start[0] __section(.__data_save_start);
-char __data_save_end[0] __section(.__data_save_end);
+char __data_save_start[0] __section(".__data_save_start");
+char __data_save_end[0] __section(".__data_save_end");
u32 cold_reboot_flag = 1;