diff options
Diffstat (limited to 'arch/arm/dts/zynqmp-zcu106-revA.dts')
| -rw-r--r-- | arch/arm/dts/zynqmp-zcu106-revA.dts | 28 |
1 files changed, 25 insertions, 3 deletions
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index f8019c592a7..b90ff61d241 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -150,6 +151,18 @@ #clock-cells = <0>; clock-frequency = <114285000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &can1 { @@ -965,12 +978,13 @@ &qspi { status = "okay"; - is-dual = <1>; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ @@ -1065,4 +1079,12 @@ phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 3>, <&psgtr 0 PHY_TYPE_DP 1 3>; + + ports { + port@5 { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; + }; + }; }; |