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-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.c8
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch38
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fdt.c31
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S9
-rw-r--r--arch/arm/dts/zynqmp-ep108.dts4
-rw-r--r--arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts9
-rw-r--r--arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts9
-rw-r--r--arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts9
-rw-r--r--arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts11
-rw-r--r--arch/arm/dts/zynqmp-zcu102-revA.dts20
-rw-r--r--arch/arm/dts/zynqmp.dtsi3
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/soc.h4
-rw-r--r--arch/arm/include/asm/arch-zynqmp/sys_proto.h1
-rw-r--r--arch/arm/lib/elf_arm_efi.lds11
-rw-r--r--arch/arm/mach-meson/eth.c4
16 files changed, 68 insertions, 75 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 73909952d0e..f2c35e32c64 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -773,7 +773,7 @@ config ARCH_ZYNQMP
select SUPPORT_SPL
select CLK
select SPL_BOARD_INIT if SPL
- select SPL_CLK
+ select SPL_CLK if SPL
select DM_USB if USB
imply FAT_WRITE
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d08262971e7..00d2564c799 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -538,8 +538,8 @@ int arch_early_init_r(void)
* erratum A009635 is valid only for LS2080A SoC and
* its personalitiesi
*/
- svr_dev_id = get_svr() >> 16;
- if (svr_dev_id == SVR_DEV_LS2080A)
+ svr_dev_id = get_svr();
+ if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
erratum_a009635();
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
@@ -604,8 +604,8 @@ int timer_init(void)
* For LS2080A SoC and its personalities, timer controller
* offset is different
*/
- svr_dev_id = get_svr() >> 16;
- if (svr_dev_id == SVR_DEV_LS2080A)
+ svr_dev_id = get_svr();
+ if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
index 025a1b7b2e0..6c98d99d0cc 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
@@ -154,8 +154,8 @@ Booting from NAND
-------------------
Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
The difference between NAND boot RCW image and NOR boot image is the PBI
-command sequence. Below is one example for PBI commands for QDS which uses
-NAND device with 2KB/page, block size 128KB.
+command sequence. Below is one example for PBI commands for LS2085AQDS which
+uses NAND device with 2KB/page, block size 128KB.
1) CCSR 4-byte write to 0x00e00404, data=0x00000000
2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
@@ -188,7 +188,7 @@ nand write <u-boot image in memory> 200000 <size of u-boot image>
With these two images in NAND device, the board can boot from NAND.
-Another example for RDB boards,
+Another example for LS2085ARDB boards,
1) CCSR 4-byte write to 0x00e00404, data=0x00000000
2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
@@ -201,6 +201,8 @@ nand write <u-boot image in memory> 80000 <size of u-boot image>
Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image
to match board NAND device with 4KB/page, block size 512KB.
+Note, LS2088A and LS1088A don't support booting from NAND.
+
Booting from SD/eMMC
-------------------
Booting from SD/eMMC requires two images, RCW and u-boot-with-spl.bin.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index cae59da803b..39ffe1ab4d5 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -42,6 +42,33 @@ void ft_fixup_cpu(void *blob)
int addr_cells;
u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
+ u32 mask = cpu_pos_mask();
+ int off_prev = -1;
+
+ off = fdt_path_offset(blob, "/cpus");
+ if (off < 0) {
+ puts("couldn't find /cpus node\n");
+ return;
+ }
+
+ fdt_support_default_count_cells(blob, off, &addr_cells, NULL);
+
+ off = fdt_node_offset_by_prop_value(blob, off_prev, "device_type",
+ "cpu", 4);
+ while (off != -FDT_ERR_NOTFOUND) {
+ reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
+ if (reg) {
+ core_id = fdt_read_number(reg, addr_cells);
+ if (!test_bit(id_to_core(core_id), &mask)) {
+ fdt_del_node(blob, off);
+ off = off_prev;
+ }
+ }
+ off_prev = off;
+ off = fdt_node_offset_by_prop_value(blob, off_prev,
+ "device_type", "cpu", 4);
+ }
+
#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
int node;
@@ -145,7 +172,7 @@ static void fdt_fixup_gic(void *blob)
val = gur_in32(&gur->svr);
- if (SVR_SOC_VER(val) != SVR_LS1043A) {
+ if (!IS_SVR_DEV(val, SVR_DEV(SVR_LS1043A))) {
align_64k = 1;
} else if (SVR_REV(val) != REV1_0) {
val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT);
@@ -327,7 +354,7 @@ static void fdt_fixup_msi(void *blob)
rev = gur_in32(&gur->svr);
- if (SVR_SOC_VER(rev) != SVR_LS1043A)
+ if (!IS_SVR_DEV(rev, SVR_DEV(SVR_LS1043A)))
return;
rev = SVR_REV(rev);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index fa93096c688..c089ceef326 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -37,9 +37,8 @@ ENTRY(get_gic_offset)
ldr x2, =DCFG_CCSR_SVR
ldr w2, [x2]
rev w2, w2
- mov w3, w2
- ands w3, w3, #SVR_WO_E << 8
- mov w4, #SVR_LS1043A << 8
+ lsr w3, w2, #16
+ ldr w4, =SVR_DEV(SVR_LS1043A)
cmp w3, w4
b.ne 1f
ands w2, w2, #0xff
@@ -92,7 +91,7 @@ ENTRY(lowlevel_init)
*/
bl get_svr
lsr w0, w0, #16
- ldr w1, =SVR_DEV_LS2080A
+ ldr w1, =SVR_DEV(SVR_LS2080A)
cmp w0, w1
b.eq 1f
@@ -224,7 +223,7 @@ ENTRY(lowlevel_init)
*/
bl get_svr
lsr w0, w0, #16
- ldr w1, =SVR_DEV_LS2080A
+ ldr w1, =SVR_DEV(SVR_LS2080A)
cmp w0, w1
b.eq 1f
diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts
index b0096f14b44..a16ffdc3f0c 100644
--- a/arch/arm/dts/zynqmp-ep108.dts
+++ b/arch/arm/dts/zynqmp-ep108.dts
@@ -65,7 +65,7 @@
status = "okay";
clock-frequency = <400000>;
eeprom@54 {
- compatible = "at,24c64";
+ compatible = "atmel,24c64";
reg = <0x54>;
};
};
@@ -74,7 +74,7 @@
status = "okay";
clock-frequency = <400000>;
eeprom@55 {
- compatible = "at,24c64";
+ compatible = "atmel,24c64";
reg = <0x55>;
};
};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 1f3c30277a4..04d82c4d2ec 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -43,16 +43,10 @@
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
- xlnx,overfetch; /* for testing purpose */
- xlnx,ratectrl = <0>; /* for testing purpose */
- xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
- xlnx,ratectrl = <100>; /* for testing purpose */
- xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
@@ -61,7 +55,6 @@
&fpd_dma_chan4 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
@@ -70,7 +63,6 @@
&fpd_dma_chan6 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
@@ -79,7 +71,6 @@
&fpd_dma_chan8 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&gem3 {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 87df36012ed..7dfe960135a 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -53,16 +53,10 @@
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
- xlnx,overfetch; /* for testing purpose */
- xlnx,ratectrl = <0>; /* for testing purpose */
- xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
- xlnx,ratectrl = <100>; /* for testing purpose */
- xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
@@ -71,7 +65,6 @@
&fpd_dma_chan4 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
@@ -80,7 +73,6 @@
&fpd_dma_chan6 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
@@ -89,7 +81,6 @@
&fpd_dma_chan8 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&gem2 {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index 799b87a04c1..648e3ba7993 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -55,16 +55,10 @@
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
- xlnx,overfetch; /* for testing purpose */
- xlnx,ratectrl = <0>; /* for testing purpose */
- xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
- xlnx,ratectrl = <100>; /* for testing purpose */
- xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
@@ -73,7 +67,6 @@
&fpd_dma_chan4 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
@@ -82,7 +75,6 @@
&fpd_dma_chan6 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
@@ -91,7 +83,6 @@
&fpd_dma_chan8 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&lpd_dma_chan1 {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index 6de8296b735..f3020a57600 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -28,7 +28,7 @@
};
chosen {
- bootargs = "earlycon=cdns,mmio,0xff000000,115200n8";
+ bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
@@ -41,16 +41,10 @@
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
- xlnx,overfetch; /* for testing purpose */
- xlnx,ratectrl = <0>; /* for testing purpose */
- xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
- xlnx,ratectrl = <100>; /* for testing purpose */
- xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
@@ -59,7 +53,6 @@
&fpd_dma_chan4 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
@@ -68,7 +61,6 @@
&fpd_dma_chan6 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
@@ -77,7 +69,6 @@
&fpd_dma_chan8 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&gem1 {
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index a2128ebfd8c..64a883b96e3 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -14,6 +14,7 @@
#include "zynqmp-clk.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU102 RevA";
@@ -80,16 +81,10 @@
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
- xlnx,overfetch; /* for testing purpose */
- xlnx,ratectrl = <0>; /* for testing purpose */
- xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
- xlnx,ratectrl = <100>; /* for testing purpose */
- xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
@@ -98,7 +93,6 @@
&fpd_dma_chan4 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
@@ -107,7 +101,6 @@
&fpd_dma_chan6 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
@@ -116,7 +109,6 @@
&fpd_dma_chan8 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&gem3 {
@@ -884,6 +876,8 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
};
/* SD1 with level shifter */
@@ -895,6 +889,10 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
xlnx,mio_bank = <1>;
};
+&serdes {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
pinctrl-names = "default";
@@ -917,6 +915,10 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
&dwc3_0 {
status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
+ maximum-speed = "super-speed";
};
&watchdog0 {
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 247344fcbb8..5bdab611645 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -261,7 +261,7 @@
method = "smc";
};
- firmware {
+ pmufw: firmware {
compatible = "xlnx,zynqmp-pm";
method = "smc";
interrupt-parent = <&gic>;
@@ -804,6 +804,7 @@
};
qspi: spi@ff0f0000 {
+ u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-qspi-1.0";
status = "disabled";
clock-names = "ref_clk", "pclk";
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 247f09e0f5f..09f64e7bd7e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -76,8 +76,6 @@ struct cpu_type {
#define SVR_LS2081A 0x870918
#define SVR_LS2041A 0x870914
-#define SVR_DEV_LS2080A 0x8701
-
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
#define SVR_REV(svr) (((svr) >> 0) & 0xff)
@@ -85,6 +83,8 @@ struct cpu_type {
#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
#define IS_SVR_REV(svr, maj, min) \
((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
+#define SVR_DEV(svr) ((svr) >> 8)
+#define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev))
/* ahci port register default value */
#define AHCI_PORT_PHY_1_CFG 0xa003fffe
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index f256c7d4a99..ad285686336 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -30,6 +30,7 @@ enum {
TCM_SPLIT,
};
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
unsigned int zynqmp_get_silicon_version(void);
void psu_init(void);
diff --git a/arch/arm/lib/elf_arm_efi.lds b/arch/arm/lib/elf_arm_efi.lds
index 59f66a1d4ab..15c9c5c6722 100644
--- a/arch/arm/lib/elf_arm_efi.lds
+++ b/arch/arm/lib/elf_arm_efi.lds
@@ -55,16 +55,13 @@ SECTIONS
.rel.data : { *(.rel.data) *(.rel.data*) }
_data_size = . - _etext;
- . = ALIGN(4096);
- .dynsym : { *(.dynsym) }
- . = ALIGN(4096);
- .dynstr : { *(.dynstr) }
- . = ALIGN(4096);
- .note.gnu.build-id : { *(.note.gnu.build-id) }
/DISCARD/ : {
*(.rel.reloc)
*(.eh_frame)
*(.note.GNU-stack)
+ *(.dynsym)
+ *(.dynstr)
+ *(.note.gnu.build-id)
+ *(.comment)
}
- .comment 0 : { *(.comment) }
}
diff --git a/arch/arm/mach-meson/eth.c b/arch/arm/mach-meson/eth.c
index 2debe93952c..8c6577b06f0 100644
--- a/arch/arm/mach-meson/eth.c
+++ b/arch/arm/mach-meson/eth.c
@@ -38,8 +38,8 @@ void meson_gx_eth_init(phy_interface_t mode, unsigned int flags)
/* Use GXL RMII Internal PHY */
if (IS_ENABLED(CONFIG_MESON_GXL) &&
(flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) {
- writel(GXBB_ETH_REG_2, 0x10110181);
- writel(GXBB_ETH_REG_3, 0xe40908ff);
+ writel(0x10110181, GXBB_ETH_REG_2);
+ writel(0xe40908ff, GXBB_ETH_REG_3);
}
break;
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-13 15:00:06 +0000