diff options
Diffstat (limited to 'arch/x86')
24 files changed, 3092 insertions, 101 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 7e7cb612d7c..f07567c81ac 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -242,6 +242,15 @@ config FSP_SYS_MALLOC_F_LEN help Additional size of malloc() pool before relocation. +config FSP_USE_UPD + bool + depends on HAVE_FSP + default y + help + Most FSPs use UPD data region for some FSP customization. But there + are still some FSPs that might not even have UPD. For such FSPs, + override this to n in their platform Kconfig files. + config ENABLE_MRC_CACHE bool "Enable MRC cache" depends on !EFI && !SYS_COREBOOT diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index a72d615f21f..d49b8d27371 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -121,16 +121,23 @@ const struct pch_azalia_config azalia_config = { }; /** - * Override the FSP's UPD. + * Override the FSP's configuration data. * If the device tree does not specify an integer setting, use the default * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file. */ -void update_fsp_upd(struct upd_region *fsp_upd) +void update_fsp_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf) { + struct upd_region *fsp_upd = &config->fsp_upd; struct memory_down_data *mem; const void *blob = gd->fdt_blob; int node; + /* Initialize runtime buffer for fsp_init() */ + rt_buf->common.stack_top = config->common.stack_top - 32; + rt_buf->common.boot_mode = config->common.boot_mode; + rt_buf->common.upd_data = &config->fsp_upd; + fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config; node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP); diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 56abd8fae35..1768a26a352 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -48,7 +48,6 @@ config DCACHE_RAM_MRC_VAR_SIZE config CPU_SPECIFIC_OPTIONS def_bool y select SMM_TSEG - select HAVE_INTEL_ME select X86_RAMTEST config SMM_TSEG_SIZE diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index 4334f5b3e5a..7917350bff2 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -20,8 +20,11 @@ #include <asm/mtrr.h> #include <asm/processor.h> #include <asm/sipi.h> +#include <asm/fw_cfg.h> #include <dm/device-internal.h> #include <dm/uclass-internal.h> +#include <dm/lists.h> +#include <dm/root.h> #include <linux/linkage.h> DECLARE_GLOBAL_DATA_PTR; @@ -104,7 +107,7 @@ static void ap_do_flight_plan(struct udevice *cpu) } } -static int find_cpu_by_apid_id(int apic_id, struct udevice **devp) +static int find_cpu_by_apic_id(int apic_id, struct udevice **devp) { struct udevice *dev; @@ -137,7 +140,7 @@ static void ap_init(unsigned int cpu_index) enable_lapic(); apic_id = lapicid(); - ret = find_cpu_by_apid_id(apic_id, &dev); + ret = find_cpu_by_apic_id(apic_id, &dev); if (ret) { debug("Unknown CPU apic_id %x\n", apic_id); goto done; @@ -210,7 +213,7 @@ static int save_bsp_msrs(char *start, int size) return msr_count; } -static int load_sipi_vector(atomic_t **ap_countp) +static int load_sipi_vector(atomic_t **ap_countp, int num_cpus) { struct sipi_params_16bit *params16; struct sipi_params *params; @@ -239,7 +242,7 @@ static int load_sipi_vector(atomic_t **ap_countp) params->idt_ptr = (uint32_t)x86_get_idt(); params->stack_size = CONFIG_AP_STACK_SIZE; - size = params->stack_size * CONFIG_MAX_CPUS; + size = params->stack_size * num_cpus; stack = memalign(size, 4096); if (!stack) return -ENOMEM; @@ -432,7 +435,7 @@ static int init_bsp(struct udevice **devp) lapic_setup(); apic_id = lapicid(); - ret = find_cpu_by_apid_id(apic_id, devp); + ret = find_cpu_by_apic_id(apic_id, devp); if (ret) { printf("Cannot find boot CPU, APIC ID %d\n", apic_id); return ret; @@ -441,6 +444,69 @@ static int init_bsp(struct udevice **devp) return 0; } +#ifdef CONFIG_QEMU +static int qemu_cpu_fixup(void) +{ + int ret; + int cpu_num; + int cpu_online; + struct udevice *dev, *pdev; + struct cpu_platdata *plat; + char *cpu; + + /* first we need to find '/cpus' */ + for (device_find_first_child(dm_root(), &pdev); + pdev; + device_find_next_child(&pdev)) { + if (!strcmp(pdev->name, "cpus")) + break; + } + if (!pdev) { + printf("unable to find cpus device\n"); + return -ENODEV; + } + + /* calculate cpus that are already bound */ + cpu_num = 0; + for (uclass_find_first_device(UCLASS_CPU, &dev); + dev; + uclass_find_next_device(&dev)) { + cpu_num++; + } + + /* get actual cpu number */ + cpu_online = qemu_fwcfg_online_cpus(); + if (cpu_online < 0) { + printf("unable to get online cpu number: %d\n", cpu_online); + return cpu_online; + } + + /* bind addtional cpus */ + dev = NULL; + for (; cpu_num < cpu_online; cpu_num++) { + /* + * allocate device name here as device_bind_driver() does + * not copy device name, 8 bytes are enough for + * sizeof("cpu@") + 3 digits cpu number + '\0' + */ + cpu = malloc(8); + if (!cpu) { + printf("unable to allocate device name\n"); + return -ENOMEM; + } + sprintf(cpu, "cpu@%d", cpu_num); + ret = device_bind_driver(pdev, "cpu_qemu", cpu, &dev); + if (ret) { + printf("binding cpu@%d failed: %d\n", cpu_num, ret); + return ret; + } + plat = dev_get_parent_platdata(dev); + plat->cpu_id = cpu_num; + } + return 0; +} +#endif + int mp_init(struct mp_params *p) { int num_aps; @@ -454,6 +520,12 @@ int mp_init(struct mp_params *p) if (ret) return ret; +#ifdef CONFIG_QEMU + ret = qemu_cpu_fixup(); + if (ret) + return ret; +#endif + ret = init_bsp(&cpu); if (ret) { debug("Cannot init boot CPU: err=%d\n", ret); @@ -483,7 +555,7 @@ int mp_init(struct mp_params *p) mp_info.records = p->flight_plan; /* Load the SIPI vector */ - ret = load_sipi_vector(&ap_count); + ret = load_sipi_vector(&ap_count, num_cpus); if (ap_count == NULL) return -1; diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile index 3f3958aa8e1..176ea54ae4e 100644 --- a/arch/x86/cpu/qemu/Makefile +++ b/arch/x86/cpu/qemu/Makefile @@ -7,5 +7,5 @@ ifndef CONFIG_EFI_STUB obj-y += car.o dram.o endif -obj-y += qemu.o +obj-y += cpu.o fw_cfg.o qemu.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c new file mode 100644 index 00000000000..a1b70c6bde7 --- /dev/null +++ b/arch/x86/cpu/qemu/cpu.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2015, Miao Yan <yanmiaobest@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <cpu.h> +#include <dm.h> +#include <errno.h> +#include <asm/cpu.h> +#include <asm/fw_cfg.h> + +DECLARE_GLOBAL_DATA_PTR; + +int cpu_qemu_get_desc(struct udevice *dev, char *buf, int size) +{ + if (size < CPU_MAX_NAME_LEN) + return -ENOSPC; + + cpu_get_name(buf); + + return 0; +} + +static int cpu_qemu_get_count(struct udevice *dev) +{ + return qemu_fwcfg_online_cpus(); +} + +static const struct cpu_ops cpu_qemu_ops = { + .get_desc = cpu_qemu_get_desc, + .get_count = cpu_qemu_get_count, +}; + +static const struct udevice_id cpu_qemu_ids[] = { + { .compatible = "cpu-qemu" }, + { } +}; + +U_BOOT_DRIVER(cpu_qemu_drv) = { + .name = "cpu_qemu", + .id = UCLASS_CPU, + .of_match = cpu_qemu_ids, + .ops = &cpu_qemu_ops, +}; diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/cpu/qemu/fw_cfg.c new file mode 100644 index 00000000000..05992145cf0 --- /dev/null +++ b/arch/x86/cpu/qemu/fw_cfg.c @@ -0,0 +1,283 @@ +/* + * (C) Copyright 2015 Miao Yan <yanmiaoebst@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <errno.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/fw_cfg.h> + +static bool fwcfg_present; +static bool fwcfg_dma_present; + +/* Read configuration item using fw_cfg PIO interface */ +static void qemu_fwcfg_read_entry_pio(uint16_t entry, + uint32_t size, void *address) +{ + uint32_t i = 0; + uint8_t *data = address; + + /* + * writting FW_CFG_INVALID will cause read operation to resume at + * last offset, otherwise read will start at offset 0 + */ + if (entry != FW_CFG_INVALID) + outw(entry, FW_CONTROL_PORT); + while (size--) + data[i++] = inb(FW_DATA_PORT); +} + +/* Read configuration item using fw_cfg DMA interface */ +static void qemu_fwcfg_read_entry_dma(uint16_t entry, + uint32_t size, void *address) +{ + struct fw_cfg_dma_access dma; + + dma.length = cpu_to_be32(size); + dma.address = cpu_to_be64((uintptr_t)address); + dma.control = cpu_to_be32(FW_CFG_DMA_READ); + + /* + * writting FW_CFG_INVALID will cause read operation to resume at + * last offset, otherwise read will start at offset 0 + */ + if (entry != FW_CFG_INVALID) + dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16)); + + barrier(); + + debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n", + address, size, be32_to_cpu(dma.control)); + + outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH); + + while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR) + __asm__ __volatile__ ("pause"); +} + +static bool qemu_fwcfg_present(void) +{ + uint32_t qemu; + + qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu); + return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE; +} + +static bool qemu_fwcfg_dma_present(void) +{ + uint8_t dma_enabled; + + qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled); + if (dma_enabled & FW_CFG_DMA_ENABLED) + return true; + + return false; +} + +static void qemu_fwcfg_read_entry(uint16_t entry, + uint32_t length, void *address) +{ + if (fwcfg_dma_present) + qemu_fwcfg_read_entry_dma(entry, length, address); + else + qemu_fwcfg_read_entry_pio(entry, length, address); +} + +int qemu_fwcfg_online_cpus(void) +{ + uint16_t nb_cpus; + + if (!fwcfg_present) + return -ENODEV; + + qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus); + + return le16_to_cpu(nb_cpus); +} + +/* + * This function prepares kernel for zboot. It loads kernel data + * to 'load_addr', initrd to 'initrd_addr' and kernel command + * line using qemu fw_cfg interface. + */ +static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr) +{ + char *data_addr; + uint32_t setup_size, kernel_size, cmdline_size, initrd_size; + + qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size); + qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size); + + if (setup_size == 0 || kernel_size == 0) { + printf("warning: no kernel available\n"); + return -1; + } + + data_addr = load_addr; + qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA, + le32_to_cpu(setup_size), data_addr); + data_addr += le32_to_cpu(setup_size); + + qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA, + le32_to_cpu(kernel_size), data_addr); + data_addr += le32_to_cpu(kernel_size); + + data_addr = initrd_addr; + qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size); + if (initrd_size == 0) { + printf("warning: no initrd available\n"); + } else { + qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA, + le32_to_cpu(initrd_size), data_addr); + data_addr += le32_to_cpu(initrd_size); + } + + qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size); + if (cmdline_size) { + qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA, + le32_to_cpu(cmdline_size), data_addr); + /* + * if kernel cmdline only contains '\0', (e.g. no -append + * when invoking qemu), do not update bootargs + */ + if (*data_addr != '\0') { + if (setenv("bootargs", data_addr) < 0) + printf("warning: unable to change bootargs\n"); + } + } + + printf("loading kernel to address %p size %x", load_addr, + le32_to_cpu(kernel_size)); + if (initrd_size) + printf(" initrd %p size %x\n", + initrd_addr, + le32_to_cpu(initrd_size)); + else + printf("\n"); + + return 0; +} + +static int qemu_fwcfg_list_firmware(void) +{ + int i; + uint32_t count; + struct fw_cfg_files *files; + + qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count); + if (!count) + return 0; + + count = be32_to_cpu(count); + files = malloc(count * sizeof(struct fw_cfg_file)); + if (!files) + return -ENOMEM; + + files->count = count; + qemu_fwcfg_read_entry(FW_CFG_INVALID, + count * sizeof(struct fw_cfg_file), + files->files); + + for (i = 0; i < files->count; i++) + printf("%-56s\n", files->files[i].name); + free(files); + return 0; +} + +void qemu_fwcfg_init(void) +{ + fwcfg_present = qemu_fwcfg_present(); + if (fwcfg_present) + fwcfg_dma_present = qemu_fwcfg_dma_present(); +} + +static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + if (qemu_fwcfg_list_firmware() < 0) + return CMD_RET_FAILURE; + + return 0; +} + +static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + int ret = qemu_fwcfg_online_cpus(); + if (ret < 0) { + printf("QEMU fw_cfg interface not found\n"); + return CMD_RET_FAILURE; + } + + printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus()); + + return 0; +} + +static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + char *env; + void *load_addr; + void *initrd_addr; + + env = getenv("loadaddr"); + load_addr = env ? + (void *)simple_strtoul(env, NULL, 16) : + (void *)CONFIG_LOADADDR; + + env = getenv("ramdiskaddr"); + initrd_addr = env ? + (void *)simple_strtoul(env, NULL, 16) : + (void *)CONFIG_RAMDISK_ADDR; + + if (argc == 2) { + load_addr = (void *)simple_strtoul(argv[0], NULL, 16); + initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16); + } else if (argc == 1) { + load_addr = (void *)simple_strtoul(argv[0], NULL, 16); + } + + return qemu_fwcfg_setup_kernel(load_addr, initrd_addr); +} + +static cmd_tbl_t fwcfg_commands[] = { + U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""), + U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""), + U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""), +}; + +static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int ret; + cmd_tbl_t *fwcfg_cmd; + + if (!fwcfg_present) { + printf("QEMU fw_cfg interface not found\n"); + return CMD_RET_USAGE; + } + + fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands, + ARRAY_SIZE(fwcfg_commands)); + argc -= 2; + argv += 2; + if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs) + return CMD_RET_USAGE; + + ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv); + + return cmd_process_error(fwcfg_cmd, ret); +} + +U_BOOT_CMD( + qfw, 4, 1, do_qemu_fw, + "QEMU firmware interface", + "<command>\n" + " - list : print firmware(s) currently loaded\n" + " - cpus : print online cpu number\n" + " - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n" +) diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 1f93f72dc8d..46111c9cf05 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -11,6 +11,7 @@ #include <asm/processor.h> #include <asm/arch/device.h> #include <asm/arch/qemu.h> +#include <asm/fw_cfg.h> static bool i440fx; @@ -57,6 +58,8 @@ static void qemu_chipset_init(void) x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, CONFIG_PCIE_ECAM_BASE | BAR_EN); } + + qemu_fwcfg_init(); } int arch_cpu_init(void) diff --git a/arch/x86/cpu/queensbay/fsp_configs.c b/arch/x86/cpu/queensbay/fsp_configs.c index 78bc966bbd0..f83bb5f2214 100644 --- a/arch/x86/cpu/queensbay/fsp_configs.c +++ b/arch/x86/cpu/queensbay/fsp_configs.c @@ -8,13 +8,13 @@ #include <common.h> #include <asm/fsp/fsp_support.h> -void update_fsp_upd(struct upd_region *fsp_upd) +void update_fsp_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf) { - /* Override any UPD setting if required */ - - /* Uncomment the line below to enable DEBUG message */ - /* fsp_upd->serial_dbgport_type = 1; */ + /* Initialize runtime buffer for fsp_init() */ + rt_buf->common.stack_top = config->common.stack_top - 32; + rt_buf->common.boot_mode = config->common.boot_mode; + rt_buf->common.upd_data = &config->fsp_upd; - /* Examples on how to initialize the pointers in UPD region */ - /* fsp_upd->pcd_example = (EXAMPLE_DATA *)&example; */ + /* Override any UPD setting if required */ } diff --git a/arch/x86/dts/microcode/m12306a2_00000008.dtsi b/arch/x86/dts/microcode/m12306a2_00000008.dtsi new file mode 100644 index 00000000000..6b35c39f8fe --- /dev/null +++ b/arch/x86/dts/microcode/m12306a2_00000008.dtsi @@ -0,0 +1,554 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x8>; +intel,date-code = <0x5182011>; +intel,processor-signature = <0x306a2>; +intel,checksum = <0xa0e51feb>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x08000000 0x11201805 0xa2060300 + 0xeb1fe5a0 0x01000000 0x12000000 0xd01f0000 + 0x00200000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x08000000 + 0x00000000 0x00000000 0x17051120 0xd1070000 + 0x01000000 0xa2060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x5665ff94 0x179da7cf 0x1e819fb2 0xb0c24e8e + 0x5cb7beb5 0x43af9a6c 0xcb0b4ccc 0x195d8712 + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6 + 0x5fb36178 0xbc17d76b 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a/arch/x86/dts/microcode/m12306a4_00000007.dtsi b/arch/x86/dts/microcode/m12306a4_00000007.dtsi new file mode 100644 index 00000000000..c39fbd3cdf8 --- /dev/null +++ b/arch/x86/dts/microcode/m12306a4_00000007.dtsi @@ -0,0 +1,618 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x7>; +intel,date-code = <0x9082011>; +intel,processor-signature = <0x306a4>; +intel,checksum = <0x7e23e5af>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x07000000 0x11200809 0xa4060300 + 0xafe5237e 0x01000000 0x12000000 0xd0230000 + 0x00240000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x07000000 + 0x00000000 0x00000000 0x07091120 0xd1080000 + 0x01000000 0xa4060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x9539a0b3 0xc7bb991d 0x308f0f1a 0xb1ba077d + 0x8bd7260b 0xd710ad0c 0xf82ee64b 0xe6f11ce1 + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6 + 0x5fb36178 0xbc17d76b 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b/arch/x86/dts/microcode/m12306a5_00000007.dtsi new file mode 100644 index 00000000000..de5037252b1 --- /dev/null +++ b/arch/x86/dts/microcode/m12306a5_00000007.dtsi @@ -0,0 +1,618 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x7>; +intel,date-code = <0x9092011>; +intel,processor-signature = <0x306a5>; +intel,checksum = <0x8e38731>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x07000000 0x11200909 0xa5060300 + 0x3187e308 0x01000000 0x12000000 0xd0230000 + 0x00240000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x07000000 + 0x00000000 0x00000000 0x08091120 0x71080000 + 0x01000000 0xa5060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x27649db1 0x904b6445 0x6acff7e8 0xc4ac0631 + 0x6830ec45 0x3aece98d 0x97bf40c8 0x83b8fef0 + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6 + 0x5fb36178 0xbc17d76b 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b/arch/x86/dts/microcode/m12306a8_00000010.dtsi new file mode 100644 index 00000000000..0672ff1af0a --- /dev/null +++ b/arch/x86/dts/microcode/m12306a8_00000010.dtsi @@ -0,0 +1,682 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x10>; +intel,date-code = <0x2202012>; +intel,processor-signature = <0x306a8>; +intel,checksum = <0xe44a4ef2>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x10000000 0x12202002 0xa8060300 + 0xf24e4ae4 0x01000000 0x12000000 0xd0270000 + 0x00280000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x10000000 + 0x00000000 0x00000000 0x17021220 0xe1090000 + 0x01000000 0xa8060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x493d401b 0x64106cf1 0x0ffc7f0f 0x9b4b97f6 + 0xb8fab9c2 0x46353316 0x0247d91b 0x3c36c361 + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6 + 0x5fb36178 0xbc17d76b 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0xc52a9d5a + 0x62aa1fa6 0x68ca34ad 0x1ac94c91 0x1794e58d + 0xa74691ef 0x0e22c1d3 0x66be923f 0x6f6f2c45 + 0x15ce79a4 0x3b8c9c40 0xa11ff2f9 0xb18f0e8a + 0x1e0763e8 0xab472e97 0xd011b9c7 0x7f4cd77e + 0x60291b08 0xfc4746db 0x1101cb2f 0x7127e03e + 0x39dd8454 0x9e18e09b 0x449c71ba 0xc1106522 + 0xee38c53b 0x8e30f2a1 0x30a5c398 0xbde9c623 + 0x49ff1078 0x36360091 0x2b797c99 0x553ff25a + 0x063174e2 0xcd5fb064 0xbaf1c003 0xbbbba060 + 0x9e7bd54a 0xe3bb944c 0xa7586ca4 0x4586a706 + 0x5bd43e12 0x9139b258 0x5962b23e 0xb20799b8 + 0x23ef9a21 0xb505a156 0xed51d1ae 0x82dced20 + 0xfed14015 0xe50de153 0xcb1de201 0x20407156 + 0x6e6c8c9f 0x4e33f0f7 0xb61006ea 0x81bcca2d + 0x8fd94695 0x576fe5c7 0x074ff2db 0xd707ccf4 + 0x581503ca 0xfcc1c71b 0xcfc21805 0xcb8251a8 + 0x69361b9a 0x14ec2bbe 0x2df3d3f6 0xa5e66081 + 0xc5c70b23 0x5dfa028b 0x22338ffa 0x1932168a + 0x11a0ed71 0xf676d717 0x823b48d7 0xe02bc37e + 0xfc624cac 0x03795ade 0x845ff149 0x5b657ed4 + 0xbe434a2e 0x8a77afde 0x3615b39d 0xba7200d9 + 0x674e4541 0x12f91c65 0x694cb6ab 0x22e78146 + 0x8f574161 0x58f35068 0xce5b6f43 0xd1f0f21e + 0x1be73d35 0x7b2dd03f 0x39bf4987 0xd9a00a8b + 0xa1285004 0x64b6871e 0xee7377af 0x51d239c8 + 0x54521a4e 0xcb661f19 0xf26dc3a8 0x8772cda3 + 0x2c827fa9 0x16f8f76f 0x1de27a89 0xf8b4a070 + 0xab4243b4 0x2c910203 0x1fc663ad 0xe310c2a3 + 0x9476000d 0x11e66913 0x346d42a8 0xa513fd81 + 0xfc260d0f 0x54c7995a 0x228585bc 0xefc0dbb0 + 0xb9999ca4 0x7dfc9ec2 0x1556bde4 0x2749b83f + 0x753da831 0x5d415b40 0x763debe4 0x94a2d4df + 0xcc560707 0x08a3de8d 0x7d9f0997 0xe3ff555e + 0xa8d05131 0xc75a1e9c 0xd696df91 0x633551a7 + 0x7ead2980 0x6c8b10b9 0x2b97f758 0xa785048f + 0x744ba0dc 0xd350342d 0x6dbdccaa 0x10a5e224 + 0x0963176d 0x71a4325c 0xa9bfeca5 0x73c90b16 + 0x5f486277 0xc897525a 0x57a8234d 0x78a73eeb + 0x2640604e 0x1598efd9 0x135cb408 0x486bd6d3 + 0xef98ab1b 0x0ce2744c 0x6a690e5d 0xa65e3af1 + 0x5263f69d 0x10feb14e 0xd857d93a 0x94d52946 + 0x52162f56 0xe72a0b7d 0x3e7d7b23 0xdff4b663 + 0xcbad0105 0x4886da29 0x7d5521d0 0xa37ad7b6 + 0xe4e79a68 0x4c6cc715 0xbb746a87 0x0a222aa2 + 0xcff26451 0xe5b51d1a 0xd786658d 0x0edc8ddc + 0x95a91b59 0x2b7b0dd7 0xc4003ca8 0xa90e574b + 0xf6d1b6c5 0x0880fcaa 0xda31fd31 0x5e2c3099 + 0x9e9cf801 0x069347b4 0x66215bcc 0x8698d9cc + 0x5d53b7ce 0x3b0a3025 0x1765a598 0xba1f4f29 + 0xa6017b4a 0x1db6bb22 0xd9b63caf 0x531e2601 + 0x24fa819b 0x8ab091a2 0xbbc3b96a 0x6d4e061d + 0x5f7b1d3a 0x13fc2925 0x564b9a06 0x2b0d7a90 + 0x933a10c7 0x8aa5e38a 0x9b79b254 0x9444c3c2 + 0xd737212d 0xb13f74df 0x7193f8c1 0xa95f42de + 0x6c5a39de 0xf1263eb0 0x57c322ea 0x829cf7e7 + 0xf8c58a2e 0x2408ad3a 0xe05fa2b7 0xf61c2132 + 0x47bcb102 0x167f4eb3 0x6a9ca49a 0x03c76439 + 0x69fa64cc 0xd715eab1 0x26b9ff58 0x65a0d362 + 0x168ed37e 0x1c4f3752 0xd4e7d4de 0x26e7865d + 0xfbd25786 0x347be5c6 0xb610ff32 0xdae6720f + 0xa01ff608 0x4a093466 0x7dce182b 0x5eb3cc1e + 0xadd542b4 0xfff308b2 0x9deaf2fb 0xd6fa9bac + 0x7f1729b9 0x54ae192c 0x85e8e337 0x840f4bfc + 0x566993d1 0x2cf2af63 0xf86cbf7b 0xa78e4aa1 + 0x11806adc 0x06070f3d 0xa833c724 0x3ffef088 + 0x78febf93 0x2cf6ae38 0x8c4d8867 0x485a2845 + 0x003a5def 0xe8d1b155 0xcb675ca8 0xcf4fec75 + 0xb7fe3198 0xf5da0890 0x9f1599b4 0xb952a34e + 0x7f1bc151 0x362e7bbb 0x063507a0 0x99c65de4 + 0xd5130eb3 0x8613ee0b 0xfd6a8987 0x01c85a32 + 0xed25a8ce 0x3e81114d 0x3f96d0be 0xfa892912 + 0xb8ab3d94 0x7f10a909 0xe20ebd7e 0x30e900b7 + 0x05b0d117 0x423ee599 0xd09dacd3 0xd385eb38 + 0xa0839eee 0x4f29f80c 0x7f253d6e 0xbc757a72 + 0x326c615c 0x43e0c8e2 0x21771593 0xa71e6072 + 0xf355b109 0xf2852219 0x9a6ab7b6 0x9b1c39ad + 0x2edb942f 0x51234e78 0xbbe44b02 0x9078446a + 0x1ff97b31 0xb2967297 0x5f1267ac 0xf8ccd029 + 0x846ccba2 0x3a2a8297 0xf60c1eae 0xd8b7a467 + 0x517e2f1f 0xe0087865 0x2a952fa4 0x75963d8d + 0x1bb14788 0x1375edb3 0x941303f7 0x6738a9c9 + 0xe3c99502 0x5f42b5ec 0xb53339d3 0x65896cac + 0x8d992623 0x8b09fdc1 0x47e71464 0xc09733fb + 0xfa8cfbfe 0x898ba57d 0xe74ca247 0x4fc21f9f + 0xc880e39a 0x973ab5b7 0x78628ad6 0x8a6fe2a0 + 0x92a5a189 0x7a6ff475 0x7db81d10 0x81deea09 + 0xa4ff44fd 0x056e383e 0x7cd47b4c 0x2182a401 + 0xd0c4ce01 0xeb313665 0x8bbb4e07 0xbb4d4a64 + 0x15fe41cb 0x53a267ce 0x8ee4ae7c 0x01678630 + 0xda477daf 0x7ee74db4 0xf6e9228b 0x06c57aef + 0x5b9c8e80 0x1e05611b 0x26682707 0x7111591a + 0x7646cb3b 0x20f2d117 0x4dae44a9 0x395871da + 0x54e6172c 0x4ab90f71 0x65209536 0xb3b57c85 + 0x11d10b0b 0xc9e50256 0x47521f5a 0x4416012f + 0x6d8042b6 0x454542fa 0x77f0fea3 0xce983a27 + 0x40f74a4e 0xabc2d476 0xcd6a647d 0xca633336 + 0xeb7fa467 0x4b14425f 0xd7abae15 0xb9652306 + 0x990b3a98 0x03e6f53a 0xa5f3ec3c 0xb40c953f + 0x5cd8470a 0xbf93da01 0x89a52e28 0x5984bd42 + 0xe9d93e95 0xa3b67bbf 0x099ff7cf 0x07b80086 + 0x20cdf1cb 0xcfbbdb2e 0xeb0da53d 0x33b82f36 + 0x28fb9aca 0x013bb5b7 0xcfbfefea 0x7f4400d1 + 0xd3ad108f 0xe32556f3 0xa9e77e41 0x92955338 + 0x3d102663 0x63bde93f 0xbbb464c4 0xcc1ff27f + 0x7968d83b 0xca32b52d 0x1d4102ff 0x84cfd695 + 0x8303a6d3 0xc6f8ba69 0xdd78d4ef 0x98b195af + 0x50f92a15 0x2066c503 0x61281597 0x5d0197b7 + 0x59e6f0be 0x02423dd6 0x9b4d27af 0xb2a0755d + 0x72f2eb4e 0xdb5aa819 0xddb42e82 0x9688712a + 0xb430e384 0x6484e439 0x44f68d17 0x195c6382 + 0xddee2db1 0xd9af2e18 0x7fbd30d6 0x2ac223db + 0x0d3bd809 0xec982530 0x1a41d13f 0xef2849a8 + 0x9c233021 0xc074a29c 0xe7b8f28f 0xd0adf47f + 0x23cdf70d 0x6795e85d 0x1168d6ea 0x3c8bb4c7 + 0xad1d00c9 0xf3eeb5d0 0x2f950982 0x9fbbde57 + 0xdc733a93 0xb23e2beb 0x7dbb34af 0xf1323cff + 0xf6c9a9bc 0xf69900a6 0x9447ab0b 0xf03e55fa + 0x2816479b 0x487e507e 0x494087fb 0x0601d1ef + 0x27c86510 0x6a14691a 0xb78886de 0xe89e8c84 + 0xf2cd073c 0x09144b70 0xa82227a5 0x82f88828 + 0x71f7e10a 0x6c2b46b6 0xf813fe7d 0xf76d2602 + 0x044d5543 0x9e1b6a76 0x967ad7b5 0xe803b0a7 + 0x01e03dd9 0x6d5c94d8 0x112357c8 0x8e0bfe12 + 0xcc8c7461 0xfbc1c562 0x9838886c 0xa16c46a7 + 0x020631ad 0x70fb29ff 0x5f5f1795 0x07a762e8 + 0x3467aa2b 0xd396d1d7 0xa12aaf4c 0xd3c13b6b + 0xf158d7dd 0x17b1317a 0xd847a91d 0x7612ab8e + >; diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index 8a062294798..9086b461b9d 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -32,17 +32,10 @@ cpu@0 { device_type = "cpu"; - compatible = "cpu-x86"; + compatible = "cpu-qemu"; reg = <0>; intel,apic-id = <0>; }; - - cpu@1 { - device_type = "cpu"; - compatible = "cpu-x86"; - reg = <1>; - intel,apic-id = <1>; - }; }; tsc-timer { diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index 0b685c8b799..145e8115cec 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -43,17 +43,10 @@ cpu@0 { device_type = "cpu"; - compatible = "cpu-x86"; + compatible = "cpu-qemu"; reg = <0>; intel,apic-id = <0>; }; - - cpu@1 { - device_type = "cpu"; - compatible = "cpu-x86"; - reg = <1>; - intel,apic-id = <1>; - }; }; tsc-timer { diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h new file mode 100644 index 00000000000..e539890c337 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_CONFIGS_H__ +#define __FSP_CONFIGS_H__ + +struct fsp_config_data { + struct fsp_cfg_common common; + struct upd_region fsp_upd; +}; + +struct fspinit_rtbuf { + struct common_buf common; /* FSP common runtime data structure */ +}; + +#endif /* __FSP_CONFIGS_H__ */ diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 21df083842c..31437c8618d 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -105,6 +105,8 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define GPIO_ROUT 0xb8 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define COMB_DEC_RANGE (1 << 4) /* 0x2f8-0x2ff (COM2) */ +#define COMA_DEC_RANGE (0 << 0) /* 0x3f8-0x3ff (COM1) */ #define LPC_EN 0x82 /* LPC IF Enables Register */ #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ @@ -121,6 +123,14 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ #define LPC_GENX_DEC(x) (0x84 + 4 * (x)) +#define GEN_DEC_RANGE_256B 0xfc0000 /* 256 Bytes */ +#define GEN_DEC_RANGE_128B 0x7c0000 /* 128 Bytes */ +#define GEN_DEC_RANGE_64B 0x3c0000 /* 64 Bytes */ +#define GEN_DEC_RANGE_32B 0x1c0000 /* 32 Bytes */ +#define GEN_DEC_RANGE_16B 0x0c0000 /* 16 Bytes */ +#define GEN_DEC_RANGE_8B 0x040000 /* 8 Bytes */ +#define GEN_DEC_RANGE_4B 0x000000 /* 4 Bytes */ +#define GEN_DEC_RANGE_EN (1 << 0) /* Range Enable */ /* PCI Configuration Space (D31:F1): IDE */ #define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1) diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h new file mode 100644 index 00000000000..e539890c337 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_CONFIGS_H__ +#define __FSP_CONFIGS_H__ + +struct fsp_config_data { + struct fsp_cfg_common common; + struct upd_region fsp_upd; +}; + +struct fspinit_rtbuf { + struct common_buf common; /* FSP common runtime data structure */ +}; + +#endif /* __FSP_CONFIGS_H__ */ diff --git a/arch/x86/include/asm/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h index 2d34d138abd..afafb30c147 100644 --- a/arch/x86/include/asm/fsp/fsp_api.h +++ b/arch/x86/include/asm/fsp/fsp_api.h @@ -11,6 +11,16 @@ #include <linux/linkage.h> /* + * FSP common configuration structure. + * This needs to be included in the platform-specific struct fsp_config_data. + */ +struct fsp_cfg_common { + struct fsp_header *fsp_hdr; + u32 stack_top; + u32 boot_mode; +}; + +/* * FspInit continuation function prototype. * Control will be returned to this callback function after FspInit API call. */ @@ -30,7 +40,7 @@ struct common_buf { * Stack top pointer used by the bootloader. The new stack frame will be * set up at this location after FspInit API call. */ - u32 *stack_top; + u32 stack_top; u32 boot_mode; /* Current system boot mode */ void *upd_data; /* User platform configuraiton data region */ u32 reserved[7]; /* Reserved */ diff --git a/arch/x86/include/asm/fsp/fsp_platform.h b/arch/x86/include/asm/fsp/fsp_platform.h deleted file mode 100644 index 61286ceb469..00000000000 --- a/arch/x86/include/asm/fsp/fsp_platform.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: Intel - */ - -#ifndef __FSP_PLATFORM_H__ -#define __FSP_PLATFORM_H__ - -struct fspinit_rtbuf { - struct common_buf common; /* FSP common runtime data structure */ -}; - -#endif diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 7317dda9024..61d811f70e0 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -13,16 +13,10 @@ #include "fsp_ffs.h" #include "fsp_api.h" #include "fsp_hob.h" -#include "fsp_platform.h" #include "fsp_infoheader.h" #include "fsp_bootmode.h" #include <asm/arch/fsp/fsp_vpd.h> - -struct shared_data { - struct fsp_header *fsp_hdr; - u32 *stack_top; - struct upd_region fsp_upd; -}; +#include <asm/arch/fsp/fsp_configs.h> #define FSP_LOWMEM_BASE 0x100000UL #define FSP_HIGHMEM_BASE 0x100000000ULL @@ -49,14 +43,12 @@ void fsp_init_done(void *hob_list); /** * FSP Continuation function * - * @shared_data: Shared data base before stack migration * @status: Always 0 * @hob_list: HOB list pointer * * @retval: Never returns */ -void fsp_continue(struct shared_data *shared_data, u32 status, - void *hob_list); +void fsp_continue(u32 status, void *hob_list); /** * Find FSP header offset in FSP image @@ -199,13 +191,15 @@ void *fsp_get_nvs_data(const void *hob_list, u32 *len); void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len); /** - * This function overrides the default configurations in the UPD data region. + * This function overrides the default configurations of FSP. * - * @fsp_upd: A pointer to the upd_region data strcture + * @config: A pointer to the FSP configuration data structure + * @rt_buf: A pointer to the FSP runtime buffer data structure * * @return: None */ -void update_fsp_upd(struct upd_region *fsp_upd); +void update_fsp_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf); /** * fsp_init_phase_pci() - Tell the FSP that we have completed PCI init diff --git a/arch/x86/include/asm/fw_cfg.h b/arch/x86/include/asm/fw_cfg.h new file mode 100644 index 00000000000..fb110fa8e78 --- /dev/null +++ b/arch/x86/include/asm/fw_cfg.h @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FW_CFG__ +#define __FW_CFG__ + +#define FW_CONTROL_PORT 0x510 +#define FW_DATA_PORT 0x511 +#define FW_DMA_PORT_LOW 0x514 +#define FW_DMA_PORT_HIGH 0x518 + +enum qemu_fwcfg_items { + FW_CFG_SIGNATURE = 0x00, + FW_CFG_ID = 0x01, + FW_CFG_UUID = 0x02, + FW_CFG_RAM_SIZE = 0x03, + FW_CFG_NOGRAPHIC = 0x04, + FW_CFG_NB_CPUS = 0x05, + FW_CFG_MACHINE_ID = 0x06, + FW_CFG_KERNEL_ADDR = 0x07, + FW_CFG_KERNEL_SIZE = 0x08, + FW_CFG_KERNEL_CMDLINE = 0x09, + FW_CFG_INITRD_ADDR = 0x0a, + FW_CFG_INITRD_SIZE = 0x0b, + FW_CFG_BOOT_DEVICE = 0x0c, + FW_CFG_NUMA = 0x0d, + FW_CFG_BOOT_MENU = 0x0e, + FW_CFG_MAX_CPUS = 0x0f, + FW_CFG_KERNEL_ENTRY = 0x10, + FW_CFG_KERNEL_DATA = 0x11, + FW_CFG_INITRD_DATA = 0x12, + FW_CFG_CMDLINE_ADDR = 0x13, + FW_CFG_CMDLINE_SIZE = 0x14, + FW_CFG_CMDLINE_DATA = 0x15, + FW_CFG_SETUP_ADDR = 0x16, + FW_CFG_SETUP_SIZE = 0x17, + FW_CFG_SETUP_DATA = 0x18, + FW_CFG_FILE_DIR = 0x19, + FW_CFG_FILE_FIRST = 0x20, + FW_CFG_WRITE_CHANNEL = 0x4000, + FW_CFG_ARCH_LOCAL = 0x8000, + FW_CFG_INVALID = 0xffff, +}; + +#define FW_CFG_FILE_SLOTS 0x10 +#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS) +#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL) + +#define FW_CFG_MAX_FILE_PATH 56 + +#define QEMU_FW_CFG_SIGNATURE (('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U') + +#define FW_CFG_DMA_ERROR (1 << 0) +#define FW_CFG_DMA_READ (1 << 1) +#define FW_CFG_DMA_SKIP (1 << 2) +#define FW_CFG_DMA_SELECT (1 << 3) + +#define FW_CFG_DMA_ENABLED (1 << 1) + +struct fw_cfg_file { + __be32 size; + __be16 select; + __be16 reserved; + char name[FW_CFG_MAX_FILE_PATH]; +}; + +struct fw_cfg_files { + __be32 count; + struct fw_cfg_file files[]; +}; + +struct fw_cfg_dma_access { + __be32 control; + __be32 length; + __be64 address; +}; + +/** + * Initialize QEMU fw_cfg interface + */ +void qemu_fwcfg_init(void); + +/** + * Get system cpu number + * + * @return: cpu number in system + */ +int qemu_fwcfg_online_cpus(void); + +#endif diff --git a/arch/x86/lib/fsp/cmd_fsp.c b/arch/x86/lib/fsp/cmd_fsp.c index 4959edf11bb..25546638cf6 100644 --- a/arch/x86/lib/fsp/cmd_fsp.c +++ b/arch/x86/lib/fsp/cmd_fsp.c @@ -69,7 +69,7 @@ static int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("---|----------|-----------|------|-"); printf("------------------------------------------\n"); while (!end_of_hob(hdr)) { - printf("%-2d | %08x | ", i, (unsigned int)hdr); + printf("%02x | %08x | ", i, (unsigned int)hdr); type = hdr->type; if (type == HOB_TYPE_UNUSED) desc = "*Unused*"; @@ -79,7 +79,7 @@ static int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) desc = hob_type[type]; else desc = "*Invalid*"; - printf("%-9s | %-4d | ", desc, hdr->len); + printf("%-9s | %04x | ", desc, hdr->len); if (type == HOB_TYPE_MEM_ALLOC || type == HOB_TYPE_RES_DESC || type == HOB_TYPE_GUID_EXT) { diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index 1d48ff4a8e7..875c96a8f19 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -87,42 +87,28 @@ struct fsp_header *__attribute__((optimize("O0"))) find_fsp_header(void) return (struct fsp_header *)fsp; } -void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list) +void fsp_continue(u32 status, void *hob_list) { - u32 stack_len; - u32 stack_base; - u32 stack_top; - post_code(POST_MRC); assert(status == 0); - /* Get the migrated stack in normal memory */ - stack_base = (u32)fsp_get_bootloader_tmp_mem(hob_list, &stack_len); - assert(stack_base != 0); - stack_top = stack_base + stack_len - sizeof(u32); - - /* - * Old stack base is stored at the very end of the stack top, - * use it to calculate the migrated shared data base - */ - shared_data = (struct shared_data *)(stack_base + - ((u32)shared_data - *(u32 *)stack_top)); - /* The boot loader main function entry */ fsp_init_done(hob_list); } void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) { - struct shared_data shared_data; + struct fsp_config_data config_data; fsp_init_f init; struct fsp_init_params params; struct fspinit_rtbuf rt_buf; - struct vpd_region *fsp_vpd; struct fsp_header *fsp_hdr; struct fsp_init_params *params_ptr; +#ifdef CONFIG_FSP_USE_UPD + struct vpd_region *fsp_vpd; struct upd_region *fsp_upd; +#endif #ifdef CONFIG_DEBUG_UART setup_early_uart(); @@ -134,14 +120,11 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) panic("Invalid FSP header"); } - fsp_upd = &shared_data.fsp_upd; - memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf)); - - /* Reserve a gap in stack top */ - rt_buf.common.stack_top = (u32 *)stack_top - 32; - rt_buf.common.boot_mode = boot_mode; - rt_buf.common.upd_data = fsp_upd; + config_data.common.fsp_hdr = fsp_hdr; + config_data.common.stack_top = stack_top; + config_data.common.boot_mode = boot_mode; +#ifdef CONFIG_FSP_USE_UPD /* Get VPD region start */ fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base + fsp_hdr->cfg_region_off); @@ -149,15 +132,20 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) /* Verify the VPD data region is valid */ assert(fsp_vpd->sign == VPD_IMAGE_ID); + fsp_upd = &config_data.fsp_upd; + /* Copy default data from Flash */ memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset), sizeof(struct upd_region)); /* Verify the UPD data region is valid */ assert(fsp_upd->terminator == UPD_TERMINATOR); +#endif - /* Override any UPD setting if required */ - update_fsp_upd(fsp_upd); + memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf)); + + /* Override any configuration if required */ + update_fsp_configs(&config_data, &rt_buf); memset(¶ms, 0, sizeof(struct fsp_init_params)); params.nvs_buf = nvs_buf; @@ -167,28 +155,24 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init); params_ptr = ¶ms; - shared_data.fsp_hdr = fsp_hdr; - shared_data.stack_top = (u32 *)stack_top; - post_code(POST_PRE_MRC); /* Load GDT for FSP */ setup_fsp_gdt(); /* - * Use ASM code to ensure the register value in EAX & ECX - * will be passed into BlContinuationFunc + * Use ASM code to ensure the register value in EAX & EDX + * will be passed into fsp_continue */ asm volatile ( "pushl %0;" "call *%%eax;" ".global asm_continuation;" "asm_continuation:;" - "movl %%ebx, %%eax;" /* shared_data */ - "movl 4(%%esp), %%edx;" /* status */ - "movl 8(%%esp), %%ecx;" /* hob_list */ + "movl 4(%%esp), %%eax;" /* status */ + "movl 8(%%esp), %%edx;" /* hob_list */ "jmp fsp_continue;" - : : "m"(params_ptr), "a"(init), "b"(&shared_data) + : : "m"(params_ptr), "a"(init) ); /* |