diff options
Diffstat (limited to 'arch')
139 files changed, 3061 insertions, 666 deletions
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S index 26a59341893..90ee7e0fe40 100644 --- a/arch/arc/lib/start.S +++ b/arch/arc/lib/start.S @@ -50,18 +50,20 @@ ENTRY(_start) 1: #endif - /* Setup stack- and frame-pointers */ + /* Establish C runtime stack and frame */ mov %sp, CONFIG_SYS_INIT_SP_ADDR mov %fp, %sp - /* Allocate and zero GD, update SP */ + /* Allocate reserved area from current top of stack */ mov %r0, %sp - bl board_init_f_mem - - /* Update stack- and frame-pointers */ + bl board_init_f_alloc_reserve + /* Set stack below reserved area, adjust frame pointer accordingly */ mov %sp, %r0 mov %fp, %sp + /* Initialize reserved area - note: r0 already contains address */ + bl board_init_f_init_reserve + /* Zero the one and only argument of "board_init_f" */ mov_s %r0, 0 j board_init_f diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9bd6cf1d807..dd9cac91e7e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -117,7 +117,14 @@ config ARCH_MVEBU select OF_CONTROL select OF_SEPARATE select DM + select DM_ETH select DM_SERIAL + select DM_SPI + select DM_SPI_FLASH + select SPL_DM + select SPL_DM_SEQ_ALIAS + select SPL_OF_CONTROL + select SPL_SIMPLE_BUS config TARGET_DEVKIT3250 bool "Support devkit3250" @@ -769,8 +776,6 @@ source "board/BuR/kwb/Kconfig" source "board/BuR/tseries/Kconfig" source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" -source "board/Marvell/db-88f6820-gp/Kconfig" -source "board/Marvell/db-mv784mp-gp/Kconfig" source "board/Marvell/gplugd/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" @@ -809,7 +814,6 @@ source "board/h2200/Kconfig" source "board/hisilicon/hikey/Kconfig" source "board/imx31_phycore/Kconfig" source "board/isee/igep0033/Kconfig" -source "board/maxbcm/Kconfig" source "board/mpl/vcma9/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" source "board/phytec/pcm051/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 18283d1d359..3d156732139 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -49,7 +49,7 @@ machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_KEYSTONE) += keystone # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD machine-$(CONFIG_KIRKWOOD) += kirkwood -machine-$(CONFIG_ARMADA_XP) += mvebu +machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X machine-$(CONFIG_ORION5X) += orion5x diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index b1c3f8f4ad8..b6db23e981f 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -5,12 +5,14 @@ */ #include <common.h> -#include <asm/arch/cpu.h> +#include <dm.h> +#include <ns16550.h> +#include <dm/platform_data/lpc32xx_hsuart.h> + #include <asm/arch/clk.h> #include <asm/arch/uart.h> #include <asm/arch/mux.h> #include <asm/io.h> -#include <dm.h> static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; @@ -41,6 +43,37 @@ void lpc32xx_uart_init(unsigned int uart_id) &clk->u3clk + (uart_id - 3)); } +#if !CONFIG_IS_ENABLED(OF_CONTROL) +static const struct ns16550_platdata lpc32xx_uart[] = { + { UART3_BASE, 2, CONFIG_SYS_NS16550_CLK }, + { UART4_BASE, 2, CONFIG_SYS_NS16550_CLK }, + { UART5_BASE, 2, CONFIG_SYS_NS16550_CLK }, + { UART6_BASE, 2, CONFIG_SYS_NS16550_CLK }, +}; + +#if defined(CONFIG_LPC32XX_HSUART) +static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = { + { HS_UART1_BASE, }, + { HS_UART2_BASE, }, + { HS_UART7_BASE, }, +}; +#endif + +U_BOOT_DEVICES(lpc32xx_uarts) = { +#if defined(CONFIG_LPC32XX_HSUART) + { "lpc32xx_hsuart", &lpc32xx_hsuart[0], }, + { "lpc32xx_hsuart", &lpc32xx_hsuart[1], }, +#endif + { "ns16550_serial", &lpc32xx_uart[0], }, + { "ns16550_serial", &lpc32xx_uart[1], }, + { "ns16550_serial", &lpc32xx_uart[2], }, + { "ns16550_serial", &lpc32xx_uart[3], }, +#if defined(CONFIG_LPC32XX_HSUART) + { "lpc32xx_hsuart", &lpc32xx_hsuart[2], }, +#endif +}; +#endif + void lpc32xx_dma_init(void) { /* Enable DMA interface */ diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0bcd3163756..64b83711412 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -48,8 +48,11 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra210-p2571.dtb dtb-$(CONFIG_ARCH_MVEBU) += \ + armada-388-clearfog.dtb \ armada-388-gp.dtb \ - armada-xp-gp.dtb + armada-xp-gp.dtb \ + armada-xp-maxbcm.dtb \ + armada-xp-synology-ds414.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ph1-ld4-ref.dtb \ diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi index 3fffe1eec3e..c95d1d3b35d 100644 --- a/arch/arm/dts/am4372.dtsi +++ b/arch/arm/dts/am4372.dtsi @@ -25,6 +25,7 @@ serial0 = &uart0; ethernet0 = &cpsw_emac0; ethernet1 = &cpsw_emac1; + spi0 = &qspi; }; cpus { @@ -908,7 +909,9 @@ qspi: qspi@47900000 { compatible = "ti,am4372-qspi"; - reg = <0x47900000 0x100>; + reg = <0x47900000 0x100>, + <0x30000000 0x4000000>; + reg-names = "qspi_base", "qspi_mmap"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "qspi"; diff --git a/arch/arm/dts/am437x-sk-evm.dts b/arch/arm/dts/am437x-sk-evm.dts index 3f9d8080910..89feaf3eb71 100644 --- a/arch/arm/dts/am437x-sk-evm.dts +++ b/arch/arm/dts/am437x-sk-evm.dts @@ -567,7 +567,7 @@ spi-max-frequency = <48000000>; m25p80@0 { - compatible = "mx66l51235l"; + compatible = "mx66l51235l","spi-flash"; spi-max-frequency = <48000000>; reg = <0>; spi-cpol; diff --git a/arch/arm/dts/armada-370-xp.dtsi b/arch/arm/dts/armada-370-xp.dtsi index a718866ba52..0b2a78d3930 100644 --- a/arch/arm/dts/armada-370-xp.dtsi +++ b/arch/arm/dts/armada-370-xp.dtsi @@ -141,6 +141,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + u-boot,dm-pre-reloc; rtc@10300 { compatible = "marvell,orion-rtc"; diff --git a/arch/arm/dts/armada-388-clearfog.dts b/arch/arm/dts/armada-388-clearfog.dts new file mode 100644 index 00000000000..b2dfd564352 --- /dev/null +++ b/arch/arm/dts/armada-388-clearfog.dts @@ -0,0 +1,509 @@ +/* + * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828) + * + * Copyright (C) 2015 Russell King + * + * This board is in development; the contents of this file work with + * the A1 rev 2.0 of the board, which does not represent final + * production board. Things will change, don't expect this file to + * remain compatible info the future. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include "armada-388.dtsi" + +/ { + model = "SolidRun Clearfog A1"; + compatible = "solidrun,clearfog-a1", "marvell,armada388", + "marvell,armada385", "marvell,armada380"; + + aliases { + /* So that mvebu u-boot can update the MAC addresses */ + ethernet1 = ð0; + ethernet2 = ð1; + ethernet3 = ð2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; /* 256 MB */ + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 + MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 + MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; + + internal-regs { + ethernet@30000 { + mac-address = [00 50 43 02 02 02]; + phy-mode = "sgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + ethernet@34000 { + mac-address = [00 50 43 02 02 03]; + managed = "in-band-status"; + phy-mode = "sgmii"; + status = "okay"; + }; + + ethernet@70000 { + mac-address = [00 50 43 02 02 01]; + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + phy = <&phy_dedicated>; + phy-mode = "rgmii-id"; + status = "okay"; + }; + + i2c@11000 { + /* Is there anything on this? */ + clock-frequency = <100000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* + * PCA9655 GPIO expander, up to 1MHz clock. + * 0-CON3 CLKREQ# + * 1-CON3 PERST# + * 2-CON2 PERST# + * 3-CON3 W_DISABLE + * 4-CON2 CLKREQ# + * 5-USB3 overcurrent + * 6-USB3 power + * 7-CON2 W_DISABLE + * 8-JP4 P1 + * 9-JP4 P4 + * 10-JP4 P5 + * 11-m.2 DEVSLP + * 12-SFP_LOS + * 13-SFP_TX_FAULT + * 14-SFP_TX_DISABLE + * 15-SFP_MOD_DEF0 + */ + expander0: gpio-expander@20 { + /* + * This is how it should be: + * compatible = "onnn,pca9655", + * "nxp,pca9555"; + * but you can't do this because of + * the way I2C works. + */ + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + + pcie1_0_clkreq { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + input; + line-name = "pcie1.0-clkreq"; + }; + pcie1_0_w_disable { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pcie1.0-w-disable"; + }; + pcie2_0_clkreq { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + input; + line-name = "pcie2.0-clkreq"; + }; + pcie2_0_w_disable { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pcie2.0-w-disable"; + }; + usb3_ilimit { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + input; + line-name = "usb3-current-limit"; + }; + usb3_power { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb3-power"; + }; + m2_devslp { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "m.2 devslp"; + }; + }; + + /* The MCP3021 is 100kHz clock only */ + mikrobus_adc: mcp3021@4c { + compatible = "microchip,mcp3021"; + reg = <0x4c>; + }; + + /* Also something at 0x64 */ + }; + + i2c@11100 { + /* + * Routed to SFP, mikrobus, and PCIe. + * SFP limits this to 100kHz, and requires + * an AT24C01A/02/04 with address pins tied + * low, which takes addresses 0x50 and 0x51. + * Mikrobus doesn't specify beyond an I2C + * bus being present. + * PCIe uses ARP to assign addresses, or + * 0x63-0x64. + */ + clock-frequency = <100000>; + pinctrl-0 = <&clearfog_i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + mdio@72004 { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + + phy_dedicated: ethernet-phy@0 { + /* + * Annoyingly, the marvell phy driver + * configures the LED register, rather + * than preserving reset-loaded setting. + * We undo that rubbish here. + */ + marvell,reg-init = <3 16 0 0x101e>; + reg = <0>; + }; + }; + + pinctrl@18000 { + clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins { + marvell,pins = "mpp46"; + marvell,function = "ref"; + }; + clearfog_dsa0_pins: clearfog-dsa0-pins { + marvell,pins = "mpp23", "mpp41"; + marvell,function = "gpio"; + }; + clearfog_i2c1_pins: i2c1-pins { + /* SFP, PCIe, mSATA, mikrobus */ + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c1"; + }; + clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + clearfog_sdhci_pins: clearfog-sdhci-pins { + marvell,pins = "mpp21", "mpp28", + "mpp37", "mpp38", + "mpp39", "mpp40"; + marvell,function = "sd0"; + }; + clearfog_spi1_cs_pins: spi1-cs-pins { + marvell,pins = "mpp55"; + marvell,function = "spi1"; + }; + mikro_pins: mikro-pins { + /* int: mpp22 rst: mpp29 */ + marvell,pins = "mpp22", "mpp29"; + marvell,function = "gpio"; + }; + mikro_spi_pins: mikro-spi-pins { + marvell,pins = "mpp43"; + marvell,function = "spi1"; + }; + mikro_uart_pins: mikro-uart-pins { + marvell,pins = "mpp24", "mpp25"; + marvell,function = "ua1"; + }; + rear_button_pins: rear-button-pins { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + }; + + rtc@a3800 { + /* + * If the rtc doesn't work, run "date reset" + * twice in u-boot. + */ + status = "okay"; + }; + + sata@a8000 { + /* pinctrl? */ + status = "okay"; + }; + + sata@e0000 { + /* pinctrl? */ + status = "okay"; + }; + + sdhci@d8000 { + bus-width = <4>; + cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + no-1-8-v; + pinctrl-0 = <&clearfog_sdhci_pins + &clearfog_sdhci_cd_pins>; + pinctrl-names = "default"; + status = "okay"; + vmmc = <®_3p3v>; + wp-inverted; + }; + + serial@12000 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + serial@12100 { + /* mikrobus uart */ + pinctrl-0 = <&mikro_uart_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + spi@10680 { + /* + * We don't seem to have the W25Q32 on the + * A1 Rev 2.0 boards, so disable SPI. + * CS0: W25Q32 (doesn't appear to be present) + * CS1: + * CS2: mikrobus + */ + pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>; + pinctrl-names = "default"; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "w25q32", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <3000000>; + status = "disabled"; + }; + }; + + usb3@f8000 { + status = "okay"; + }; + }; + + pcie-controller { + status = "okay"; + /* + * The two PCIe units are accessible through + * the mini-PCIe connectors on the board. + */ + pcie@2,0 { + /* Port 1, Lane 0. CONN3, nearest power. */ + reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + pcie@3,0 { + /* Port 2, Lane 0. CONN2, nearest CPU. */ + reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + }; + }; + + sfp: sfp { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; + moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>; + sfp,ethernet = <ð2>; + tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; + }; + + dsa@0 { + compatible = "marvell,dsa"; + dsa,ethernet = <ð1>; + dsa,mii-bus = <&mdio>; + pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; + pinctrl-names = "default"; + #address-cells = <2>; + #size-cells = <0>; + + switch@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4 0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "lan5"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + }; + + port@6 { + /* 88E1512 external phy */ + reg = <6>; + label = "lan6"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&rear_button_pins>; + pinctrl-names = "default"; + + button_0 { + /* The rear SW3 button */ + label = "Rear Button"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + linux,can-disable; + linux,code = <BTN_0>; + }; + }; +}; + +/* ++#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011 +MPP18: gpio ? (pca9655 int?) +MPP19: gpio ? (clkreq?) +MPP20: gpio ? (sd0 detect) +MPP21: sd0:cmd x sd0 +MPP22: gpio x mikro int +MPP23: gpio x switch irq ++#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333 +MPP24: ua1:rxd x mikro rx +MPP25: ua1:txd x mikro tx +MPP26: i2c1:sck x mikro sck +MPP27: i2c1:sda x mikro sda +MPP28: sd0:clk x sd0 +MPP29: gpio x mikro rst +MPP30: ge1:txd2 ? (config) +MPP31: ge1:txd3 ? (config) ++#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002 +MPP32: ge1:txctl ? (unused) +MPP33: gpio ? (pic_com0) +MPP34: gpio x rear button (pic_com1) +MPP35: gpio ? (pic_com2) +MPP36: gpio ? (unused) +MPP37: sd0:d3 x sd0 +MPP38: sd0:d0 x sd0 +MPP39: sd0:d1 x sd0 ++#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004 +MPP40: sd0:d2 x sd0 +MPP41: gpio x switch reset +MPP42: gpio ? sw1-1 +MPP43: spi1:cs2 x mikro cs +MPP44: sata3:prsnt ? (unused) +MPP45: ref:clk_out0 ? +MPP46: ref:clk_out1 x switch clk +MPP47: 4 ? (unused) ++#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333 +MPP48: tdm:pclk +MPP49: tdm:fsync +MPP50: tdm:drx +MPP51: tdm:dtx +MPP52: tdm:int +MPP53: tdm:rst +MPP54: gpio ? (pwm) +MPP55: spi1:cs1 x slic ++#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444 +MPP56: spi1:mosi x mikro mosi +MPP57: spi1:sck x mikro sck +MPP58: spi1:miso x mikro miso +MPP59: spi1:cs0 x w25q32 +*/ diff --git a/arch/arm/dts/armada-388-gp.dts b/arch/arm/dts/armada-388-gp.dts index fd4f6fd8a2e..7bc878f5a92 100644 --- a/arch/arm/dts/armada-388-gp.dts +++ b/arch/arm/dts/armada-388-gp.dts @@ -51,6 +51,12 @@ stdout-path = "serial0:115200n8"; }; + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + spi0 = &spi0; + }; + memory { device_type = "memory"; reg = <0x00000000 0x80000000>; /* 2 GB */ @@ -65,8 +71,10 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; status = "okay"; + u-boot,dm-pre-reloc; spi-flash@0 { + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p128", "jedec,spi-nor"; @@ -122,6 +130,7 @@ pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; + u-boot,dm-pre-reloc; }; /* GE1 CON15 */ diff --git a/arch/arm/dts/armada-38x.dtsi b/arch/arm/dts/armada-38x.dtsi index 04ecfe6e2bc..dc8a1a66c1f 100644 --- a/arch/arm/dts/armada-38x.dtsi +++ b/arch/arm/dts/armada-38x.dtsi @@ -70,6 +70,7 @@ soc { compatible = "marvell,armada380-mbus", "simple-bus"; + u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <1>; controller = <&mbusc>; @@ -134,6 +135,7 @@ internal-regs { compatible = "simple-bus"; + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; diff --git a/arch/arm/dts/armada-xp-gp.dts b/arch/arm/dts/armada-xp-gp.dts index bf724ca96a3..27799d1254e 100644 --- a/arch/arm/dts/armada-xp-gp.dts +++ b/arch/arm/dts/armada-xp-gp.dts @@ -68,6 +68,10 @@ stdout-path = "serial0:115200n8"; }; + aliases { + spi0 = &spi0; + }; + memory { device_type = "memory"; /* @@ -148,6 +152,7 @@ internal-regs { serial@12000 { status = "okay"; + u-boot,dm-pre-reloc; }; serial@12100 { status = "okay"; @@ -223,8 +228,10 @@ spi0: spi@10600 { status = "okay"; + u-boot,dm-pre-reloc; spi-flash@0 { + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "n25q128a13", "jedec,spi-nor"; diff --git a/arch/arm/dts/armada-xp-maxbcm.dts b/arch/arm/dts/armada-xp-maxbcm.dts new file mode 100644 index 00000000000..d7d7f65c85f --- /dev/null +++ b/arch/arm/dts/armada-xp-maxbcm.dts @@ -0,0 +1,249 @@ +/* + * Device Tree file for Marvell Armada XP maxbcm board + * + * Copyright (C) 2013-2014 Marvell + * + * Lior Amsalem <alior@marvell.com> + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "armada-xp-mv78460.dtsi" + +/ { + model = "Marvell Armada XP MAXBCM"; + compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + /* + * 8 GB of plug-in RAM modules by default.The amount + * of memory available can be changed by the + * bootloader according the size of the module + * actually plugged. However, memory between + * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is + * the address range used for I/O (internal registers, + * MBus windows). + */ + reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, + <0x00000001 0x00000000 0x00000001 0x00000000>; + }; + + cpus { + pm_pic { + ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, + <&gpio0 17 GPIO_ACTIVE_LOW>, + <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 + MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; + + devbus-bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 16 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x1000000>; + bank-width = <2>; + }; + }; + + pcie-controller { + status = "okay"; + + /* + * The 3 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@10,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; + }; + + internal-regs { + serial@12000 { + status = "okay"; + u-boot,dm-pre-reloc; + }; + serial@12100 { + status = "okay"; + }; + serial@12200 { + status = "okay"; + }; + serial@12300 { + status = "okay"; + }; + pinctrl { + pinctrl-0 = <&pic_pins>; + pinctrl-names = "default"; + pic_pins: pic-pins-0 { + marvell,pins = "mpp16", "mpp17", + "mpp18"; + marvell,function = "gpio"; + }; + }; + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + }; + + phy3: ethernet-phy@3 { + reg = <3>; + }; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "sgmii"; + }; + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "sgmii"; + }; + ethernet@30000 { + status = "okay"; + phy = <&phy2>; + phy-mode = "sgmii"; + }; + ethernet@34000 { + status = "okay"; + phy = <&phy3>; + phy-mode = "sgmii"; + }; + + /* Front-side USB slot */ + usb@50000 { + status = "okay"; + }; + + /* Back-side USB slot */ + usb@51000 { + status = "okay"; + }; + + spi0: spi@10600 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; + }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + }; + }; + }; +}; diff --git a/arch/arm/dts/armada-xp-synology-ds414.dts b/arch/arm/dts/armada-xp-synology-ds414.dts new file mode 100644 index 00000000000..0a60ddfa414 --- /dev/null +++ b/arch/arm/dts/armada-xp-synology-ds414.dts @@ -0,0 +1,337 @@ +/* + * Device Tree file for Synology DS414 + * + * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the old 0xd0000000). + * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot + * bootloaders provided by Marvell. It is used in recent versions of + * DSM software provided by Synology. Nonetheless, some earlier boards + * were delivered with an older version of u-boot that left internal + * registers mapped at 0xd0000000. If you have such a device you will + * not be able to directly boot a kernel based on this Device Tree. In + * that case, the preferred solution is to update your bootloader (e.g. + * by upgrading to latest version of DSM, or building a new one and + * installing it from u-boot prompt) or adjust the Devive Tree + * (s/0xf1000000/0xd0000000/ in 'ranges' below). + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include "armada-xp-mv78230.dtsi" + +/ { + model = "Synology DS414"; + compatible = "synology,ds414", "marvell,armadaxp-mv78230", + "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + aliases { + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x40000000>; /* 1GB */ + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>; + + pcie-controller { + status = "okay"; + + /* + * Connected to Marvell 88SX7042 SATA-II controller + * handling the four disks. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* + * Connected to EtronTech EJ168A XHCI controller + * providing the two rear USB 3.0 ports. + */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + + internal-regs { + + /* RTC is provided by Seiko S-35390A below */ + rtc@10300 { + status = "disabled"; + }; + + spi0: spi@10600 { + status = "okay"; + u-boot,dm-pre-reloc; + + spi-flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q064"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + + /* + * Warning! + * + * Synology u-boot uses its compiled-in environment + * and it seems Synology did not care to change u-boot + * default configuration in order to allow saving a + * modified environment at a sensible location. So, + * if you do a 'saveenv' under u-boot, your modified + * environment will be saved at 1MB after the start + * of the flash, i.e. in the middle of the uImage. + * For that reason, it is strongly advised not to + * change the default environment, unless you know + * what you are doing. + */ + partition@00000000 { /* u-boot */ + label = "RedBoot"; + reg = <0x00000000 0x000d0000>; /* 832KB */ + }; + + partition@000c0000 { /* uImage */ + label = "zImage"; + reg = <0x000d0000 0x002d0000>; /* 2880KB */ + }; + + partition@003a0000 { /* uInitramfs */ + label = "rd.gz"; + reg = <0x003a0000 0x00430000>; /* 4250KB */ + }; + + partition@007d0000 { /* MAC address and serial number */ + label = "vendor"; + reg = <0x007d0000 0x00010000>; /* 64KB */ + }; + + partition@007e0000 { + label = "RedBoot config"; + reg = <0x007e0000 0x00010000>; /* 64KB */ + }; + + partition@007f0000 { + label = "FIS directory"; + reg = <0x007f0000 0x00010000>; /* 64KB */ + }; + }; + }; + + i2c@11000 { + clock-frequency = <400000>; + status = "okay"; + + s35390a: s35390a@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + }; + + /* Connected to a header on device's PCB. This + * provides the main console for the device. + * + * Warning: the device may not boot with a 3.3V + * USB-serial converter connected when the power + * button is pressed. The converter needs to be + * connected a few seconds after pressing the + * power button. This is possibly due to UART0_TXD + * pin being sampled at reset (bit 0 of SAR). + */ + serial@12000 { + status = "okay"; + u-boot,dm-pre-reloc; + }; + + /* Connected to a Microchip PIC16F883 for power control */ + serial@12100 { + status = "okay"; + }; + + poweroff@12100 { + compatible = "synology,power-off"; + reg = <0x12100 0x100>; + clocks = <&coreclk 0>; + }; + + /* Front USB 2.0 port */ + usb@50000 { + status = "okay"; + }; + + mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1512 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1512 */ + reg = <1>; + }; + }; + + ethernet@70000 { + status = "okay"; + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin + &sata3_pwr_pin &sata4_pwr_pin>; + pinctrl-names = "default"; + + sata1_regulator: sata1-regulator { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <2000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + sata2_regulator: sata2-regulator { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "SATA2 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <4000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + sata3_regulator: sata3-regulator { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "SATA3 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <6000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + + sata4_regulator: sata4-regulator { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "SATA4 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <8000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinctrl { + sata1_pwr_pin: sata1-pwr-pin { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + sata2_pwr_pin: sata2-pwr-pin { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + sata3_pwr_pin: sata3-pwr-pin { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + sata4_pwr_pin: sata4-pwr-pin { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + sata1_pres_pin: sata1-pres-pin { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + sata2_pres_pin: sata2-pres-pin { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + + sata3_pres_pin: sata3-pres-pin { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + sata4_pres_pin: sata4-pres-pin { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + syno_id_bit0_pin: syno-id-bit0-pin { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + + syno_id_bit1_pin: syno-id-bit1-pin { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + syno_id_bit2_pin: syno-id-bit2-pin { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + fan1_alarm_pin: fan1-alarm-pin { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + + fan2_alarm_pin: fan2-alarm-pin { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/dts/armada-xp.dtsi b/arch/arm/dts/armada-xp.dtsi index 3de9b761cc1..3fac39e41d7 100644 --- a/arch/arm/dts/armada-xp.dtsi +++ b/arch/arm/dts/armada-xp.dtsi @@ -63,6 +63,7 @@ soc { compatible = "marvell,armadaxp-mbus", "simple-bus"; + u-boot,dm-pre-reloc; bootrom { compatible = "marvell,bootrom"; diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts index e4daa991e95..797d411d6f7 100644 --- a/arch/arm/dts/dra7-evm.dts +++ b/arch/arm/dts/dra7-evm.dts @@ -487,7 +487,7 @@ spi-max-frequency = <48000000>; m25p80@0 { - compatible = "s25fl256s1"; + compatible = "s25fl256s1","spi-flash"; spi-max-frequency = <48000000>; reg = <0>; spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi index feb3708dc62..e7fecf76564 100644 --- a/arch/arm/dts/dra7.dtsi +++ b/arch/arm/dts/dra7.dtsi @@ -41,6 +41,7 @@ ethernet1 = &cpsw_emac1; d_can0 = &dcan1; d_can1 = &dcan2; + spi0 = &qspi; }; timer { @@ -1113,8 +1114,11 @@ qspi: qspi@4b300000 { compatible = "ti,dra7xxx-qspi"; - reg = <0x4b300000 0x100>; - reg-names = "qspi_base"; + reg = <0x4b300000 0x100>, + <0x5c000000 0x4000000>, + <0x4a002558 0x4>; + reg-names = "qspi_base", "qspi_mmap", + "qspi_ctrlmod"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "qspi"; diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts index efb544c6bb6..a62550f0e02 100644 --- a/arch/arm/dts/dra72-evm.dts +++ b/arch/arm/dts/dra72-evm.dts @@ -604,7 +604,7 @@ spi-max-frequency = <48000000>; m25p80@0 { - compatible = "s25fl256s1"; + compatible = "s25fl256s1","spi-flash"; spi-max-frequency = <48000000>; reg = <0>; spi-tx-bus-width = <1>; diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index d76514e4cb7..3b7f6bdb720 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -16,35 +16,21 @@ #define CONFIG_NR_DRAM_BANKS_MAX 2 /* UART configuration */ -#if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2) -#elif (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ +#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ (CONFIG_SYS_LPC32XX_UART == 7) +#if !defined(CONFIG_LPC32XX_HSUART) #define CONFIG_LPC32XX_HSUART -#else -#error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7" #endif - -#if defined(CONFIG_SYS_NS16550_SERIAL) - -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#define CONFIG_SYS_NS16550_COM1 UART3_BASE -#define CONFIG_SYS_NS16550_COM2 UART4_BASE -#define CONFIG_SYS_NS16550_COM3 UART5_BASE -#define CONFIG_SYS_NS16550_COM4 UART6_BASE #endif -#if defined(CONFIG_LPC32XX_HSUART) -#if CONFIG_SYS_LPC32XX_UART == 1 -#define HS_UART_BASE HS_UART1_BASE -#elif CONFIG_SYS_LPC32XX_UART == 2 -#define HS_UART_BASE HS_UART2_BASE -#else /* CONFIG_SYS_LPC32XX_UART == 7 */ -#define HS_UART_BASE HS_UART7_BASE +#if !defined(CONFIG_SYS_NS16550_CLK) +#define CONFIG_SYS_NS16550_CLK 13000000 #endif + +#if !defined(CONFIG_LPC32XX_HSUART) +#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2) +#else +#define CONFIG_CONS_INDEX CONFIG_SYS_LPC32XX_UART #endif #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 80548ebbf6d..2f4c14e96bf 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -83,8 +83,11 @@ ENTRY(_main) bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ #endif mov r0, sp - bl board_init_f_mem + bl board_init_f_alloc_reserve mov sp, r0 + /* set up gd here, outside any C code */ + mov r9, r0 + bl board_init_f_init_reserve mov r0, #0 bl board_init_f @@ -133,6 +136,7 @@ here: bl spl_relocate_stack_gd cmp r0, #0 movne sp, r0 + movne r9, r0 # endif ldr r0, =__bss_start /* this is auto-relocated! */ diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index cef1c7171c6..cad22c7b41f 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -75,8 +75,12 @@ ENTRY(_main) ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) #endif bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ - bl board_init_f_mem + mov x0, sp + bl board_init_f_alloc_reserve mov sp, x0 + /* set up gd here, outside any C code */ + mov x18, x0 + bl board_init_f_init_reserve mov x0, #0 bl board_init_f diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index d0493950363..0c4309ff007 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -135,4 +135,9 @@ #define CONFIG_SYS_I2C_SPEED 100000 #endif +/* Use common timer */ +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK + #endif /* _KW_CONFIG_H */ diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 79ff0e82786..b9628462eab 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -1,31 +1,74 @@ if ARCH_MVEBU +config ARMADA_38X + bool + +config ARMADA_XP + bool + +config MV78230 + bool + select ARMADA_XP + +config MV78260 + bool + select ARMADA_XP + +config MV78460 + bool + select ARMADA_XP + +config DB_88F6820_GP + bool + select ARMADA_38X + choice prompt "Marvell MVEBU (Armada XP/38x) board select" optional +config TARGET_CLEARFOG + bool "Support ClearFog" + select DB_88F6820_GP + config TARGET_DB_88F6820_GP bool "Support DB-88F6820-GP" + select DB_88F6820_GP config TARGET_DB_MV784MP_GP bool "Support db-mv784mp-gp" + select MV78460 + +config TARGET_DS414 + bool "Support Synology DS414" + select MV78230 config TARGET_MAXBCM bool "Support maxbcm" + select MV78460 endchoice -config SYS_SOC - default "mvebu" +config SYS_BOARD + default "clearfog" if TARGET_CLEARFOG + default "db-88f6820-gp" if TARGET_DB_88F6820_GP + default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP + default "ds414" if TARGET_DS414 + default "maxbcm" if TARGET_MAXBCM -config MVEBU_BOOTROM_UARTBOOT - bool "Use kwboot to boot via BootROM xmodem protocol" - help - This option provides support for booting via the Marvell - xmodem protocol, used by the kwboot tool. +config SYS_CONFIG_NAME + default "clearfog" if TARGET_CLEARFOG + default "db-88f6820-gp" if TARGET_DB_88F6820_GP + default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP + default "ds414" if TARGET_DS414 + default "maxbcm" if TARGET_MAXBCM - Please don't forget to configure the boot device in - the board specific kwbimage.cfg file this way: - BOOT_FROM uart +config SYS_VENDOR + default "Marvell" if TARGET_DB_MV784MP_GP + default "Marvell" if TARGET_DB_88F6820_GP + default "solidrun" if TARGET_CLEARFOG + default "Synology" if TARGET_DS414 + +config SYS_SOC + default "mvebu" endif diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 21c56a4d969..b96b81bd393 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -15,8 +15,8 @@ else obj-y = cpu.o obj-y += dram.o ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += ../../../drivers/ddr/marvell/a38x/xor.o -obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += ../../../drivers/ddr/marvell/axp/xor.o +obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o +obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o endif obj-y += gpio.o obj-y += mbus.o @@ -24,7 +24,7 @@ obj-y += timer.o obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o -obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += serdes/a38x/ -obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += serdes/axp/ +obj-$(CONFIG_ARMADA_38X) += serdes/a38x/ +obj-$(CONFIG_ARMADA_XP) += serdes/axp/ endif diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 895ad929b10..30b175c6465 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -1,11 +1,10 @@ /* - * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> + * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> -#include <netdev.h> #include <ahci.h> #include <linux/mbus.h> #include <asm/io.h> @@ -50,25 +49,106 @@ int mvebu_soc_family(void) { u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; - if (devid == SOC_MV78460_ID) + switch (devid) { + case SOC_MV78230_ID: + case SOC_MV78260_ID: + case SOC_MV78460_ID: return MVEBU_SOC_AXP; - - if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID || - devid == SOC_88F6828_ID) + case SOC_88F6810_ID: + case SOC_88F6820_ID: + case SOC_88F6828_ID: return MVEBU_SOC_A38X; - + } return MVEBU_SOC_UNKNOWN; } #if defined(CONFIG_DISPLAY_CPUINFO) + +#if defined(CONFIG_ARMADA_38X) +/* SAR frequency values for Armada 38x */ +static const struct sar_freq_modes sar_freq_tab[] = { + { 0x0, 0x0, 666, 333, 333 }, + { 0x2, 0x0, 800, 400, 400 }, + { 0x4, 0x0, 1066, 533, 533 }, + { 0x6, 0x0, 1200, 600, 600 }, + { 0x8, 0x0, 1332, 666, 666 }, + { 0xc, 0x0, 1600, 800, 800 }, + { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ +}; +#else +/* SAR frequency values for Armada XP */ +static const struct sar_freq_modes sar_freq_tab[] = { + { 0xa, 0x5, 800, 400, 400 }, + { 0x1, 0x5, 1066, 533, 533 }, + { 0x2, 0x5, 1200, 600, 600 }, + { 0x2, 0x9, 1200, 600, 400 }, + { 0x3, 0x5, 1333, 667, 667 }, + { 0x4, 0x5, 1500, 750, 750 }, + { 0x4, 0x9, 1500, 750, 500 }, + { 0xb, 0x9, 1600, 800, 533 }, + { 0xb, 0xa, 1600, 800, 640 }, + { 0xb, 0x5, 1600, 800, 800 }, + { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ +}; +#endif + +void get_sar_freq(struct sar_freq_modes *sar_freq) +{ + u32 val; + u32 freq; + int i; + + val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ + freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS; +#if !defined(CONFIG_ARMADA_38X) + /* + * Shift CPU0 clock frequency select bit from SAR2 register + * into correct position + */ + freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK) + >> SAR2_CPU_FREQ_OFFS) << 3; +#endif + for (i = 0; sar_freq_tab[i].val != 0xff; i++) { + if (sar_freq_tab[i].val == freq) { +#if defined(CONFIG_ARMADA_38X) + *sar_freq = sar_freq_tab[i]; + return; +#else + int k; + u8 ffc; + + ffc = (val & SAR_FFC_FREQ_MASK) >> + SAR_FFC_FREQ_OFFS; + for (k = i; sar_freq_tab[k].ffc != 0xff; k++) { + if (sar_freq_tab[k].ffc == ffc) { + *sar_freq = sar_freq_tab[k]; + return; + } + } + i = k; +#endif + } + } + + /* SAR value not found, return 0 for frequencies */ + *sar_freq = sar_freq_tab[i - 1]; +} + int print_cpuinfo(void) { u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; + struct sar_freq_modes sar_freq; puts("SoC: "); switch (devid) { + case SOC_MV78230_ID: + puts("MV78230-"); + break; + case SOC_MV78260_ID: + puts("MV78260-"); + break; case SOC_MV78460_ID: puts("MV78460-"); break; @@ -89,13 +169,13 @@ int print_cpuinfo(void) if (mvebu_soc_family() == MVEBU_SOC_AXP) { switch (revid) { case 1: - puts("A0\n"); + puts("A0"); break; case 2: - puts("B0\n"); + puts("B0"); break; default: - printf("?? (%x)\n", revid); + printf("?? (%x)", revid); break; } } @@ -103,17 +183,20 @@ int print_cpuinfo(void) if (mvebu_soc_family() == MVEBU_SOC_A38X) { switch (revid) { case MV_88F68XX_Z1_ID: - puts("Z1\n"); + puts("Z1"); break; case MV_88F68XX_A0_ID: - puts("A0\n"); + puts("A0"); break; default: - printf("?? (%x)\n", revid); + printf("?? (%x)", revid); break; } } + get_sar_freq(&sar_freq); + printf(" at %d MHz\n", sar_freq.p_clk); + return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ @@ -199,10 +282,10 @@ static void setup_usb_phys(void) clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605); /* Power up PLL and PHY channel */ - clrsetbits_le32(MV_USB_PHY_PLL_REG(2), 0, BIT(9)); + setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9)); /* Assert VCOCAL_START */ - clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0, BIT(21)); + setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21)); mdelay(1); @@ -211,18 +294,20 @@ static void setup_usb_phys(void) */ for (dev = 0; dev < 3; dev++) { - clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), 0, BIT(15)); + setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15)); /* Assert REG_RCAL_START in channel REG 1 */ - clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), 0, BIT(12)); + setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); udelay(40); - clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12), 0); + clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); } } +/* + * This function is not called from the SPL U-Boot version + */ int arch_cpu_init(void) { -#if !defined(CONFIG_SPL_BUILD) struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; @@ -233,27 +318,26 @@ int arch_cpu_init(void) * still locked to cache. */ mmu_disable(); -#endif /* Linux expects the internal registers to be at 0xf1000000 */ writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); set_cbar(SOC_REGS_PHY_BASE + 0xC000); -#if !defined(CONFIG_SPL_BUILD) /* * From this stage on, the SoC detection is working. As we have * configured the internal register base to the value used * in the macros / defines in the U-Boot header (soc.h). */ - /* - * To fully release / unlock this area from cache, we need - * to flush all caches and disable the L2 cache. - */ - icache_disable(); - dcache_disable(); - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); -#endif + if (mvebu_soc_family() == MVEBU_SOC_A38X) { + /* + * To fully release / unlock this area from cache, we need + * to flush all caches and disable the L2 cache. + */ + icache_disable(); + dcache_disable(); + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + } /* * We need to call mvebu_mbus_probe() before calling @@ -326,30 +410,6 @@ int arch_misc_init(void) } #endif /* CONFIG_ARCH_MISC_INIT */ -#ifdef CONFIG_MVNETA -int cpu_eth_init(bd_t *bis) -{ - u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE, - MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE }; - u8 phy_addr[] = CONFIG_PHY_ADDR; - int i; - - /* - * Only Armada XP supports all 4 ethernet interfaces. A38x has - * slightly different base addresses for its 2-3 interfaces. - */ - if (mvebu_soc_family() != MVEBU_SOC_AXP) { - enet_base[1] = MVEBU_EGIGA2_BASE; - enet_base[2] = MVEBU_EGIGA3_BASE; - } - - for (i = 0; i < ARRAY_SIZE(phy_addr); i++) - mvneta_initialize(bis, enet_base[i], i, phy_addr[i]); - - return 0; -} -#endif - #ifdef CONFIG_MV_SDHCI int board_mmc_init(bd_t *bis) { @@ -413,20 +473,43 @@ void scsi_init(void) } #endif -#ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { - struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; - - /* First disable L2 cache - may still be enable from BootROM */ - if (mvebu_soc_family() == MVEBU_SOC_A38X) - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - /* Avoid problem with e.g. neta ethernet driver */ invalidate_dcache_all(); /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } -#endif + +void v7_outer_cache_enable(void) +{ + if (mvebu_soc_family() == MVEBU_SOC_AXP) { + struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + u32 u; + + /* The L2 cache is already disabled at this point */ + + /* + * For Aurora cache in no outer mode, enable via the CP15 + * coprocessor broadcasting of cache commands to L2. + */ + asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u)); + u |= BIT(8); /* Set the FW bit */ + asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); + + isb(); + + /* Enable the L2 cache */ + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + } +} + +void v7_outer_cache_disable(void) +{ + struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index ddc5b7ee3ea..a8ec5ea21b6 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -12,11 +12,8 @@ #include <asm/arch/cpu.h> #include <asm/arch/soc.h> -#ifdef CONFIG_SYS_MVEBU_DDR_A38X -#include "../../../drivers/ddr/marvell/axp/xor.h" -#include "../../../drivers/ddr/marvell/axp/xor_regs.h" -#endif -#ifdef CONFIG_SYS_MVEBU_DDR_AXP +#if defined(CONFIG_ARCH_MVEBU) +/* Use common XOR definitions for A3x and AXP */ #include "../../../drivers/ddr/marvell/axp/xor.h" #include "../../../drivers/ddr/marvell/axp/xor_regs.h" #endif @@ -112,7 +109,7 @@ void mvebu_sdram_size_adjust(enum memory_bank bank) mvebu_sdram_bs_set(bank, size); } -#if defined(CONFIG_SYS_MVEBU_DDR_A38X) || defined(CONFIG_SYS_MVEBU_DDR_AXP) +#if defined(CONFIG_ARCH_MVEBU) static u32 xor_ctrl_save; static u32 xor_base_save; static u32 xor_mask_save; @@ -292,11 +289,18 @@ void dram_init_banksize(void) } } +#if defined(CONFIG_ARCH_MVEBU) void board_add_ram_info(int use_default) { + struct sar_freq_modes sar_freq; + + get_sar_freq(&sar_freq); + printf(" (%d MHz, ", sar_freq.d_clk); + if (ecc_enabled()) - printf(" (ECC"); + printf("ECC"); else - printf(" (ECC not"); + printf("ECC not"); printf(" enabled)"); } +#endif diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 1d49cab7fd8..cc1fc5f9d4b 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -17,12 +17,22 @@ #include <asm/arch/soc.h> -#if defined(CONFIG_ARMADA_XP) +#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_38X) +/* + * Set this for the common xor register definitions needed in dram.c + * for A38x as well here. + */ #define MV88F78X60 /* for the DDR training bin_hdr code */ #endif #define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_L2_PL310 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#endif + /* * By default kwbimage.cfg from board specific folder is used * If for some board, different configuration file need to be used, @@ -47,8 +57,7 @@ * SPI Flash configuration */ #ifdef CONFIG_CMD_SF -#define CONFIG_HARD_SPI 1 -#define CONFIG_KIRKWOOD_SPI 1 +#define CONFIG_KIRKWOOD_SPI #ifndef CONFIG_ENV_SPI_BUS # define CONFIG_ENV_SPI_BUS 0 #endif @@ -60,6 +69,9 @@ #endif #endif +/* Needed for SPI NOR booting in SPL */ +#define CONFIG_DM_SEQ_ALIAS 1 + /* * Ethernet Driver configuration */ @@ -85,9 +97,9 @@ #define CONFIG_SYS_I2C_SPEED 100000 #endif -/* Common SPL configuration */ -#ifndef CONFIG_SPL_LDSCRIPT -#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-mvebu/u-boot-spl.lds" -#endif +/* Use common timer */ +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) +#define CONFIG_SYS_TIMER_RATE 25000000 #endif /* __MVEBU_CONFIG_H */ diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 5e8bf0c4ce0..47f45c1512a 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -106,6 +106,14 @@ struct kwgpio_registers { u32 irq_level; }; +struct sar_freq_modes { + u8 val; + u8 ffc; /* Fabric Frequency Configuration */ + u32 p_clk; + u32 nb_clk; + u32 d_clk; +}; + /* Needed for dynamic (board-specific) mbus configuration */ extern struct mvebu_mbus_state mbus_state; @@ -123,6 +131,8 @@ void return_to_bootrom(void); int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); +void get_sar_freq(struct sar_freq_modes *sar_freq); + /* * Highspeed SERDES PHY config init, ported from bin_hdr * to mainline U-Boot diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 22abde080e1..cb216bc2cc6 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -11,6 +11,8 @@ #ifndef _MVEBU_SOC_H #define _MVEBU_SOC_H +#define SOC_MV78230_ID 0x7823 +#define SOC_MV78260_ID 0x7826 #define SOC_MV78460_ID 0x7846 #define SOC_88F6810_ID 0x6810 #define SOC_88F6820_ID 0x6820 @@ -33,10 +35,11 @@ #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) #if defined(CONFIG_SPL_BUILD) /* - * On A38x switching the regs base address without running from - * SDRAM doesn't seem to work. So let the SPL still use the - * default base address and switch to the new address in the - * main u-boot later. + * The SPL U-Boot version still runs with the default + * address for the internal registers, configured by + * the BootROM. Only the main U-Boot version uses the + * new internal register base address, that also is + * required for the Linux kernel. */ #define SOC_REGS_PHY_BASE 0xd0000000 #else @@ -47,10 +50,7 @@ #define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) #define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) #define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE -#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600)) #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) -#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000)) -#define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100)) #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) #define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100)) #define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140)) @@ -60,13 +60,9 @@ #define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000)) #define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180)) #define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300)) -#define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000)) -#define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000)) #define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000)) #define MVEBU_AXP_USB_BASE (MVEBU_REGISTER(0x50000)) #define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000)) -#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000)) -#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000)) #define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000)) #define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000)) #define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000)) @@ -101,4 +97,49 @@ #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE +#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8)) + +/* BootROM error register (also includes some status infos) */ +#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0)) +#define BOOTROM_ERR_MODE_OFFS 28 +#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS) +#define BOOTROM_ERR_MODE_UART 0x6 + +#if defined(CONFIG_ARMADA_38X) +/* SAR values for Armada 38x */ +#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) + +#define SAR_CPU_FREQ_OFFS 10 +#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) +#define SAR_BOOT_DEVICE_OFFS 4 +#define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS) + +#define BOOT_DEV_SEL_OFFS 4 +#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) + +#define BOOT_FROM_UART 0x28 +#define BOOT_FROM_SPI 0x32 +#define BOOT_FROM_MMC 0x30 +#define BOOT_FROM_MMC_ALT 0x31 +#else +/* SAR values for Armada XP */ +#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) +#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) + +#define SAR_CPU_FREQ_OFFS 21 +#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) +#define SAR_FFC_FREQ_OFFS 24 +#define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS) +#define SAR2_CPU_FREQ_OFFS 20 +#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS) +#define SAR_BOOT_DEVICE_OFFS 5 +#define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS) + +#define BOOT_DEV_SEL_OFFS 5 +#define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS) + +#define BOOT_FROM_UART 0x2 +#define BOOT_FROM_SPI 0x3 +#endif + #endif /* _MVEBU_SOC_H */ diff --git a/arch/arm/mach-mvebu/lowlevel_spl.S b/arch/arm/mach-mvebu/lowlevel_spl.S index 2e2181ecea5..49e0b906d58 100644 --- a/arch/arm/mach-mvebu/lowlevel_spl.S +++ b/arch/arm/mach-mvebu/lowlevel_spl.S @@ -5,7 +5,6 @@ #include <config.h> #include <linux/linkage.h> -#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT ENTRY(save_boot_params) stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */ ldr r12, =CONFIG_SPL_BOOTROM_SAVE @@ -19,11 +18,6 @@ ENTRY(return_to_bootrom) mov r0, #0x0 /* @ return value: 0x0 NO_ERR */ ldmfd sp!, {r0 - r12, pc} /* @ restore regs and return */ ENDPROC(return_to_bootrom) -#else -ENTRY(save_boot_params) - b save_boot_params_ret -ENDPROC(save_boot_params) -#endif /* * cache_inv - invalidate Cache line diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index 346278e1bee..df263bc3b39 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -491,7 +491,7 @@ int mvebu_mbus_probe(struct mbus_win windows[], int count) #if defined(CONFIG_KIRKWOOD) mbus_state.soc = &kirkwood_mbus_data; #endif -#if defined(CONFIG_ARMADA_XP) +#if defined(CONFIG_ARCH_MVEBU) mbus_state.soc = &armada_370_xp_mbus_data; #endif diff --git a/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h index 36e0ed80f0d..c8d9485b7bb 100644 --- a/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h +++ b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h @@ -32,7 +32,7 @@ #define BOARD_ID_BASE 0x0 /* New board ID numbers */ -#define DB_88F78XX0_BP_ID (BOARD_ID_BASE) +#define DB_88F78XX0_BP_ID (BOARD_ID_BASE + 1) #define RD_78460_SERVER_ID (DB_88F78XX0_BP_ID + 1) #define DB_78X60_PCAC_ID (RD_78460_SERVER_ID + 1) #define FPGA_88F78XX0_ID (DB_78X60_PCAC_ID + 1) @@ -44,7 +44,7 @@ #define DB_784MP_GP_ID (RD_78460_SERVER_REV2_ID + 1) #define RD_78460_CUSTOMER_ID (DB_784MP_GP_ID + 1) #define MV_MAX_BOARD_ID (RD_78460_CUSTOMER_ID + 1) -#define INVALID_BAORD_ID 0xFFFFFFFF +#define INVALID_BOARD_ID 0xFFFFFFFF /* Sample at Reset */ #define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4)) diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c index 702273aee12..afc0cefda3c 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c @@ -75,16 +75,24 @@ static u32 board_id_get(void) #endif } -static u8 board_sat_r_get(u8 dev_num, u8 reg) +__weak u8 board_sat_r_get(u8 dev_num, u8 reg) { u8 data; u8 *dev; u32 board_id = board_id_get(); int ret; - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - switch (board_id) { + case DB_78X60_AMC_ID: + case DB_78X60_PCAC_REV2_ID: + case RD_78460_CUSTOMER_ID: + case RD_78460_SERVER_ID: + case RD_78460_SERVER_REV2_ID: + case DB_78X60_PCAC_ID: + return (0x1 << 1) | 1; + case FPGA_88F78XX0_ID: + case RD_78460_NAS_ID: + return (0x0 << 1) | 1; case DB_784MP_GP_ID: dev = rd78460gp_twsi_dev; @@ -94,15 +102,12 @@ static u8 board_sat_r_get(u8 dev_num, u8 reg) dev = db88f78xx0rev2_twsi_dev; break; - case DB_78X60_PCAC_ID: - case FPGA_88F78XX0_ID: - case DB_78X60_PCAC_REV2_ID: - case RD_78460_SERVER_REV2_ID: default: return 0; } /* Read MPP module ID */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1); if (ret) return MV_ERROR; @@ -190,8 +195,17 @@ __weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) u16 ctrl_model_get(void) { - /* Right now only MV78460 supported */ + /* + * SoC version can't be autodetected. So we need to rely on a define + * from the config system here. + */ +#if defined(CONFIG_MV78230) + return MV_78230_DEV_ID; +#elif defined(CONFIG_MV78260) + return MV_78260_DEV_ID; +#else return MV_78460_DEV_ID; +#endif } u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info) @@ -202,6 +216,20 @@ u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info) return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF; } +static int serdes_max_lines_get(void) +{ + switch (ctrl_model_get()) { + case MV_78230_DEV_ID: + return 7; + case MV_78260_DEV_ID: + return 12; + case MV_78460_DEV_ID: + return 16; + } + + return 0; +} + int serdes_phy_config(void) { int status = MV_OK; @@ -221,39 +249,19 @@ int serdes_phy_config(void) u8 device_rev; u32 rx_high_imp_mode; u16 ctrl_mode; - u32 board_id = board_id_get(); u32 pex_if; u32 pex_if_num; /* - * TODO: - * Right now we only support the MV78460 with 16 serdes lines + * Get max. serdes lines count */ - max_serdes_lines = 16; + max_serdes_lines = serdes_max_lines_get(); if (max_serdes_lines == 0) return MV_OK; - switch (board_id) { - case DB_78X60_AMC_ID: - case DB_78X60_PCAC_REV2_ID: - case RD_78460_CUSTOMER_ID: - case RD_78460_SERVER_ID: - case RD_78460_SERVER_REV2_ID: - case DB_78X60_PCAC_ID: - satr11 = (0x1 << 1) | 1; - break; - case FPGA_88F78XX0_ID: - case RD_78460_NAS_ID: - satr11 = (0x0 << 1) | 1; - break; - case DB_88F78XX0_BP_REV2_ID: - case DB_784MP_GP_ID: - case DB_88F78XX0_BP_ID: - satr11 = board_sat_r_get(1, 1); - if ((u8) MV_ERROR == (u8) satr11) - return MV_ERROR; - break; - } + satr11 = board_sat_r_get(1, 1); + if ((u8) MV_ERROR == (u8) satr11) + return MV_ERROR; board_modules_scan(); memset(addr, 0, sizeof(addr)); @@ -1356,19 +1364,19 @@ int serdes_phy_config(void) pex_if, PEX_DEVICE_AND_VENDOR_ID)); devId &= 0xFFFF; devId |= ((ctrl_mode << 16) & 0xffff0000); - DEBUG_INIT_S("Update Device ID PEX"); - DEBUG_INIT_D(pex_if, 1); - DEBUG_INIT_D(devId, 8); - DEBUG_INIT_S("\n"); + DEBUG_INIT_FULL_S("Update Device ID PEX"); + DEBUG_INIT_FULL_D(pex_if, 1); + DEBUG_INIT_FULL_D(devId, 8); + DEBUG_INIT_FULL_S("\n"); reg_write(PEX_CFG_DIRECT_ACCESS (pex_if, PEX_DEVICE_AND_VENDOR_ID), devId); if ((pex_if < 8) && (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)) pex_if += 3; } - DEBUG_INIT_S("Update PEX Device ID 0x"); - DEBUG_INIT_D(ctrl_mode, 4); - DEBUG_INIT_S("0\n"); + DEBUG_INIT_FULL_S("Update PEX Device ID 0x"); + DEBUG_INIT_FULL_D(ctrl_mode, 4); + DEBUG_INIT_FULL_S("0\n"); } tmp = reg_read(PEX_DBG_STATUS_REG(0)); DEBUG_RD_REG(PEX_DBG_STATUS_REG(0), tmp); diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 0ab729aa5d8..0879873b972 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -1,10 +1,13 @@ /* - * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <dm.h> +#include <debug_uart.h> +#include <fdtdec.h> #include <spl.h> #include <asm/io.h> #include <asm/arch/cpu.h> @@ -12,14 +15,45 @@ DECLARE_GLOBAL_DATA_PTR; -u32 spl_boot_device(void) +static u32 get_boot_device(void) { -#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) - return BOOT_DEVICE_SPI; -#endif -#if defined(CONFIG_SPL_MMC_SUPPORT) - return BOOT_DEVICE_MMC1; + u32 val; + u32 boot_device; + + /* + * First check, if UART boot-mode is active. This can only + * be done, via the bootrom error register. Here the + * MSB marks if the UART mode is active. + */ + val = readl(CONFIG_BOOTROM_ERR_REG); + boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS; + debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device); + if (boot_device == BOOTROM_ERR_MODE_UART) + return BOOT_DEVICE_UART; + + /* + * Now check the SAR register for the strapped boot-device + */ + val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ + boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS; + debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device); + switch (boot_device) { +#ifdef CONFIG_SPL_MMC_SUPPORT + case BOOT_FROM_MMC: + case BOOT_FROM_MMC_ALT: + return BOOT_DEVICE_MMC1; #endif + case BOOT_FROM_UART: + return BOOT_DEVICE_UART; + case BOOT_FROM_SPI: + default: + return BOOT_DEVICE_SPI; + }; +} + +u32 spl_boot_device(void) +{ + return get_boot_device(); } #ifdef CONFIG_SPL_MMC_SUPPORT @@ -31,18 +65,7 @@ u32 spl_boot_mode(void) void board_init_f(ulong dummy) { -#ifndef CONFIG_MVEBU_BOOTROM_UARTBOOT - /* - * Only call arch_cpu_init() when not returning to the - * Marvell BootROM, which is done when booting via - * the xmodem protocol (kwboot tool). Otherwise the - * internal register will get remapped and the BootROM - * can't continue to run correctly. - */ - - /* Linux expects the internal registers to be at 0xf1000000 */ - arch_cpu_init(); -#endif + int ret; /* * Pin muxing needs to be done before UART output, since @@ -51,6 +74,27 @@ void board_init_f(ulong dummy) */ board_early_init_f(); + /* Example code showing how to enable the debug UART on MVEBU */ +#ifdef EARLY_UART + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ +#endif + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + /* Use special translation offset for SPL */ + dm_set_translation_offset(0xd0000000 - 0xf1000000); + preloader_console_init(); timer_init(); @@ -61,7 +105,6 @@ void board_init_f(ulong dummy) /* Setup DDR */ ddr3_init(); -#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT /* * Return to the BootROM to continue the Marvell xmodem * UART boot protocol. As initiated by the kwboot tool. @@ -73,6 +116,6 @@ void board_init_f(ulong dummy) * need to return to the BootROM to enable this xmodem * UART download. */ - return_to_bootrom(); -#endif + if (get_boot_device() == BOOT_DEVICE_UART) + return_to_bootrom(); } diff --git a/arch/arm/mach-mvebu/timer.c b/arch/arm/mach-mvebu/timer.c index 5449a8926c5..f5c2eaa808a 100644 --- a/arch/arm/mach-mvebu/timer.c +++ b/arch/arm/mach-mvebu/timer.c @@ -2,6 +2,8 @@ * Copyright (C) Marvell International Ltd. and its affiliates * Written-by: Prafulla Wadaskar <prafulla@marvell.com> * + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,108 +11,14 @@ #include <asm/io.h> #include <asm/arch/soc.h> -#define UBOOT_CNTR 0 /* counter to use for U-Boot timer */ - -/* - * ARM Timers Registers Map - */ -#define CNTMR_CTRL_REG &tmr_regs->ctrl -#define CNTMR_RELOAD_REG(tmrnum) &tmr_regs->tmr[tmrnum].reload -#define CNTMR_VAL_REG(tmrnum) &tmr_regs->tmr[tmrnum].val - -/* - * ARM Timers Control Register - * CPU_TIMERS_CTRL_REG (CTCR) - */ -#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) -#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) - -#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) -#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) - -/* Only Armada XP have the 25MHz enable bit (Kirkwood doesn't) */ -#if defined(CONFIG_ARMADA_XP) -#define CTCR_ARM_TIMER_25MHZ_OFFS(cntr) (cntr + 11) -#define CTCR_ARM_TIMER_25MHZ(cntr) (1 << CTCR_ARM_TIMER_25MHZ_OFFS(cntr)) -#else -#define CTCR_ARM_TIMER_25MHZ(cntr) 0 -#endif - -#define TIMER_LOAD_VAL 0xffffffff - -#define timestamp gd->arch.tbl -#define lastdec gd->arch.lastinc - -static int init_done __attribute__((section(".data"))) = 0; - -/* Timer reload and current value registers */ -struct kwtmr_val { - u32 reload; /* Timer reload reg */ - u32 val; /* Timer value reg */ -}; - -/* Timer registers */ -struct kwtmr_registers { - u32 ctrl; /* Timer control reg */ - u32 pad[3]; - struct kwtmr_val tmr[4]; - u32 wdt_reload; - u32 wdt_val; -}; - DECLARE_GLOBAL_DATA_PTR; -static struct kwtmr_registers *tmr_regs = - (struct kwtmr_registers *)MVEBU_TIMER_BASE; - -static inline ulong read_timer(void) -{ - return readl(CNTMR_VAL_REG(UBOOT_CNTR)) / (CONFIG_SYS_TCLK / 1000); -} - -ulong get_timer_masked(void) -{ - ulong now = read_timer(); - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + - (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; - } - lastdec = now; +#define TIMER_LOAD_VAL 0xffffffff - return timestamp; -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -void __udelay(unsigned long usec) -{ - uint current; - ulong delayticks; - - current = readl(CNTMR_VAL_REG(UBOOT_CNTR)); - delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); - - if (current < delayticks) { - delayticks -= current; - while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ; - while ((TIMER_LOAD_VAL - delayticks) < - readl(CNTMR_VAL_REG(UBOOT_CNTR))) ; - } else { - while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) > - (current - delayticks)) ; - } -} +static int init_done __attribute__((section(".data"))) = 0; /* - * init the counter + * Timer initialization */ int timer_init(void) { @@ -120,35 +28,15 @@ int timer_init(void) init_done = 1; /* load value into timer */ - writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR)); - writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR)); + writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x10); + writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x14); +#if defined(CONFIG_ARCH_MVEBU) + /* On Armada XP / 38x ..., the 25MHz clock source needs to be enabled */ + setbits_le32(MVEBU_TIMER_BASE + 0x00, BIT(11)); +#endif /* enable timer in auto reload mode */ - clrsetbits_le32(CNTMR_CTRL_REG, CTCR_ARM_TIMER_25MHZ(UBOOT_CNTR), - CTCR_ARM_TIMER_EN(UBOOT_CNTR) | - CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR)); - - /* init the timestamp and lastdec value */ - lastdec = read_timer(); - timestamp = 0; + setbits_le32(MVEBU_TIMER_BASE + 0x00, 0x3); return 0; } - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - return (ulong)CONFIG_SYS_HZ; -} diff --git a/arch/arm/mach-mvebu/u-boot-spl.lds b/arch/arm/mach-mvebu/u-boot-spl.lds deleted file mode 100644 index eee1db49eed..00000000000 --- a/arch/arm/mach-mvebu/u-boot-spl.lds +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Aneesh V <aneesh@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ - LENGTH = CONFIG_SPL_MAX_SIZE } -MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ - LENGTH = CONFIG_SPL_BSS_MAX_SIZE } - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - .text : - { - __start = .; - arch/arm/cpu/armv7/start.o (.text*) - *(.text*) - *(.vectors) - } >.sram - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram - - . = ALIGN(4); - .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*_i2c_*))); - } >.sram - - . = ALIGN(4); - __image_copy_end = .; - - .end : - { - *(.__end) - } - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } >.sdram -} diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index b703c3c1f2c..1cc4a96bf41 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -11,7 +11,6 @@ else obj-$(CONFIG_ROCKCHIP_RK3288) += board.o endif obj-y += rk_timer.o -obj-y += rk_early_print.o obj-$(CONFIG_$(SPL_)ROCKCHIP_COMMON) += common.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c index 3a1491cab33..801548109b9 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <debug_uart.h> #include <asm/io.h> #include <asm/arch/grf_rk3036.h> #include <asm/arch/hardware.h> @@ -34,7 +35,7 @@ void board_init_f(ulong dummy) GPIO1C2_MASK << GPIO1C2_SHIFT, GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); - rk_uart_init((void *)DEBUG_UART_BASE); + debug_uart_init(); #endif rockchip_timer_init(); sdram_init(); @@ -53,3 +54,9 @@ void board_init_r(gd_t *id, ulong dest_addr) while (1) ; } + +void hang(void) +{ + while (1) + ; +} diff --git a/arch/arm/mach-rockchip/rk_early_print.c b/arch/arm/mach-rockchip/rk_early_print.c deleted file mode 100644 index a1c14b02104..00000000000 --- a/arch/arm/mach-rockchip/rk_early_print.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/io.h> -#include <asm/arch/uart.h> -#include <common.h> - -static struct rk_uart *uart_ptr; - -static void uart_wrtie_byte(char byte) -{ - writel(byte, &uart_ptr->rbr); - while (!(readl(&uart_ptr->lsr) & 0x40)) - ; -} - -void print(char *s) -{ - while (*s) { - if (*s == '\n') - uart_wrtie_byte('\r'); - uart_wrtie_byte(*s); - s++; - } -} - -void print_hex(unsigned int n) -{ - int i; - int temp; - - uart_wrtie_byte('0'); - uart_wrtie_byte('x'); - - for (i = 8; i > 0; i--) { - temp = (n >> (i - 1) * 4) & 0x0f; - if (temp < 10) - uart_wrtie_byte((char)(temp + '0')); - else - uart_wrtie_byte((char)(temp - 10 + 'a')); - } - uart_wrtie_byte('\n'); - uart_wrtie_byte('\r'); -} - -/* - * TODO: since rk3036 only 4K sram to use in SPL, for saving space, - * we implement uart driver this way, we should convert this to use - * ns16550 driver in future, which support DEBUG_UART in the standard way - */ -void rk_uart_init(void *base) -{ - uart_ptr = (struct rk_uart *)base; - writel(0x83, &uart_ptr->lcr); - writel(0x0d, &uart_ptr->rbr); - writel(0x03, &uart_ptr->lcr); - - /* fifo enable, sfe is shadow register of FCR[0] */ - writel(0x01, &uart_ptr->sfe); -} diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index fbfb204e6ec..48a387c9571 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -3,6 +3,7 @@ if TEGRA config TEGRA_COMMON bool "Tegra common options" select DM + select DM_ETH select DM_GPIO select DM_I2C select DM_KEYBOARD diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 9e6ac3a0ffc..03256be4030 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -70,8 +70,17 @@ config CMD_PINMON config CMD_DDRPHY_DUMP bool "Enable dump command of DDR PHY parameters" + depends on ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_PRO4 || \ + ARCH_UNIPHIER_PH1_SLD8 help The command "ddrphy" shows the resulting parameters of DDR PHY training; it is useful for the evaluation of DDR PHY training. +config CMD_DDRMPHY_DUMP + bool "Enable dump command of DDR Multi PHY parameters" + depends on ARCH_UNIPHIER_PROXSTREAM2 || ARCH_UNIPHIER_PH1_LD6B + help + The command "ddrmphy" shows the resulting parameters of DDR Multi PHY + training; it is useful for the evaluation of DDR Multi PHY training. + endif diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 5b19f93ea99..ea3ae5425e7 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -24,8 +24,6 @@ obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o obj-y += reset.o obj-y += cache_uniphier.o -obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o -obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o obj-y += pinctrl/ clk/ diff --git a/arch/arm/mach-uniphier/include/mach/arm-mpcore.h b/arch/arm/mach-uniphier/arm-mpcore.h index cf7cd46c10c..cf7cd46c10c 100644 --- a/arch/arm/mach-uniphier/include/mach/arm-mpcore.h +++ b/arch/arm/mach-uniphier/arm-mpcore.h diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c index e9d3761fde9..f82c7d1f8ea 100644 --- a/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c +++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/bcu-regs.h> -#include <mach/init.h> + +#include "../init.h" +#include "bcu-regs.h" #define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c index cb6f8627211..75ccd155b0d 100644 --- a/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c +++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/bcu-regs.h> -#include <mach/init.h> + +#include "../init.h" +#include "bcu-regs.h" #define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) diff --git a/arch/arm/mach-uniphier/include/mach/bcu-regs.h b/arch/arm/mach-uniphier/bcu/bcu-regs.h index 0dfd94e5d78..0dfd94e5d78 100644 --- a/arch/arm/mach-uniphier/include/mach/bcu-regs.h +++ b/arch/arm/mach-uniphier/bcu/bcu-regs.h diff --git a/arch/arm/mach-uniphier/board_common.c b/arch/arm/mach-uniphier/board_common.c index 198004b59b0..020ffcae1d5 100644 --- a/arch/arm/mach-uniphier/board_common.c +++ b/arch/arm/mach-uniphier/board_common.c @@ -5,7 +5,8 @@ */ #include <common.h> -#include <mach/micro-support-card.h> + +#include "micro-support-card.h" int board_init(void) { diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c index 5e0d246ce42..824da25ac77 100644 --- a/arch/arm/mach-uniphier/board_early_init_f.c +++ b/arch/arm/mach-uniphier/board_early_init_f.c @@ -4,9 +4,9 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <mach/init.h> -#include <mach/micro-support-card.h> -#include <mach/soc_info.h> +#include "init.h" +#include "micro-support-card.h" +#include "soc-info.h" int board_early_init_f(void) { diff --git a/arch/arm/mach-uniphier/board_early_init_r.c b/arch/arm/mach-uniphier/board_early_init_r.c index 28c7f822287..b26da3633f1 100644 --- a/arch/arm/mach-uniphier/board_early_init_r.c +++ b/arch/arm/mach-uniphier/board_early_init_r.c @@ -5,7 +5,8 @@ */ #include <common.h> -#include <mach/micro-support-card.h> + +#include "micro-support-card.h" int board_early_init_r(void) { diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index d075a11ca20..f12415022be 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -7,7 +7,8 @@ #include <common.h> #include <libfdt.h> #include <linux/kernel.h> -#include <mach/init.h> + +#include "init.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile index 0797d6e6157..be0de8f9a98 100644 --- a/arch/arm/mach-uniphier/boot-mode/Makefile +++ b/arch/arm/mach-uniphier/boot-mode/Makefile @@ -11,3 +11,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += boot-mode-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += boot-mode-ph1-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += boot-mode-proxstream2.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += boot-mode-proxstream2.o + +obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o diff --git a/arch/arm/mach-uniphier/include/mach/boot-device.h b/arch/arm/mach-uniphier/boot-mode/boot-device.h index 2ab5a535fa0..2ab5a535fa0 100644 --- a/arch/arm/mach-uniphier/include/mach/boot-device.h +++ b/arch/arm/mach-uniphier/boot-mode/boot-device.h diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c index f974d9f08d1..8334373f08c 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c @@ -7,9 +7,9 @@ #include <common.h> #include <spl.h> #include <linux/io.h> -#include <mach/boot-device.h> -#include <mach/sg-regs.h> -#include <mach/sbc-regs.h> + +#include "../sg-regs.h" +#include "boot-device.h" struct boot_device_info boot_device_table[] = { {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"}, diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c index c68cb59fc0c..0ec6a088797 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c @@ -7,9 +7,9 @@ #include <common.h> #include <spl.h> #include <linux/io.h> -#include <mach/boot-device.h> -#include <mach/sbc-regs.h> -#include <mach/sg-regs.h> + +#include "../sg-regs.h" +#include "boot-device.h" static struct boot_device_info boot_device_table[] = { {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c index c943e12db15..b0f3f9a805d 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c @@ -7,9 +7,9 @@ #include <common.h> #include <spl.h> #include <linux/io.h> -#include <mach/boot-device.h> -#include <mach/sg-regs.h> -#include <mach/sbc-regs.h> + +#include "../sg-regs.h" +#include "boot-device.h" static struct boot_device_info boot_device_table[] = { {BOOT_DEVICE_NONE, "Reserved"}, diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c index 10a47c6fccf..de129535850 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c @@ -7,10 +7,9 @@ #include <common.h> #include <spl.h> #include <linux/io.h> -#include <mach/boot-device.h> -#include <mach/init.h> -#include <mach/sbc-regs.h> -#include <mach/sg-regs.h> + +#include "../sg-regs.h" +#include "boot-device.h" static struct boot_device_info boot_device_table[] = { {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"}, diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c index c6cafa7919c..0c5749badbb 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c @@ -6,10 +6,10 @@ #include <common.h> #include <spl.h> -#include <linux/io.h> -#include <mach/boot-device.h> -#include <mach/sbc-regs.h> -#include <mach/soc_info.h> + +#include "../sbc/sbc-regs.h" +#include "../soc-info.h" +#include "boot-device.h" u32 spl_boot_device(void) { diff --git a/arch/arm/mach-uniphier/cmd_pinmon.c b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c index b15ee9dd60d..3ff756b7dda 100644 --- a/arch/arm/mach-uniphier/cmd_pinmon.c +++ b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c @@ -5,9 +5,10 @@ */ #include <common.h> -#include <mach/boot-device.h> -#include <mach/sbc-regs.h> -#include <mach/soc_info.h> + +#include "../sbc/sbc-regs.h" +#include "../soc-info.h" +#include "boot-device.h" static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/arch/arm/mach-uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/cache_uniphier.c index bf85ad6fd9a..b4ca8b69341 100644 --- a/arch/arm/mach-uniphier/cache_uniphier.c +++ b/arch/arm/mach-uniphier/cache_uniphier.c @@ -7,7 +7,8 @@ #include <common.h> #include <linux/io.h> #include <asm/armv7.h> -#include <mach/ssc-regs.h> + +#include "ssc-regs.h" #ifdef CONFIG_UNIPHIER_L2CACHE_ON static void uniphier_cache_maint_all(u32 operation) diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c index 8b95fbb008a..4de9bfb102c 100644 --- a/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c +++ b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" void ph1_ld4_clk_init(void) { diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c index 2e1b20a423c..3df017edd27 100644 --- a/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c +++ b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" void ph1_pro4_clk_init(void) { diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c b/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c index f78edbbe3fe..039da737d01 100644 --- a/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c +++ b/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" void ph1_pro5_clk_init(void) { diff --git a/arch/arm/mach-uniphier/clk/clk-proxstream2.c b/arch/arm/mach-uniphier/clk/clk-proxstream2.c index b494021ecfa..a528f048f76 100644 --- a/arch/arm/mach-uniphier/clk/clk-proxstream2.c +++ b/arch/arm/mach-uniphier/clk/clk-proxstream2.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" void proxstream2_clk_init(void) { diff --git a/arch/arm/mach-uniphier/cmd_ddrmphy.c b/arch/arm/mach-uniphier/cmd_ddrmphy.c new file mode 100644 index 00000000000..c18f099f2c0 --- /dev/null +++ b/arch/arm/mach-uniphier/cmd_ddrmphy.c @@ -0,0 +1,329 @@ +/* + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/io.h> + +#include "../init.h" +#include "ddrmphy-regs.h" + +/* Select either decimal or hexadecimal */ +#if 1 +#define PRINTF_FORMAT "%2d" +#else +#define PRINTF_FORMAT "%02x" +#endif +/* field separator */ +#define FS " " + +static void __iomem *get_phy_base(int ch) +{ + return (void __iomem *)(0x5b830000 + ch * 0x00200000); +} + +static int get_nr_ch(void) +{ + const struct uniphier_board_data *bd = uniphier_get_board_param(); + + return bd->dram_ch2_width ? 3 : 2; +} + +static int get_nr_datx8(int ch) +{ + unsigned int width; + + const struct uniphier_board_data *bd = uniphier_get_board_param(); + + switch (ch) { + case 0: + width = bd->dram_ch0_width; + break; + case 1: + width = bd->dram_ch1_width; + break; + default: + width = bd->dram_ch2_width; + break; + } + + return width / 8; +} + +static void print_bdl(void __iomem *reg, int n) +{ + u32 val = readl(reg); + int i; + + for (i = 0; i < n; i++) + printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f); +} + +static void dump_loop(void (*callback)(void __iomem *)) +{ + int ch, dx, nr_ch, nr_dx; + void __iomem *dx_base; + + nr_ch = get_nr_ch(); + + for (ch = 0; ch < nr_ch; ch++) { + dx_base = get_phy_base(ch) + DMPHY_DX_BASE; + nr_dx = get_nr_datx8(ch); + + for (dx = 0; dx < nr_dx; dx++) { + printf("CH%dDX%d:", ch, dx); + (*callback)(dx_base); + dx_base += DMPHY_DX_STRIDE; + printf("\n"); + } + } +} + +static void zq_dump(void) +{ + int ch, zq, nr_ch, nr_zq, i; + void __iomem *zq_base; + u32 dr, pr; + + printf("\n--- Impedance Data ---\n"); + printf(" ZPD ZPU OPD OPU ZDV ODV\n"); + + nr_ch = get_nr_ch(); + + for (ch = 0; ch < nr_ch; ch++) { + zq_base = get_phy_base(ch) + DMPHY_ZQ_BASE; + nr_zq = 3; + + for (zq = 0; zq < nr_zq; zq++) { + printf("CH%dZQ%d:", ch, zq); + + dr = readl(zq_base + DMPHY_ZQ_DR); + for (i = 0; i < 4; i++) { + printf(FS PRINTF_FORMAT, dr & 0x7f); + dr >>= 7; + } + + pr = readl(zq_base + DMPHY_ZQ_PR); + for (i = 0; i < 2; i++) { + printf(FS PRINTF_FORMAT, pr & 0xf); + pr >>= 4; + } + + zq_base += DMPHY_ZQ_STRIDE; + printf("\n"); + } + } +} + +static void __wbdl_dump(void __iomem *dx_base) +{ + print_bdl(dx_base + DMPHY_DX_BDLR0, 4); + print_bdl(dx_base + DMPHY_DX_BDLR1, 4); + print_bdl(dx_base + DMPHY_DX_BDLR2, 2); + + printf(FS "(+" PRINTF_FORMAT ")", + readl(dx_base + DMPHY_DX_LCDLR1) & 0xff); +} + +static void wbdl_dump(void) +{ + printf("\n--- Write Bit Delay Line ---\n"); + printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n"); + + dump_loop(&__wbdl_dump); +} + +static void __rbdl_dump(void __iomem *dx_base) +{ + print_bdl(dx_base + DMPHY_DX_BDLR3, 4); + print_bdl(dx_base + DMPHY_DX_BDLR4, 4); + print_bdl(dx_base + DMPHY_DX_BDLR5, 1); + + printf(FS "(+" PRINTF_FORMAT ")", + (readl(dx_base + DMPHY_DX_LCDLR1) >> 8) & 0xff); + + printf(FS "(+" PRINTF_FORMAT ")", + (readl(dx_base + DMPHY_DX_LCDLR1) >> 16) & 0xff); +} + +static void rbdl_dump(void) +{ + printf("\n--- Read Bit Delay Line ---\n"); + printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD) (RDQSND)\n"); + + dump_loop(&__rbdl_dump); +} + +static void __wld_dump(void __iomem *dx_base) +{ + int rank; + u32 lcdlr0 = readl(dx_base + DMPHY_DX_LCDLR0); + u32 gtr = readl(dx_base + DMPHY_DX_GTR); + + for (rank = 0; rank < 4; rank++) { + u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */ + u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */ + + printf(FS PRINTF_FORMAT "%sT", wld, + wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1"); + } +} + +static void wld_dump(void) +{ + printf("\n--- Write Leveling Delay ---\n"); + printf(" Rank0 Rank1 Rank2 Rank3\n"); + + dump_loop(&__wld_dump); +} + +static void __dqsgd_dump(void __iomem *dx_base) +{ + int rank; + u32 lcdlr2 = readl(dx_base + DMPHY_DX_LCDLR2); + u32 gtr = readl(dx_base + DMPHY_DX_GTR); + + for (rank = 0; rank < 4; rank++) { + u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */ + u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */ + + printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl); + } +} + +static void dqsgd_dump(void) +{ + printf("\n--- DQS Gating Delay ---\n"); + printf(" Rank0 Rank1 Rank2 Rank3\n"); + + dump_loop(&__dqsgd_dump); +} + +static void __mdl_dump(void __iomem *dx_base) +{ + int i; + u32 mdl = readl(dx_base + DMPHY_DX_MDLR); + + for (i = 0; i < 3; i++) + printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff); +} + +static void mdl_dump(void) +{ + printf("\n--- Master Delay Line ---\n"); + printf(" IPRD TPRD MDLD\n"); + + dump_loop(&__mdl_dump); +} + +#define REG_DUMP(x) \ + { int ofst = DMPHY_ ## x; void __iomem *reg = phy_base + ofst; \ + printf("%3d: %-10s: %p : %08x\n", \ + ofst >> DMPHY_SHIFT, #x, reg, readl(reg)); } + +#define DX_REG_DUMP(dx, x) \ + { int ofst = DMPHY_DX_BASE + DMPHY_DX_STRIDE * (dx) + \ + DMPHY_DX_## x; \ + void __iomem *reg = phy_base + ofst; \ + printf("%3d: DX%d%-7s: %p : %08x\n", \ + ofst >> DMPHY_SHIFT, (dx), #x, reg, readl(reg)); } + +static void reg_dump(void) +{ + int ch, dx, nr_ch, nr_dx; + void __iomem *phy_base; + + printf("\n--- DDR PHY registers ---\n"); + + nr_ch = get_nr_ch(); + + for (ch = 0; ch < nr_ch; ch++) { + phy_base = get_phy_base(ch); + nr_dx = get_nr_datx8(ch); + + printf("== Ch%d ==\n", ch); + printf(" No: Name : Address : Data\n"); + + REG_DUMP(RIDR); + REG_DUMP(PIR); + REG_DUMP(PGCR0); + REG_DUMP(PGCR1); + REG_DUMP(PGCR2); + REG_DUMP(PGCR3); + REG_DUMP(PGSR0); + REG_DUMP(PGSR1); + REG_DUMP(PLLCR); + REG_DUMP(PTR0); + REG_DUMP(PTR1); + REG_DUMP(PTR2); + REG_DUMP(PTR3); + REG_DUMP(PTR4); + REG_DUMP(ACMDLR); + REG_DUMP(ACBDLR0); + REG_DUMP(DXCCR); + REG_DUMP(DSGCR); + REG_DUMP(DCR); + REG_DUMP(DTPR0); + REG_DUMP(DTPR1); + REG_DUMP(DTPR2); + REG_DUMP(DTPR3); + REG_DUMP(MR0); + REG_DUMP(MR1); + REG_DUMP(MR2); + REG_DUMP(MR3); + + for (dx = 0; dx < nr_dx; dx++) { + DX_REG_DUMP(dx, GCR0); + DX_REG_DUMP(dx, GCR1); + DX_REG_DUMP(dx, GCR2); + DX_REG_DUMP(dx, GCR3); + DX_REG_DUMP(dx, GTR); + } + } +} + +static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char *cmd = argv[1]; + + if (argc == 1) + cmd = "all"; + + if (!strcmp(cmd, "zq") || !strcmp(cmd, "all")) + zq_dump(); + + if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all")) + wbdl_dump(); + + if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all")) + rbdl_dump(); + + if (!strcmp(cmd, "wld") || !strcmp(cmd, "all")) + wld_dump(); + + if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all")) + dqsgd_dump(); + + if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all")) + mdl_dump(); + + if (!strcmp(cmd, "reg") || !strcmp(cmd, "all")) + reg_dump(); + + return 0; +} + +U_BOOT_CMD( + ddrm, 2, 1, do_ddrm, + "UniPhier DDR PHY parameters dumper", + "- dump all of the followings\n" + "ddrm zq - dump Impedance Data\n" + "ddrm wbdl - dump Write Bit Delay\n" + "ddrm rbdl - dump Read Bit Delay\n" + "ddrm wld - dump Write Leveling\n" + "ddrm dqsgd - dump DQS Gating Delay\n" + "ddrm mdl - dump Master Delay Line\n" + "ddrm reg - dump registers\n" +); diff --git a/arch/arm/mach-uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c index 935b209fa1f..4e9d01bafdc 100644 --- a/arch/arm/mach-uniphier/cpu_info.c +++ b/arch/arm/mach-uniphier/cpu_info.c @@ -6,7 +6,8 @@ #include <common.h> #include <linux/io.h> -#include <mach/sg-regs.h> + +#include "sg-regs.h" int print_cpuinfo(void) { diff --git a/arch/arm/mach-uniphier/debug_ll.S b/arch/arm/mach-uniphier/debug_ll.S index d8c9fe43e3e..6aa5f897a1a 100644 --- a/arch/arm/mach-uniphier/debug_ll.S +++ b/arch/arm/mach-uniphier/debug_ll.S @@ -8,9 +8,10 @@ #include <linux/serial_reg.h> #include <linux/linkage.h> -#include <mach/bcu-regs.h> -#include <mach/sc-regs.h> -#include <mach/sg-regs.h> + +#include "bcu/bcu-regs.h" +#include "sc-regs.h" +#include "sg-regs.h" #if !defined(CONFIG_DEBUG_SEMIHOSTING) #include CONFIG_DEBUG_LL_INCLUDE diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile index d3a767b5255..cab7df1653b 100644 --- a/arch/arm/mach-uniphier/dram/Makefile +++ b/arch/arm/mach-uniphier/dram/Makefile @@ -8,3 +8,8 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o \ ddrphy-training.o ddrphy-ph1-pro4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o \ ddrphy-training.o ddrphy-ph1-sld8.o +obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += umc-proxstream2.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += umc-proxstream2.o + +obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o +obj-$(CONFIG_CMD_DDRMPHY_DUMP) += cmd_ddrmphy.o diff --git a/arch/arm/mach-uniphier/cmd_ddrphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c index f9b79ab3d90..078eb6f71b4 100644 --- a/arch/arm/mach-uniphier/cmd_ddrphy.c +++ b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c @@ -6,7 +6,8 @@ #include <common.h> #include <linux/io.h> -#include <mach/ddrphy-regs.h> + +#include "ddrphy-regs.h" /* Select either decimal or hexadecimal */ #if 1 diff --git a/arch/arm/mach-uniphier/dram/ddrmphy-regs.h b/arch/arm/mach-uniphier/dram/ddrmphy-regs.h new file mode 100644 index 00000000000..569504d657d --- /dev/null +++ b/arch/arm/mach-uniphier/dram/ddrmphy-regs.h @@ -0,0 +1,146 @@ +/* + * UniPhier DDR MultiPHY registers + * + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_DDRMPHY_REGS_H +#define ARCH_DDRMPHY_REGS_H + +#include <linux/bitops.h> + +#define DMPHY_SHIFT 2 + +#define DMPHY_RIDR (0x000 << DMPHY_SHIFT) +#define DMPHY_PIR (0x001 << DMPHY_SHIFT) +#define DMPHY_PIR_INIT BIT(0) /* Initialization Trigger */ +#define DMPHY_PIR_ZCAL BIT(1) /* Impedance Calibration */ +#define DMPHY_PIR_PLLINIT BIT(4) /* PLL Initialization */ +#define DMPHY_PIR_DCAL BIT(5) /* DDL Calibration */ +#define DMPHY_PIR_PHYRST BIT(6) /* PHY Reset */ +#define DMPHY_PIR_DRAMRST BIT(7) /* DRAM Reset */ +#define DMPHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */ +#define DMPHY_PIR_WL BIT(9) /* Write Leveling */ +#define DMPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */ +#define DMPHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */ +#define DMPHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */ +#define DMPHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */ +#define DMPHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */ +#define DMPHY_PIR_WREYE BIT(15) /* Write Data Eye Training */ +#define DMPHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */ +#define DMPHY_PIR_INITBYP BIT(31) /* Initialization Bypass */ +#define DMPHY_PGCR0 (0x002 << DMPHY_SHIFT) +#define DMPHY_PGCR0_PHYFRST BIT(26) /* PHY FIFO Reset */ +#define DMPHY_PGCR1 (0x003 << DMPHY_SHIFT) +#define DMPHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */ +#define DMPHY_PGCR2 (0x004 << DMPHY_SHIFT) +#define DMPHY_PGCR2_DUALCHN BIT(28) /* Dual Channel Configuration*/ +#define DMPHY_PGCR2_ACPDDC BIT(29) /* AC Power-Down with Dual Ch*/ +#define DMPHY_PGCR3 (0x005 << DMPHY_SHIFT) +#define DMPHY_PGSR0 (0x006 << DMPHY_SHIFT) +#define DMPHY_PGSR0_IDONE BIT(0) /* Initialization Done */ +#define DMPHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */ +#define DMPHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */ +#define DMPHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */ +#define DMPHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */ +#define DMPHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */ +#define DMPHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */ +#define DMPHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */ +#define DMPHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */ +#define DMPHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */ +#define DMPHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */ +#define DMPHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */ +#define DMPHY_PGSR0_ZCERR BIT(20) /* Impedance Calib Error */ +#define DMPHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */ +#define DMPHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */ +#define DMPHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */ +#define DMPHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */ +#define DMPHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */ +#define DMPHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */ +#define DMPHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */ +#define DMPHY_PGSR1 (0x007 << DMPHY_SHIFT) +#define DMPHY_PGSR1_VTSTOP BIT(30) /* VT Stop */ +#define DMPHY_PLLCR (0x008 << DMPHY_SHIFT) +#define DMPHY_PTR0 (0x009 << DMPHY_SHIFT) +#define DMPHY_PTR1 (0x00A << DMPHY_SHIFT) +#define DMPHY_PTR2 (0x00B << DMPHY_SHIFT) +#define DMPHY_PTR3 (0x00C << DMPHY_SHIFT) +#define DMPHY_PTR4 (0x00D << DMPHY_SHIFT) +#define DMPHY_ACMDLR (0x00E << DMPHY_SHIFT) +#define DMPHY_ACLCDLR (0x00F << DMPHY_SHIFT) +#define DMPHY_ACBDLR0 (0x010 << DMPHY_SHIFT) +#define DMPHY_ACBDLR1 (0x011 << DMPHY_SHIFT) +#define DMPHY_ACBDLR2 (0x012 << DMPHY_SHIFT) +#define DMPHY_ACBDLR3 (0x013 << DMPHY_SHIFT) +#define DMPHY_ACBDLR4 (0x014 << DMPHY_SHIFT) +#define DMPHY_ACBDLR5 (0x015 << DMPHY_SHIFT) +#define DMPHY_ACBDLR6 (0x016 << DMPHY_SHIFT) +#define DMPHY_ACBDLR7 (0x017 << DMPHY_SHIFT) +#define DMPHY_ACBDLR8 (0x018 << DMPHY_SHIFT) +#define DMPHY_ACBDLR9 (0x019 << DMPHY_SHIFT) +#define DMPHY_ACIOCR0 (0x01A << DMPHY_SHIFT) +#define DMPHY_ACIOCR1 (0x01B << DMPHY_SHIFT) +#define DMPHY_ACIOCR2 (0x01C << DMPHY_SHIFT) +#define DMPHY_ACIOCR3 (0x01D << DMPHY_SHIFT) +#define DMPHY_ACIOCR4 (0x01E << DMPHY_SHIFT) +#define DMPHY_ACIOCR5 (0x01F << DMPHY_SHIFT) +#define DMPHY_DXCCR (0x020 << DMPHY_SHIFT) +#define DMPHY_DSGCR (0x021 << DMPHY_SHIFT) +#define DMPHY_DCR (0x022 << DMPHY_SHIFT) +#define DMPHY_DTPR0 (0x023 << DMPHY_SHIFT) +#define DMPHY_DTPR1 (0x024 << DMPHY_SHIFT) +#define DMPHY_DTPR2 (0x025 << DMPHY_SHIFT) +#define DMPHY_DTPR3 (0x026 << DMPHY_SHIFT) +#define DMPHY_MR0 (0x027 << DMPHY_SHIFT) +#define DMPHY_MR1 (0x028 << DMPHY_SHIFT) +#define DMPHY_MR2 (0x029 << DMPHY_SHIFT) +#define DMPHY_MR3 (0x02A << DMPHY_SHIFT) +#define DMPHY_ODTCR (0x02B << DMPHY_SHIFT) +#define DMPHY_DTCR (0x02C << DMPHY_SHIFT) +#define DMPHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */ +#define DMPHY_DTCR_RANKEN_MASK (0xf << (DMPHY_DTCR_RANKEN_SHIFT)) +#define DMPHY_DTAR0 (0x02D << DMPHY_SHIFT) +#define DMPHY_DTAR1 (0x02E << DMPHY_SHIFT) +#define DMPHY_DTAR2 (0x02F << DMPHY_SHIFT) +#define DMPHY_DTAR3 (0x030 << DMPHY_SHIFT) +#define DMPHY_DTDR0 (0x031 << DMPHY_SHIFT) +#define DMPHY_DTDR1 (0x032 << DMPHY_SHIFT) +#define DMPHY_DTEDR0 (0x033 << DMPHY_SHIFT) +#define DMPHY_DTEDR1 (0x034 << DMPHY_SHIFT) +#define DMPHY_ZQCR (0x090 << DMPHY_SHIFT) +#define DMPHY_ZQCR_AVGEN BIT(16) /* Average Algorithm */ +#define DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE BIT(27) /* force VT update */ +/* ZQ */ +#define DMPHY_ZQ_BASE (0x091 << DMPHY_SHIFT) +#define DMPHY_ZQ_STRIDE (0x004 << DMPHY_SHIFT) +#define DMPHY_ZQ_PR (0x000 << DMPHY_SHIFT) +#define DMPHY_ZQ_DR (0x001 << DMPHY_SHIFT) +#define DMPHY_ZQ_SR (0x002 << DMPHY_SHIFT) +/* DATX8 */ +#define DMPHY_DX_BASE (0x0A0 << DMPHY_SHIFT) +#define DMPHY_DX_STRIDE (0x020 << DMPHY_SHIFT) +#define DMPHY_DX_GCR0 (0x000 << DMPHY_SHIFT) +#define DMPHY_DX_GCR0_WLRKEN_SHIFT 26 /* Write Level Rank Enable */ +#define DMPHY_DX_GCR0_WLRKEN_MASK (0xf << (DMPHY_DX_GCR0_WLRKEN_SHIFT)) +#define DMPHY_DX_GCR1 (0x001 << DMPHY_SHIFT) +#define DMPHY_DX_GCR2 (0x002 << DMPHY_SHIFT) +#define DMPHY_DX_GCR3 (0x003 << DMPHY_SHIFT) +#define DMPHY_DX_GSR0 (0x004 << DMPHY_SHIFT) +#define DMPHY_DX_GSR1 (0x005 << DMPHY_SHIFT) +#define DMPHY_DX_GSR2 (0x006 << DMPHY_SHIFT) +#define DMPHY_DX_BDLR0 (0x007 << DMPHY_SHIFT) +#define DMPHY_DX_BDLR1 (0x008 << DMPHY_SHIFT) +#define DMPHY_DX_BDLR2 (0x009 << DMPHY_SHIFT) +#define DMPHY_DX_BDLR3 (0x00A << DMPHY_SHIFT) +#define DMPHY_DX_BDLR4 (0x00B << DMPHY_SHIFT) +#define DMPHY_DX_BDLR5 (0x00C << DMPHY_SHIFT) +#define DMPHY_DX_BDLR6 (0x00D << DMPHY_SHIFT) +#define DMPHY_DX_LCDLR0 (0x00E << DMPHY_SHIFT) +#define DMPHY_DX_LCDLR1 (0x00F << DMPHY_SHIFT) +#define DMPHY_DX_LCDLR2 (0x010 << DMPHY_SHIFT) +#define DMPHY_DX_MDLR (0x011 << DMPHY_SHIFT) +#define DMPHY_DX_GTR (0x012 << DMPHY_SHIFT) + +#endif /* ARCH_DDRMPHY_REGS_H */ diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c index 991d9294fd0..d2bc5a15d4a 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c @@ -6,7 +6,8 @@ #include <linux/types.h> #include <linux/io.h> -#include <mach/ddrphy-regs.h> + +#include "ddrphy-regs.h" int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) { diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c index bc47ba3280d..2c8cbc25798 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c @@ -6,7 +6,8 @@ #include <linux/types.h> #include <linux/io.h> -#include <mach/ddrphy-regs.h> + +#include "ddrphy-regs.h" int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) { diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c index 39024a09d5e..651069073c2 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c @@ -7,7 +7,8 @@ #include <config.h> #include <linux/types.h> #include <linux/io.h> -#include <mach/ddrphy-regs.h> + +#include "ddrphy-regs.h" int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) { diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-regs.h index 03aedc2e63d..03aedc2e63d 100644 --- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/dram/ddrphy-regs.h diff --git a/arch/arm/mach-uniphier/dram/ddrphy-training.c b/arch/arm/mach-uniphier/dram/ddrphy-training.c index 4852f2dec81..a3481363fe6 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-training.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-training.c @@ -7,7 +7,8 @@ #include <common.h> #include <linux/err.h> #include <linux/io.h> -#include <mach/ddrphy-regs.h> + +#include "ddrphy-regs.h" void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank) { diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index 81246850b38..ffd7aa97b28 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c @@ -8,9 +8,10 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> -#include <mach/init.h> -#include <mach/umc-regs.h> -#include <mach/ddrphy-regs.h> + +#include "../init.h" +#include "ddrphy-regs.h" +#include "umc-regs.h" static void umc_start_ssif(void __iomem *ssif_base) { diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index 8c9f0579fc7..4d976e3a976 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -8,9 +8,10 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> -#include <mach/init.h> -#include <mach/umc-regs.h> -#include <mach/ddrphy-regs.h> + +#include "../init.h" +#include "ddrphy-regs.h" +#include "umc-regs.h" static void umc_start_ssif(void __iomem *ssif_base) { diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index bc60a3472e1..09f9ccfb43e 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -8,9 +8,10 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> -#include <mach/init.h> -#include <mach/umc-regs.h> -#include <mach/ddrphy-regs.h> + +#include "../init.h" +#include "ddrphy-regs.h" +#include "umc-regs.h" static void umc_start_ssif(void __iomem *ssif_base) { diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-proxstream2.c new file mode 100644 index 00000000000..63a84e68c0b --- /dev/null +++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c @@ -0,0 +1,669 @@ +/* + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * based on commit 21b6e480f92ccc38fe0502e3116411d6509d3bf2 of Diag by: + * Copyright (C) 2015 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/sizes.h> +#include <asm/processor.h> + +#include "../init.h" +#include "../soc-info.h" +#include "ddrmphy-regs.h" + +/* UM registers */ +#define UMC_MBUS0 0x00080004 +#define UMC_MBUS1 0x00081004 +#define UMC_MBUS2 0x00082004 +#define UMC_MBUS3 0x00083004 + +/* UD registers */ +#define UMC_BITPERPIXELMODE_D0 0x010 +#define UMC_PAIR1DOFF_D0 0x054 + +/* DC registers */ +#define UMC_INITSET 0x014 +#define UMC_INITSTAT 0x018 +#define UMC_CMDCTLA 0x000 +#define UMC_CMDCTLB 0x004 +#define UMC_SPCCTLA 0x030 +#define UMC_SPCCTLB 0x034 +#define UMC_SPCSETB 0x03c +#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ +#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ +#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */ +#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */ +#define UMC_ACSSETA 0x060 +#define UMC_FLOWCTLA 0x400 +#define UMC_FLOWCTLB 0x404 +#define UMC_FLOWCTLC 0x408 +#define UMC_FLOWCTLG 0x508 +#define UMC_FLOWCTLOB0 0x520 +#define UMC_FLOWCTLOB1 0x524 +#define UMC_RDATACTL_D0 0x600 +#define UMC_RDATACTL_RADLTY_SHIFT 4 +#define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT)) +#define UMC_RDATACTL_RAD2LTY_SHIFT 8 +#define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT)) +#define UMC_WDATACTL_D0 0x604 +#define UMC_RDATACTL_D1 0x608 +#define UMC_WDATACTL_D1 0x60c +#define UMC_DATASET 0x610 +#define UMC_RESPCTL 0x624 +#define UMC_DCCGCTL 0x720 +#define UMC_ERRMASKA 0x958 +#define UMC_ERRMASKB 0x95c +#define UMC_BSICMAPSET 0x988 +#define UMC_DIOCTLA 0xc00 +#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */ +#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */ +#define UMC_DFICUPDCTLA 0xc20 + +enum dram_freq { + FREQ_1866M, + FREQ_2133M, + FREQ_NR, +}; + +enum dram_size { + SIZE_0, + SIZE_512M, + SIZE_1G, + SIZE_NR, +}; + +static u32 ddrphy_pgcr2[FREQ_NR] = {0x00FC7E5D, 0x00FC90AB}; +static u32 ddrphy_ptr0[FREQ_NR] = {0x0EA09205, 0x10C0A6C6}; +static u32 ddrphy_ptr1[FREQ_NR] = {0x0DAC041B, 0x0FA104B1}; +static u32 ddrphy_ptr3[FREQ_NR] = {0x15171e45, 0x18182357}; +static u32 ddrphy_ptr4[FREQ_NR] = {0x0e9ad8e9, 0x10b34157}; +static u32 ddrphy_dtpr0[FREQ_NR] = {0x35a00d88, 0x39e40e88}; +static u32 ddrphy_dtpr1[FREQ_NR] = {0x2288cc2c, 0x228a04d0}; +static u32 ddrphy_dtpr2[FREQ_NR] = {0x50005e00, 0x50006a00}; +static u32 ddrphy_dtpr3[FREQ_NR] = {0x0010cb49, 0x0010ec89}; +static u32 ddrphy_mr0[FREQ_NR] = {0x00000115, 0x00000125}; +static u32 ddrphy_mr2[FREQ_NR] = {0x000002a0, 0x000002a8}; + +static u32 umc_cmdctla[FREQ_NR] = {0x66DD131D, 0x77EE1722}; +/* + * The ch2 is a different generation UMC core. + * The register spec is different, unfortunately. + */ +static u32 umc_cmdctlb_ch01[FREQ_NR] = {0x13E87C44, 0x18F88C44}; +static u32 umc_cmdctlb_ch2[FREQ_NR] = {0x19E8DC44, 0x1EF8EC44}; +static u32 umc_spcctla[FREQ_NR][SIZE_NR] = { + {0x00000000, 0x004A071D, 0x0078071D}, + {0x00000000, 0x0055081E, 0x0089081E}, +}; + +static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B}; +/* The ch2 is different for some reason only hardware guys know... */ +static u32 umc_flowctla_ch01[] = {0x0800001E, 0x08000022}; +static u32 umc_flowctla_ch2[] = {0x0800001E, 0x0800001E}; + +/* DDR multiPHY */ +static inline int ddrphy_get_rank(int dx) +{ + return dx / 2; +} + +static void ddrphy_fifo_reset(void __iomem *phy_base) +{ + u32 tmp; + + tmp = readl(phy_base + DMPHY_PGCR0); + tmp &= ~DMPHY_PGCR0_PHYFRST; + writel(tmp, phy_base + DMPHY_PGCR0); + + udelay(1); + + tmp |= DMPHY_PGCR0_PHYFRST; + writel(tmp, phy_base + DMPHY_PGCR0); + + udelay(1); +} + +static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable) +{ + u32 tmp; + + tmp = readl(phy_base + DMPHY_PGCR1); + + if (enable) + tmp &= ~DMPHY_PGCR1_INHVT; + else + tmp |= DMPHY_PGCR1_INHVT; + + writel(tmp, phy_base + DMPHY_PGCR1); + + if (!enable) { + while (!(readl(phy_base + DMPHY_PGSR1) & DMPHY_PGSR1_VTSTOP)) + cpu_relax(); + } +} + +static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step) +{ + int dx; + u32 lcdlr1, rdqsd; + void __iomem *dx_base = phy_base + DMPHY_DX_BASE; + + ddrphy_vt_ctrl(phy_base, 0); + + for (dx = 0; dx < nr_dx; dx++) { + lcdlr1 = readl(dx_base + DMPHY_DX_LCDLR1); + rdqsd = (lcdlr1 >> 8) & 0xff; + rdqsd = clamp(rdqsd + step, 0U, 0xffU); + lcdlr1 = (lcdlr1 & ~(0xff << 8)) | (rdqsd << 8); + writel(lcdlr1, dx_base + DMPHY_DX_LCDLR1); + readl(dx_base + DMPHY_DX_LCDLR1); /* relax */ + dx_base += DMPHY_DX_STRIDE; + } + + ddrphy_vt_ctrl(phy_base, 1); +} + +static int ddrphy_get_system_latency(void __iomem *phy_base, int width) +{ + void __iomem *dx_base = phy_base + DMPHY_DX_BASE; + const int nr_dx = width / 8; + int dx, rank; + u32 gtr; + int dgsl, dgsl_min = INT_MAX, dgsl_max = 0; + + for (dx = 0; dx < nr_dx; dx++) { + gtr = readl(dx_base + DMPHY_DX_GTR); + for (rank = 0; rank < 4; rank++) { + dgsl = gtr & 0x7; + /* if dgsl is zero, this rank was not trained. skip. */ + if (dgsl) { + dgsl_min = min(dgsl_min, dgsl); + dgsl_max = max(dgsl_max, dgsl); + } + gtr >>= 3; + } + dx_base += DMPHY_DX_STRIDE; + } + + if (dgsl_min != dgsl_max) + printf("DQS Gateing System Latencies are not all leveled.\n"); + + return dgsl_max; +} + +static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width) +{ + u32 tmp; + void __iomem *zq_base, *dx_base; + int zq, dx; + int nr_dx; + + nr_dx = width / 8; + + writel(DMPHY_PIR_ZCALBYP, phy_base + DMPHY_PIR); + /* + * Disable RGLVT bit (Read DQS Gating LCDL Delay VT Compensation) + * to avoid read error issue. + */ + writel(0x07d81e37, phy_base + DMPHY_PGCR0); + writel(0x0200c4e0, phy_base + DMPHY_PGCR1); + + tmp = ddrphy_pgcr2[freq]; + if (width >= 32) + tmp |= DMPHY_PGCR2_DUALCHN | DMPHY_PGCR2_ACPDDC; + writel(tmp, phy_base + DMPHY_PGCR2); + + writel(ddrphy_ptr0[freq], phy_base + DMPHY_PTR0); + writel(ddrphy_ptr1[freq], phy_base + DMPHY_PTR1); + writel(0x00083def, phy_base + DMPHY_PTR2); + writel(ddrphy_ptr3[freq], phy_base + DMPHY_PTR3); + writel(ddrphy_ptr4[freq], phy_base + DMPHY_PTR4); + + writel(0x55555555, phy_base + DMPHY_ACIOCR1); + writel(0x00000000, phy_base + DMPHY_ACIOCR2); + writel(0x55555555, phy_base + DMPHY_ACIOCR3); + writel(0x00000000, phy_base + DMPHY_ACIOCR4); + writel(0x00000055, phy_base + DMPHY_ACIOCR5); + writel(0x00181aa4, phy_base + DMPHY_DXCCR); + + writel(0x0024641e, phy_base + DMPHY_DSGCR); + writel(0x0000040b, phy_base + DMPHY_DCR); + writel(ddrphy_dtpr0[freq], phy_base + DMPHY_DTPR0); + writel(ddrphy_dtpr1[freq], phy_base + DMPHY_DTPR1); + writel(ddrphy_dtpr2[freq], phy_base + DMPHY_DTPR2); + writel(ddrphy_dtpr3[freq], phy_base + DMPHY_DTPR3); + writel(ddrphy_mr0[freq], phy_base + DMPHY_MR0); + writel(0x00000006, phy_base + DMPHY_MR1); + writel(ddrphy_mr2[freq], phy_base + DMPHY_MR2); + writel(0x00000000, phy_base + DMPHY_MR3); + + tmp = 0; + for (dx = 0; dx < nr_dx; dx++) + tmp |= BIT(DMPHY_DTCR_RANKEN_SHIFT + ddrphy_get_rank(dx)); + writel(0x90003087 | tmp, phy_base + DMPHY_DTCR); + + writel(0x00000000, phy_base + DMPHY_DTAR0); + writel(0x00000008, phy_base + DMPHY_DTAR1); + writel(0x00000010, phy_base + DMPHY_DTAR2); + writel(0x00000018, phy_base + DMPHY_DTAR3); + writel(0xdd22ee11, phy_base + DMPHY_DTDR0); + writel(0x7788bb44, phy_base + DMPHY_DTDR1); + + /* impedance control settings */ + writel(0x04048900, phy_base + DMPHY_ZQCR); + + zq_base = phy_base + DMPHY_ZQ_BASE; + for (zq = 0; zq < 4; zq++) { + /* + * board-dependent + * PXS2: CH0ZQ0=0x5B, CH1ZQ0=0x5B, CH2ZQ0=0x59, others=0x5D + */ + writel(0x0007BB5D, zq_base + DMPHY_ZQ_PR); + zq_base += DMPHY_ZQ_STRIDE; + } + + /* DATX8 settings */ + dx_base = phy_base + DMPHY_DX_BASE; + for (dx = 0; dx < 4; dx++) { + tmp = readl(dx_base + DMPHY_DX_GCR0); + tmp &= ~DMPHY_DX_GCR0_WLRKEN_MASK; + tmp |= BIT(DMPHY_DX_GCR0_WLRKEN_SHIFT + ddrphy_get_rank(dx)) & + DMPHY_DX_GCR0_WLRKEN_MASK; + writel(tmp, dx_base + DMPHY_DX_GCR0); + + writel(0x00000000, dx_base + DMPHY_DX_GCR1); + writel(0x00000000, dx_base + DMPHY_DX_GCR2); + writel(0x00000000, dx_base + DMPHY_DX_GCR3); + dx_base += DMPHY_DX_STRIDE; + } + + while (!(readl(phy_base + DMPHY_PGSR0) & DMPHY_PGSR0_IDONE)) + cpu_relax(); + + ddrphy_dqs_delay_fixup(phy_base, nr_dx, -4); +} + +struct ddrphy_init_sequence { + char *description; + u32 init_flag; + u32 done_flag; + u32 err_flag; +}; + +static const struct ddrphy_init_sequence impedance_calibration_sequence[] = { + { + "Impedance Calibration", + DMPHY_PIR_ZCAL, + DMPHY_PGSR0_ZCDONE, + DMPHY_PGSR0_ZCERR, + }, + { /* sentinel */ } +}; + +static const struct ddrphy_init_sequence dram_init_sequence[] = { + { + "DRAM Initialization", + DMPHY_PIR_DRAMRST | DMPHY_PIR_DRAMINIT, + DMPHY_PGSR0_DIDONE, + 0, + }, + { /* sentinel */ } +}; + +static const struct ddrphy_init_sequence training_sequence[] = { + { + "Write Leveling", + DMPHY_PIR_WL, + DMPHY_PGSR0_WLDONE, + DMPHY_PGSR0_WLERR, + }, + { + "Read DQS Gate Training", + DMPHY_PIR_QSGATE, + DMPHY_PGSR0_QSGDONE, + DMPHY_PGSR0_QSGERR, + }, + { + "Write Leveling Adjustment", + DMPHY_PIR_WLADJ, + DMPHY_PGSR0_WLADONE, + DMPHY_PGSR0_WLAERR, + }, + { + "Read Bit Deskew", + DMPHY_PIR_RDDSKW, + DMPHY_PGSR0_RDDONE, + DMPHY_PGSR0_RDERR, + }, + { + "Write Bit Deskew", + DMPHY_PIR_WRDSKW, + DMPHY_PGSR0_WDDONE, + DMPHY_PGSR0_WDERR, + }, + { + "Read Eye Training", + DMPHY_PIR_RDEYE, + DMPHY_PGSR0_REDONE, + DMPHY_PGSR0_REERR, + }, + { + "Write Eye Training", + DMPHY_PIR_WREYE, + DMPHY_PGSR0_WEDONE, + DMPHY_PGSR0_WEERR, + }, + { /* sentinel */ } +}; + +static int __ddrphy_training(void __iomem *phy_base, + const struct ddrphy_init_sequence *seq) +{ + const struct ddrphy_init_sequence *s; + u32 pgsr0; + u32 init_flag = DMPHY_PIR_INIT; + u32 done_flag = DMPHY_PGSR0_IDONE; + int timeout = 50000; /* 50 msec is long enough */ +#ifdef DISPLAY_ELAPSED_TIME + ulong start = get_timer(0); +#endif + + for (s = seq; s->description; s++) { + init_flag |= s->init_flag; + done_flag |= s->done_flag; + } + + writel(init_flag, phy_base + DMPHY_PIR); + + do { + if (--timeout < 0) { + printf("%s: error: timeout during DDR training\n", + __func__); + return -ETIMEDOUT; + } + udelay(1); + pgsr0 = readl(phy_base + DMPHY_PGSR0); + } while ((pgsr0 & done_flag) != done_flag); + + for (s = seq; s->description; s++) { + if (pgsr0 & s->err_flag) { + printf("%s: error: %s failed\n", __func__, + s->description); + return -EIO; + } + } + +#ifdef DISPLAY_ELAPSED_TIME + printf("%s: info: elapsed time %ld msec\n", get_timer(start)); +#endif + + return 0; +} + +static int ddrphy_impedance_calibration(void __iomem *phy_base) +{ + int ret; + u32 tmp; + + ret = __ddrphy_training(phy_base, impedance_calibration_sequence); + if (ret) + return ret; + + /* + * Because of a hardware bug, IDONE flag is set when the first ZQ block + * is calibrated. The flag does not guarantee the completion for all + * the ZQ blocks. Wait a little more just in case. + */ + udelay(1); + + /* reflect ZQ settings and enable average algorithm*/ + tmp = readl(phy_base + DMPHY_ZQCR); + tmp |= DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE; + writel(tmp, phy_base + DMPHY_ZQCR); + tmp &= ~DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE; + tmp |= DMPHY_ZQCR_AVGEN; + writel(tmp, phy_base + DMPHY_ZQCR); + + return 0; +} + +static int ddrphy_dram_init(void __iomem *phy_base) +{ + return __ddrphy_training(phy_base, dram_init_sequence); +} + +static int ddrphy_training(void __iomem *phy_base) +{ + return __ddrphy_training(phy_base, training_sequence); +} + +/* UMC */ +static void umc_set_system_latency(void __iomem *umc_dc_base, int phy_latency) +{ + u32 val; + int latency; + + val = readl(umc_dc_base + UMC_RDATACTL_D0); + latency = (val & UMC_RDATACTL_RADLTY_MASK) >> UMC_RDATACTL_RADLTY_SHIFT; + latency += (val & UMC_RDATACTL_RAD2LTY_MASK) >> + UMC_RDATACTL_RAD2LTY_SHIFT; + /* + * UMC works at the half clock rate of the PHY. + * The LSB of latency is ignored + */ + latency += phy_latency & ~1; + + val &= ~(UMC_RDATACTL_RADLTY_MASK | UMC_RDATACTL_RAD2LTY_MASK); + if (latency > 0xf) { + val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT; + val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT; + } else { + val |= latency << UMC_RDATACTL_RADLTY_SHIFT; + } + + writel(val, umc_dc_base + UMC_RDATACTL_D0); + writel(val, umc_dc_base + UMC_RDATACTL_D1); + + readl(umc_dc_base + UMC_RDATACTL_D1); /* relax */ +} + +/* enable/disable auto refresh */ +void umc_refresh_ctrl(void __iomem *umc_dc_base, int enable) +{ + u32 tmp; + + tmp = readl(umc_dc_base + UMC_SPCSETB); + tmp &= ~UMC_SPCSETB_AREFMD_MASK; + + if (enable) + tmp |= UMC_SPCSETB_AREFMD_ARB; + else + tmp |= UMC_SPCSETB_AREFMD_REG; + + writel(tmp, umc_dc_base + UMC_SPCSETB); + udelay(1); +} + +static void umc_ud_init(void __iomem *umc_base, int ch) +{ + writel(0x00000003, umc_base + UMC_BITPERPIXELMODE_D0); + + if (ch == 2) + writel(0x00000033, umc_base + UMC_PAIR1DOFF_D0); +} + +static void umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq, + enum dram_size size, int ch, int width) +{ + int latency; + u32 val; + + writel(umc_cmdctla[freq], umc_dc_base + UMC_CMDCTLA); + + writel(ch == 2 ? umc_cmdctlb_ch2[freq] : umc_cmdctlb_ch01[freq], + umc_dc_base + UMC_CMDCTLB); + + writel(umc_spcctla[freq][size / (width / 16)], + umc_dc_base + UMC_SPCCTLA); + writel(umc_spcctlb[freq], umc_dc_base + UMC_SPCCTLB); + + val = 0x000e000e; + latency = 12; + /* ES2 inserted one more FF to the logic. */ + if (uniphier_get_soc_model() >= 2) + latency += 2; + + if (latency > 0xf) { + val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT; + val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT; + } else { + val |= latency << UMC_RDATACTL_RADLTY_SHIFT; + } + + writel(val, umc_dc_base + UMC_RDATACTL_D0); + if (width >= 32) + writel(val, umc_dc_base + UMC_RDATACTL_D1); + + writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D0); + if (width >= 32) + writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D1); + writel(0x04000000, umc_dc_base + UMC_DATASET); + writel(0x00400020, umc_dc_base + UMC_DCCGCTL); + writel(0x00000084, umc_dc_base + UMC_FLOWCTLG); + writel(0x00000000, umc_dc_base + UMC_ACSSETA); + + writel(ch == 2 ? umc_flowctla_ch2[freq] : umc_flowctla_ch01[freq], + umc_dc_base + UMC_FLOWCTLA); + + writel(0x00004400, umc_dc_base + UMC_FLOWCTLC); + writel(0x200A0A00, umc_dc_base + UMC_SPCSETB); + writel(0x00000520, umc_dc_base + UMC_DFICUPDCTLA); + writel(0x0000000D, umc_dc_base + UMC_RESPCTL); + + if (ch != 2) { + writel(0x00202000, umc_dc_base + UMC_FLOWCTLB); + writel(0xFDBFFFFF, umc_dc_base + UMC_FLOWCTLOB0); + writel(0xFFFFFFFF, umc_dc_base + UMC_FLOWCTLOB1); + writel(0x00080700, umc_dc_base + UMC_BSICMAPSET); + } else { + writel(0x00200000, umc_dc_base + UMC_FLOWCTLB); + writel(0x00000000, umc_dc_base + UMC_BSICMAPSET); + } + + writel(0x00000000, umc_dc_base + UMC_ERRMASKA); + writel(0x00000000, umc_dc_base + UMC_ERRMASKB); +} + +static int umc_init(void __iomem *umc_base, enum dram_freq freq, int ch, + enum dram_size size, int width) +{ + void __iomem *umc_dc_base = umc_base + 0x00011000; + void __iomem *phy_base = umc_base + 0x00030000; + int ret; + + writel(0x00000002, umc_dc_base + UMC_INITSET); + while (readl(umc_dc_base + UMC_INITSTAT) & BIT(2)) + cpu_relax(); + + /* deassert PHY reset signals */ + writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST, + umc_dc_base + UMC_DIOCTLA); + + ddrphy_init(phy_base, freq, width); + + ret = ddrphy_impedance_calibration(phy_base); + if (ret) + return ret; + + ddrphy_dram_init(phy_base); + if (ret) + return ret; + + umc_dc_init(umc_dc_base, freq, size, ch, width); + + umc_ud_init(umc_base, ch); + + if (size) { + ret = ddrphy_training(phy_base); + if (ret) + return ret; + } + + udelay(1); + + /* match the system latency between UMC and PHY */ + umc_set_system_latency(umc_dc_base, + ddrphy_get_system_latency(phy_base, width)); + + udelay(1); + + /* stop auto refresh before clearing FIFO in PHY */ + umc_refresh_ctrl(umc_dc_base, 0); + ddrphy_fifo_reset(phy_base); + umc_refresh_ctrl(umc_dc_base, 1); + + udelay(10); + + return 0; +} + +static void um_init(void __iomem *um_base) +{ + writel(0x000000ff, um_base + UMC_MBUS0); + writel(0x000000ff, um_base + UMC_MBUS1); + writel(0x000000ff, um_base + UMC_MBUS2); + writel(0x000000ff, um_base + UMC_MBUS3); +} + +int proxstream2_umc_init(const struct uniphier_board_data *bd) +{ + void __iomem *um_base = (void __iomem *)0x5b600000; + void __iomem *umc_ch0_base = (void __iomem *)0x5b800000; + void __iomem *umc_ch1_base = (void __iomem *)0x5ba00000; + void __iomem *umc_ch2_base = (void __iomem *)0x5bc00000; + enum dram_freq freq; + int ret; + + switch (bd->dram_freq) { + case 1866: + freq = FREQ_1866M; + break; + case 2133: + freq = FREQ_2133M; + break; + default: + printf("unsupported DRAM frequency %d MHz\n", bd->dram_freq); + return -EINVAL; + } + + ret = umc_init(umc_ch0_base, freq, 0, bd->dram_ch0_size / SZ_256M, + bd->dram_ch0_width); + if (ret) { + printf("failed to initialize UMC ch0\n"); + return ret; + } + + ret = umc_init(umc_ch1_base, freq, 1, bd->dram_ch1_size / SZ_256M, + bd->dram_ch1_width); + if (ret) { + printf("failed to initialize UMC ch1\n"); + return ret; + } + + ret = umc_init(umc_ch2_base, freq, 2, bd->dram_ch2_size / SZ_256M, + bd->dram_ch2_width); + if (ret) { + printf("failed to initialize UMC ch2\n"); + return ret; + } + + um_init(um_base); + + return 0; +} diff --git a/arch/arm/mach-uniphier/include/mach/umc-regs.h b/arch/arm/mach-uniphier/dram/umc-regs.h index 6159281fd37..6159281fd37 100644 --- a/arch/arm/mach-uniphier/include/mach/umc-regs.h +++ b/arch/arm/mach-uniphier/dram/umc-regs.h diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c index f646c9b7df9..6574767f30c 100644 --- a/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c +++ b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c @@ -7,8 +7,9 @@ #include <common.h> #include <spl.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c index 007d3b85708..d98635878b8 100644 --- a/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c +++ b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c b/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c index c303f16a578..a573a96ee56 100644 --- a/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c +++ b/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c @@ -7,8 +7,9 @@ #include <common.h> #include <spl.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" int proxstream2_early_clk_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c index 1bb9375016d..7923644cd54 100644 --- a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c +++ b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <mach/init.h> -#include <mach/sg-regs.h> +#include "../init.h" +#include "../sg-regs.h" int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/include/mach/init.h b/arch/arm/mach-uniphier/init.h index 27ae27dc9f4..0a47e70dcf7 100644 --- a/arch/arm/mach-uniphier/include/mach/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -80,6 +80,7 @@ int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd); int ph1_ld4_umc_init(const struct uniphier_board_data *bd); int ph1_pro4_umc_init(const struct uniphier_board_data *bd); int ph1_sld8_umc_init(const struct uniphier_board_data *bd); +int proxstream2_umc_init(const struct uniphier_board_data *bd); void ph1_sld3_pin_init(void); void ph1_ld4_pin_init(void); diff --git a/arch/arm/mach-uniphier/init/init-ph1-ld4.c b/arch/arm/mach-uniphier/init/init-ph1-ld4.c index 8d0ef0389e1..a9c6d72e0b6 100644 --- a/arch/arm/mach-uniphier/init/init-ph1-ld4.c +++ b/arch/arm/mach-uniphier/init/init-ph1-ld4.c @@ -6,9 +6,9 @@ #include <common.h> #include <spl.h> -#include <linux/compiler.h> -#include <mach/init.h> -#include <mach/micro-support-card.h> + +#include "../init.h" +#include "../micro-support-card.h" int ph1_ld4_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/init/init-ph1-pro4.c b/arch/arm/mach-uniphier/init/init-ph1-pro4.c index b9ce08d88f9..6fcd8b6c857 100644 --- a/arch/arm/mach-uniphier/init/init-ph1-pro4.c +++ b/arch/arm/mach-uniphier/init/init-ph1-pro4.c @@ -6,9 +6,9 @@ #include <common.h> #include <spl.h> -#include <linux/compiler.h> -#include <mach/init.h> -#include <mach/micro-support-card.h> + +#include "../init.h" +#include "../micro-support-card.h" int ph1_pro4_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/init/init-ph1-pro5.c b/arch/arm/mach-uniphier/init/init-ph1-pro5.c index 92b3f21d93c..45c65cf49a7 100644 --- a/arch/arm/mach-uniphier/init/init-ph1-pro5.c +++ b/arch/arm/mach-uniphier/init/init-ph1-pro5.c @@ -6,9 +6,9 @@ #include <common.h> #include <spl.h> -#include <linux/compiler.h> -#include <mach/init.h> -#include <mach/micro-support-card.h> + +#include "../init.h" +#include "../micro-support-card.h" int ph1_pro5_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/init/init-ph1-sld3.c b/arch/arm/mach-uniphier/init/init-ph1-sld3.c index 1146fdab977..7827ec0bdc4 100644 --- a/arch/arm/mach-uniphier/init/init-ph1-sld3.c +++ b/arch/arm/mach-uniphier/init/init-ph1-sld3.c @@ -6,9 +6,9 @@ #include <common.h> #include <spl.h> -#include <linux/compiler.h> -#include <mach/init.h> -#include <mach/micro-support-card.h> + +#include "../init.h" +#include "../micro-support-card.h" int ph1_sld3_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/init/init-ph1-sld8.c b/arch/arm/mach-uniphier/init/init-ph1-sld8.c index 741e88c212f..6c96aede2ae 100644 --- a/arch/arm/mach-uniphier/init/init-ph1-sld8.c +++ b/arch/arm/mach-uniphier/init/init-ph1-sld8.c @@ -6,9 +6,9 @@ #include <common.h> #include <spl.h> -#include <linux/compiler.h> -#include <mach/init.h> -#include <mach/micro-support-card.h> + +#include "../init.h" +#include "../micro-support-card.h" int ph1_sld8_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/init/init-proxstream2.c b/arch/arm/mach-uniphier/init/init-proxstream2.c index 8d03b8f86a0..029c5449979 100644 --- a/arch/arm/mach-uniphier/init/init-proxstream2.c +++ b/arch/arm/mach-uniphier/init/init-proxstream2.c @@ -6,12 +6,14 @@ #include <common.h> #include <spl.h> -#include <linux/compiler.h> -#include <mach/init.h> -#include <mach/micro-support-card.h> + +#include "../init.h" +#include "../micro-support-card.h" int proxstream2_init(const struct uniphier_board_data *bd) { + int ret; + proxstream2_sbc_init(bd); support_card_reset(); @@ -37,5 +39,11 @@ int proxstream2_init(const struct uniphier_board_data *bd) led_puts("L4"); + ret = proxstream2_umc_init(bd); + if (ret) + return ret; + + led_puts("L5"); + return 0; } diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c index eda169e3740..b30f3bd9d62 100644 --- a/arch/arm/mach-uniphier/init/init.c +++ b/arch/arm/mach-uniphier/init/init.c @@ -6,8 +6,9 @@ #include <common.h> #include <spl.h> -#include <mach/init.h> -#include <mach/soc_info.h> + +#include "../init.h" +#include "../soc-info.h" void spl_board_init(void) { diff --git a/arch/arm/mach-uniphier/late_lowlevel_init.S b/arch/arm/mach-uniphier/late_lowlevel_init.S index 1363364c80e..cce91dfac7b 100644 --- a/arch/arm/mach-uniphier/late_lowlevel_init.S +++ b/arch/arm/mach-uniphier/late_lowlevel_init.S @@ -6,7 +6,8 @@ */ #include <linux/linkage.h> -#include <mach/ssc-regs.h> + +#include "ssc-regs.h" ENTRY(lowlevel_init) ldr r1, = SSCC diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S index 5936045e866..291337070e6 100644 --- a/arch/arm/mach-uniphier/lowlevel_init.S +++ b/arch/arm/mach-uniphier/lowlevel_init.S @@ -8,9 +8,8 @@ #include <linux/linkage.h> #include <linux/sizes.h> #include <asm/system.h> -#include <mach/arm-mpcore.h> -#include <mach/sbc-regs.h> -#include <mach/ssc-regs.h> + +#include "ssc-regs.h" ENTRY(lowlevel_init) mov r8, lr @ persevere link reg across call diff --git a/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c index e13f56d1dcb..9718cc560fa 100644 --- a/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c +++ b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c @@ -8,8 +8,9 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" int ph1_sld3_memconf_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c b/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c index d7bf0d4e5fa..9a91fb33ef3 100644 --- a/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c +++ b/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c @@ -8,8 +8,9 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" int proxstream2_memconf_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/memconf/memconf.c b/arch/arm/mach-uniphier/memconf/memconf.c index d490736fa43..f2a0eaf3f52 100644 --- a/arch/arm/mach-uniphier/memconf/memconf.c +++ b/arch/arm/mach-uniphier/memconf/memconf.c @@ -8,8 +8,9 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" int memconf_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/micro-support-card.c b/arch/arm/mach-uniphier/micro-support-card.c index 4c34748c25c..f777ac1ffe4 100644 --- a/arch/arm/mach-uniphier/micro-support-card.c +++ b/arch/arm/mach-uniphier/micro-support-card.c @@ -7,7 +7,8 @@ #include <common.h> #include <linux/ctype.h> #include <linux/io.h> -#include <mach/micro-support-card.h> + +#include "micro-support-card.h" #define MICRO_SUPPORT_CARD_BASE 0x43f00000 #define SMC911X_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x00000) @@ -70,7 +71,6 @@ int board_eth_init(bd_t *bis) #if !defined(CONFIG_SYS_NO_FLASH) #include <mtd/cfi_flash.h> -#include <mach/sbc-regs.h> struct memory_bank { phys_addr_t base; diff --git a/arch/arm/mach-uniphier/include/mach/micro-support-card.h b/arch/arm/mach-uniphier/micro-support-card.h index 5da0ada7261..5da0ada7261 100644 --- a/arch/arm/mach-uniphier/include/mach/micro-support-card.h +++ b/arch/arm/mach-uniphier/micro-support-card.h diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c index 160d3ef2991..8168a63d313 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" void ph1_ld4_pin_init(void) { diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c index 4f950d3fc63..4faeaf535cd 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" void ph1_ld6b_pin_init(void) { diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c index f50644c52bb..23b5f9349ab 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" void ph1_pro4_pin_init(void) { diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c index a6cc0824e23..79160d6c95d 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" void ph1_pro5_pin_init(void) { diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c index f1b2bbbb4a2..6fc0dee70e4 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <mach/init.h> -#include <mach/sg-regs.h> +#include "../init.h" +#include "../sg-regs.h" void ph1_sld3_pin_init(void) { diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c index f936a53d1f1..a4e3e7a6145 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" void ph1_sld8_pin_init(void) { diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c index 96abd0235c2..a662db8ac98 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" void proxstream2_pin_init(void) { diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c index a272a900e11..b2de9e8d5ef 100644 --- a/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c +++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c @@ -7,9 +7,10 @@ #include <common.h> #include <linux/err.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sc-regs.h" +#include "../sg-regs.h" #undef DPLL_SSC_RATE_1PER diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c index 906c22f6c58..69d518d2657 100644 --- a/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c +++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c @@ -7,9 +7,10 @@ #include <common.h> #include <linux/err.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sc-regs.h" +#include "../sg-regs.h" #undef DPLL_SSC_RATE_1PER diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c index 6294a452c29..b93806cdc09 100644 --- a/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c +++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <mach/init.h> +#include "../init.h" int ph1_sld3_pll_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c index f249abeeda3..3c7550446ac 100644 --- a/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c +++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c @@ -6,9 +6,10 @@ #include <common.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sc-regs.h" +#include "../sg-regs.h" static void dpll_init(void) { diff --git a/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c index cad0ed8cdd4..a1c8089de73 100644 --- a/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c +++ b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c @@ -5,8 +5,9 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c index 43dc9736549..94654eeba0a 100644 --- a/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c +++ b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c @@ -6,8 +6,9 @@ #include <common.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sc-regs.h> + +#include "../init.h" +#include "../sc-regs.h" int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/print_misc_info.c b/arch/arm/mach-uniphier/print_misc_info.c index 5140b0c4383..695b7aeeb32 100644 --- a/arch/arm/mach-uniphier/print_misc_info.c +++ b/arch/arm/mach-uniphier/print_misc_info.c @@ -1,11 +1,10 @@ /* - * Copyright (C) 2015 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ -#include <mach/micro-support-card.h> +#include "micro-support-card.h" int misc_init_f(void) { diff --git a/arch/arm/mach-uniphier/reset.c b/arch/arm/mach-uniphier/reset.c index 4c825116f74..b5825bc0c7f 100644 --- a/arch/arm/mach-uniphier/reset.c +++ b/arch/arm/mach-uniphier/reset.c @@ -6,7 +6,8 @@ #include <common.h> #include <linux/io.h> -#include <mach/sc-regs.h> + +#include "sc-regs.h" void reset_cpu(unsigned long ignored) { diff --git a/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c index 929f50a883a..fcce43cb995 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c @@ -6,9 +6,10 @@ #include <common.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sbc-regs.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" +#include "sbc-regs.h" int ph1_ld4_sbc_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c index 1032c54e644..8313c5a3e53 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c @@ -6,9 +6,10 @@ #include <common.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sbc-regs.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" +#include "sbc-regs.h" int ph1_pro4_sbc_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c index fb707be83a2..c03c2843a65 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c +++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c @@ -6,9 +6,10 @@ #include <common.h> #include <linux/io.h> -#include <mach/init.h> -#include <mach/sbc-regs.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" +#include "sbc-regs.h" int ph1_sld3_sbc_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c b/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c index 9c3aeb7cd0b..0d9ffe153f1 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c +++ b/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c @@ -5,9 +5,10 @@ */ #include <linux/io.h> -#include <mach/init.h> -#include <mach/sbc-regs.h> -#include <mach/sg-regs.h> + +#include "../init.h" +#include "../sg-regs.h" +#include "sbc-regs.h" int proxstream2_sbc_init(const struct uniphier_board_data *bd) { diff --git a/arch/arm/mach-uniphier/include/mach/sbc-regs.h b/arch/arm/mach-uniphier/sbc/sbc-regs.h index 493363bb642..493363bb642 100644 --- a/arch/arm/mach-uniphier/include/mach/sbc-regs.h +++ b/arch/arm/mach-uniphier/sbc/sbc-regs.h diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h index 474b82d2430..474b82d2430 100644 --- a/arch/arm/mach-uniphier/include/mach/sc-regs.h +++ b/arch/arm/mach-uniphier/sc-regs.h diff --git a/arch/arm/mach-uniphier/include/mach/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index 678d437fc97..678d437fc97 100644 --- a/arch/arm/mach-uniphier/include/mach/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h diff --git a/arch/arm/mach-uniphier/include/mach/soc_info.h b/arch/arm/mach-uniphier/soc-info.h index 3cfd1e9d6e0..3cfd1e9d6e0 100644 --- a/arch/arm/mach-uniphier/include/mach/soc_info.h +++ b/arch/arm/mach-uniphier/soc-info.h diff --git a/arch/arm/mach-uniphier/soc_info.c b/arch/arm/mach-uniphier/soc_info.c index 6cdeae65784..fd799ca39a4 100644 --- a/arch/arm/mach-uniphier/soc_info.c +++ b/arch/arm/mach-uniphier/soc_info.c @@ -6,8 +6,9 @@ #include <linux/io.h> #include <linux/types.h> -#include <mach/sg-regs.h> -#include <mach/soc_info.h> + +#include "sg-regs.h" +#include "soc-info.h" #if UNIPHIER_MULTI_SOC enum uniphier_soc_id uniphier_get_soc_type(void) diff --git a/arch/arm/mach-uniphier/include/mach/ssc-regs.h b/arch/arm/mach-uniphier/ssc-regs.h index 02fca3b6f61..02fca3b6f61 100644 --- a/arch/arm/mach-uniphier/include/mach/ssc-regs.h +++ b/arch/arm/mach-uniphier/ssc-regs.h diff --git a/arch/arm/mach-uniphier/timer.c b/arch/arm/mach-uniphier/timer.c index 27ada2924c9..a34e30b72bc 100644 --- a/arch/arm/mach-uniphier/timer.c +++ b/arch/arm/mach-uniphier/timer.c @@ -6,7 +6,8 @@ #include <common.h> #include <linux/io.h> -#include <mach/arm-mpcore.h> + +#include "arm-mpcore.h" #define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */ #define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1) diff --git a/arch/arm/mvebu-common/Makefile b/arch/arm/mvebu-common/Makefile deleted file mode 100644 index de243feaab5..00000000000 --- a/arch/arm/mvebu-common/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = dram.o -obj-y += gpio.o -obj-$(CONFIG_ARMADA_XP) += mbus.o -obj-y += timer.o - -obj-y += serdes/ diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 14f46a8f046..206be3e3ee5 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -25,7 +25,7 @@ _start: addi r8, r0, __end mts rslr, r8 - /* TODO: Redo this code to call board_init_f_mem() */ + /* TODO: Redo this code to call board_init_f_*() */ #if defined(CONFIG_SPL_BUILD) addi r1, r0, CONFIG_SPL_STACK_ADDR mts rshr, r1 @@ -142,7 +142,7 @@ _start: ori r12, r12, 0x1a0 mts rmsr, r12 - /* TODO: Redo this code to call board_init_f_mem() */ + /* TODO: Redo this code to call board_init_f_*() */ clear_bss: /* clear BSS segments */ addi r5, r0, __bss_start diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index 54787c53ca7..204d0cd9d4a 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -106,14 +106,18 @@ _reloc: stw r0, 4(sp) mov fp, sp - /* Allocate and zero GD, update SP */ + /* Allocate and initialize reserved area, update SP */ mov r4, sp - movhi r2, %hi(board_init_f_mem@h) - ori r2, r2, %lo(board_init_f_mem@h) + movhi r2, %hi(board_init_f_alloc_reserve@h) + ori r2, r2, %lo(board_init_f_alloc_reserve@h) callr r2 - - /* Update stack- and frame-pointers */ mov sp, r2 + mov r4, sp + movhi r2, %hi(board_init_f_init_reserve@h) + ori r2, r2, %lo(board_init_f_init_reserve@h) + callr r2 + + /* Update frame-pointer */ mov fp, sp /* Call board_init_f -- never returns */ diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 3dd0557aa66..137afce37a8 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -762,8 +762,9 @@ _start: bl cpu_init_f /* run low-level CPU init code (from Flash) */ #ifdef CONFIG_SYS_GENERIC_BOARD mr r3, r1 - bl board_init_f_mem + bl board_init_f_alloc_reserve mr r1, r3 + bl board_init_f_init_reserve li r0,0 stwu r0, -4(r1) stwu r0, -4(r1) @@ -1038,8 +1039,9 @@ _start: bl cpu_init_f /* run low-level CPU init code (from Flash) */ #ifdef CONFIG_SYS_GENERIC_BOARD mr r3, r1 - bl board_init_f_mem + bl board_init_f_alloc_reserve mr r1, r3 + bl board_init_f_init_reserve stwu r0, -4(r1) stwu r0, -4(r1) #endif diff --git a/arch/sandbox/cpu/eth-raw-os.c b/arch/sandbox/cpu/eth-raw-os.c index b76a7319aee..528865f5d3f 100644 --- a/arch/sandbox/cpu/eth-raw-os.c +++ b/arch/sandbox/cpu/eth-raw-os.c @@ -76,6 +76,10 @@ static int _raw_packet_start(const char *ifname, unsigned char *ethmac, printf("Failed to set promiscuous mode: %d %s\n" "Falling back to the old \"flags\" way...\n", errno, strerror(errno)); + if (strlen(ifname) >= IFNAMSIZ) { + printf("Interface name %s is too long.\n", ifname); + return -EINVAL; + } strncpy(ifr.ifr_name, ifname, IFNAMSIZ); if (ioctl(priv->sd, SIOCGIFFLAGS, &ifr) < 0) { printf("Failed to read flags: %d %s\n", errno, diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index 9b30451b28e..7299f2cddc9 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -14,12 +14,12 @@ static struct pci_device_id mmc_supported[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD }, + {}, }; int cpu_mmc_init(bd_t *bis) { - return pci_mmc_init("ValleyView SDHCI", mmc_supported, - ARRAY_SIZE(mmc_supported)); + return pci_mmc_init("ValleyView SDHCI", mmc_supported); } #ifndef CONFIG_EFI_APP diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 3e7a907e00f..434dfd649f6 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -86,8 +86,10 @@ static int bd82x6x_probe(struct udevice *dev) debug("%s: Cannot find GMA node\n", __func__); return -EINVAL; } - ret = gma_func0_init(PCH_VIDEO_DEV, pci_bus_to_hose(0), blob, - gma_node); + ret = dm_pci_bus_find_bdf(PCH_VIDEO_DEV, &dev); + if (ret) + return ret; + ret = gma_func0_init(dev, blob, gma_node); if (ret) return ret; diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index 89d4a5e9cca..85a09c64b67 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -728,8 +728,7 @@ static int int15_handler(void) return res; } -int gma_func0_init(pci_dev_t dev, struct pci_controller *hose, - const void *blob, int node) +int gma_func0_init(struct udevice *dev, const void *blob, int node) { #ifdef CONFIG_VIDEO ulong start; @@ -740,16 +739,16 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose, int ret; /* IGD needs to be Bus Master */ - reg32 = x86_pci_read_config32(dev, PCI_COMMAND); + dm_pci_read_config32(dev, PCI_COMMAND, ®32); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - x86_pci_write_config32(dev, PCI_COMMAND, reg32); + dm_pci_write_config32(dev, PCI_COMMAND, reg32); /* Use write-combining for the graphics memory, 256MB */ - base = pci_read_bar32(hose, dev, 2); + base = dm_pci_read_bar32(dev, 2); mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20); mtrr_commit(true); - gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0); + gtt_bar = (void *)dm_pci_read_bar32(dev, 0); debug("GT bar %p\n", gtt_bar); ret = gma_pm_init_pre_vbios(gtt_bar); if (ret) @@ -757,8 +756,8 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose, #ifdef CONFIG_VIDEO start = get_timer(0); - ret = pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE | - PCI_ROM_ALLOW_FALLBACK); + ret = dm_pci_run_vga_bios(dev, int15_handler, + PCI_ROM_USE_NATIVE | PCI_ROM_ALLOW_FALLBACK); debug("BIOS ran in %lums\n", get_timer(start)); #endif /* Post VBIOS init */ diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index c2bf497d684..37ce3940b08 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -19,6 +19,7 @@ static struct pci_device_id mmc_supported[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO }, + {}, }; /* @@ -337,8 +338,7 @@ int arch_early_init_r(void) int cpu_mmc_init(bd_t *bis) { - return pci_mmc_init("Quark SDHCI", mmc_supported, - ARRAY_SIZE(mmc_supported)); + return pci_mmc_init("Quark SDHCI", mmc_supported); } void cpu_irq_init(void) diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c index 9faf1b92bb0..b76dd7de697 100644 --- a/arch/x86/cpu/queensbay/topcliff.c +++ b/arch/x86/cpu/queensbay/topcliff.c @@ -11,10 +11,10 @@ static struct pci_device_id mmc_supported[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 }, + {}, }; int cpu_mmc_init(bd_t *bis) { - return pci_mmc_init("Topcliff SDHCI", mmc_supported, - ARRAY_SIZE(mmc_supported)); + return pci_mmc_init("Topcliff SDHCI", mmc_supported); } diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 5b4ee79d884..485868ff576 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -123,8 +123,9 @@ car_init_ret: #endif /* Set up global data */ mov %esp, %eax - call board_init_f_mem + call board_init_f_alloc_reserve mov %eax, %esp + call board_init_f_init_reserve #ifdef CONFIG_DEBUG_UART call debug_uart_init diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index 7786493be74..fcdf6e26cbb 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -12,8 +12,7 @@ void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node); void bd82x6x_pci_init(pci_dev_t dev); void bd82x6x_usb_ehci_init(pci_dev_t dev); void bd82x6x_usb_xhci_init(pci_dev_t dev); -int gma_func0_init(pci_dev_t dev, struct pci_controller *hose, - const void *blob, int node); +int gma_func0_init(struct udevice *dev, const void *blob, int node); int bd82x6x_init(void); /** diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c index 1d75cfc263c..9324bdb83e8 100644 --- a/arch/x86/lib/bios.c +++ b/arch/x86/lib/bios.c @@ -242,9 +242,10 @@ static void vbe_set_graphics(int vesa_mode, struct vbe_mode_info *mode_info) vbe_set_mode(mode_info); } -void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode, +void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode, struct vbe_mode_info *mode_info) { + pci_dev_t pcidev = dm_pci_get_bdf(dev); u32 num_dev; num_dev = PCI_BUS(pcidev) << 8 | PCI_DEV(pcidev) << 3 | diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c index 47d9f599a30..e8ca6e60f22 100644 --- a/arch/x86/lib/bios_interrupts.c +++ b/arch/x86/lib/bios_interrupts.c @@ -105,13 +105,15 @@ int int1a_handler(void) unsigned short func = (unsigned short)M.x86.R_EAX; int retval = 1; unsigned short devid, vendorid, devfn; + struct udevice *dev; /* Use short to get rid of gabage in upper half of 32-bit register */ short devindex; unsigned char bus; - pci_dev_t dev; + pci_dev_t bdf; u32 dword; u16 word; u8 byte, reg; + int ret; switch (func) { case 0xb101: /* PCIBIOS Check */ @@ -131,17 +133,20 @@ int int1a_handler(void) devid = M.x86.R_ECX; vendorid = M.x86.R_EDX; devindex = M.x86.R_ESI; - dev = pci_find_device(vendorid, devid, devindex); - if (dev != -1) { + bdf = -1; + ret = dm_pci_find_device(vendorid, devid, devindex, &dev); + if (!ret) { unsigned short busdevfn; + + bdf = dm_pci_get_bdf(dev); M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ M.x86.R_EAX |= PCIBIOS_SUCCESSFUL; /* * busnum is an unsigned char; * devfn is an int, so we mask it off. */ - busdevfn = (PCI_BUS(dev) << 8) | PCI_DEV(dev) << 3 | - PCI_FUNC(dev); + busdevfn = (PCI_BUS(bdf) << 8) | PCI_DEV(bdf) << 3 | + PCI_FUNC(bdf); debug("0x%x: return 0x%x\n", func, busdevfn); M.x86.R_EBX = busdevfn; retval = 1; @@ -160,35 +165,40 @@ int int1a_handler(void) devfn = M.x86.R_EBX & 0xff; bus = M.x86.R_EBX >> 8; reg = M.x86.R_EDI; - dev = PCI_BDF(bus, devfn >> 3, devfn & 7); + bdf = PCI_BDF(bus, devfn >> 3, devfn & 7); + + ret = dm_pci_bus_find_bdf(bdf, &dev); + if (ret) { + debug("%s: Device %x not found\n", __func__, bdf); + break; + } switch (func) { case 0xb108: /* Read Config Byte */ - byte = x86_pci_read_config8(dev, reg); + dm_pci_read_config8(dev, reg, &byte); M.x86.R_ECX = byte; break; case 0xb109: /* Read Config Word */ - word = x86_pci_read_config16(dev, reg); + dm_pci_read_config16(dev, reg, &word); M.x86.R_ECX = word; break; case 0xb10a: /* Read Config Dword */ - dword = x86_pci_read_config32(dev, reg); + dm_pci_read_config32(dev, reg, &dword); M.x86.R_ECX = dword; break; case 0xb10b: /* Write Config Byte */ byte = M.x86.R_ECX; - x86_pci_write_config8(dev, reg, byte); + dm_pci_write_config8(dev, reg, byte); break; case 0xb10c: /* Write Config Word */ word = M.x86.R_ECX; - x86_pci_write_config16(dev, reg, word); + dm_pci_write_config16(dev, reg, word); break; case 0xb10d: /* Write Config Dword */ dword = M.x86.R_ECX; - x86_pci_write_config32(dev, reg, dword); + dm_pci_write_config32(dev, reg, dword); break; } - #ifdef CONFIG_REALMODE_DEBUG debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func, bus, devfn, reg, M.x86.R_ECX); diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 5276ce6ab1a..8479af1d7e4 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -90,8 +90,8 @@ int x86_fsp_init(void) /* * The second time we enter here, adjust the size of malloc() * pool before relocation. Given gd->malloc_base was adjusted - * after the call to board_init_f_mem() in arch/x86/cpu/start.S, - * we should fix up gd->malloc_limit here. + * after the call to board_init_f_init_reserve() in arch/x86/ + * cpu/start.S, we should fix up gd->malloc_limit here. */ gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN; } |