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-rw-r--r--arch/arm/cpu/armv7/mpu_v7r.c11
-rw-r--r--arch/arm/lib/cache-cp15.c12
2 files changed, 22 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mpu_v7r.c b/arch/arm/cpu/armv7/mpu_v7r.c
index 567d9134144..7adecffff87 100644
--- a/arch/arm/cpu/armv7/mpu_v7r.c
+++ b/arch/arm/cpu/armv7/mpu_v7r.c
@@ -106,3 +106,14 @@ void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns)
icache_enable();
}
+
+void enable_caches(void)
+{
+ /*
+ * setup_mpu_regions() might have enabled Icache. So add a check
+ * before enabling Icache
+ */
+ if (!icache_status())
+ icache_enable();
+ dcache_enable();
+}
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index febb253f833..0688f1e6a67 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -8,11 +8,13 @@
#include <asm/system.h>
#include <asm/cache.h>
#include <linux/compiler.h>
+#include <asm/armv7_mpu.h>
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SYS_ARM_MMU
__weak void arm_init_before_mmu(void)
{
}
@@ -201,15 +203,23 @@ static int mmu_enabled(void)
{
return get_cr() & CR_M;
}
+#endif /* CONFIG_SYS_ARM_MMU */
/* cache_bit must be either CR_I or CR_C */
static void cache_enable(uint32_t cache_bit)
{
uint32_t reg;
- /* The data cache is not active unless the mmu is enabled too */
+ /* The data cache is not active unless the mmu/mpu is enabled too */
+#ifdef CONFIG_SYS_ARM_MMU
if ((cache_bit == CR_C) && !mmu_enabled())
mmu_setup();
+#elif defined(CONFIG_SYS_ARM_MPU)
+ if ((cache_bit == CR_C) && !mpu_enabled()) {
+ printf("Consider enabling MPU before enabling caches\n");
+ return;
+ }
+#endif
reg = get_cr(); /* get control reg. */
set_cr(reg | cache_bit);
}