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-rw-r--r--arch/arm/Kconfig8
-rw-r--r--arch/arm/dts/Makefile2
-rw-r--r--arch/arm/dts/k3-am654-r5-base-board.dts27
-rw-r--r--arch/arm/dts/k3-j721e-mcu-wakeup.dtsi11
-rw-r--r--arch/arm/dts/k3-j721e-r5-common-proc-board.dts44
-rw-r--r--arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi20
-rw-r--r--arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi20
-rw-r--r--arch/arm/dts/phytium-durian.dts33
-rw-r--r--arch/arm/include/asm/io.h97
-rw-r--r--arch/arm/lib/cache-cp15.c6
-rw-r--r--arch/arm/mach-k3/am6_init.c7
-rw-r--r--arch/arm/mach-k3/j721e_init.c7
-rw-r--r--arch/arm/mach-socfpga/Kconfig3
13 files changed, 285 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 629c5e8c2d3..7b80630aa1c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1631,6 +1631,13 @@ config ARCH_ASPEED
select OF_CONTROL
imply CMD_DM
+config TARGET_DURIAN
+ bool "Support Phytium Durian Platform"
+ select ARM64
+ help
+ Support for durian platform.
+ It has 2GB Sdram, uart and pcie.
+
endchoice
config ARCH_SUPPORT_TFABOOT
@@ -1830,6 +1837,7 @@ source "board/woodburn/Kconfig"
source "board/xilinx/Kconfig"
source "board/xilinx/zynq/Kconfig"
source "board/xilinx/zynqmp/Kconfig"
+source "board/phytium/durian/Kconfig"
source "arch/arm/Kconfig.debug"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 251d32ca62d..89ab8001ce7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -834,6 +834,8 @@ dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb
dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb
+dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 174d2023060..5c110ef9dde 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -97,6 +97,13 @@
u-boot,dm-spl;
};
+ wkup_vtm0: wkup_vtm@42050000 {
+ compatible = "ti,am654-vtm", "ti,am654-avs";
+ reg = <0x42050000 0x25c>;
+ power-domains = <&k3_pds 80>;
+ #thermal-sensor-cells = <1>;
+ };
+
clk_200mhz: dummy_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -131,6 +138,12 @@
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
+&wkup_vtm0 {
+ vdd-supply-3 = <&vdd_mpu>;
+ vdd-supply-4 = <&vdd_mpu>;
+ u-boot,dm-spl;
+};
+
&wkup_pmx0 {
u-boot,dm-spl;
wkup_uart0_pins_default: wkup_uart0_pins_default {
@@ -211,4 +224,18 @@
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
+ u-boot,dm-spl;
+
+ vdd_mpu: tps62363@60 {
+ compatible = "ti,tps62363";
+ reg = <0x60>;
+ regulator-name = "VDD_MPU";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1770000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ti,vsel0-state-high;
+ ti,vsel1-state-high;
+ u-boot,dm-spl;
+ };
};
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
index 92beeea34db..5dd07ac4daf 100644
--- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
@@ -57,6 +57,17 @@
clock-names = "fclk";
};
+ wkup_i2c0: i2c@42120000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x42120000 0x0 0x100>;
+ interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 197 0>;
+ power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
+ };
+
mcu_uart0: serial@40a00000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 54d7998d27a..41af48214f6 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -59,6 +59,13 @@
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx";
};
+
+ wkup_vtm0: wkup_vtm@42040000 {
+ compatible = "ti,am654-vtm", "ti,j721e-avs";
+ reg = <0x0 0x42040000 0x0 0x330>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
&dmsc {
@@ -86,6 +93,13 @@
J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
>;
};
+
+ wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
+ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
+ >;
+ };
};
&main_pmx0 {
@@ -140,4 +154,34 @@
ti,driver-strength-ohm = <50>;
};
+&wkup_i2c0 {
+ u-boot,dm-spl;
+ tps659413a: tps659413a@48 {
+ reg = <0x48>;
+ compatible = "ti,tps659413";
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ regulators: regulators {
+ u-boot,dm-spl;
+ buck12_reg: buck12 {
+ /*VDD_MPU*/
+ regulator-name = "buck12";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ u-boot,dm-spl;
+ };
+ };
+ };
+};
+
+&wkup_vtm0 {
+ vdd-supply-2 = <&buck12_reg>;
+ u-boot,dm-spl;
+};
+
#include "k3-j721e-common-proc-board-u-boot.dtsi"
diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi
index 1abd9a38870..e5d9e4f1b1d 100644
--- a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi
+++ b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi
@@ -17,6 +17,26 @@
};
};
+&gpio1 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio2 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio3 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio5 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio6 {
+ /delete-property/ u-boot,dm-spl;
+};
+
&i2c1 {
clock-frequency = <400000>;
};
diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi
index 976330f8971..76f74326ae8 100644
--- a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi
+++ b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi
@@ -21,6 +21,26 @@
clock-frequency = <400000>;
};
+&gpio1 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio2 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio3 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio5 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio6 {
+ /delete-property/ u-boot,dm-spl;
+};
+
/delete-node/ &uart2;
/delete-node/ &uart3;
/delete-node/ &mmc2;
diff --git a/arch/arm/dts/phytium-durian.dts b/arch/arm/dts/phytium-durian.dts
new file mode 100644
index 00000000000..3b76949a264
--- /dev/null
+++ b/arch/arm/dts/phytium-durian.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Phytium Ltd.
+ * shuyiqi <shuyiqi@phytium.com.cn>
+ */
+
+/dts-v1/;
+
+/ {
+ model = "Phytium Durian";
+ compatible = "phytium,durian";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie-controller@40000000 {
+ compatible = "phytium,pcie-host-1.0";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0x0 0x40000000 0x0 0x10000000>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x1000000 0x0 0x0 0x0 0x50000000 0x0 0xF00000>,
+ <0x2000000 0x0 0x58000000 0x0 0x58000000 0x0 0x28000000>,
+ <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>;
+ };
+
+ uart@28001000 {
+ compatible = "arm,pl011";
+ reg = <0x0 0x28001000 0x0 0x1000>;
+ clock = <48000000>;
+ };
+};
+
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 723f3cf497d..8959749ad65 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -23,6 +23,7 @@
#ifdef __KERNEL__
#include <linux/types.h>
+#include <linux/kernel.h>
#include <asm/byteorder.h>
#include <asm/memory.h>
#include <asm/barriers.h>
@@ -315,9 +316,105 @@ extern void _memset_io(unsigned long, int, size_t);
extern void __readwrite_bug(const char *fn);
+/* Optimized copy functions to read from/write to IO sapce */
+#ifdef CONFIG_ARM64
+/*
+ * Copy data from IO memory space to "real" memory space.
+ */
+static inline
+void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count)
+{
+ while (count && !IS_ALIGNED((unsigned long)from, 8)) {
+ *(u8 *)to = __raw_readb(from);
+ from++;
+ to++;
+ count--;
+ }
+
+ while (count >= 8) {
+ *(u64 *)to = __raw_readq(from);
+ from += 8;
+ to += 8;
+ count -= 8;
+ }
+
+ while (count) {
+ *(u8 *)to = __raw_readb(from);
+ from++;
+ to++;
+ count--;
+ }
+}
+
+/*
+ * Copy data from "real" memory space to IO memory space.
+ */
+static inline
+void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count)
+{
+ while (count && !IS_ALIGNED((unsigned long)to, 8)) {
+ __raw_writeb(*(u8 *)from, to);
+ from++;
+ to++;
+ count--;
+ }
+
+ while (count >= 8) {
+ __raw_writeq(*(u64 *)from, to);
+ from += 8;
+ to += 8;
+ count -= 8;
+ }
+
+ while (count) {
+ __raw_writeb(*(u8 *)from, to);
+ from++;
+ to++;
+ count--;
+ }
+}
+
+/*
+ * "memset" on IO memory space.
+ */
+static inline
+void __memset_io(volatile void __iomem *dst, int c, size_t count)
+{
+ u64 qc = (u8)c;
+
+ qc |= qc << 8;
+ qc |= qc << 16;
+ qc |= qc << 32;
+
+ while (count && !IS_ALIGNED((unsigned long)dst, 8)) {
+ __raw_writeb(c, dst);
+ dst++;
+ count--;
+ }
+
+ while (count >= 8) {
+ __raw_writeq(qc, dst);
+ dst += 8;
+ count -= 8;
+ }
+
+ while (count) {
+ __raw_writeb(c, dst);
+ dst++;
+ count--;
+ }
+}
+#endif /* CONFIG_ARM64 */
+
+#ifdef CONFIG_ARM64
+#define memset_io(a, b, c) __memset_io((a), (b), (c))
+#define memcpy_fromio(a, b, c) __memcpy_fromio((a), (b), (c))
+#define memcpy_toio(a, b, c) __memcpy_toio((a), (b), (c))
+#else
#define memset_io(a, b, c) memset((void *)(a), (b), (c))
#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
+#endif
/*
* If this architecture has ISA IO, then define the isa_read/isa_write
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index b2913e8165a..47c223917a0 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -235,12 +235,18 @@ static void cache_disable(uint32_t cache_bit)
/* if cache isn;t enabled no need to disable */
if ((reg & CR_C) != CR_C)
return;
+#ifdef CONFIG_SYS_ARM_MMU
/* if disabling data cache, disable mmu too */
cache_bit |= CR_M;
+#endif
}
reg = get_cr();
+#ifdef CONFIG_SYS_ARM_MMU
if (cache_bit == (CR_C | CR_M))
+#elif defined(CONFIG_SYS_ARM_MPU)
+ if (cache_bit == CR_C)
+#endif
flush_dcache_all();
set_cr(reg & ~cache_bit);
}
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index 0b564f7bd16..99edcd9a247 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -116,6 +116,13 @@ void board_init_f(ulong dummy)
/* Perform EEPROM-based board detection */
do_board_detect();
+#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
+ &dev);
+ if (ret)
+ printf("AVS init failed: %d\n", ret);
+#endif
+
#ifdef CONFIG_K3_AM654_DDRSS
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret)
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 5e3813252ba..d0bf86abeb2 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -118,6 +118,13 @@ void board_init_f(ulong dummy)
preloader_console_init();
#endif
+#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
+ &dev);
+ if (ret)
+ printf("AVS init failed: %d\n", ret);
+#endif
+
#if defined(CONFIG_K3_J721E_DDRSS)
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index fc0a54214f8..3770e072585 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -1,5 +1,8 @@
if ARCH_SOCFPGA
+config ERR_PTR_OFFSET
+ default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
+
config NR_DRAM_BANKS
default 1
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-21 10:46:12 +0000