diff options
Diffstat (limited to 'arch')
618 files changed, 56761 insertions, 57064 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index b6fb9e92733..abd406d4884 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -20,6 +20,12 @@ config SYS_CACHE_SHIFT_6 config SYS_CACHE_SHIFT_7 bool +config 32BIT + bool + +config 64BIT + bool + config SYS_CACHELINE_SIZE int default 128 if SYS_CACHE_SHIFT_7 @@ -248,7 +254,6 @@ config X86 imply CMD_PCI imply CMD_SF imply CMD_SF_TEST - imply CMD_ZBOOT imply DM_GPIO imply DM_KEYBOARD imply DM_MMC @@ -361,7 +366,16 @@ config SYS_BOARD leave this option empty. config SYS_CONFIG_NAME - string + string "Board header file" if ARCH_MESON || ARCH_VERSAL || \ + ARCH_VERSAL_NET || ARCH_ZYNQ || ARCH_ZYNQMP || \ + ARCH_ZYNQMP_R5 || MICROBLAZE || NIOS2 + default "meson64" if ARCH_MESON + default "microblaze-generic" if MICROBLAZE + default "xilinx_versal" if ARCH_VERSAL + default "xilinx_versal_net" if ARCH_VERSAL_NET + default "xilinx_zynqmp" if ARCH_ZYNQMP + default "xilinx_zynqmp_r5" if ARCH_ZYNQMP_R5 + default "zynq-common" if ARCH_ZYNQ help This option should contain the base name of board header file. The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9b83b2e6f8f..9b17ad3e3f8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -6,6 +6,7 @@ config SYS_ARCH config ARM64 bool + select 64BIT select PHYS_64BIT select SYS_CACHE_SHIFT_6 imply SPL_SEPARATE_BSS @@ -28,6 +29,7 @@ config COUNTER_FREQUENCY ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A default 100000000 if ARCH_ZYNQMP + default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5 default 0 help For platforms with ARMv8-A and ARMv7-A which features a system @@ -122,6 +124,15 @@ config GIC_V3_ITS ARM GICV3 has limitation, once the LPI table is enabled, LPI configuration table can not be re-programmed, unless GICV3 reset. +config GICV3_SUPPORT_GIC600 + bool "ARM GICV3 GIC600 SUPPORT" + help + ARM GIC-600 IP complies with ARM GICv3 architecture, but among others, + implements a power control register in the Redistributor frame.This + register must be programmed to mark the frame as powered on, before + accessing other registers in the frame. Rest of initialization sequence + remains the same. + config STATIC_RELA bool default y if ARM64 @@ -631,20 +642,6 @@ config ARCH_ORION5X select SPL_SEPARATE_BSS if SPL select TIMER -config TARGET_STV0991 - bool "Support stv0991" - select CPU_V7A - select DM - select DM_SERIAL - select DM_SPI - select DM_SPI_FLASH - select GPIO_EXTRA_HEADER - select PL01X_SERIAL - select MTD - select SPI - select SPI_FLASH - imply CMD_DM - config ARCH_BCM283X bool "Broadcom BCM283X family" select DM @@ -699,15 +696,6 @@ config TARGET_BCMNS ARMv7 Cortex-A9 SoC family including BCM4708, BCM47094, BCM5301x etc. -config TARGET_BCMNS2 - bool "Support Broadcom Northstar2" - select ARM64 - select GPIO_EXTRA_HEADER - help - Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit - ARMv8 Cortex-A57 processors targeting a broad range of networking - applications. - config TARGET_BCMNS3 bool "Support Broadcom NS3" select ARM64 @@ -1080,6 +1068,7 @@ config ARCH_RENESAS imply BOARD_EARLY_INIT_F imply CMD_DM imply FAT_WRITE + imply OF_UPSTREAM imply SYS_THUMB_BUILD imply ARCH_MISC_INIT if DISPLAY_CPUINFO @@ -1090,12 +1079,17 @@ config ARCH_SNAPDRAGON select DM_GPIO select DM_SERIAL select DM_RESET + select POWER_DOMAIN select GPIO_EXTRA_HEADER select MSM_SMEM select OF_CONTROL select OF_SEPARATE select SMEM select SPMI + select BOARD_LATE_INIT + select OF_BOARD + select SAVE_PREV_BL_FDT_ADDR + select LINUX_KERNEL_IMAGE_HEADER imply CMD_DM config ARCH_SOCFPGA @@ -1116,6 +1110,8 @@ config ARCH_SOCFPGA select SPL_LIBGENERIC_SUPPORT select SPL_OF_CONTROL select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 + select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64 + select SPL_SOCFPGA_DT_REG if TARGET_SOCFPGA_SOC64 select SPL_SERIAL select SPL_SYSRESET select SPL_WATCHDOG @@ -1124,7 +1120,8 @@ config ARCH_SOCFPGA select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64 + select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \ + TARGET_SOCFPGA_SOC64 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY @@ -1325,6 +1322,14 @@ config ARCH_ZYNQMP select SPL_DM_SPI_FLASH if SPL_DM_SPI select SPL_DM_MAILBOX if SPL imply SPL_FIRMWARE if SPL + imply SPL_FS_FAT if SPL + imply SPL_LIBCOMMON_SUPPORT if SPL + imply SPL_LIBDISK_SUPPORT if SPL + imply SPL_LIBGENERIC_SUPPORT if SPL + imply SPL_MMC if SPL && MMC_SDHCI_ZYNQ + imply SPL_SERIAL if SPL + imply SPL_SPI if SPL && ZYNQ_QSPI + imply SPL_SPI_FLASH_SUPPORT if SPL && ZYNQ_QSPI select SPL_SEPARATE_BSS if SPL select SUPPORT_SPL imply ZYNQMP_IPI if DM_MAILBOX @@ -1340,7 +1345,7 @@ config ARCH_ZYNQMP config ARCH_TEGRA bool "NVIDIA Tegra" select GPIO_EXTRA_HEADER - imply DISTRO_DEFAULTS + imply BOOTSTD_DEFAULTS imply FAT_WRITE imply SPL_TIMER if SPL @@ -2363,7 +2368,6 @@ source "board/samsung/common/Kconfig" source "board/siemens/common/Kconfig" source "board/seeed/npi_imx6ull/Kconfig" source "board/socionext/developerbox/Kconfig" -source "board/st/stv0991/Kconfig" source "board/tcl/sl50/Kconfig" source "board/traverse/ten64/Kconfig" source "board/variscite/dart_6ul/Kconfig" diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 653eef8ad79..99cf9eb515f 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -37,7 +37,6 @@ obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/ obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/ obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/ obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/ -obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_VF610) += vf610/ obj-$(CONFIG_ARCH_S5P4418) += s5p4418/ diff --git a/arch/arm/cpu/armv7/s5p4418/Makefile b/arch/arm/cpu/armv7/s5p4418/Makefile index 321b257b6d4..58042581c42 100644 --- a/arch/arm/cpu/armv7/s5p4418/Makefile +++ b/arch/arm/cpu/armv7/s5p4418/Makefile @@ -2,5 +2,8 @@ # # (C) Copyright 2016 Nexell # Hyunseok, Jung <hsjung@nexell.co.kr> +# +# Copyright (C) 2023 Stefan Bosch <stefan_b@posteo.net> obj-y += cpu.o +obj-y += relocate.o diff --git a/arch/arm/cpu/armv7/s5p4418/relocate.S b/arch/arm/cpu/armv7/s5p4418/relocate.S new file mode 100644 index 00000000000..d6e76adceb1 --- /dev/null +++ b/arch/arm/cpu/armv7/s5p4418/relocate.S @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * relocate - S5P4418 specific relocation for ARM U-Boot + * + * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net> + * Copyright (C) 2023 Stefan Bosch <stefan_b@posteo.net> + */ + +#include <asm-offsets.h> +#include <asm/assembler.h> +#include <linux/linkage.h> + +ENTRY(relocate_vectors) + + /* + * The s5p4418 SoC has the security extensions, so use VBAR to relocate + * the exception vectors. + */ + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ + add r0, #0x400 /* vectors are after NSIH + 0x200 */ + mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */ + ret lr + +ENDPROC(relocate_vectors) diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 69e281b086a..7730a16e512 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -152,9 +152,38 @@ ENDPROC(c_runtime_cpu_setup) * *************************************************************************/ WEAK(save_boot_params) +#if (IS_ENABLED(CONFIG_BLOBLIST)) + /* Calculate the PC-relative address of saved_args */ + adr r12, saved_args_offset + ldr r13, saved_args_offset + add r12, r12, r13 + + /* + * Intentionally swapping r0 with r2 in order to simplify the C + * function we use later. + */ + str r2, [r12] + str r1, [r12, #4] + str r0, [r12, #8] + str r3, [r12, #12] +#endif b save_boot_params_ret @ back to my caller ENDPROC(save_boot_params) +#if (IS_ENABLED(CONFIG_BLOBLIST)) +saved_args_offset: + .long saved_args - . /* offset from current code to save_args */ + + .section .data + .align 2 + .global saved_args +saved_args: + .rept 4 + .word 0 + .endr +END(saved_args) +#endif + #ifdef CONFIG_ARMV7_LPAE WEAK(switch_to_hypervisor) b switch_to_hypervisor_ret diff --git a/arch/arm/cpu/armv7/stv0991/Makefile b/arch/arm/cpu/armv7/stv0991/Makefile deleted file mode 100644 index 3be5eba4b12..00000000000 --- a/arch/arm/cpu/armv7/stv0991/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2014, STMicroelectronics - All Rights Reserved -# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - -obj-y := timer.o clock.o pinmux.o reset.o -obj-y += lowlevel.o diff --git a/arch/arm/cpu/armv7/stv0991/clock.c b/arch/arm/cpu/armv7/stv0991/clock.c deleted file mode 100644 index 1e35deed353..00000000000 --- a/arch/arm/cpu/armv7/stv0991/clock.c +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/stv0991_cgu.h> -#include<asm/arch/stv0991_periph.h> - -static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ - (struct stv0991_cgu_regs *) (CGU_BASE_ADDR); - -void enable_pll1(void) -{ - /* pll1 already configured for 1000Mhz, just need to enable it */ - writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01), - &stv0991_cgu_regs->pll1_ctrl); -} - -void clock_setup(int peripheral) -{ - switch (peripheral) { - case UART_CLOCK_CFG: - writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq); - break; - case ETH_CLOCK_CFG: - enable_pll1(); - writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq); - - /* Clock selection for ethernet tx_clk & rx_clk*/ - writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK) - | ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl); - break; - case QSPI_CLOCK_CFG: - writel(QSPI_CLK_CTRL, &stv0991_cgu_regs->qspi_freq); - break; - default: - break; - } -} diff --git a/arch/arm/cpu/armv7/stv0991/lowlevel.S b/arch/arm/cpu/armv7/stv0991/lowlevel.S deleted file mode 100644 index 5733eaa15c0..00000000000 --- a/arch/arm/cpu/armv7/stv0991/lowlevel.S +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 STMicroelectronics - */ - -#include <config.h> -#include <linux/linkage.h> - -ENTRY(lowlevel_init) - mov pc, lr -ENDPROC(lowlevel_init) diff --git a/arch/arm/cpu/armv7/stv0991/pinmux.c b/arch/arm/cpu/armv7/stv0991/pinmux.c deleted file mode 100644 index 6c44ffe50e8..00000000000 --- a/arch/arm/cpu/armv7/stv0991/pinmux.c +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#include <asm/io.h> -#include <asm/arch/stv0991_creg.h> -#include <asm/arch/stv0991_periph.h> -#include <asm/arch/hardware.h> - -static struct stv0991_creg *const stv0991_creg = \ - (struct stv0991_creg *)CREG_BASE_ADDR; - -int stv0991_pinmux_config(int peripheral) -{ - switch (peripheral) { - case UART_GPIOC_30_31: - /* SSDA/SSCL pad muxing to UART Rx/Dx */ - writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) | - CFG_GPIOC_31_UART_RX, - &stv0991_creg->mux12); - writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) | - CFG_GPIOC_30_UART_TX, - &stv0991_creg->mux12); - /* SSDA/SSCL pad config to push pull*/ - writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) | - CFG_GPIOC_31_MODE_PP, - &stv0991_creg->cfg_pad6); - writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) | - CFG_GPIOC_30_MODE_HIGH, - &stv0991_creg->cfg_pad6); - break; - case UART_GPIOB_16_17: - /* ethernet rx_6/7 to UART Rx/Dx */ - writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) | - CFG_GPIOB_17_UART_RX, - &stv0991_creg->mux7); - writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) | - CFG_GPIOB_16_UART_TX, - &stv0991_creg->mux7); - break; - case ETH_GPIOB_10_31_C_0_4: - writel(readl(&stv0991_creg->mux6) & 0x000000FF, - &stv0991_creg->mux6); - writel(0x00000000, &stv0991_creg->mux7); - writel(0x00000000, &stv0991_creg->mux8); - writel(readl(&stv0991_creg->mux9) & 0xFFF00000, - &stv0991_creg->mux9); - /* Ethernet Voltage configuration to 1.8V*/ - writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | - ETH_VDD_CFG, &stv0991_creg->vdd_pad1); - writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | - ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1); - - break; - case QSPI_CS_CLK_PAD: - writel((readl(&stv0991_creg->mux13) & FLASH_CS_NC_MASK) | - CFG_FLASH_CS_NC, &stv0991_creg->mux13); - writel((readl(&stv0991_creg->mux13) & FLASH_CLK_MASK) | - CFG_FLASH_CLK, &stv0991_creg->mux13); - default: - break; - } - return 0; -} diff --git a/arch/arm/cpu/armv7/stv0991/reset.c b/arch/arm/cpu/armv7/stv0991/reset.c deleted file mode 100644 index 77d4477c8dc..00000000000 --- a/arch/arm/cpu/armv7/stv0991/reset.c +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#include <common.h> -#include <cpu_func.h> -#include <asm/io.h> -#include <asm/arch/stv0991_wdru.h> -#include <linux/delay.h> -void reset_cpu(void) -{ - puts("System is going to reboot ...\n"); - /* - * This 1 second delay will allow the above message - * to be printed before reset - */ - udelay((1000 * 1000)); - - /* Setting bit 1 of the WDRU unit will reset the SoC */ - writel(WDRU_RST_SYS, &stv0991_wd_ru_ptr->wdru_ctrl1); - - /* system will restart */ - while (1) - ; -} diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c deleted file mode 100644 index f7cc45772f9..00000000000 --- a/arch/arm/cpu/armv7/stv0991/timer.c +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#include <common.h> -#include <init.h> -#include <time.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch-stv0991/hardware.h> -#include <asm/arch-stv0991/stv0991_cgu.h> -#include <asm/arch-stv0991/stv0991_gpt.h> -#include <linux/delay.h> - -static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ - (struct stv0991_cgu_regs *) (CGU_BASE_ADDR); - -#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) -#define GPT_RESOLUTION (CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp gd->arch.tbl -#define lastdec gd->arch.lastinc - -static ulong get_timer_masked(void); - -int timer_init(void) -{ - /* Timer1 clock configuration */ - writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq); - writel(readl(&stv0991_cgu_regs->cgu_enable_2) | - TIMER1_CLK_EN, &stv0991_cgu_regs->cgu_enable_2); - - /* Stop the timer */ - writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1); - writel(GPT_PRESCALER_128, &gpt1_regs_ptr->psc); - /* Configure timer for auto-reload */ - writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD, - &gpt1_regs_ptr->cr1); - - /* load value for free running */ - writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr); - - /* start timer */ - writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN, - &gpt1_regs_ptr->cr1); - - /* Reset the timer */ - lastdec = READ_TIMER(); - timestamp = 0; - - return 0; -} - -/* - * timer without interrupts - */ -ulong get_timer(ulong base) -{ - return (get_timer_masked() / GPT_RESOLUTION) - base; -} - -void __udelay(unsigned long usec) -{ - ulong tmo; - ulong start = get_timer_masked(); - ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100); - ulong rndoff; - - rndoff = (usec % 10) ? 1 : 0; - - /* tenudelcnt timer tick gives 10 microsecconds delay */ - tmo = ((usec / 10) + rndoff) * tenudelcnt; - - while ((ulong) (get_timer_masked() - start) < tmo) - ; -} - -static ulong get_timer_masked(void) -{ - ulong now = READ_TIMER(); - - if (now >= lastdec) { - /* normal mode */ - timestamp += now - lastdec; - } else { - /* we have an overflow ... */ - timestamp += now + GPT_FREE_RUNNING - lastdec; - } - lastdec = now; - - return timestamp; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 3fe935cf283..c9e46859b4f 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -20,6 +20,7 @@ * * x0: cache level * x1: 0 clean & invalidate, 1 invalidate only + * x16: FEAT_CCIDX * x2~x9: clobbered */ .pushsection .text.__asm_dcache_level, "ax" @@ -29,8 +30,14 @@ ENTRY(__asm_dcache_level) isb /* sync change of cssidr_el1 */ mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ ubfx x2, x6, #0, #3 /* x2 <- log2(cache line size)-4 */ + cbz x16, 3f /* check for FEAT_CCIDX */ + ubfx x3, x6, #3, #21 /* x3 <- number of cache ways - 1 */ + ubfx x4, x6, #32, #24 /* x4 <- number of cache sets - 1 */ + b 4f +3: ubfx x3, x6, #3, #10 /* x3 <- number of cache ways - 1 */ ubfx x4, x6, #13, #15 /* x4 <- number of cache sets - 1 */ +4: add x2, x2, #4 /* x2 <- log2(cache line size) */ clz w5, w3 /* bit position of #ways */ /* x12 <- cache level << 1 */ @@ -74,6 +81,8 @@ ENTRY(__asm_dcache_all) ubfx x11, x10, #24, #3 /* x11 <- loc */ cbz x11, finished /* if loc is 0, exit */ mov x15, lr + mrs x16, s3_0_c0_c7_2 /* read value of id_aa64mmfr2_el1*/ + ubfx x16, x16, #20, #4 /* save FEAT_CCIDX identifier in x16 */ mov x0, #0 /* start flush at cache level 0 */ /* x0 <- cache level */ /* x10 <- clidr_el1 */ diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 697334086fd..57d06f0575d 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -326,6 +326,8 @@ static void map_range(u64 virt, u64 phys, u64 size, int level, /* Going one level down */ if (pte_type(&table[i]) == PTE_TYPE_FAULT) set_pte_table(&table[i], create_table()); + else if (pte_type(&table[i]) != PTE_TYPE_TABLE) + split_block(&table[i], level); next_table = (u64 *)(table[i] & GENMASK_ULL(47, PAGE_SHIFT)); next_size = min(map_size - (virt & (map_size - 1)), size); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c index 1541dfb3ec4..b1bb29bcaf5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -258,7 +258,7 @@ int setup_serdes_volt(u32 svdd) /* Wait for SVDD to stabilize */ udelay(100); - /* For each PLL that’s not disabled via RCW */ + /* For each PLL that's not disabled via RCW */ #ifdef CONFIG_SYS_FSL_SRDS_1 cfg_tmp = (cfg_rcw5 >> 22) & 0x3; for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index c0efc341afc..fbd5fd7d433 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -483,7 +483,7 @@ int setup_serdes_volt(u32 svdd) ret = -1; } - /* For each PLL that’s not disabled via RCW enable the SERDES */ + /* For each PLL that's not disabled via RCW enable the SERDES */ #ifdef CONFIG_SYS_FSL_SRDS_1 cfg_tmp = cfg_rcwsrds1 & 0x3; do_serdes_enable(cfg_tmp, serdes1_base); diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 6cc1d26e5e2..74612802617 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -370,5 +370,28 @@ ENTRY(c_runtime_cpu_setup) ENDPROC(c_runtime_cpu_setup) WEAK(save_boot_params) +#if (IS_ENABLED(CONFIG_BLOBLIST)) + /* Calculate the PC-relative address of saved_args */ + adr x9, saved_args_offset + ldr w10, saved_args_offset + add x9, x9, w10, sxtw + + stp x0, x1, [x9] + stp x2, x3, [x9, #16] +#endif b save_boot_params_ret /* back to my caller */ ENDPROC(save_boot_params) + +#if (IS_ENABLED(CONFIG_BLOBLIST)) +saved_args_offset: + .long saved_args - . /* offset from current code to save_args */ + + .section .data + .align 2 + .global saved_args +saved_args: + .rept 4 + .dword 0 + .endr +END(saved_args) +#endif diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds index 7cb9d731246..ef8af67e11c 100644 --- a/arch/arm/cpu/armv8/u-boot-spl.lds +++ b/arch/arm/cpu/armv8/u-boot-spl.lds @@ -21,9 +21,9 @@ OUTPUT_ARCH(aarch64) ENTRY(_start) SECTIONS { + __image_copy_start = ADDR(.text); .text : { . = ALIGN(8); - __image_copy_start = .; CPUDIR/start.o (.text*) *(.text*) } >.sram @@ -51,10 +51,8 @@ SECTIONS KEEP(*(SORT(__u_boot_list*))); } >.sram - .image_copy_end : { - . = ALIGN(8); - *(.__image_copy_end) - } >.sram + . = ALIGN(8); + __image_copy_end = .; .end : { . = ALIGN(8); @@ -63,18 +61,11 @@ SECTIONS _image_binary_end = .; - .bss_start (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.__bss_start)); - } >.sdram - - .bss (NOLOAD) : { + .bss : { + __bss_start = .; *(.bss*) - . = ALIGN(8); - } >.sdram - - .bss_end (NOLOAD) : { - KEEP(*(.__bss_end)); + . = ALIGN(8); + __bss_end = .; } >.sdram /DISCARD/ : { *(.rela*) } @@ -89,3 +80,6 @@ SECTIONS #include "linux-kernel-image-header-vars.h" #endif } + +ASSERT(ADDR(.bss) % 8 == 0, \ + ".bss must be 8-byte aligned"); diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds index fb6a30c922f..857f44412e0 100644 --- a/arch/arm/cpu/armv8/u-boot.lds +++ b/arch/arm/cpu/armv8/u-boot.lds @@ -21,9 +21,9 @@ SECTIONS . = 0x00000000; . = ALIGN(8); + __image_copy_start = ADDR(.text); .text : { - *(.__image_copy_start) CPUDIR/start.o (.text*) } @@ -115,8 +115,6 @@ SECTIONS KEEP(*(SORT(__u_boot_list*))); } - . = ALIGN(8); - .efi_runtime_rel : { __efi_runtime_rel_start = .; *(.rel*.efi_runtime) @@ -125,43 +123,24 @@ SECTIONS } . = ALIGN(8); - - .image_copy_end : - { - *(.__image_copy_end) - } - - . = ALIGN(8); - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } + __image_copy_end = .; .rela.dyn : { + __rel_dyn_start = .; *(.rela*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) + __rel_dyn_end = .; } _end = .; - . = ALIGN(8); - - .bss_start : { - KEEP(*(.__bss_start)); - } - - .bss : { + /* + * arch/arm/lib/crt0_64.S assumes __bss_start - __bss_end % 8 == 0 + */ + .bss ALIGN(8) : { + __bss_start = .; *(.bss*) - . = ALIGN(8); - } - - .bss_end : { - KEEP(*(.__bss_end)); + . = ALIGN(8); + __bss_end = .; } /DISCARD/ : { *(.dynsym) } diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index fb2189d50de..9ed62395a9c 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -14,9 +14,9 @@ SECTIONS . = 0x00000000; . = ALIGN(4); + __image_copy_start = ADDR(.text); .text : { - __image_copy_start = .; *(.vectors) CPUDIR/start.o (.text*) *(.text*) diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 7724c9332c3..707b19795f0 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -35,26 +35,20 @@ SECTIONS . = 0x00000000; . = ALIGN(4); + __image_copy_start = ADDR(.text); .text : { - *(.__image_copy_start) *(.vectors) CPUDIR/start.o (.text*) } /* This needs to come before *(.text*) */ - .__efi_runtime_start : { - *(.__efi_runtime_start) - } - .efi_runtime : { + __efi_runtime_start = .; *(.text.efi_runtime*) *(.rodata.efi_runtime*) *(.data.efi_runtime*) - } - - .__efi_runtime_stop : { - *(.__efi_runtime_stop) + __efi_runtime_stop = .; } .text_rest : @@ -152,42 +146,24 @@ SECTIONS KEEP(*(SORT(__u_boot_list*))); } - . = ALIGN(4); - - .efi_runtime_rel_start : - { - *(.__efi_runtime_rel_start) - } - .efi_runtime_rel : { + __efi_runtime_rel_start = .; *(.rel*.efi_runtime) *(.rel*.efi_runtime.*) - } - - .efi_runtime_rel_stop : - { - *(.__efi_runtime_rel_stop) + __efi_runtime_rel_stop = .; } . = ALIGN(4); + __image_copy_end = .; - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { + /* + * if CONFIG_USE_ARCH_MEMSET is not selected __bss_end - __bss_start + * needs to be a multiple of 4 and we overlay .bss with .rel.dyn + */ + .rel.dyn ALIGN(4) : { + __rel_dyn_start = .; *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) + __rel_dyn_end = .; } .end : @@ -207,23 +183,15 @@ SECTIONS } /* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) + * These sections occupy the same memory, but their lifetimes do + * not overlap: U-Boot initializes .bss only after applying dynamic + * relocations and therefore after it doesn't need .rel.dyn any more. */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { + .bss ADDR(.rel.dyn) (OVERLAY): { + __bss_start = .; *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); + . = ALIGN(4); + __bss_end = .; } .dynsym _image_binary_end : { *(.dynsym) } diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b102ffb5f68..b1c9c6222e5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -47,33 +47,7 @@ dtb-$(CONFIG_ARCH_DAVINCI) += \ dtb-$(CONFIG_ARCH_KIRKWOOD) += \ kirkwood-atl-sbx81lifkw.dtb \ - kirkwood-atl-sbx81lifxcat.dtb \ - kirkwood-blackarmor-nas220.dtb \ - kirkwood-d2net.dtb \ - kirkwood-dns325.dtb \ - kirkwood-dockstar.dtb \ - kirkwood-dreamplug.dtb \ - kirkwood-ds109.dtb \ - kirkwood-goflexnet.dtb \ - kirkwood-guruplug-server-plus.dtb \ - kirkwood-ib62x0.dtb \ - kirkwood-iconnect.dtb \ - kirkwood-is2.dtb \ - kirkwood-lsxhl.dtb \ - kirkwood-lschlv2.dtb \ - kirkwood-net2big.dtb \ - kirkwood-ns2.dtb \ - kirkwood-ns2lite.dtb \ - kirkwood-ns2max.dtb \ - kirkwood-ns2mini.dtb \ - kirkwood-nsa310s.dtb \ - kirkwood-nsa325.dtb \ - kirkwood-openrd-base.dtb \ - kirkwood-openrd-client.dtb \ - kirkwood-openrd-ultimate.dtb \ - kirkwood-pogo_e02.dtb \ - kirkwood-pogoplug-series-4.dtb \ - kirkwood-sheevaplug.dtb + kirkwood-atl-sbx81lifxcat.dtb dtb-$(CONFIG_MACH_S900) += \ bubblegum_96.dtb @@ -174,6 +148,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-anbernic-rgxx3.dtb \ + rk3566-pinetab2-v0.1.dtb \ + rk3566-pinetab2-v2.0.dtb \ rk3566-quartz64-a.dtb \ rk3566-quartz64-b.dtb \ rk3566-radxa-cm3-io.dtb \ @@ -191,16 +167,20 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3568-rock-3a.dtb dtb-$(CONFIG_ROCKCHIP_RK3588) += \ + rk3588s-coolpi-4b.dts \ + rk3588-coolpi-cm5-evb.dts \ rk3588-edgeble-neu6a-io.dtb \ rk3588-edgeble-neu6b-io.dtb \ rk3588-evb1-v10.dtb \ + rk3588-generic.dtb \ + rk3588-jaguar.dtb \ rk3588-nanopc-t6.dtb \ rk3588s-orangepi-5.dtb \ rk3588-orangepi-5-plus.dtb \ rk3588-quartzpro64.dtb \ - rk3588-turing-rk1.dtb \ rk3588s-rock-5a.dtb \ - rk3588-rock-5b.dtb + rk3588-rock-5b.dtb \ + rk3588-turing-rk1.dtb dtb-$(CONFIG_ROCKCHIP_RV1108) += \ rv1108-elgin-r1.dtb \ @@ -213,48 +193,8 @@ dtb-$(CONFIG_ARCH_S5P4418) += \ s5p4418-nanopi2.dtb dtb-$(CONFIG_ARCH_MESON) += \ - meson-a1-ad401.dtb \ - meson-axg-s400.dtb \ - meson-axg-jethome-jethub-j100.dtb \ - meson-gxbb-kii-pro.dtb \ - meson-gxbb-nanopi-k2.dtb \ - meson-gxbb-odroidc2.dtb \ - meson-gxbb-nanopi-k2.dtb \ - meson-gxbb-p200.dtb \ - meson-gxbb-p201.dtb \ - meson-gxbb-wetek-hub.dtb \ - meson-gxbb-wetek-play2.dtb \ - meson-gxl-s805x-libretech-ac.dtb \ - meson-gxl-s905d-libretech-pc.dtb \ - meson-gxl-s905w-jethome-jethub-j80.dtb \ - meson-gxl-s905x-khadas-vim.dtb \ - meson-gxl-s905x-libretech-cc.dtb \ - meson-gxl-s905x-libretech-cc-v2.dtb \ - meson-gxl-s905x-p212.dtb \ - meson-gxm-gt1-ultimate.dtb \ - meson-gxm-khadas-vim2.dtb \ - meson-gxm-s912-libretech-pc.dtb \ - meson-gxm-wetek-core2.dtb \ - meson-g12a-radxa-zero.dtb \ - meson-g12a-sei510.dtb \ - meson-g12a-u200.dtb \ - meson-g12b-a311d-bananapi-m2s.dtb \ - meson-g12b-a311d-khadas-vim3.dtb \ - meson-g12b-bananapi-cm4-cm4io.dtb \ - meson-g12b-gsking-x.dtb \ - meson-g12b-gtking.dtb \ - meson-g12b-gtking-pro.dtb \ - meson-g12b-odroid-go-ultra.dtb \ - meson-g12b-odroid-n2.dtb \ - meson-g12b-odroid-n2l.dtb \ - meson-g12b-odroid-n2-plus.dtb \ - meson-g12b-radxa-zero2.dtb \ - meson-sm1-bananapi-m2-pro.dtb \ - meson-sm1-bananapi-m5.dtb \ - meson-sm1-khadas-vim3l.dtb \ - meson-sm1-odroid-c4.dtb \ - meson-sm1-odroid-hc4.dtb \ - meson-sm1-sei610.dtb + meson-a1-ad401.dtb + dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ @@ -548,6 +488,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_agilex_socdk.dtb \ + socfpga_agilex5_socdk.dtb \ socfpga_arria5_secu1.dtb \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3_270_2.dtb \ @@ -577,7 +518,6 @@ dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ am574x-idk.dtb \ am572x-idk.dtb \ am571x-idk.dtb -dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ ls1021a-qds-lpuart.dtb \ @@ -632,10 +572,11 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \ dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb -dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb -dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb -dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb -dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb +dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \ + apq8096-db820c.dtb \ + sdm845-db845c.dtb \ + sdm845-samsung-starqltechn.dtb \ + qcs404-evb-4000.dtb dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb @@ -1075,7 +1016,6 @@ dtb-$(CONFIG_ARCH_IMX8ULP) += \ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-data-modul-edm-sbc.dtb \ - imx8mm-evk.dtb \ imx8mm-icore-mx8mm-ctouch2.dtb \ imx8mm-icore-mx8mm-edimm2.2.dtb \ imx8mm-kontron-bl.dtb \ @@ -1084,30 +1024,12 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-phg.dtb \ imx8mm-phyboard-polis-rdk.dtb \ imx8mm-phygate-tauri-l.dtb \ - imx8mm-venice.dtb \ - imx8mm-venice-gw71xx-0x.dtb \ - imx8mm-venice-gw72xx-0x.dtb \ - imx8mm-venice-gw73xx-0x.dtb \ - imx8mm-venice-gw7901.dtb \ - imx8mm-venice-gw7902.dtb \ - imx8mm-venice-gw7903.dtb \ - imx8mm-venice-gw7904.dtb \ - imx8mm-venice-gw7905-0x.dtb \ - imx8mm-verdin-wifi-dev.dtb \ imx8mn-bsh-smm-s2.dtb \ imx8mn-bsh-smm-s2pro.dtb \ - imx8mn-ddr4-evk.dtb \ imx8mq-cm.dtb \ - imx8mn-evk.dtb \ imx8mn-var-som-symphony.dtb \ - imx8mn-venice.dtb \ - imx8mn-venice-gw7902.dtb \ - imx8mq-evk.dtb \ - imx8mm-beacon-kit.dtb \ - imx8mn-beacon-kit.dtb \ imx8mq-mnt-reform2.dtb \ imx8mq-phanbell.dtb \ - imx8mp-beacon-kit.dtb \ imx8mp-data-modul-edm-sbc.dtb \ imx8mp-dhcom-som-overlay-rev100.dtbo \ imx8mp-dhcom-som-overlay-eth1xfast.dtbo \ @@ -1117,17 +1039,9 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-dhcom-pdk2.dtb \ imx8mp-dhcom-pdk3.dtb \ imx8mp-dhcom-pdk3-overlay-rev100.dtbo \ - imx8mp-evk.dtb \ imx8mp-icore-mx8mp-edimm2.2.dtb \ imx8mp-msc-sm2s.dtb \ imx8mp-phyboard-pollux-rdk.dtb \ - imx8mp-venice.dtb \ - imx8mp-venice-gw71xx-2x.dtb \ - imx8mp-venice-gw72xx-2x.dtb \ - imx8mp-venice-gw73xx-2x.dtb \ - imx8mp-venice-gw74xx.dtb \ - imx8mp-venice-gw7905-2x.dtb \ - imx8mp-verdin-wifi-dev.dtb \ imx8mq-pico-pi.dtb \ imx8mq-kontron-pitx-imx8m.dtb \ imx8mq-librem5-r4.dtb @@ -1142,41 +1056,41 @@ dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1170-evk.dtb \ dtb-$(CONFIG_RCAR_GEN2) += \ - r8a7790-lager-u-boot.dtb \ - r8a7790-stout-u-boot.dtb \ - r8a7791-koelsch-u-boot.dtb \ - r8a7791-porter-u-boot.dtb \ - r8a7792-blanche-u-boot.dtb \ - r8a7793-gose-u-boot.dtb \ - r8a7794-alt-u-boot.dtb \ - r8a7794-silk-u-boot.dtb + r8a7790-lager.dtb \ + r8a7790-stout.dtb \ + r8a7791-koelsch.dtb \ + r8a7791-porter.dtb \ + r8a7792-blanche.dtb \ + r8a7793-gose.dtb \ + r8a7794-alt.dtb \ + r8a7794-silk.dtb dtb-$(CONFIG_RCAR_GEN3) += \ r8a774a1-beacon-rzg2m-kit.dtb \ r8a774b1-beacon-rzg2n-kit.dtb \ r8a774e1-beacon-rzg2h-kit.dtb \ - r8a774a1-hihope-rzg2m-u-boot.dtb \ - r8a774b1-hihope-rzg2n-u-boot.dtb \ - r8a774c0-ek874-u-boot.dtb \ - r8a774e1-hihope-rzg2h-u-boot.dtb \ - r8a77950-ulcb-u-boot.dtb \ - r8a77950-salvator-x-u-boot.dtb \ - r8a77960-ulcb-u-boot.dtb \ - r8a77960-salvator-x-u-boot.dtb \ - r8a77965-ulcb-u-boot.dtb \ - r8a77965-salvator-x-u-boot.dtb \ - r8a77970-eagle-u-boot.dtb \ - r8a77970-v3msk-u-boot.dtb \ - r8a77980-condor-u-boot.dtb \ - r8a77980-v3hsk-u-boot.dtb \ - r8a77990-ebisu-u-boot.dtb \ - r8a77995-draak-u-boot.dtb + r8a774a1-hihope-rzg2m.dtb \ + r8a774b1-hihope-rzg2n.dtb \ + r8a774c0-ek874.dtb \ + r8a774e1-hihope-rzg2h.dtb \ + r8a77951-ulcb.dtb \ + r8a77951-salvator-x.dtb \ + r8a77960-ulcb.dtb \ + r8a77960-salvator-x.dtb \ + r8a77965-ulcb.dtb \ + r8a77965-salvator-x.dtb \ + r8a77970-eagle.dtb \ + r8a77970-v3msk.dtb \ + r8a77980-condor.dtb \ + r8a77980-v3hsk.dtb \ + r8a77990-ebisu.dtb \ + r8a77995-draak.dtb dtb-$(CONFIG_RCAR_GEN4) += \ - r8a779a0-falcon-u-boot.dtb \ - r8a779f0-spider-u-boot.dtb \ - r8a779g0-white-hawk-u-boot.dtb \ - r8a779h0-gray-hawk-u-boot.dtb + r8a779a0-falcon.dtb \ + r8a779f0-spider.dtb \ + r8a779g0-white-hawk.dtb \ + r8a779h0-gray-hawk.dtb dtb-$(CONFIG_TARGET_RZG2L) += \ r9a07g044l2-smarc.dts @@ -1186,7 +1100,7 @@ DTC_FLAGS += -R 4 -p 0x1000 endif dtb-$(CONFIG_RZA1) += \ - r7s72100-gr-peach-u-boot.dtb + r7s72100-gr-peach.dtb dtb-$(CONFIG_ARCH_KEYSTONE) += keystone-k2hk-evm.dtb \ keystone-k2l-evm.dtb \ @@ -1267,6 +1181,9 @@ dtb-$(CONFIG_TARGET_OMAP4_SDP4430) += \ dtb-$(CONFIG_TARGET_SAMA7G5EK) += \ at91-sama7g5ek.dtb +dtb-$(CONFIG_TARGET_SAMA7G54_CURIOSITY) += \ + at91-sama7g54_curiosity.dtb + dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \ at91-sama5d2_ptc_ek.dtb @@ -1366,7 +1283,9 @@ dtb-$(CONFIG_BCM6878) += \ bcm96878.dtb dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb -dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb +dtb-$(CONFIG_ASPEED_AST2600) += \ + ast2600-evb.dtb \ + ast2600-x4tf.dtb dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb @@ -1421,16 +1340,19 @@ dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\ k3-am68-sk-r5-base-board.dtb\ k3-j721s2-common-proc-board.dtb\ k3-j721s2-r5-common-proc-board.dtb -dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \ - k3-am642-r5-evm.dtb \ - k3-am642-sk.dtb \ - k3-am642-r5-sk.dtb + +dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \ + k3-j784s4-r5-evm.dtb + +dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-r5-evm.dtb \ + k3-am642-r5-sk.dtb \ + k3-am642-phyboard-electra-rdk.dtb \ + k3-am642-r5-phycore-som-2gb.dtb dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ k3-am625-r5-sk.dtb \ k3-am625-beagleplay.dtb \ k3-am625-r5-beagleplay.dtb \ - k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-r5.dtb \ k3-am625-phyboard-lyra-rdk.dtb \ k3-am625-r5-phycore-som-2gb.dtb @@ -1438,6 +1360,8 @@ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-sk.dtb \ k3-am62a7-r5-sk.dtb +dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ diff --git a/arch/arm/dts/apq8016-sbc-u-boot.dtsi b/arch/arm/dts/apq8016-sbc-u-boot.dtsi new file mode 100644 index 00000000000..585d54d2962 --- /dev/null +++ b/arch/arm/dts/apq8016-sbc-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024, Linaro Ltd. + */ + +/ { + /* When running as a first-stage bootloader this isn't filled in automatically */ + memory@80000000 { + reg = <0 0x80000000 0 0x3da00000>; + }; +}; + +/* + * When running as a first-stage bootloader, we need to re-configure the UART pins + * because SBL de-initialises them. Indicate that the UART pins should be configured + * during all boot stages. + */ +&blsp_uart2_default { + bootph-all; +}; diff --git a/arch/arm/dts/apq8016-sbc.dts b/arch/arm/dts/apq8016-sbc.dts new file mode 100644 index 00000000000..9ffad7d1f2b --- /dev/null +++ b/arch/arm/dts/apq8016-sbc.dts @@ -0,0 +1,729 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/pinctrl/qcom,pmic-mpp.h> +#include <dt-bindings/sound/apq8016-lpass.h> + +/ { + model = "Qualcomm Technologies, Inc. APQ 8016 SBC"; + compatible = "qcom,apq8016-sbc", "qcom,apq8016"; + + aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; + serial1 = &blsp_uart1; + usid0 = &pm8916_0; + i2c0 = &blsp_i2c2; + i2c1 = &blsp_i2c6; + i2c3 = &blsp_i2c4; + spi0 = &blsp_spi5; + spi1 = &blsp_spi3; + }; + + chosen { + stdout-path = "serial0"; + }; + + reserved-memory { + ramoops@bff00000 { + compatible = "ramoops"; + reg = <0x0 0xbff00000 0x0 0x100000>; + + record-size = <0x20000>; + console-size = <0x20000>; + ftrace-size = <0x20000>; + }; + }; + + usb2513 { + compatible = "smsc,usb3503"; + reset-gpios = <&pm8916_gpios 3 GPIO_ACTIVE_LOW>; + initial-mode = <1>; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_id_default>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7533_out>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&msm_key_volp_n_default>; + + button { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&tlmm_leds>, + <&pm8916_gpios_leds>, + <&pm8916_mpps_leds>; + + compatible = "gpio-leds"; + + led@1 { + label = "apq8016-sbc:green:user1"; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; + gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led@2 { + label = "apq8016-sbc:green:user2"; + function = LED_FUNCTION_DISK_ACTIVITY; + color = <LED_COLOR_ID_GREEN>; + gpios = <&tlmm 120 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@3 { + label = "apq8016-sbc:green:user3"; + function = LED_FUNCTION_DISK_ACTIVITY; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led@4 { + label = "apq8016-sbc:green:user4"; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + panic-indicator; + default-state = "off"; + }; + + led@5 { + label = "apq8016-sbc:yellow:wlan"; + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_YELLOW>; + gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + led@6 { + label = "apq8016-sbc:blue:bt"; + function = LED_FUNCTION_BLUETOOTH; + color = <LED_COLOR_ID_BLUE>; + gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + }; +}; + +&blsp_i2c2 { + /* On Low speed expansion: LS-I2C0 */ + status = "okay"; +}; + +&blsp_i2c4 { + /* On High speed expansion: HS-I2C2 */ + status = "okay"; + + adv_bridge: bridge@39 { + status = "okay"; + + compatible = "adi,adv7533"; + reg = <0x39>; + + interrupt-parent = <&tlmm>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + + adi,dsi-lanes = <4>; + clocks = <&rpmcc RPM_SMD_BB_CLK2>; + clock-names = "cec"; + + pd-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; + + avdd-supply = <&pm8916_l6>; + a2vdd-supply = <&pm8916_l6>; + dvdd-supply = <&pm8916_l6>; + pvdd-supply = <&pm8916_l6>; + v1p2-supply = <&pm8916_l6>; + v3p3-supply = <&pm8916_l17>; + + pinctrl-names = "default","sleep"; + pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>; + pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>; + #sound-dai-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7533_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7533_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&blsp_i2c6 { + /* On Low speed expansion: LS-I2C1 */ + status = "okay"; +}; + +&blsp_spi3 { + /* On High speed expansion: HS-SPI1 */ + status = "okay"; +}; + +&blsp_spi5 { + /* On Low speed expansion: LS-SPI0 */ + status = "okay"; +}; + +&blsp_uart1 { + status = "okay"; + label = "LS-UART0"; +}; + +&blsp_uart2 { + status = "okay"; + label = "LS-UART1"; +}; + +&camss { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&lpass { + status = "okay"; +}; + +&lpass_codec { + status = "okay"; +}; + +&mba_mem { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&adv7533_in>; +}; + +&mpss { + status = "okay"; + + firmware-name = "qcom/apq8016/mba.mbn", "qcom/apq8016/modem.mbn"; +}; + +&mpss_mem { + status = "okay"; + reg = <0x0 0x86800000 0x0 0x2b00000>; +}; + +&pm8916_codec { + status = "okay"; + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; +}; + +&pm8916_resin { + status = "okay"; + linux,code = <KEY_VOLUMEDOWN>; +}; + +&pm8916_rpm_regulators { + /* + * The 96Boards specification expects a 1.8V power rail on the low-speed + * expansion connector that is able to provide at least 0.18W / 100 mA. + * L15/L16 are connected in parallel to provide 55 mA each. A minimum load + * must be specified to ensure the regulators are not put in LPM where they + * would only provide 5 mA. + */ + pm8916_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-system-load = <50000>; + regulator-allow-set-load; + regulator-always-on; + }; + pm8916_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-system-load = <50000>; + regulator-allow-set-load; + regulator-always-on; + }; + + pm8916_l17: l17 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; +}; + +&sound { + status = "okay"; + + pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>; + pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>; + pinctrl-names = "default", "sleep"; + model = "DB410c"; + audio-routing = + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; + + quaternary-dai-link { + link-name = "ADV7533"; + cpu { + sound-dai = <&lpass MI2S_QUATERNARY>; + }; + codec { + sound-dai = <&adv_bridge 0>; + }; + }; + + primary-dai-link { + link-name = "WCD"; + cpu { + sound-dai = <&lpass MI2S_PRIMARY>; + }; + codec { + sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>; + }; + }; + + tertiary-dai-link { + link-name = "WCD-Capture"; + cpu { + sound-dai = <&lpass MI2S_TERTIARY>; + }; + codec { + sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>; + }; + }; +}; + +&usb { + status = "okay"; + extcon = <&usb_id>, <&usb_id>; + + pinctrl-names = "default", "device"; + pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>; + pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&venus { + status = "okay"; +}; + +&venus_mem { + status = "okay"; +}; + +&wcnss { + status = "okay"; + firmware-name = "qcom/apq8016/wcnss.mbn"; +}; + +&wcnss_ctrl { + firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + +&wcnss_mem { + status = "okay"; +}; + +/* Enable CoreSight */ +&cti0 { status = "okay"; }; +&cti1 { status = "okay"; }; +&cti12 { status = "okay"; }; +&cti13 { status = "okay"; }; +&cti14 { status = "okay"; }; +&cti15 { status = "okay"; }; +&debug0 { status = "okay"; }; +&debug1 { status = "okay"; }; +&debug2 { status = "okay"; }; +&debug3 { status = "okay"; }; +&etf { status = "okay"; }; +&etm0 { status = "okay"; }; +&etm1 { status = "okay"; }; +&etm2 { status = "okay"; }; +&etm3 { status = "okay"; }; +&etr { status = "okay"; }; +&funnel0 { status = "okay"; }; +&funnel1 { status = "okay"; }; +&replicator { status = "okay"; }; +&stm { status = "okay"; }; +&tpiu { status = "okay"; }; + +/* + * 2mA drive strength is not enough when connecting multiple + * I2C devices with different pull up resistors. + */ +&blsp_i2c2_default { + drive-strength = <16>; +}; + +&blsp_i2c4_default { + drive-strength = <16>; +}; + +&blsp_i2c6_default { + drive-strength = <16>; +}; + +/* + * GPIO name legend: proper name = the GPIO line is used as GPIO + * NC = not connected (pin out but not routed from the chip to + * anything the board) + * "[PER]" = pin is muxed for [peripheral] (not GPIO) + * LSEC = Low Speed External Connector + * HSEC = High Speed External Connector + * + * Line names are taken from the schematic "DragonBoard410c" + * dated monday, august 31, 2015. Page 5 in particular. + * + * For the lines routed to the external connectors the + * lines are named after the 96Boards CE Specification 1.0, + * Appendix "Expansion Connector Signal Description". + * + * When the 96Board naming of a line and the schematic name of + * the same line are in conflict, the 96Board specification + * takes precedence, which means that the external UART on the + * LSEC is named UART0 while the schematic and SoC names this + * UART3. This is only for the informational lines i.e. "[FOO]", + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only + * ones actually used for GPIO. + */ + +&tlmm { + gpio-line-names = + "[UART0_TX]", /* GPIO_0, LSEC pin 5 */ + "[UART0_RX]", /* GPIO_1, LSEC pin 7 */ + "[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */ + "[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */ + "[UART1_TX]", /* GPIO_4, LSEC pin 11 */ + "[UART1_RX]", /* GPIO_5, LSEC pin 13 */ + "[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */ + "[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */ + "[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */ + "[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */ + "[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */ + "[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */ + "GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */ + "GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */ + "[I2C3_SDA]", /* HSEC pin 38 */ + "[I2C3_SCL]", /* HSEC pin 36 */ + "[SPI0_MOSI]", /* LSEC pin 14 */ + "[SPI0_MISO]", /* LSEC pin 10 */ + "[SPI0_CS_N]", /* LSEC pin 12 */ + "[SPI0_CLK]", /* LSEC pin 8 */ + "HDMI_HPD_N", /* GPIO 20 */ + "USR_LED_1_CTRL", + "[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */ + "[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */ + "GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */ + "GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */ + "[CSI0_MCLK]", /* HSEC pin 15 */ + "[CSI1_MCLK]", /* HSEC pin 17 */ + "GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */ + "[I2C2_SDA]", /* HSEC pin 34 */ + "[I2C2_SCL]", /* HSEC pin 32 */ + "DSI2HDMI_INT_N", + "DSI_SW_SEL_APQ", + "GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */ + "GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */ + "GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */ + "GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */ + "FORCED_USB_BOOT", + "SD_CARD_DET_N", + "[WCSS_BT_SSBI]", + "[WCSS_WLAN_DATA_2]", /* GPIO 40 */ + "[WCSS_WLAN_DATA_1]", + "[WCSS_WLAN_DATA_0]", + "[WCSS_WLAN_SET]", + "[WCSS_WLAN_CLK]", + "[WCSS_FM_SSBI]", + "[WCSS_FM_SDI]", + "[WCSS_BT_DAT_CTL]", + "[WCSS_BT_DAT_STB]", + "NC", + "NC", /* GPIO 50 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", /* GPIO 60 */ + "NC", + "NC", + "[CDC_PDM0_CLK]", + "[CDC_PDM0_SYNC]", + "[CDC_PDM0_TX0]", + "[CDC_PDM0_RX0]", + "[CDC_PDM0_RX1]", + "[CDC_PDM0_RX2]", + "GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */ + "NC", /* GPIO 70 */ + "NC", + "NC", + "NC", + "NC", /* GPIO 74 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "BOOT_CONFIG_0", /* GPIO 80 */ + "BOOT_CONFIG_1", + "BOOT_CONFIG_2", + "BOOT_CONFIG_3", + "NC", + "NC", + "BOOT_CONFIG_5", + "NC", + "NC", + "NC", + "NC", /* GPIO 90 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", /* GPIO 100 */ + "NC", + "NC", + "NC", + "SSBI_GPS", + "NC", + "NC", + "KEY_VOLP_N", + "NC", + "NC", + "[LS_EXP_MI2S_WS]", /* GPIO 110 */ + "NC", + "NC", + "[LS_EXP_MI2S_SCK]", + "[LS_EXP_MI2S_DATA0]", + "GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */ + "NC", + "[DSI2HDMI_MI2S_WS]", + "[DSI2HDMI_MI2S_SCK]", + "[DSI2HDMI_MI2S_DATA0]", + "USR_LED_2_CTRL", /* GPIO 120 */ + "SB_HS_ID"; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tlmm_leds: tlmm-leds-state { + pins = "gpio21", "gpio120"; + function = "gpio"; + + output-low; + }; + + usb_id_default: usb-id-default-state { + pins = "gpio121"; + function = "gpio"; + + drive-strength = <8>; + bias-pull-up; + }; + + adv7533_int_active: adv533-int-active-state { + pins = "gpio31"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + }; + + adv7533_int_suspend: adv7533-int-suspend-state { + pins = "gpio31"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + adv7533_switch_active: adv7533-switch-active-state { + pins = "gpio32"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + }; + + adv7533_switch_suspend: adv7533-switch-suspend-state { + pins = "gpio32"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + msm_key_volp_n_default: msm-key-volp-n-default-state { + pins = "gpio107"; + function = "gpio"; + + drive-strength = <8>; + bias-pull-up; + }; +}; + +&pm8916_gpios { + gpio-line-names = + "USR_LED_3_CTRL", + "USR_LED_4_CTRL", + "USB_HUB_RESET_N_PM", + "USB_SW_SEL_PM"; + + usb_hub_reset_pm: usb-hub-reset-pm-state { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + + input-disable; + output-high; + }; + + usb_hub_reset_pm_device: usb-hub-reset-pm-device-state { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + + output-low; + }; + + usb_sw_sel_pm: usb-sw-sel-pm-state { + pins = "gpio4"; + function = PMIC_GPIO_FUNC_NORMAL; + + power-source = <PM8916_GPIO_VPH>; + input-disable; + output-high; + }; + + usb_sw_sel_pm_device: usb-sw-sel-pm-device-state { + pins = "gpio4"; + function = PMIC_GPIO_FUNC_NORMAL; + + power-source = <PM8916_GPIO_VPH>; + input-disable; + output-low; + }; + + pm8916_gpios_leds: pm8916-gpios-leds-state { + pins = "gpio1", "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + + output-low; + }; +}; + +&pm8916_mpps { + gpio-line-names = + "VDD_PX_BIAS", + "WLAN_LED_CTRL", + "BT_LED_CTRL", + "GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */ + + pinctrl-names = "default"; + pinctrl-0 = <&ls_exp_gpio_f>; + + ls_exp_gpio_f: pm8916-mpp4-state { + pins = "mpp4"; + function = "digital"; + + output-low; + power-source = <PM8916_MPP_L5>; /* 1.8V */ + }; + + pm8916_mpps_leds: pm8916-mpps-state { + pins = "mpp2", "mpp3"; + function = "digital"; + + output-low; + }; +}; diff --git a/arch/arm/dts/apq8096-db820c-u-boot.dtsi b/arch/arm/dts/apq8096-db820c-u-boot.dtsi new file mode 100644 index 00000000000..be61ea262b9 --- /dev/null +++ b/arch/arm/dts/apq8096-db820c-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024, Linaro Ltd. + */ + +/ { + /* Ensure that the fdtfile variable is generated properly */ + compatible = "qcom,apq8096-db820c", "qcom,apq8096"; +}; + +&sdhc2 { + status = "okay"; + clock-frequency = <100000000>; +}; diff --git a/arch/arm/dts/apq8096-db820c.dts b/arch/arm/dts/apq8096-db820c.dts new file mode 100644 index 00000000000..e8148b3d6c5 --- /dev/null +++ b/arch/arm/dts/apq8096-db820c.dts @@ -0,0 +1,1137 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "msm8996.dtsi" +#include "pm8994.dtsi" +#include "pmi8994.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/sound/qcom,q6afe.h> +#include <dt-bindings/sound/qcom,q6asm.h> +#include <dt-bindings/sound/qcom,wcd9335.h> + +/* + * GPIO name legend: proper name = the GPIO line is used as GPIO + * NC = not connected (pin out but not routed from the chip to + * anything the board) + * "[PER]" = pin is muxed for [peripheral] (not GPIO) + * LSEC = Low Speed External Connector + * P HSEC = Primary High Speed External Connector + * S HSEC = Secondary High Speed External Connector + * J14 = Camera Connector + * TP = Test Points + * + * Line names are taken from the schematic "DragonBoard 820c", + * drawing no: LM25-P2751-1 + * + * For the lines routed to the external connectors the + * lines are named after the 96Boards CE Specification 1.0, + * Appendix "Expansion Connector Signal Description". + * + * When the 96Board naming of a line and the schematic name of + * the same line are in conflict, the 96Board specification + * takes precedence, which means that the external UART on the + * LSEC is named UART0 while the schematic and SoC names this + * UART3. This is only for the informational lines i.e. "[FOO]", + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only + * ones actually used for GPIO. + */ + +/ { + model = "Qualcomm Technologies, Inc. DB820c"; + compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096"; + + aliases { + serial0 = &blsp2_uart2; + serial1 = &blsp2_uart3; + serial2 = &blsp1_uart2; + i2c0 = &blsp1_i2c3; + i2c1 = &blsp2_i2c1; + i2c2 = &blsp2_i2c1; + spi0 = &blsp1_spi1; + spi1 = &blsp2_spi6; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + div1_mclk: divclk1 { + compatible = "gpio-gate-clock"; + pinctrl-0 = <&audio_mclk>; + pinctrl-names = "default"; + clocks = <&rpmcc RPM_SMD_DIV_CLK1>; + #clock-cells = <0>; + enable-gpios = <&pm8994_gpios 15 0>; + }; + + divclk4: divclk4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "divclk4"; + + pinctrl-names = "default"; + pinctrl-0 = <&divclk4_pin_a>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&volume_up_gpio>; + + button { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; + }; + }; + + usb2_id: usb2-id { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_det_gpio>; + }; + + usb3_id: usb3-id { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_vbus_det_gpio>; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + wlan_en: wlan-en-1-8v { + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_gpios>; + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8994_gpios 8 0>; + + /* WLAN card specific delay */ + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&blsp1_i2c3 { + /* On Low speed expansion: LS-I2C0 */ + status = "okay"; +}; + +&blsp1_spi1 { + /* On Low speed expansion */ + status = "okay"; +}; + +&blsp1_uart2 { + label = "BT-UART"; + status = "okay"; + + bluetooth { + compatible = "qcom,qca6174-bt"; + + /* bt_disable_n gpio */ + enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; + + clocks = <&divclk4>; + }; +}; + +&adsp_pil { + status = "okay"; + firmware-name = "qcom/apq8096/adsp.mbn"; +}; + +&blsp2_i2c1 { + /* On High speed expansion: HS-I2C2 */ + status = "okay"; +}; + +&blsp2_i2c1 { + /* On Low speed expansion: LS-I2C1 */ + status = "okay"; +}; + +&blsp2_spi6 { + /* On High speed expansion */ + status = "okay"; +}; + +&blsp2_uart2 { + label = "LS-UART1"; + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart2_2pins_default>; + pinctrl-1 = <&blsp2_uart2_2pins_sleep>; +}; + +&blsp2_uart3 { + label = "LS-UART0"; + status = "disabled"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart3_4pins_default>; + pinctrl-1 = <&blsp2_uart3_4pins_sleep>; +}; + +&camss { + vdda-supply = <&vreg_l2a_1p25>; +}; + +&gpu { + status = "okay"; +}; + +&hsusb_phy1 { + status = "okay"; + + vdd-supply = <&vreg_l28a_0p925>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +}; + +&hsusb_phy2 { + status = "okay"; + + vdd-supply = <&vreg_l28a_0p925>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +}; + +&mdp { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_hdmi { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>; + pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>; + + core-vdda-supply = <&vreg_l12a_1p8>; + core-vcc-supply = <&vreg_s4a_1p8>; +}; + +&mdss_hdmi_phy { + status = "okay"; + + vddio-supply = <&vreg_l12a_1p8>; + vcca-supply = <&vreg_l28a_0p925>; + #phy-cells = <0>; +}; + +&mmcc { + vdd-gfx-supply = <&vdd_gfx>; +}; + +&mss_pil { + status = "okay"; + pll-supply = <&vreg_l12a_1p8>; + firmware-name = "qcom/apq8096/mba.mbn", "qcom/apq8096/modem.mbn"; +}; + +&pm8994_resin { + status = "okay"; + linux,code = <KEY_VOLUMEDOWN>; +}; + +&tlmm { + gpio-line-names = + "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */ + "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */ + "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */ + "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */ + "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */ + "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */ + "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */ + "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */ + "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */ + "TP93", /* GPIO_9 */ + "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */ + "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */ + "NC", /* GPIO_12 */ + "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */ + "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */ + "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */ + "TP99", /* GPIO_16 */ + "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */ + "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */ + "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */ + "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */ + "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */ + "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */ + "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */ + "GPIO-D", /* GPIO_24, LSEC pin 26 */ + "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */ + "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */ + "BLSP6_I2C_SDA", /* GPIO_27 */ + "BLSP6_I2C_SCL", /* GPIO_28 */ + "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */ + "GPIO30", /* GPIO_30, S HSEC pin 4 */ + "HDMI_CEC", /* GPIO_31 */ + "HDMI_DDC_CLOCK", /* GPIO_32 */ + "HDMI_DDC_DATA", /* GPIO_33 */ + "HDMI_HOT_PLUG_DETECT", /* GPIO_34 */ + "PCIE0_RST_N", /* GPIO_35 */ + "PCIE0_CLKREQ_N", /* GPIO_36 */ + "PCIE0_WAKE", /* GPIO_37 */ + "SD_CARD_DET_N", /* GPIO_38 */ + "TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */ + "W_DISABLE_N", /* GPIO_40 */ + "[BLSP9_UART_TX]", /* GPIO_41 */ + "[BLSP9_UART_RX]", /* GPIO_42 */ + "[BLSP2_UART_CTS_N]", /* GPIO_43 */ + "[BLSP2_UART_RFR_N]", /* GPIO_44 */ + "[BLSP3_UART_TX]", /* GPIO_45 */ + "[BLSP3_UART_RX]", /* GPIO_46 */ + "[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */ + "[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */ + "[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */ + "[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */ + "[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */ + "[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */ + "[CODEC_INT1_N]", /* GPIO_53 */ + "[CODEC_INT2_N]", /* GPIO_54 */ + "[BLSP7_I2C_SDA]", /* GPIO_55 */ + "[BLSP7_I2C_SCL]", /* GPIO_56 */ + "MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */ + "[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */ + "[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */ + "[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */ + "[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */ + "GPIO-E", /* GPIO_62, LSEC pin 27 */ + "TP87", /* GPIO_63 */ + "[CODEC_RST_N]", /* GPIO_64 */ + "[PCM1_CLK]", /* GPIO_65 */ + "[PCM1_SYNC]", /* GPIO_66 */ + "[PCM1_DIN]", /* GPIO_67 */ + "[PCM1_DOUT]", /* GPIO_68 */ + "AUDIO_REF_CLK", /* GPIO_69 */ + "SLIMBUS_CLK", /* GPIO_70 */ + "SLIMBUS_DATA0", /* GPIO_71 */ + "SLIMBUS_DATA1", /* GPIO_72 */ + "NC", /* GPIO_73 */ + "NC", /* GPIO_74 */ + "NC", /* GPIO_75 */ + "NC", /* GPIO_76 */ + "TP94", /* GPIO_77 */ + "NC", /* GPIO_78 */ + "TP95", /* GPIO_79 */ + "GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */ + "TP88", /* GPIO_81 */ + "TP89", /* GPIO_82 */ + "TP90", /* GPIO_83 */ + "TP91", /* GPIO_84 */ + "[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */ + "[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */ + "[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */ + "[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */ + "TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */ + "TSIF1_EN", /* GPIO_90, S HSEC pin 46 */ + "TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */ + "NC", /* GPIO_92 */ + "TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */ + "TSIF2_EN", /* GPIO_94, S HSEC pin 56 */ + "TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */ + "TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */ + "NC", /* GPIO_97 */ + "CAM1_STANDBY_N", /* GPIO_98 */ + "NC", /* GPIO_99 */ + "NC", /* GPIO_100 */ + "[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */ + "BOOT_CONFIG1", /* GPIO_102 */ + "USB_HUB_RESET", /* GPIO_103 */ + "CAM1_RST_N", /* GPIO_104 */ + "NC", /* GPIO_105 */ + "NC", /* GPIO_106 */ + "NC", /* GPIO_107 */ + "NC", /* GPIO_108 */ + "NC", /* GPIO_109 */ + "NC", /* GPIO_110 */ + "NC", /* GPIO_111 */ + "NC", /* GPIO_112 */ + "PMI8994_BUA", /* GPIO_113 */ + "PCIE2_RST_N", /* GPIO_114 */ + "PCIE2_CLKREQ_N", /* GPIO_115 */ + "PCIE2_WAKE", /* GPIO_116 */ + "SSC_IRQ_0", /* GPIO_117 */ + "SSC_IRQ_1", /* GPIO_118 */ + "SSC_IRQ_2", /* GPIO_119 */ + "NC", /* GPIO_120 */ + "GPIO121", /* GPIO_121, S HSEC pin 2 */ + "NC", /* GPIO_122 */ + "SSC_IRQ_6", /* GPIO_123 */ + "SSC_IRQ_7", /* GPIO_124 */ + "GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */ + "BOOT_CONFIG5", /* GPIO_126 */ + "NC", /* GPIO_127 */ + "NC", /* GPIO_128 */ + "BOOT_CONFIG7", /* GPIO_129 */ + "PCIE1_RST_N", /* GPIO_130 */ + "PCIE1_CLKREQ_N", /* GPIO_131 */ + "PCIE1_WAKE", /* GPIO_132 */ + "GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */ + "NC", /* GPIO_134 */ + "NC", /* GPIO_135 */ + "BOOT_CONFIG8", /* GPIO_136 */ + "NC", /* GPIO_137 */ + "NC", /* GPIO_138 */ + "GPS_SSBI2", /* GPIO_139 */ + "GPS_SSBI1", /* GPIO_140 */ + "NC", /* GPIO_141 */ + "NC", /* GPIO_142 */ + "NC", /* GPIO_143 */ + "BOOT_CONFIG6", /* GPIO_144 */ + "NC", /* GPIO_145 */ + "NC", /* GPIO_146 */ + "NC", /* GPIO_147 */ + "NC", /* GPIO_148 */ + "NC"; /* GPIO_149 */ + + sdc2_cd_on: sdc2-cd-on-state { + pins = "gpio38"; + function = "gpio"; + bias-pull-up; + drive-strength = <16>; + }; + + sdc2_cd_off: sdc2-cd-off-state { + pins = "gpio38"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + hdmi_hpd_active: hdmi-hpd-active-state { + pins = "gpio34"; + function = "hdmi_hot"; + bias-pull-down; + drive-strength = <16>; + }; + + hdmi_hpd_suspend: hdmi-hpd-suspend-state { + pins = "gpio34"; + function = "hdmi_hot"; + bias-pull-down; + drive-strength = <2>; + }; + + hdmi_ddc_active: hdmi-ddc-active-state { + pins = "gpio32", "gpio33"; + function = "hdmi_ddc"; + drive-strength = <2>; + bias-pull-up; + }; + + hdmi_ddc_suspend: hdmi-ddc-suspend-state { + pins = "gpio32", "gpio33"; + function = "hdmi_ddc"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +&pcie0 { + status = "okay"; + perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + vddpe-3v3-supply = <&wlan_en>; + vdda-supply = <&vreg_l28a_0p925>; +}; + +&pcie1 { + status = "okay"; + perst-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; + vdda-supply = <&vreg_l28a_0p925>; +}; + +&pcie2 { + status = "okay"; + perst-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>; + vdda-supply = <&vreg_l28a_0p925>; +}; + +&pcie_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l28a_0p925>; + vdda-pll-supply = <&vreg_l12a_1p8>; +}; + +&pm8994_gpios { + gpio-line-names = + "NC", + "KEY_VOLP_N", + "NC", + "BL1_PWM", + "GPIO-F", /* BL0_PWM, LSEC pin 28 */ + "BL1_EN", + "NC", + "WLAN_EN", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "DIVCLK1", + "DIVCLK2", + "DIVCLK3", + "DIVCLK4", + "BT_EN", + "PMIC_SLB", + "PMIC_BUA", + "USB_VBUS_DET"; + + pinctrl-names = "default"; + pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>; + + ls_exp_gpio_f: pm8994-gpio5-state { + pinconf { + pins = "gpio5"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + power-source = <PM8994_GPIO_S4>; /* 1.8V */ + }; + }; + + bt_en_gpios: bt-en-pios-state { + pinconf { + pins = "gpio19"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + power-source = <PM8994_GPIO_S4>; /* 1.8V */ + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + bias-pull-down; + }; + }; + + wlan_en_gpios: wlan-en-gpios-state { + pinconf { + pins = "gpio8"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + power-source = <PM8994_GPIO_S4>; /* 1.8V */ + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + bias-pull-down; + }; + }; + + audio_mclk: clk-div1-state { + pinconf { + pins = "gpio15"; + function = "func1"; + power-source = <PM8994_GPIO_S4>; /* 1.8V */ + }; + }; + + volume_up_gpio: pm8996-gpio2-state { + pinconf { + pins = "gpio2"; + function = "normal"; + input-enable; + drive-push-pull; + bias-pull-up; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; + power-source = <PM8994_GPIO_S4>; /* 1.8V */ + }; + }; + + divclk4_pin_a: divclk4-state { + pinconf { + pins = "gpio18"; + function = PMIC_GPIO_FUNC_FUNC2; + + bias-disable; + power-source = <PM8994_GPIO_S4>; + }; + }; + + usb3_vbus_det_gpio: pm8996-gpio22-state { + pinconf { + pins = "gpio22"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-down; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; + power-source = <PM8994_GPIO_S4>; /* 1.8V */ + }; + }; +}; + +&pm8994_mpps { + gpio-line-names = + "VDDPX_BIAS", + "WIFI_LED", + "NC", + "BT_LED", + "PM_MPP05", + "PM_MPP06", + "PM_MPP07", + "NC"; +}; + +&pm8994_spmi_regulators { + qcom,saw-reg = <&saw3>; + vdd_s11-supply = <&vph_pwr>; + + s9 { + qcom,saw-slave; + }; + s10 { + qcom,saw-slave; + }; + s11 { + qcom,saw-leader; + regulator-name = "VDD_APCC"; + regulator-always-on; + regulator-min-microvolt = <980000>; + regulator-max-microvolt = <980000>; + }; +}; + +&pmi8994_gpios { + gpio-line-names = + "NC", + "SPKR_AMP_EN1", + "SPKR_AMP_EN2", + "TP61", + "NC", + "USB2_VBUS_DET", + "NC", + "NC", + "NC", + "NC"; + + usb2_vbus_det_gpio: pmi8996-gpio6-state { + pinconf { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-down; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; + power-source = <PM8994_GPIO_S4>; /* 1.8V */ + }; + }; +}; + +&pmi8994_lpg { + qcom,power-source = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmi8994_mpp2_userled4>; + + qcom,dtest = <0 0>, + <0 0>, + <0 0>, + <4 1>; + + status = "okay"; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <1>; + + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <0>; + }; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <2>; + }; + + led@4 { + reg = <4>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <3>; + }; +}; + +&pmi8994_mpps { + pmi8994_mpp2_userled4: mpp2-userled4-state { + pins = "mpp2"; + function = "sink"; + + output-low; + qcom,dtest = <4>; + }; +}; + +&pmi8994_spmi_regulators { + vdd_s2-supply = <&vph_pwr>; + + vdd_gfx: s2 { + regulator-name = "VDD_GFX"; + regulator-min-microvolt = <980000>; + regulator-max-microvolt = <980000>; + }; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm8994-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_s8-supply = <&vph_pwr>; + vdd_s9-supply = <&vph_pwr>; + vdd_s10-supply = <&vph_pwr>; + vdd_s11-supply = <&vph_pwr>; + vdd_s12-supply = <&vph_pwr>; + vdd_l1-supply = <&vreg_s1b_1p025>; + vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; + vdd_l3_l11-supply = <&vreg_s3a_1p3>; + vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; + vdd_l5_l7-supply = <&vreg_s5a_2p15>; + vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; + vdd_l8_l16_l30-supply = <&vph_pwr>; + vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>; + vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>; + vdd_l14_l15-supply = <&vreg_s5a_2p15>; + vdd_l17_l29-supply = <&vph_pwr_bbyp>; + vdd_l20_l21-supply = <&vph_pwr_bbyp>; + vdd_l25-supply = <&vreg_s3a_1p3>; + vdd_lvs1_2-supply = <&vreg_s4a_1p8>; + + vreg_s3a_1p3: s3 { + regulator-name = "vreg_s3a_1p3"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + /** + * 1.8v required on LS expansion + * for mezzanine boards + */ + vreg_s4a_1p8: s4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + vreg_s5a_2p15: s5 { + regulator-name = "vreg_s5a_2p15"; + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + vreg_s7a_1p0: s7 { + regulator-name = "vreg_s7a_1p0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l1a_1p0: l1 { + regulator-name = "vreg_l1a_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + vreg_l2a_1p25: l2 { + regulator-name = "vreg_l2a_1p25"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + }; + vreg_l3a_0p875: l3 { + regulator-name = "vreg_l3a_0p875"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + }; + vreg_l4a_1p225: l4 { + regulator-name = "vreg_l4a_1p225"; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + vreg_l6a_1p2: l6 { + regulator-name = "vreg_l6a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + vreg_l8a_1p8: l8 { + regulator-name = "vreg_l8a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l9a_1p8: l9 { + regulator-name = "vreg_l9a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l10a_1p8: l10 { + regulator-name = "vreg_l10a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l11a_1p15: l11 { + regulator-name = "vreg_l11a_1p15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + vreg_l12a_1p8: l12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l13a_2p95: l13 { + regulator-name = "vreg_l13a_2p95"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + vreg_l14a_1p8: l14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l15a_1p8: l15 { + regulator-name = "vreg_l15a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l16a_2p7: l16 { + regulator-name = "vreg_l16a_2p7"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + vreg_l17a_2p8: l17 { + regulator-name = "vreg_l17a_2p8"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + vreg_l18a_2p85: l18 { + regulator-name = "vreg_l18a_2p85"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + vreg_l19a_2p8: l19 { + regulator-name = "vreg_l19a_2p8"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + vreg_l20a_2p95: l20 { + regulator-name = "vreg_l20a_2p95"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + vreg_l21a_2p95: l21 { + regulator-name = "vreg_l21a_2p95"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + vreg_l22a_3p0: l22 { + regulator-name = "vreg_l22a_3p0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + vreg_l23a_2p8: l23 { + regulator-name = "vreg_l23a_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + vreg_l24a_3p075: l24 { + regulator-name = "vreg_l24a_3p075"; + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + vreg_l25a_1p2: l25 { + regulator-name = "vreg_l25a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-allow-set-load; + }; + vreg_l26a_0p8: l27 { + regulator-name = "vreg_l26a_0p8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + vreg_l28a_0p925: l28 { + regulator-name = "vreg_l28a_0p925"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-allow-set-load; + }; + vreg_l29a_2p8: l29 { + regulator-name = "vreg_l29a_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + vreg_l30a_1p8: l30 { + regulator-name = "vreg_l30a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l32a_1p8: l32 { + regulator-name = "vreg_l32a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-name = "vreg_lvs1a_1p8"; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-name = "vreg_lvs2a_1p8"; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pmi8994-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_bst_byp-supply = <&vph_pwr>; + + vph_pwr_bbyp: boost-bypass { + regulator-name = "vph_pwr_bbyp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vreg_s1b_1p025: s1 { + regulator-name = "vreg_s1b_1p025"; + regulator-min-microvolt = <1025000>; + regulator-max-microvolt = <1025000>; + }; + }; +}; + +&sdhc2 { + /* External SD card */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_state_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_state_off &sdc2_cd_off>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vreg_l13a_2p95>; + status = "okay"; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; +}; + +&slim_msm { + status = "okay"; + + slim@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + + tasha_ifd: tas-ifd@0,0 { + compatible = "slim217,1a0"; + reg = <0 0>; + }; + + wcd9335: codec@1,0 { + compatible = "slim217,1a0"; + reg = <1 0>; + + clock-names = "mclk", "slimbus"; + clocks = <&div1_mclk>, + <&rpmcc RPM_SMD_BB_CLK1>; + interrupt-parent = <&tlmm>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, + <53 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr1", "intr2"; + interrupt-controller; + #interrupt-cells = <1>; + + pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + slim-ifc-dev = <&tasha_ifd>; + + #sound-dai-cells = <1>; + + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + }; + }; +}; + +&sound { + compatible = "qcom,apq8096-sndcard"; + model = "DB820c"; + audio-routing = "RX_BIAS", "MCLK", + "MM_DL1", "MultiMedia1 Playback", + "MM_DL2", "MultiMedia2 Playback", + "MultiMedia3 Capture", "MM_UL3"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + hdmi-dai-link { + link-name = "HDMI"; + cpu { + sound-dai = <&q6afedai HDMI_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&mdss_hdmi 0>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback"; + cpu { + sound-dai = <&q6afedai SLIMBUS_6_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9335 AIF4_PB>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9335 AIF1_CAP>; + }; + }; +}; + +&ufsphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l28a_0p925>; + vdda-pll-supply = <&vreg_l12a_1p8>; +}; + +&ufshc { + status = "okay"; + + vcc-supply = <&vreg_l20a_2p95>; + vccq-supply = <&vreg_l25a_1p2>; + vccq2-supply = <&vreg_s4a_1p8>; + vdd-hba-supply = <&vreg_l25a_1p2>; + + vcc-max-microamp = <600000>; + vccq-max-microamp = <450000>; + vccq2-max-microamp = <450000>; +}; + +&usb2 { + status = "okay"; + extcon = <&usb2_id>; +}; + +&usb2_dwc3 { + extcon = <&usb2_id>; + dr_mode = "otg"; + maximum-speed = "high-speed"; +}; + +&usb3 { + status = "okay"; + extcon = <&usb3_id>; +}; + +&usb3_dwc3 { + extcon = <&usb3_id>; + dr_mode = "otg"; +}; + +&usb3phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l28a_0p925>; + vdda-pll-supply = <&vreg_l12a_1p8>; +}; + +&venus { + status = "okay"; +}; diff --git a/arch/arm/dts/ast2600-x4tf.dts b/arch/arm/dts/ast2600-x4tf.dts new file mode 100644 index 00000000000..4bf4b66a9ce --- /dev/null +++ b/arch/arm/dts/ast2600-x4tf.dts @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2024 ASUS Corp. +/dts-v1/; + +#include "ast2600-u-boot.dtsi" + +/ { + model = "AST2600 ASUS X4TF"; + compatible = "aspeed,ast2600-asus", "aspeed,ast2600"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + chosen { + stdout-path = &uart5; + }; + + aliases { + spi0 = &fmc; + ethernet0 = &mac2; + ethernet1 = &mac3; + }; + + cpus { + cpu@0 { + clock-frequency = <800000000>; + }; + + cpu@1 { + clock-frequency = <800000000>; + }; + }; +}; + +&uart5 { + status = "okay"; +}; + +&sdrammc { + clock-frequency = <400000000>; +}; + +&wdt1 { + status = "okay"; +}; + +&wdt2 { + status = "okay"; +}; + +&wdt3 { + status = "okay"; +}; + +&mac2 { + status = "okay"; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; +}; + +&mac3 { + status = "okay"; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; +}; + +&fmc { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor", "macronix,mx66l2g45g"; + status = "okay"; + spi-max-frequency = <25000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; + + flash@1 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <25000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&hace { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "disabled"; +}; + +&i2c13 { + status = "disabled"; +}; + +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&display_port { + status = "okay"; +}; diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index beabcf14f81..43db80edfe5 100644 --- a/arch/arm/dts/ast2600.dtsi +++ b/arch/arm/dts/ast2600.dtsi @@ -2028,6 +2028,26 @@ groups = "SPI2MOSI"; }; + pinctrl_thru0_default: thru0_default { + function = "THRU0"; + groups = "THRU0"; + }; + + pinctrl_thru1_default: thru1_default { + function = "THRU1"; + groups = "THRU1"; + }; + + pinctrl_thru2_default: thru2_default { + function = "THRU2"; + groups = "THRU2"; + }; + + pinctrl_thru3_default: thru3_default { + function = "THRU3"; + groups = "THRU3"; + }; + pinctrl_timer3_default: timer3_default { function = "TIMER3"; groups = "TIMER3"; diff --git a/arch/arm/dts/at91-sama7g54_curiosity-u-boot.dtsi b/arch/arm/dts/at91-sama7g54_curiosity-u-boot.dtsi new file mode 100644 index 00000000000..04d7d9e522d --- /dev/null +++ b/arch/arm/dts/at91-sama7g54_curiosity-u-boot.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * at91-sama7g54_curiosity-u-boot.dtsi - Device Tree file for SAMA7G5 SoC u-boot properties. + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Mihai Sain <mihai.sain@microchip.com> + * + */ + +/ { + chosen { + bootph-all; + }; +}; + +&main_rc { + bootph-all; +}; + +&main_xtal { + bootph-all; +}; + +&pioA { + bootph-all; +}; + +&pinctrl_flx3_default { + bootph-all; +}; + +&pinctrl_sdmmc1_default { + bootph-all; +}; + +&pit64b0 { + bootph-all; +}; + +&pmc { + bootph-all; +}; + +&sdmmc1 { + bootph-all; +}; + +&slow_rc_osc { + bootph-all; +}; + +&slow_xtal { + bootph-all; +}; + +&uart3 { + bootph-all; +}; diff --git a/arch/arm/dts/at91-sama7g54_curiosity.dts b/arch/arm/dts/at91-sama7g54_curiosity.dts new file mode 100644 index 00000000000..93c230be0a3 --- /dev/null +++ b/arch/arm/dts/at91-sama7g54_curiosity.dts @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama7g54_curiosity.dts - Device Tree file for SAMA7G54 CURIOSITY board + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Mihai Sain <mihai.sain@microchip.com> + * + */ +/dts-v1/; +#include "sama7g5-pinfunc.h" +#include "sama7g5.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/mfd/atmel-flexcom.h> +#include <dt-bindings/pinctrl/at91.h> + +/ { + model = "Microchip SAMA7G54 Curiosity"; + compatible = "microchip,sama7g54-curiosity", "microchip,sama7g5", "microchip,sama7"; + + aliases { + serial0 = &uart3; + i2c0 = &i2c10; + }; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait"; + stdout-path = "serial0:115200n8"; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <24000000>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + + led-red { + label = "red"; + gpios = <&pioA PIN_PD13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-green { + label = "green"; + gpios = <&pioA PIN_PD14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-blue { + label = "blue"; + gpios = <&pioA PIN_PB15 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x10000000>; // 256 MiB DDR3L-1066 16-bit + }; +}; + +&ebi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand_default>; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + }; + }; +}; + +&flx3 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; + status = "okay"; + + uart3: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx3_default>; + status = "okay"; + }; +}; + +&flx10 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; + status = "okay"; + + i2c10: i2c@600 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx10_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + + adc@1f { + compatible = "microchip,pac1934"; + reg = <0x1f>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + size = <256>; + }; + + pmic@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + }; + }; +}; + +&pioA { + pinctrl_flx3_default: flx3-default { + pinmux = <PIN_PD16__FLEXCOM3_IO0>, + <PIN_PD17__FLEXCOM3_IO1>; + bias-pull-up; + }; + + pinctrl_flx10_default: flx10-default { + pinmux = <PIN_PC30__FLEXCOM10_IO0>, + <PIN_PC31__FLEXCOM10_IO1>; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led-gpio-default { + pinmux = <PIN_PD13__GPIO>, + <PIN_PD14__GPIO>, + <PIN_PB15__GPIO>; + bias-pull-up; + }; + + pinctrl_nand_default: nand-default { + pinmux = <PIN_PD9__D0>, + <PIN_PD10__D1>, + <PIN_PD11__D2>, + <PIN_PC21__D3>, + <PIN_PC22__D4>, + <PIN_PC23__D5>, + <PIN_PC24__D6>, + <PIN_PD2__D7>, + <PIN_PD3__NANDRDY>, + <PIN_PD4__NCS3_NANDCS>, + <PIN_PD5__NWE_NWR0_NANDWE>, + <PIN_PD6__NRD_NANDOE>, + <PIN_PD7__A21_NANDALE>, + <PIN_PD8__A22_NANDCLE>; + bias-disable; + slew-rate = <0>; + }; + + pinctrl_qspi1_default: qspi1-default { + pinmux = <PIN_PB22__QSPI1_IO3>, + <PIN_PB23__QSPI1_IO2>, + <PIN_PB24__QSPI1_IO1>, + <PIN_PB25__QSPI1_IO0>, + <PIN_PB26__QSPI1_CS>, + <PIN_PB27__QSPI1_SCK>; + bias-pull-up; + slew-rate = <0>; + }; + + pinctrl_sdmmc0_default: sdmmc0-default { + pinmux = <PIN_PA0__SDMMC0_CK>, + <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_RSTN>, + <PIN_PA3__SDMMC0_DAT0>, + <PIN_PA4__SDMMC0_DAT1>, + <PIN_PA5__SDMMC0_DAT2>, + <PIN_PA6__SDMMC0_DAT3>; + bias-pull-up; + slew-rate = <0>; + }; + + pinctrl_sdmmc1_default: sdmmc1-default { + pinmux = <PIN_PB29__SDMMC1_CMD>, + <PIN_PB30__SDMMC1_CK>, + <PIN_PB31__SDMMC1_DAT0>, + <PIN_PC0__SDMMC1_DAT1>, + <PIN_PC1__SDMMC1_DAT2>, + <PIN_PC2__SDMMC1_DAT3>, + <PIN_PC4__SDMMC1_CD>; + bias-pull-up; + slew-rate = <0>; + }; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_default>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + }; +}; + +// M.2 slot for wireless card +&sdmmc0 { + bus-width = <4>; + cd-gpios = <&pioA 31 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <50000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + status = "okay"; +}; + +// micro SD socket +&sdmmc1 { + bus-width = <4>; + disable-wp; + max-frequency = <50000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + status = "okay"; +}; diff --git a/arch/arm/dts/dragonboard410c-uboot.dtsi b/arch/arm/dts/dragonboard410c-uboot.dtsi deleted file mode 100644 index cec64bf80f9..00000000000 --- a/arch/arm/dts/dragonboard410c-uboot.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * U-Boot addition to handle Dragonboard 410c pins - * - * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> - */ - -/ { - - smem { - bootph-all; - }; - - soc { - bootph-all; - - pinctrl@1000000 { - bootph-all; - - uart { - bootph-all; - }; - }; - - qcom,gcc@1800000 { - bootph-all; - }; - - serial@78b0000 { - bootph-all; - }; - }; -}; - - -&pm8916_gpios { - usb_hub_reset_pm { - gpios = <&pm8916_gpios 2 0>; - }; - - usb_sw_sel_pm { - gpios = <&pm8916_gpios 3 0>; - }; -}; diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts deleted file mode 100644 index 6a4e3ccf17b..00000000000 --- a/arch/arm/dts/dragonboard410c.dts +++ /dev/null @@ -1,209 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Qualcomm APQ8016 based Dragonboard 410C board device tree source - * - * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> - */ - -/dts-v1/; - -#include "skeleton64.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Qualcomm Technologies, Inc. Dragonboard 410c"; - compatible = "qcom,dragonboard", "qcom,apq8016-sbc"; - qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>; - qcom,board-id = <0x10018 0x0>; - #address-cells = <0x2>; - #size-cells = <0x2>; - - aliases { - usb0 = "/soc/ehci@78d9000"; - }; - - memory { - device_type = "memory"; - reg = <0 0x80000000 0 0x3da00000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - smem_mem: smem_region@86300000 { - reg = <0x0 0x86300000 0x0 0x100000>; - no-map; - }; - }; - - chosen { - stdout-path = "/soc/serial@78b0000"; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - }; - - soc { - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges = <0x0 0x0 0x0 0xffffffff>; - compatible = "simple-bus"; - - rpm_msg_ram: memory@60000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x60000 0x8000>; - }; - - soc_gpios: pinctrl@1000000 { - compatible = "qcom,msm8916-pinctrl"; - reg = <0x1000000 0x400000>; - gpio-controller; - gpio-count = <122>; - gpio-bank-name="soc"; - #gpio-cells = <2>; - - blsp1_uart: uart { - function = "blsp1_uart"; - pins = "GPIO_4", "GPIO_5"; - drive-strength = <8>; - bias-disable; - }; - }; - clkc: qcom,gcc@1800000 { - compatible = "qcom,gcc-apq8016"; - reg = <0x1800000 0x80000>; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - serial@78b0000 { - compatible = "qcom,msm-uartdm-v1.4"; - reg = <0x78b0000 0x200>; - clock = <&clkc 4>; - pinctrl-names = "uart"; - pinctrl-0 = <&blsp1_uart>; - }; - - ehci@78d9000 { - compatible = "qcom,ehci-host"; - reg = <0x78d9000 0x400>; - phys = <&ehci_phy>; - }; - - ehci_phy: ehci_phy@78d9000 { - compatible = "qcom,apq8016-usbphy"; - reg = <0x78d9000 0x400>; - #phy-cells = <0>; - }; - - sdhci@07824000 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x7824900 0x11c 0x7824000 0x800>; - bus-width = <0x8>; - index = <0x0>; - non-removable; - clock = <&clkc 0>; - clock-frequency = <100000000>; - }; - - sdhci@07864000 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x7864900 0x11c 0x7864000 0x800>; - index = <0x1>; - bus-width = <0x4>; - clock = <&clkc 1>; - clock-frequency = <200000000>; - cd-gpios = <&soc_gpios 38 GPIO_ACTIVE_LOW>; - }; - - wcnss { - bt { - compatible="qcom,wcnss-bt"; - }; - - wifi { - compatible="qcom,wcnss-wlan"; - }; - }; - - spmi_bus: spmi@200f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0200f000 0x001000>, - <0x02400000 0x400000>, - <0x02c00000 0x400000>, - <0x03800000 0x200000>, - <0x0200a000 0x002100>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - #address-cells = <0x1>; - #size-cells = <0x1>; - pmic0: pm8916@0 { - compatible = "qcom,spmi-pmic"; - reg = <0x0 0x1>; - #address-cells = <0x1>; - #size-cells = <0x1>; - - pon@800 { - compatible = "qcom,pm8916-pon"; - reg = <0x800 0x100>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; - - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - debounce = <15625>; - bias-pull-up; - }; - - pm8916_resin: resin { - compatible = "qcom,pm8941-resin"; - debounce = <15625>; - bias-pull-up; - }; - }; - - pm8916_gpios: pm8916_gpios@c000 { - compatible = "qcom,pm8916-gpio"; - reg = <0xc000 0x400>; - gpio-controller; - gpio-ranges = <&pm8916_gpios 0 0 4>; - #gpio-cells = <2>; - }; - }; - - pmic1: pm8916@1 { - compatible = "qcom,spmi-pmic"; - reg = <0x1 0x1>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - user1 { - label = "green:user1"; - gpios = <&soc_gpios 21 0>; - }; - - user2 { - label = "green:user2"; - gpios = <&soc_gpios 120 0>; - }; - - user3 { - label = "green:user3"; - gpios = <&pm8916_gpios 0 0>; - }; - - user4 { - label = "green:user4"; - gpios = <&pm8916_gpios 1 0>; - }; - }; -}; - -#include "dragonboard410c-uboot.dtsi" diff --git a/arch/arm/dts/dragonboard820c-uboot.dtsi b/arch/arm/dts/dragonboard820c-uboot.dtsi deleted file mode 100644 index d93c7c1fbde..00000000000 --- a/arch/arm/dts/dragonboard820c-uboot.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * U-Boot addition to handle Dragonboard 820c pins - * - * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> - */ - -/ { - smem { - bootph-all; - }; - - soc { - bootph-all; - - pinctrl@1010000 { - bootph-all; - - uart { - bootph-all; - }; - }; - - clock-controller@300000 { - bootph-all; - }; - - serial@75b0000 { - bootph-all; - }; - }; -}; diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts deleted file mode 100644 index 146a0af8aaf..00000000000 --- a/arch/arm/dts/dragonboard820c.dts +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Qualcomm APQ8096 based Dragonboard 820C board device tree source - * - * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> - */ - -/dts-v1/; - -#include "skeleton64.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. DB820c"; - compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &blsp2_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0 0x80000000 0 0xc0000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - smem_mem: smem_region@86300000 { - reg = <0x0 0x86300000 0x0 0x200000>; - no-map; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - gcc: clock-controller@300000 { - compatible = "qcom,gcc-msm8996"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x300000 0x90000>; - }; - - pinctrl: pinctrl@1010000 { - compatible = "qcom,msm8996-pinctrl"; - reg = <0x1010000 0x400000>; - - blsp8_uart: uart { - function = "blsp_uart8"; - pins = "GPIO_4", "GPIO_5"; - drive-strength = <8>; - bias-disable; - }; - }; - - blsp2_uart2: serial@75b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x75b0000 0x1000>; - clock = <&gcc 4>; - pinctrl-names = "uart"; - pinctrl-0 = <&blsp8_uart>; - }; - - sdhc2: sdhci@74a4900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x74a4900 0x314>, <0x74a4000 0x800>; - index = <0x0>; - bus-width = <4>; - clock = <&gcc 0>; - clock-frequency = <200000000>; - }; - - spmi_bus: spmi@400f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0400f000 0x1000>, - <0x04400000 0x800000>, - <0x04c00000 0x800000>, - <0x05800000 0x200000>, - <0x0400a000 0x002100>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - #address-cells = <0x1>; - #size-cells = <0x1>; - - pmic0: pm8994@0 { - compatible = "qcom,spmi-pmic"; - reg = <0x0 0x1>; - #address-cells = <0x1>; - #size-cells = <0x1>; - - pm8994_pon: pon@800 { - compatible = "qcom,pm8916-pon"; - reg = <0x800 0x100>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; - - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - debounce = <15625>; - bias-pull-up; - }; - - pm8994_resin: resin { - compatible = "qcom,pm8941-resin"; - debounce = <15625>; - bias-pull-up; - }; - }; - - pm8994_gpios: pm8994_gpios@c000 { - compatible = "qcom,pm8994-gpio"; - reg = <0xc000 0x400>; - gpio-controller; - gpio-ranges = <&pm8994_gpios 0 0 22>; - #gpio-cells = <2>; - }; - }; - - pmic1: pm8994@1 { - compatible = "qcom,spmi-pmic"; - reg = <0x1 0x1>; - #address-cells = <0x1>; - #size-cells = <0x1>; - }; - }; - }; - -}; - -#include "dragonboard820c-uboot.dtsi" diff --git a/arch/arm/dts/dragonboard845c-uboot.dtsi b/arch/arm/dts/dragonboard845c-uboot.dtsi deleted file mode 100644 index 775f45c0149..00000000000 --- a/arch/arm/dts/dragonboard845c-uboot.dtsi +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * U-Boot addition to handle Qualcomm Robotics RB3 Development Platform - * (dragonboard845c) pins - * - * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org> - */ - -/ -{ - soc { - bootph-all; - - serial@a84000 { - bootph-all; - }; - - clock-controller@100000 { - bootph-all; - }; - - pinctrl@3400000 { - bootph-all; - }; - }; -}; diff --git a/arch/arm/dts/dragonboard845c.dts b/arch/arm/dts/dragonboard845c.dts deleted file mode 100644 index 054f253eb32..00000000000 --- a/arch/arm/dts/dragonboard845c.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Qualcomm Robotics RB3 Development (dragonboard845c) board device - * tree source - * - * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org> - */ - -/dts-v1/; - -#include "sdm845.dtsi" - -/ { - model = "Thundercomm Dragonboard 845c"; - compatible = "thundercomm,db845c", "qcom,sdm845"; - #address-cells = <2>; - #size-cells = <2>; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &uart9; - }; - - memory { - device_type = "memory"; - reg = <0 0x80000000 0 0xfdfa0000>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - soc: soc { - serial@a84000 { - status = "okay"; - }; - }; -}; - -&pm8998_resin { - status = "okay"; -}; - -#include "dragonboard845c-uboot.dtsi" diff --git a/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi b/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi index e9b188ed658..358cf8abc4f 100644 --- a/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ #include "imx6qdl-u-boot.dtsi" +#include "imx6qdl-sr-som-u-boot.dtsi" / { board-detect { diff --git a/arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi b/arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi new file mode 100644 index 00000000000..0bd7df02dd6 --- /dev/null +++ b/arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include <dt-bindings/gpio/gpio.h> + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; + phy-handle = <&phy>; + phy-mode = "rgmii-id"; + + /* + * The PHY seems to require a long-enough reset duration to avoid + * some rare issues where the PHY gets stuck in an inconsistent and + * non-functional state at boot-up. 10ms proved to be fine . + */ + phy-reset-duration = <10>; + phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + status = "disabled"; + }; + + ethernet-phy@1 { + status = "disabled"; + }; + + ethernet-phy@4 { + status = "disabled"; + }; + + phy: ethernet-phy@ffffffff { + /* + * The PHY can appear either: + * - AR8035: at address 0 or 4 + * - ADIN1300: at address 1 + * Actual address being detected at runtime. + */ + reg = <0xffffffff>; + qca,clk-out-frequency = <125000000>; + qca,smarteee-tw-us-1g = <24>; + adi,phy-output-clock = "125mhz-free-running"; + }; + }; +}; diff --git a/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi b/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi index 68142769d36..854bf2798ae 100644 --- a/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi +++ b/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi @@ -51,3 +51,7 @@ }; }; }; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8mm-beacon-kit.dts b/arch/arm/dts/imx8mm-beacon-kit.dts deleted file mode 100644 index 74a7b0cc10c..00000000000 --- a/arch/arm/dts/imx8mm-beacon-kit.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2020 Compass Electronics Group, LLC - */ - -/dts-v1/; - -#include "imx8mm.dtsi" -#include "imx8mm-beacon-som.dtsi" -#include "imx8mm-beacon-baseboard.dtsi" - -/ { - model = "Beacon EmbeddedWorks i.MX8M Mini Development Kit"; - compatible = "beacon,imx8mm-beacon-kit", "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; -}; diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi deleted file mode 100644 index cf07987ccc1..00000000000 --- a/arch/arm/dts/imx8mm-beacon-som.dtsi +++ /dev/null @@ -1,461 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2020 Compass Electronics Group, LLC - */ - -/ { - aliases { - rtc0 = &rtc; - rtc1 = &snvs_rtc; - }; - - usdhc1_pwrseq: usdhc1_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_gpio>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - clocks = <&osc_32k>; - clock-names = "ext_clock"; - post-power-on-delay-ms = <80>; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi>; - status = "okay"; - - flash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - eeprom@50 { - compatible = "microchip,24c64", "atmel,24c64"; - pagesize = <32>; - read-only; /* Manufacturing EEPROM programmed at factory */ - reg = <0x50>; - }; - - rtc: rtc@51 { - compatible = "nxp,pcf85263"; - reg = <0x51>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MM_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; - clocks = <&osc_32k>; - max-speed = <4000000>; - clock-names = "extclk"; - }; -}; - -&usdhc1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <4>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - mmc-pwrseq = <&usdhc1_pwrseq>; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan>; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_flexspi: flexspigrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 - MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 - MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 - MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 - MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 - MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 - >; - }; - - pinctrl_usdhc1_gpio: usdhc1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 - >; - }; - - pinctrl_wlan: wlangrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts deleted file mode 100644 index a2b24d4d4e3..00000000000 --- a/arch/arm/dts/imx8mm-evk.dts +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019-2020 NXP - */ - -/dts-v1/; - -#include <dt-bindings/usb/pd.h> -#include "imx8mm-evk.dtsi" - -/ { - model = "FSL i.MX8MM EVK board"; - compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; - - aliases { - spi0 = &flexspi; - }; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi>; - status = "okay"; - - flash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - }; -}; - -&usdhc3 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_flexspi: flexspigrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 - MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi deleted file mode 100644 index 7d6317d95b1..00000000000 --- a/arch/arm/dts/imx8mm-evk.dtsi +++ /dev/null @@ -1,615 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 NXP - */ - -/dts-v1/; - -#include <dt-bindings/phy/phy-imx8-pcie.h> -#include <dt-bindings/usb/pd.h> -#include "imx8mm.dtsi" - -/ { - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - status { - label = "status"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_pcie0: regulator-pcie { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0_reg>; - regulator-name = "MPCIE_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000 0>; - brightness-levels = <0 255>; - num-interpolated-steps = <255>; - default-brightness-level = <250>; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - linux,autosuspend-period = <125>; - }; - - audio_codec_bt_sco: audio-codec-bt-sco { - compatible = "linux,bt-sco"; - #sound-dai-cells = <1>; - }; - - wm8524: audio-codec { - #sound-dai-cells = <0>; - compatible = "wlf,wm8524"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_wlf>; - wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; - }; - - sound-bt-sco { - compatible = "simple-audio-card"; - simple-audio-card,name = "bt-sco-audio"; - simple-audio-card,format = "dsp_a"; - simple-audio-card,bitclock-inversion; - simple-audio-card,frame-master = <&btcpu>; - simple-audio-card,bitclock-master = <&btcpu>; - - btcpu: simple-audio-card,cpu { - sound-dai = <&sai2>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - - simple-audio-card,codec { - sound-dai = <&audio_codec_bt_sco 1>; - }; - }; - - sound-wm8524 { - compatible = "simple-audio-card"; - simple-audio-card,name = "wm8524-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&cpudai>; - simple-audio-card,bitclock-master = <&cpudai>; - simple-audio-card,widgets = - "Line", "Left Line Out Jack", - "Line", "Right Line Out Jack"; - simple-audio-card,routing = - "Left Line Out Jack", "LINEVOUTL", - "Right Line Out Jack", "LINEVOUTR"; - - cpudai: simple-audio-card,cpu { - sound-dai = <&sai3>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <32>; - }; - - simple-audio-card,codec { - sound-dai = <&wm8524>; - clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; - }; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - qca,disable-smarteee; - vddio-supply = <&vddio>; - - vddio: vddio-regulator { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec1>; - reg = <0x50>; - interrupt-parent = <&gpio2>; - interrupts = <11 8>; - status = "okay"; - - port { - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - - typec1_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - data-role = "dual"; - try-power-role = "sink"; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) - PDO_VAR(5000, 20000, 3000)>; - op-sink-microwatt = <15000000>; - self-powered; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,tx-deemph-gen1 = <0x2d>; - fsl,tx-deemph-gen2 = <0xf>; - clocks = <&pcie0_refclk>; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - vpcie-supply = <®_pcie0>; - status = "okay"; -}; - -&sai2 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MM_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - disable-over-current; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 - >; - }; - - pinctrl_ir: irgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f - >; - }; - - pinctrl_gpio_wlf: gpiowlfgrp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 - MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 - >; - }; - - pinctrl_pcie0_reg: pcie0reggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - >; - }; - - pinctrl_typec1: typec1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw700x.dtsi b/arch/arm/dts/imx8mm-venice-gw700x.dtsi deleted file mode 100644 index c305e325d00..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw700x.dtsi +++ /dev/null @@ -1,525 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/net/ti-dp83867.h> - -/ { - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-user-pb { - label = "user_pb"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = <BTN_0>; - }; - - key-user-pb1x { - label = "user_pb1x"; - linux,code = <BTN_1>; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key_erased"; - linux,code = <BTN_2>; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - key-eeprom-wp { - label = "eeprom_wp"; - linux,code = <BTN_3>; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - key-tamper { - label = "tamper"; - linux,code = <BTN_4>; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = <BTN_5>; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; -}; - -&A53_0 { - cpu-supply = <&buck3_reg>; -}; - -&A53_1 { - cpu-supply = <&buck3_reg>; -}; - -&A53_2 { - cpu-supply = <&buck3_reg>; -}; - -&A53_3 { - cpu-supply = <&buck3_reg>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - pinctrl-0 = <&pinctrl_gsc>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@16 { - gw,mode = <4>; - reg = <0x16>; - label = "fan_tach"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vdd_vin"; - gw,voltage-divider-ohms = <22100 1000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vdd_adc1"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_adc2"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_dram"; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_1p2"; - }; - - channel@8e { - gw,mode = <2>; - reg = <0x8e>; - label = "vdd_1p0"; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_2p5"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@98 { - gw,mode = <2>; - reg = <0x98>; - label = "vdd_0p95"; - }; - - channel@9a { - gw,mode = <2>; - reg = <0x9a>; - label = "vdd_1p8"; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - - fan-controller@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "gw,gsc-fan"; - reg = <0x0a>; - }; - }; - - gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; - - pmic@69 { - compatible = "mps,mp5416"; - reg = <0x69>; - - regulators { - /* vdd_0p95: DRAM/GPU/VPU */ - buck1 { - regulator-name = "buck1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - regulator-min-microamp = <3800000>; - regulator-max-microamp = <6800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_soc */ - buck2 { - regulator-name = "buck2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-min-microamp = <2200000>; - regulator-max-microamp = <5200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_arm */ - buck3_reg: buck3 { - regulator-name = "buck3"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - regulator-min-microamp = <3800000>; - regulator-max-microamp = <6800000>; - regulator-always-on; - }; - - /* vdd_1p8 */ - buck4 { - regulator-name = "buck4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-min-microamp = <2200000>; - regulator-max-microamp = <5200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* nvcc_snvs_1p8 */ - ldo1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_snvs_0p8 */ - ldo2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_0p9 */ - ldo3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_1p8 */ - ldo4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; - pagesize = <32>; - }; -}; - -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 - >; - }; - - pinctrl_gsc: gscgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi index b3592331c72..07789c8d883 100644 --- a/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi @@ -25,6 +25,13 @@ gpios = <9 GPIO_ACTIVE_HIGH>; line-name = "dio1"; }; + + tpm_rst { + gpio-hog; + output-high; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "tpm_rst#"; + }; }; &gpio4 { diff --git a/arch/arm/dts/imx8mm-venice-gw71xx-0x.dts b/arch/arm/dts/imx8mm-venice-gw71xx-0x.dts deleted file mode 100644 index 3f88c4ad571..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw71xx-0x.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mm.dtsi" -#include "imx8mm-venice-gw700x.dtsi" -#include "imx8mm-venice-gw71xx.dtsi" - -/ { - model = "Gateworks Venice GW71xx-0x i.MX8MM Development Kit"; - compatible = "gw,imx8mm-gw71xx-0x", "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw71xx.dtsi b/arch/arm/dts/imx8mm-venice-gw71xx.dtsi deleted file mode 100644 index c557dbf4dcd..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw71xx.dtsi +++ /dev/null @@ -1,239 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - aliases { - usb0 = &usbotg1; - usb1 = &usbotg2; - }; - - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_en>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpio1 { - gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0", - "", "dio1", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - accelerometer@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio4>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -/* off-board header */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* off-board header */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - over-current-active-low; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ - MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000041 /* DIO2 */ - MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIO2 */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 - >; - }; - - pinctrl_reg_usb1_en: regusb1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141 - MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw72xx-0x.dts b/arch/arm/dts/imx8mm-venice-gw72xx-0x.dts deleted file mode 100644 index 641be3af989..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw72xx-0x.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mm.dtsi" -#include "imx8mm-venice-gw700x.dtsi" -#include "imx8mm-venice-gw72xx.dtsi" - -/ { - model = "Gateworks Venice GW72xx-0x i.MX8MM Development Kit"; - compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw72xx.dtsi b/arch/arm/dts/imx8mm-venice-gw72xx.dtsi deleted file mode 100644 index 97ed34a3c58..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw72xx.dtsi +++ /dev/null @@ -1,400 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - aliases { - ethernet1 = ð1; - usb0 = &usbotg1; - usb1 = &usbotg2; - }; - - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_en>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2_en>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, - <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; - - tpm@1 { - compatible = "tcg,tpm_tis-spi"; - reg = <0x1>; - spi-max-frequency = <36000000>; - }; -}; - -&gpio1 { - gpio-line-names = "rs485_term", "mipi_gpio4", "", "", - "", "", "pci_usb_sel", "dio0", - "", "dio1", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2", - "mipi_gpio1", "", "", "pci_wdis#", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - accelerometer@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio4>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -/* off-board header */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - status = "okay"; - - pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - pcie@1,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - pcie@2,3 { - reg = <0x1800 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - eth1: pcie@5,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - local-mac-address = [00 00 00 00 00 00]; - }; - }; - }; - }; -}; - -/* off-board header */ -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* off-board header */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* RS232 */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - over-current-active-low; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - vbus-supply = <®_usb_otg2_vbus>; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */ - MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */ - MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 - >; - }; - - pinctrl_reg_usb1_en: regusb1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 - MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 - >; - }; - - pinctrl_reg_usb2_en: regusb2grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 - MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 - MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw73xx-0x.dts b/arch/arm/dts/imx8mm-venice-gw73xx-0x.dts deleted file mode 100644 index 6905437ff28..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw73xx-0x.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mm.dtsi" -#include "imx8mm-venice-gw700x.dtsi" -#include "imx8mm-venice-gw73xx.dtsi" - -/ { - model = "Gateworks Venice GW73xx-0x i.MX8MM Development Kit"; - compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw73xx.dtsi b/arch/arm/dts/imx8mm-venice-gw73xx.dtsi deleted file mode 100644 index 7b2130dbdb2..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw73xx.dtsi +++ /dev/null @@ -1,452 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - aliases { - ethernet1 = ð1; - usb0 = &usbotg1; - usb1 = &usbotg2; - }; - - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_en>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2_en>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_wifi_en: regulator-wifi-en { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wl>; - compatible = "regulator-fixed"; - regulator-name = "wl"; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100>; - enable-active-high; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, - <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; - - tpm@1 { - compatible = "tcg,tpm_tis-spi"; - reg = <0x1>; - spi-max-frequency = <36000000>; - }; -}; - -&gpio1 { - gpio-line-names = "rs485_term", "mipi_gpio4", "", "", - "", "", "pci_usb_sel", "dio0", - "", "dio1", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2", - "mipi_gpio1", "", "", "pci_wdis#", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - accelerometer@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio4>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -/* off-board header */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - status = "okay"; - - pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - pcie@1,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - pcie@2,4 { - reg = <0x2000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - eth1: pcie@6,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - local-mac-address = [00 00 00 00 00 00]; - }; - }; - }; - }; -}; - -/* off-board header */ -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* bluetooth HCI */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>; - cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; -}; - -/* RS232 */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - over-current-active-low; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - vbus-supply = <®_usb_otg2_vbus>; - status = "okay"; -}; - -/* SDIO WiFi */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wifi_en>; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */ - MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */ - MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 - >; - }; - - pinctrl_bten: btengrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 - >; - }; - - pinctrl_reg_wl: regwlgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 - >; - }; - - pinctrl_reg_usb1_en: regusb1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 - MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 - >; - }; - - pinctrl_reg_usb2_en: regusb2grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 - MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 - MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi index e68030e7b22..9fa21942c0c 100644 --- a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi @@ -43,6 +43,20 @@ }; &gpio4 { + dig1ctl { + gpio-hog; + output-low; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "dig1_ctl"; + }; + + dig2ctl { + gpio-hog; + output-low; + gpios = <5 GPIO_ACTIVE_HIGH>; + line-name = "dig2_ctl"; + }; + uart3_rs232 { gpio-hog; output-high; diff --git a/arch/arm/dts/imx8mm-venice-gw7901.dts b/arch/arm/dts/imx8mm-venice-gw7901.dts deleted file mode 100644 index 826627bd450..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw7901.dts +++ /dev/null @@ -1,1137 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 Gateworks Corporation - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -#include "imx8mm.dtsi" - -/ { - model = "Gateworks Venice GW7901 i.MX8MM board"; - compatible = "gw,imx8mm-gw7901", "fsl,imx8mm"; - - aliases { - ethernet0 = &fec1; - ethernet1 = &lan1; - ethernet2 = &lan2; - ethernet3 = &lan3; - ethernet4 = &lan4; - usb0 = &usbotg1; - usb1 = &usbotg2; - }; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-user-pb { - label = "user_pb"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = <BTN_0>; - }; - - key-user-pb1x { - label = "user_pb1x"; - linux,code = <BTN_1>; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key_erased"; - linux,code = <BTN_2>; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - key-eeprom-wp { - label = "eeprom_wp"; - linux,code = <BTN_3>; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - key-tamper { - label = "tamper"; - linux,code = <BTN_4>; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = <BTN_5>; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - led-controller { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led01_red"; - gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led01_grn"; - gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-2 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led02_red"; - gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-3 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led02_grn"; - gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-4 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led03_red"; - gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-5 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led03_grn"; - gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-6 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led04_red"; - gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-7 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led04_grn"; - gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-8 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led05_red"; - gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-9 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led05_grn"; - gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-a { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led06_red"; - gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-b { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led06_grn"; - gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - regulator-ioexp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_ioexp>; - compatible = "regulator-fixed"; - regulator-name = "ioexp"; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - regulator-isouart { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_isouart>; - compatible = "regulator-fixed"; - regulator-name = "iso_uart"; - gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; - startup-delay-us = <100>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb2_vbus: regulator-usb2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2>; - compatible = "regulator-fixed"; - regulator-name = "usb_usb2_vbus"; - gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_wifi: regulator-wifi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wl>; - compatible = "regulator-fixed"; - regulator-name = "wifi"; - gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&disp_blk_ctrl { - status = "disabled"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - status = "okay"; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - local-mac-address = [00 00 00 00 00 00]; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gpio1 { - gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#", - "", "uart1_rs232#", "dig1_in", "dig1_out", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = "", "", "", "", - "", "", "uart3_rs232#", "uart3_rs422#", - "uart3_rs485#", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", ""; -}; - -&gpio5 { - gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "", - "", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpu_2d { - status = "disabled"; -}; - -&gpu_3d { - status = "disabled"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - pinctrl-0 = <&pinctrl_gsc>; - interrupt-parent = <&gpio4>; - interrupts = <16 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <1>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vin_aux1"; - gw,voltage-divider-ohms = <22100 1000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vin_aux2"; - gw,voltage-divider-ohms = <22100 1000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_vin"; - gw,voltage-divider-ohms = <22100 1000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_2p5"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@8e { - gw,mode = <2>; - reg = <0x8e>; - label = "vdd_0p95"; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_soc"; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_arm"; - }; - - channel@98 { - gw,mode = <2>; - reg = <0x98>; - label = "vdd_1p8"; - }; - - channel@9a { - gw,mode = <2>; - reg = <0x9a>; - label = "vdd_1p2"; - }; - - channel@9c { - gw,mode = <2>; - reg = <0x9c>; - label = "vdd_dram"; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - }; - - gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio3>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - /* vdd_soc: 0.805-0.900V (typ=0.8V) */ - BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - /* vdd_arm: 0.805-1.0V (typ=0.9V) */ - BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ - BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_3p3 */ - BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_1p8 */ - BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_dram */ - BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - /* nvcc_snvs_1p8 */ - LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_snvs_0p8 */ - LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdda_1p8 */ - LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - leds_gpio: gpio@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - switch: switch@5f { - compatible = "microchip,ksz9897"; - reg = <0x5f>; - pinctrl-0 = <&pinctrl_ksz>; - interrupt-parent = <&gpio4>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - phy-mode = "rgmii-id"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - lan1: port@0 { - reg = <0>; - label = "lan1"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - lan2: port@1 { - reg = <1>; - label = "lan2"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - lan3: port@2 { - reg = <2>; - label = "lan3"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - lan4: port@3 { - reg = <3>; - label = "lan4"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&fec1>; - phy-mode = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - - crypto@60 { - compatible = "atmel,atecc508a"; - reg = <0x60>; - }; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - status = "okay"; -}; - -&pgc_gpu { - status = "disabled"; -}; - -&pgc_gpumix { - status = "disabled"; -}; - -&pgc_mipi { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; - rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; -}; - -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; - cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>; - cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -/* SDIO WiFi */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wifi>; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */ - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */ - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */ - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */ - MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */ - MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */ - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */ - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */ - MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */ - >; - }; - - pinctrl_gsc: gscgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 - >; - }; - - pinctrl_ksz: kszgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41 - MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */ - >; - }; - - pinctrl_pcie0: pciegrp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */ - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 - >; - }; - - pinctrl_reg_isouart: regisouartgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 - >; - }; - - pinctrl_reg_ioexp: regioexpgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 - >; - }; - - pinctrl_reg_wl: regwlgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041 - >; - }; - - pinctrl_reg_usb2: regusb1grp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x41 - MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140 - MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x140 - >; - }; - - pinctrl_spi1: spi1grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 - MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 - MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140 - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140 - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140 - >; - }; - - pinctrl_uart1_gpio: uart1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */ - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */ - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140 - MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 - >; - }; - - pinctrl_uart3_gpio: uart3gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */ - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */ - MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */ - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 - MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 - MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140 - MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140 - >; - }; - - pinctrl_uart4_gpio: uart4gpiogrp { - fsl,pins = < - - MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */ - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */ - MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */ - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2-gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts deleted file mode 100644 index 11481e09c75..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw7902.dts +++ /dev/null @@ -1,1052 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2021 Gateworks Corporation - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/net/ti-dp83867.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -#include "imx8mm.dtsi" - -/ { - model = "Gateworks Venice GW7902 i.MX8MM board"; - compatible = "gw,imx8mm-gw7902", "fsl,imx8mm"; - - aliases { - ethernet1 = ð1; - usb0 = &usbotg1; - usb1 = &usbotg2; - }; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - can20m: can20m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <20000000>; - clock-output-names = "can20m"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-user-pb { - label = "user_pb"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = <BTN_0>; - }; - - key-user-pb1x { - label = "user_pb1x"; - linux,code = <BTN_1>; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key_erased"; - linux,code = <BTN_2>; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - key-eeprom-wp { - label = "eeprom_wp"; - linux,code = <BTN_3>; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - key-tamper { - label = "tamper"; - linux,code = <BTN_4>; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = <BTN_5>; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel1"; - gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel2"; - gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-2 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel3"; - gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-3 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel4"; - gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-4 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel5"; - gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb1_vbus: regulator-usb1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1>; - regulator-name = "usb_usb1_vbus"; - gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_wifi: regulator-wifi { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wl>; - regulator-name = "wifi"; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&can20m>; - interrupt-parent = <&gpio2>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - spi-max-frequency = <10000000>; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - local-mac-address = [00 00 00 00 00 00]; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; - }; -}; - -&gpio1 { - gpio-line-names = "", "", "", "", "", "", "", "", - "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = "", "", "", "", "", "", "", "", - "uart2_en#", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "", - "lte_pwr#", "lte_rst", "lte_int", "", - "amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485", - "", "uart1_term", "uart1_half", "app_gpio2", - "mipi_gpio1", "", "", ""; -}; - -&gpio5 { - gpio-line-names = "", "", "", "mipi_gpio4", - "mipi_gpio3", "mipi_gpio2", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - pinctrl-0 = <&pinctrl_gsc>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <1>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vin"; - gw,voltage-divider-ohms = <22100 1000>; - gw,voltage-offset-microvolt = <700000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vin_4p0"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_0p9"; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_soc"; - }; - - channel@8e { - gw,mode = <2>; - reg = <0x8e>; - label = "vdd_arm"; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_1p8"; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_dram"; - }; - - channel@98 { - gw,mode = <2>; - reg = <0x98>; - label = "vdd_1p0"; - }; - - channel@9a { - gw,mode = <2>; - reg = <0x9a>; - label = "vdd_2p5"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@9c { - gw,mode = <2>; - reg = <0x9c>; - label = "vdd_5p0"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - }; - - gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - /* vdd_soc: 0.805-0.900V (typ=0.8V) */ - BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - /* vdd_arm: 0.805-1.0V (typ=0.9V) */ - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ - BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_3p3 */ - BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_1p8 */ - BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_dram */ - BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - /* nvcc_snvs_1p8 */ - LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_snvs_0p8 */ - LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdda_1p8 */ - LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - accelerometer@19 { - compatible = "st,lis2de12"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio1>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -/* off-board header */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -/* off-board header */ -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - status = "okay"; - - pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - eth1: pcie@1,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - local-mac-address = [00 00 00 00 00 00]; - }; - }; -}; - -/* off-board header */ -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -/* RS232/RS485/RS422 selectable */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; - rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; -}; - -/* RS232 console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* bluetooth HCI */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; - rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - }; -}; - -/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; - dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "host"; - vbus-supply = <®_usb1_vbus>; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -/* SDIO WiFi */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wifi>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ - MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ - MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */ - MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */ - MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */ - MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ - MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */ - MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */ - MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */ - MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ - MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ - MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ - MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */ - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */ - MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ - >; - }; - - pinctrl_gsc: gscgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 - MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 - MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 - MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 - MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 - >; - }; - - pinctrl_pcie0: pciegrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x41 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */ - >; - }; - - pinctrl_reg_wl: regwlgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */ - >; - }; - - pinctrl_reg_usb1: regusb1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - >; - }; - - pinctrl_spi1: spi1grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 - MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 - MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 - MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */ - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */ - MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */ - >; - }; - - pinctrl_uart1_gpio: uart1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */ - MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */ - MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3_gpio: uart3_gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */ - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */ - MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */ - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 - MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 - MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */ - MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */ - MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */ - MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */ - MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */ - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */ - MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */ - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw7903.dts b/arch/arm/dts/imx8mm-venice-gw7903.dts deleted file mode 100644 index 1ec91c5c6a4..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw7903.dts +++ /dev/null @@ -1,869 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Gateworks Corporation - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -#include "imx8mm.dtsi" - -/ { - model = "Gateworks Venice GW7903 i.MX8MM board"; - compatible = "gw,imx8mm-gw7903", "fsl,imx8mm"; - - aliases { - ethernet0 = &fec1; - usb0 = &usbotg1; - }; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-user-pb { - label = "user_pb"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = <BTN_0>; - }; - - key-user-pb1x { - label = "user_pb1x"; - linux,code = <BTN_1>; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key_erased"; - linux,code = <BTN_2>; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - key-eeprom-wp { - label = "eeprom_wp"; - linux,code = <BTN_3>; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = <BTN_5>; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led01_red"; - gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led01_grn"; - gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-2 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led02_red"; - gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-3 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led02_grn"; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-4 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led03_red"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-5 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led03_grn"; - gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-6 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led04_red"; - gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-7 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led04_grn"; - gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-8 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led05_red"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-9 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led05_grn"; - gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-a { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led06_red"; - gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-b { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led06_grn"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - local-mac-address = [00 00 00 00 00 00]; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - rx-internal-delay-ps = <2000>; - tx-internal-delay-ps = <2500>; - }; - }; -}; - -&gpio1 { - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = "dig2_in", "dig2_out#", "dig2_ctl", "", "", "", "dig1_ctl", "", - "dig1_out#", "dig1_in", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio5 { - gpio-line-names = "", "", "", "", "", "", "", "sim1_det#", - "sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - pinctrl-0 = <&pinctrl_gsc>; - interrupt-parent = <&gpio4>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <1>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vin"; - gw,voltage-divider-ohms = <22100 1000>; - gw,voltage-offset-microvolt = <700000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vdd_5p0"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_0p9"; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_soc"; - }; - - channel@8e { - gw,mode = <2>; - reg = <0x8e>; - label = "vdd_arm"; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_1p8"; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_dram"; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - }; - - gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - /* vdd_soc: 0.805-0.900V (typ=0.8V) */ - BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - /* vdd_arm: 0.805-1.0V (typ=0.9V) */ - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ - BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_3p3 */ - BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_1p8 */ - BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_dram */ - BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - /* nvcc_snvs_1p8 */ - LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_snvs_0p8 */ - LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdda_1p8 */ - LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - accelerometer@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - status = "okay"; -}; - -&pgc_mipi { - status = "disabled"; -}; - -/* off-board RS232/RS485/RS422 */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; -}; - -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000041 /* RS422# */ - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000041 /* RS485# */ - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */ - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */ - MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */ - MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40000041 /* DIG1_CTL */ - MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x40000041 /* DIG2_CTL */ - MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */ - MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */ - MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */ - MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x40000041 /* SIM2DET# */ - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000041 /* SIM2SEL */ - MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */ - MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */ - >; - }; - - pinctrl_gsc: gscgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 - MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19 - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19 - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x19 - MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 - MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 - MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19 - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 - >; - }; - - pinctrl_pcie0: pciegrp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140 - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140 - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x140 - MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2-gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw7904.dts b/arch/arm/dts/imx8mm-venice-gw7904.dts deleted file mode 100644 index 93c9651c315..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw7904.dts +++ /dev/null @@ -1,928 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Gateworks Corporation - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -#include "imx8mm.dtsi" - -/ { - model = "Gateworks Venice GW7904 i.MX8MM board"; - compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-0 { - label = "user_pb"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = <BTN_0>; - }; - - key-1 { - label = "user_pb1x"; - linux,code = <BTN_1>; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-2 { - label = "key_erased"; - linux,code = <BTN_2>; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - key-3 { - label = "eeprom_wp"; - linux,code = <BTN_3>; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - key-4 { - label = "switch_hold"; - linux,code = <BTN_5>; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led01_grn"; - gpios = <&gpioled 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_YELLOW>; - label = "led01_yel"; - gpios = <&gpioled 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-2 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led02_grn"; - gpios = <&gpioled 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-3 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_YELLOW>; - label = "led02_yel"; - gpios = <&gpioled 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-4 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led03_grn"; - gpios = <&gpioled 4 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-5 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_YELLOW>; - label = "led03_yel"; - gpios = <&gpioled 5 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-6 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led04_grn"; - gpios = <&gpioled 6 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-7 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_YELLOW>; - label = "led04_yel"; - gpios = <&gpioled 7 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-8 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led05_grn"; - gpios = <&gpioled 8 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-9 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_YELLOW>; - label = "led05_yel"; - gpios = <&gpioled 9 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-10 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led06_grn"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-11 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led06_red"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-12 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led07_grn"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-13 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led07_red"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-14 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led08_grn"; - gpios = <&gpioled 10 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-15 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_YELLOW>; - label = "led08_yel"; - gpios = <&gpioled 11 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-16 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led09_grn"; - gpios = <&gpioled 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-17 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_YELLOW>; - label = "led09_yel"; - gpios = <&gpioled 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-18 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led10_grn"; - gpios = <&gpioled 14 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-19 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_YELLOW>; - label = "led10_yel"; - gpios = <&gpioled 15 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - local-mac-address = [00 00 00 00 00 00]; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&gpio1 { - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "rs232_en#", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio5 { - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "pci_wdis#", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - pinctrl-0 = <&pinctrl_gsc>; - interrupt-parent = <&gpio4>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <1>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vin"; - gw,voltage-divider-ohms = <22100 1000>; - gw,voltage-offset-microvolt = <700000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vdd_5p0"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_0p9"; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_soc"; - }; - - channel@8e { - gw,mode = <2>; - reg = <0x8e>; - label = "vdd_arm"; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_1p8"; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_dram"; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - }; - - gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - /* vdd_soc: 0.805-0.900V (typ=0.8V) */ - BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - /* vdd_arm: 0.805-1.0V (typ=0.9V) */ - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ - BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_3p3 */ - BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_1p8 */ - BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_dram */ - BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - /* nvcc_snvs_1p8 */ - LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_snvs_0p8 */ - LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdda_1p8 */ - LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - accelerometer@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gpioled: gpio@27 { - compatible = "nxp,pca9555"; - reg = <0x27>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - status = "okay"; -}; - -&pgc_mipi { - status = "disabled"; -}; - -/* off-board RS232 */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* off-board RS232 */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */ - MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */ - MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000019 - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000019 - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000019 - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000019 - >; - }; - - pinctrl_gsc: gscgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 - >; - }; - - pinctrl_pcie0: pciegrp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2-gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw7905-0x.dts b/arch/arm/dts/imx8mm-venice-gw7905-0x.dts deleted file mode 100644 index 914753f062c..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw7905-0x.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mm.dtsi" -#include "imx8mm-venice-gw700x.dtsi" -#include "imx8mm-venice-gw7905.dtsi" - -/ { - model = "Gateworks Venice GW7905-0x i.MX8MM Development Kit"; - compatible = "gateworks,imx8mm-gw7905-0x", "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; -}; - -/* Disable SOM interfaces not used on baseboard */ -&fec1 { - status = "disabled"; -}; - -&usdhc1 { - status = "disabled"; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw7905.dtsi b/arch/arm/dts/imx8mm-venice-gw7905.dtsi deleted file mode 100644 index 9646eb9e492..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw7905.dtsi +++ /dev/null @@ -1,303 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_usb2_vbus: regulator-usb2-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2_en>; - compatible = "regulator-fixed"; - regulator-name = "usb2_vbus"; - gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - compatible = "regulator-fixed"; - regulator-name = "SD2_3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpio1 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "gpioa", "gpiob", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "pci_usb_sel", - "", "", "", "pci_wdis#", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", - "gpioc", "gpiod", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; - pagesize = <32>; - }; -}; - -/* off-board header */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* USB1 - Type C front panel SINK port J14 */ -&usbotg1 { - dr_mode = "peripheral"; - status = "okay"; -}; - -/* USB2 4-port USB3.0 HUB: - * P1 - USBC connector (host only) - * P2 - USB2 test connector - * P3 - miniPCIe full card - * P4 - miniPCIe half card - */ -&usbotg2 { - dr_mode = "host"; - vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000040 /* GPIOA */ - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x40000040 /* GPIOB */ - MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000106 /* PCI_USBSEL */ - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000106 /* PCIE_WDIS# */ - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000040 /* GPIOD */ - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */ - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */ - MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x6 /* LEDR */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_pcie0: pciegrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x106 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106 - >; - }; - - pinctrl_reg_usb2_en: regusb2grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x6 /* USBHUB_RST# (ext p/u) */ - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x140 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x140 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x140 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice.dts b/arch/arm/dts/imx8mm-venice.dts deleted file mode 100644 index d0929908ce8..00000000000 --- a/arch/arm/dts/imx8mm-venice.dts +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2021 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mm.dtsi" - -/ { - model = "Gateworks Venice i.MX8MM board"; - compatible = "gw,imx8mm-venice", "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; - pagesize = <32>; - }; -}; - -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1grp-gpio-grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-verdin-dev.dtsi b/arch/arm/dts/imx8mm-verdin-dev.dtsi deleted file mode 100644 index 3c4b8ca125e..00000000000 --- a/arch/arm/dts/imx8mm-verdin-dev.dtsi +++ /dev/null @@ -1,160 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/ { - sound_card: sound-card { - compatible = "simple-audio-card"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "imx8mm-nau8822"; - simple-audio-card,routing = - "Headphones", "LHP", - "Headphones", "RHP", - "Speaker", "LSPK", - "Speaker", "RSPK", - "Line Out", "AUXOUT1", - "Line Out", "AUXOUT2", - "LAUX", "Line In", - "RAUX", "Line In", - "LMICP", "Mic In", - "RMICP", "Mic In"; - simple-audio-card,widgets = - "Headphones", "Headphones", - "Line Out", "Line Out", - "Speaker", "Speaker", - "Microphone", "Mic In", - "Line", "Line In"; - - dailink_master: simple-audio-card,codec { - clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; - sound-dai = <&nau8822_1a>; - }; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - }; -}; - -/* Verdin SPI_1 */ -&ecspi2 { - status = "okay"; -}; - -/* EEPROM on display adapter boards */ -&eeprom_display_adapter { - status = "okay"; -}; - -/* EEPROM on Verdin Development board */ -&eeprom_carrier_board { - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; - -/* Verdin QSPI_1 */ -&flexspi { - status = "okay"; -}; - -/* Current measurement into module VCC */ -&hwmon { - status = "okay"; -}; - -&hwmon_temp { - vs-supply = <®_1p8v>; - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&gpio_expander_21 { - status = "okay"; -}; - -/* Verdin I2C_1 */ -&i2c4 { - status = "okay"; - - /* Audio Codec */ - nau8822_1a: audio-codec@1a { - compatible = "nuvoton,nau8822"; - reg = <0x1a>; - #sound-dai-cells = <0>; - }; -}; - -/* Verdin PCIE_1 */ -&pcie0 { - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -/* Verdin PWM_3_DSI */ -&pwm1 { - status = "okay"; -}; - -/* Verdin PWM_1 */ -&pwm2 { - status = "okay"; -}; - -/* Verdin PWM_2 */ -&pwm3 { - status = "okay"; -}; - -/* Verdin I2S_1 */ -&sai2 { - status = "okay"; -}; - -/* Verdin UART_3 */ -&uart1 { - status = "okay"; -}; - -/* Verdin UART_1, connector X50 through RS485 transceiver */ -&uart2 { - linux,rs485-enabled-at-boot-time; - rs485-rts-active-low; - rs485-rx-during-tx; - status = "okay"; -}; - -/* Verdin UART_2 */ -&uart3 { - status = "okay"; -}; - -/* Verdin USB_1 */ -&usbotg1 { - disable-over-current; - status = "okay"; -}; - -/* Verdin USB_2 */ -&usbotg2 { - disable-over-current; - status = "okay"; -}; - -/* Limit frequency on dev board due to long traces and bad signal integrity */ -&usdhc2 { - max-frequency = <100000000>; - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi index 38db56059d6..8b397f535c1 100644 --- a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi @@ -60,6 +60,11 @@ ctrl-sleep-moci-hog { bootph-pre-ram; + gpio-hog; + output-high; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + }; }; diff --git a/arch/arm/dts/imx8mm-verdin-wifi-dev.dts b/arch/arm/dts/imx8mm-verdin-wifi-dev.dts deleted file mode 100644 index ef952021832..00000000000 --- a/arch/arm/dts/imx8mm-verdin-wifi-dev.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/dts-v1/; - -#include "imx8mm-verdin.dtsi" -#include "imx8mm-verdin-wifi.dtsi" -#include "imx8mm-verdin-dev.dtsi" - -/ { - model = "Toradex Verdin iMX8M Mini WB on Verdin Development Board"; - compatible = "toradex,verdin-imx8mm-wifi-dev", - "toradex,verdin-imx8mm-wifi", - "toradex,verdin-imx8mm", - "fsl,imx8mm"; -}; diff --git a/arch/arm/dts/imx8mm-verdin-wifi.dtsi b/arch/arm/dts/imx8mm-verdin-wifi.dtsi deleted file mode 100644 index 017db9eab25..00000000000 --- a/arch/arm/dts/imx8mm-verdin-wifi.dtsi +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/ { - reg_wifi_en: regulator-wifi-en { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_pwr_en>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "PDn_AW-CM276NF"; - startup-delay-us = <2000>; - }; -}; - -&gpio3 { - gpio-line-names = "SODIMM_52", - "SODIMM_54", - "SODIMM_64", - "SODIMM_21", - "SODIMM_206", - "SODIMM_76", - "SODIMM_56", - "SODIMM_58", - "SODIMM_60", - "SODIMM_62", - "", - "", - "", - "", - "SODIMM_66", - "SODIMM_17", - "", - "", - "", - "SODIMM_244", - "", - "SODIMM_48", - "SODIMM_44", - "SODIMM_42", - "SODIMM_46"; -}; - -&gpio4 { - gpio-line-names = "SODIMM_102", - "SODIMM_90", - "SODIMM_92", - "SODIMM_94", - "SODIMM_96", - "SODIMM_100", - "", - "", - "", - "", - "SODIMM_120", - "SODIMM_104", - "SODIMM_106", - "SODIMM_108", - "SODIMM_112", - "SODIMM_114", - "SODIMM_116", - "", - "SODIMM_118", - "", - "SODIMM_88", - "SODIMM_149", - "SODIMM_147", - "SODIMM_36", - "SODIMM_32", - "SODIMM_30", - "SODIMM_34", - "SODIMM_38", - "SODIMM_252", - "SODIMM_133", - "SODIMM_135", - "SODIMM_129"; -}; - -/* On-module Wi-Fi */ -&usdhc3 { - bus-width = <4>; - keep-power-in-suspend; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>; - vmmc-supply = <®_wifi_en>; - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mm-verdin.dtsi b/arch/arm/dts/imx8mm-verdin.dtsi deleted file mode 100644 index 6f081158714..00000000000 --- a/arch/arm/dts/imx8mm-verdin.dtsi +++ /dev/null @@ -1,1319 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -#include <dt-bindings/phy/phy-imx8-pcie.h> -#include <dt-bindings/pwm/pwm.h> -#include "imx8mm.dtsi" - -/ { - chosen { - stdout-path = &uart1; - }; - - aliases { - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 45 63 88 119 158 203 255>; - default-brightness-level = <4>; - /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ - enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; - power-supply = <®_3p3v>; - /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ - pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; - status = "disabled"; - }; - - /* Fixed clock dedicated to SPI CAN controller */ - clk40m: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <40000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - key-wakeup { - debounce-interval = <10>; - /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ - gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - label = "Wake-Up"; - linux,code = <KEY_WAKEUP>; - wakeup-source; - }; - }; - - hdmi_connector: hdmi-connector { - compatible = "hdmi-connector"; - ddc-i2c-bus = <&i2c2>; - /* Verdin PWM_3_DSI (SODIMM 19) */ - hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - label = "hdmi"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>; - type = "a"; - status = "disabled"; - }; - - panel_lvds: panel-lvds { - compatible = "panel-lvds"; - backlight = <&backlight>; - data-mapping = "vesa-24"; - status = "disabled"; - }; - - /* Carrier Board Supplies */ - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8_SW"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_SW"; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "+V5_SW"; - }; - - /* Non PMIC On-module Supplies */ - reg_ethphy: regulator-ethphy { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ - off-on-delay-us = <500000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_eth>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "On-module +V3.3_ETH"; - startup-delay-us = <200000>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - compatible = "regulator-fixed"; - enable-active-high; - /* Verdin USB_1_EN (SODIMM 155) */ - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_en>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "USB_1_EN"; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2 { - compatible = "regulator-fixed"; - enable-active-high; - /* Verdin USB_2_EN (SODIMM 185) */ - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2_en>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "USB_2_EN"; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - enable-active-high; - /* Verdin SD_1_PWR_EN (SODIMM 76) */ - gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; - off-on-delay-us = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_SD"; - startup-delay-us = <2000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Use the kernel configuration settings instead */ - /delete-node/ linux,cma; - }; -}; - -&A53_0 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_1 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_2 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_3 { - cpu-supply = <®_vdd_arm>; -}; - -&cpu_alert0 { - temperature = <95000>; -}; - -&cpu_crit0 { - temperature = <105000>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25000000 { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750000000 { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -/* Verdin SPI_1 */ -&ecspi2 { - #address-cells = <1>; - #size-cells = <0>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; -}; - -/* Verdin CAN_1 (On-module) */ -&ecspi3 { - #address-cells = <1>; - #size-cells = <0>; - cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; - - can1: can@0 { - compatible = "microchip,mcp251xfd"; - clocks = <&clk40m>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_int>; - reg = <0>; - spi-max-frequency = <8500000>; - }; -}; - -/* Verdin ETH_1 (On-module PHY) */ -&fec1 { - fsl,magic-packet; - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; - phy-supply = <®_ethphy>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_fec1>; - pinctrl-1 = <&pinctrl_fec1_sleep>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - interrupt-parent = <&gpio1>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <0>; - reg = <7>; - }; - }; -}; - -/* Verdin QSPI_1 */ -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; -}; - -&gpio1 { - gpio-line-names = "SODIMM_216", - "SODIMM_19", - "", - "", - "", - "", - "", - "", - "SODIMM_220", - "SODIMM_222", - "", - "SODIMM_218", - "SODIMM_155", - "SODIMM_157", - "SODIMM_185", - "SODIMM_187"; -}; - -&gpio2 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "SODIMM_84", - "SODIMM_78", - "SODIMM_74", - "SODIMM_80", - "SODIMM_82", - "SODIMM_70", - "SODIMM_72"; -}; - -&gpio5 { - gpio-line-names = "SODIMM_131", - "", - "SODIMM_91", - "SODIMM_16", - "SODIMM_15", - "SODIMM_208", - "SODIMM_137", - "SODIMM_139", - "SODIMM_141", - "SODIMM_143", - "SODIMM_196", - "SODIMM_200", - "SODIMM_198", - "SODIMM_202", - "", - "", - "SODIMM_55", - "SODIMM_53", - "SODIMM_95", - "SODIMM_93", - "SODIMM_14", - "SODIMM_12", - "", - "", - "", - "", - "SODIMM_210", - "SODIMM_212", - "SODIMM_151", - "SODIMM_153"; - - ctrl-sleep-moci-hog { - gpio-hog; - /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ - gpios = <1 GPIO_ACTIVE_HIGH>; - line-name = "CTRL_SLEEP_MOCI#"; - output-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; - }; -}; - -/* On-module I2C */ -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pca9450: pmic@25 { - compatible = "nxp,pca9450a"; - interrupt-parent = <&gpio1>; - /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0x25>; - - /* - * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC - * behind this PMIC. - */ - - regulators { - reg_vdd_soc: BUCK1 { - nxp,dvs-run-voltage = <850000>; - nxp,dvs-standby-voltage = <800000>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <850000>; - regulator-min-microvolt = <800000>; - regulator-name = "On-module +VDD_SOC (BUCK1)"; - regulator-ramp-delay = <3125>; - }; - - reg_vdd_arm: BUCK2 { - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1050000>; - regulator-min-microvolt = <805000>; - regulator-name = "On-module +VDD_ARM (BUCK2)"; - regulator-ramp-delay = <3125>; - }; - - reg_vdd_dram: BUCK3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1000000>; - regulator-min-microvolt = <805000>; - regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; - }; - - reg_vdd_3v3: BUCK4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "On-module +V3.3 (BUCK4)"; - }; - - reg_vdd_1v8: BUCK5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "PWR_1V8_MOCI (BUCK5)"; - }; - - reg_nvcc_dram: BUCK6 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1100000>; - regulator-min-microvolt = <1100000>; - regulator-name = "On-module +VDD_DDR (BUCK6)"; - }; - - reg_nvcc_snvs: LDO1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-module +V1.8_SNVS (LDO1)"; - }; - - reg_vdd_snvs: LDO2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <800000>; - regulator-min-microvolt = <800000>; - regulator-name = "On-module +V0.8_SNVS (LDO2)"; - }; - - reg_vdda: LDO3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-module +V1.8A (LDO3)"; - }; - - reg_vdd_phy: LDO4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <900000>; - regulator-min-microvolt = <900000>; - regulator-name = "On-module +V0.9_MIPI (LDO4)"; - }; - - reg_nvcc_sd: LDO5 { - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; - }; - }; - }; - - rtc_i2c: rtc@32 { - compatible = "epson,rx8130"; - reg = <0x32>; - }; - - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - /* Verdin I2C_1 (ADC_4 - ADC_3) */ - channel@0 { - reg = <0>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 (ADC_4 - ADC_1) */ - channel@1 { - reg = <1>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 (ADC_3 - ADC_1) */ - channel@2 { - reg = <2>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 (ADC_2 - ADC_1) */ - channel@3 { - reg = <3>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 ADC_4 */ - channel@4 { - reg = <4>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 ADC_3 */ - channel@5 { - reg = <5>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 ADC_2 */ - channel@6 { - reg = <6>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 ADC_1 */ - channel@7 { - reg = <7>; - ti,datarate = <4>; - ti,gain = <2>; - }; - }; - - eeprom@50 { - compatible = "st,24c02"; - pagesize = <16>; - reg = <0x50>; - }; -}; - -/* Verdin I2C_2_DSI */ -&i2c2 { - clock-frequency = <10000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "disabled"; -}; - -/* Verdin I2C_3_HDMI N/A */ - -/* Verdin I2C_4_CSI */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -/* Verdin I2C_1 */ -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - - gpio_expander_21: gpio-expander@21 { - compatible = "nxp,pcal6416"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x21>; - vcc-supply = <®_3p3v>; - status = "disabled"; - }; - - lvds_ti_sn65dsi84: bridge@2c { - compatible = "ti,sn65dsi84"; - /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ - /* Verdin GPIO_10_DSI (SODIMM 21) */ - enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_10_dsi>; - reg = <0x2c>; - status = "disabled"; - }; - - /* Current measurement into module VCC */ - hwmon: hwmon@40 { - compatible = "ti,ina219"; - reg = <0x40>; - shunt-resistor = <10000>; - status = "disabled"; - }; - - hdmi_lontium_lt8912: hdmi@48 { - compatible = "lontium,lt8912b"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_10_dsi>; - reg = <0x48>; - /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ - /* Verdin GPIO_10_DSI (SODIMM 21) */ - reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; - status = "disabled"; - }; - - atmel_mxt_ts: touch@4a { - compatible = "atmel,maxtouch"; - /* - * Verdin GPIO_9_DSI - * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) - */ - interrupt-parent = <&gpio3>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; - reg = <0x4a>; - /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ - reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - status = "disabled"; - }; - - /* Temperature sensor on carrier board */ - hwmon_temp: sensor@4f { - compatible = "ti,tmp75c"; - reg = <0x4f>; - status = "disabled"; - }; - - /* EEPROM on display adapter (MIPI DSI Display Adapter) */ - eeprom_display_adapter: eeprom@50 { - compatible = "st,24c02"; - pagesize = <16>; - reg = <0x50>; - status = "disabled"; - }; - - /* EEPROM on carrier board */ - eeprom_carrier_board: eeprom@57 { - compatible = "st,24c02"; - pagesize = <16>; - reg = <0x57>; - status = "disabled"; - }; -}; - -/* Verdin PCIE_1 */ -&pcie0 { - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - assigned-clock-rates = <10000000>, <250000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - /* PCIE_1_RESET# (SODIMM 244) */ - reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; -}; - -&pcie_phy { - clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; - clock-names = "ref"; - fsl,clkreq-unsupported; - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; - fsl,tx-deemph-gen1 = <0x2d>; - fsl,tx-deemph-gen2 = <0xf>; -}; - -/* Verdin PWM_3_DSI */ -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_1>; - #pwm-cells = <3>; -}; - -/* Verdin PWM_1 */ -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_2>; - #pwm-cells = <3>; -}; - -/* Verdin PWM_2 */ -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_3>; - #pwm-cells = <3>; -}; - -/* Verdin I2S_1 */ -&sai2 { - #sound-dai-cells = <0>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - assigned-clocks = <&clk IMX8MM_CLK_SAI2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -/* Verdin UART_3, used as the Linux console */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -/* Verdin UART_1 */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; -}; - -/* Verdin UART_2 */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; -}; - -/* - * Verdin UART_4 - * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS - */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; -}; - -/* Verdin USB_1 */ -&usbotg1 { - adp-disable; - dr_mode = "otg"; - hnp-disable; - samsung,picophy-dc-vol-level-adjust = <7>; - samsung,picophy-pre-emp-curr-control = <3>; - srp-disable; - vbus-supply = <®_usb_otg1_vbus>; -}; - -/* Verdin USB_2 */ -&usbotg2 { - dr_mode = "host"; - samsung,picophy-dc-vol-level-adjust = <7>; - samsung,picophy-pre-emp-curr-control = <3>; - vbus-supply = <®_usb_otg2_vbus>; -}; - -&usbphynop1 { - vcc-supply = <®_vdd_3v3>; -}; - -&usbphynop2 { - power-domains = <&pgc_otg2>; - vcc-supply = <®_vdd_3v3>; -}; - -/* On-module eMMC */ -&usdhc1 { - bus-width = <8>; - keep-power-in-suspend; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - status = "okay"; -}; - -/* Verdin SD_1 */ -&usdhc2 { - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; - vmmc-supply = <®_usdhc2_vmmc>; -}; - -&wdog1 { - fsl,ext-reset-output; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, - <&pinctrl_gpio3>, <&pinctrl_gpio4>, - <&pinctrl_gpio7>, <&pinctrl_gpio8>, - <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, - <&pinctrl_pmic_tpm_ena>; - - pinctrl_can1_int: can1intgrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */ - }; - - pinctrl_can2_int: can2intgrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */ - }; - - pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { - fsl,pins = - <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */ - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = - <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */ - <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */ - <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */ - <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */ - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */ - <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */ - <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */ - <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */ - <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */ - }; - - pinctrl_fec1: fec1grp { - fsl,pins = - <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, - <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, - <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, - <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, - <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, - <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, - <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, - <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, - <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>, - <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>, - <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>, - <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>, - <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>, - <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>, - <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>; - }; - - pinctrl_fec1_sleep: fec1-sleepgrp { - fsl,pins = - <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, - <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, - <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, - <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, - <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, - <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, - <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, - <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, - <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>, - <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>, - <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>, - <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>, - <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>, - <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>, - <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>; - }; - - pinctrl_flexspi0: flexspi0grp { - fsl,pins = - <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */ - <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */ - <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */ - <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */ - <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */ - <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */ - <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */ - <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */ - }; - - pinctrl_gpio1: gpio1grp { - fsl,pins = - <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */ - }; - - pinctrl_gpio2: gpio2grp { - fsl,pins = - <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */ - }; - - pinctrl_gpio3: gpio3grp { - fsl,pins = - <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */ - }; - - pinctrl_gpio4: gpio4grp { - fsl,pins = - <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */ - }; - - pinctrl_gpio5: gpio5grp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */ - }; - - pinctrl_gpio6: gpio6grp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */ - }; - - pinctrl_gpio7: gpio7grp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */ - }; - - pinctrl_gpio8: gpio8grp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */ - }; - - /* Verdin GPIO_9_DSI (pulled-up as active-low) */ - pinctrl_gpio_9_dsi: gpio9dsigrp { - fsl,pins = - <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */ - }; - - /* Verdin GPIO_10_DSI (pulled-up as active-low) */ - pinctrl_gpio_10_dsi: gpio10dsigrp { - fsl,pins = - <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */ - }; - - pinctrl_gpio_hog1: gpiohog1grp { - fsl,pins = - <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */ - <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */ - <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */ - <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */ - <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */ - <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */ - <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */ - <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */ - <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */ - <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */ - <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */ - <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */ - <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */ - <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */ - <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */ - }; - - pinctrl_gpio_hog2: gpiohog2grp { - fsl,pins = - <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */ - }; - - pinctrl_gpio_hog3: gpiohog3grp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */ - <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */ - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = - <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */ - }; - - /* On-module I2C */ - pinctrl_i2c1: i2c1grp { - fsl,pins = - <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */ - <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */ - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = - <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */ - <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */ - }; - - /* Verdin I2C_4_CSI */ - pinctrl_i2c2: i2c2grp { - fsl,pins = - <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */ - <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */ - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = - <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */ - <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */ - }; - - /* Verdin I2C_2_DSI */ - pinctrl_i2c3: i2c3grp { - fsl,pins = - <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */ - <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */ - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = - <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */ - <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */ - }; - - /* Verdin I2C_1 */ - pinctrl_i2c4: i2c4grp { - fsl,pins = - <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */ - <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */ - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = - <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */ - <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */ - }; - - /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ - pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { - fsl,pins = - <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */ - }; - - /* Verdin I2S_2_D_OUT shared with SAI5 */ - pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { - fsl,pins = - <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */ - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = - <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */ - /* PMIC_EN_PCIe_CLK, unused */ - <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */ - }; - - /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ - pinctrl_pwm_1: pwm1grp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */ - }; - - pinctrl_pwm_2: pwm2grp { - fsl,pins = - <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */ - }; - - pinctrl_pwm_3: pwm3grp { - fsl,pins = - <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */ - }; - - /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ - pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */ - }; - - pinctrl_reg_eth: regethgrp { - fsl,pins = - <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */ - }; - - pinctrl_reg_usb1_en: regusb1engrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */ - }; - - pinctrl_reg_usb2_en: regusb2engrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */ - }; - - pinctrl_sai2: sai2grp { - fsl,pins = - <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */ - <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */ - <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */ - <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */ - <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */ - }; - - pinctrl_sai5: sai5grp { - fsl,pins = - <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */ - <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */ - <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */ - <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */ - }; - - /* control signal for optional ATTPM20P or SE050 */ - pinctrl_pmic_tpm_ena: pmictpmenagrp { - fsl,pins = - <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */ - }; - - pinctrl_tsp: tspgrp { - fsl,pins = - <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */ - <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */ - <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */ - <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */ - <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */ - }; - - pinctrl_uart1: uart1grp { - fsl,pins = - <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */ - <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */ - }; - - pinctrl_uart2: uart2grp { - fsl,pins = - <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */ - <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */ - <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */ - <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */ - }; - - pinctrl_uart3: uart3grp { - fsl,pins = - <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */ - <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */ - <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */ - <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */ - }; - - pinctrl_uart4: uart4grp { - fsl,pins = - <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */ - <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */ - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = - <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>, - <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>, - <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>, - <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>, - <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>, - <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>, - <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>, - <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>, - <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>, - <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>, - <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, - <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = - <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>, - <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>, - <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>, - <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>, - <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>, - <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>, - <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>, - <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>, - <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>, - <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>, - <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, - <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = - <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>, - <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>, - <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>, - <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>, - <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>, - <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>, - <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>, - <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>, - <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>, - <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>, - <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, - <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>; - }; - - pinctrl_usdhc2_cd: usdhc2cdgrp { - fsl,pins = - <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */ - }; - - pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { - fsl,pins = - <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */ - }; - - pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { - fsl,pins = - <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */ - }; - - /* - * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the - * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. - */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, - <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */ - <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */ - <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */ - <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */ - <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */ - <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */ - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, - <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>, - <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>, - <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>, - <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>, - <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>, - <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, - <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>, - <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>, - <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>, - <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>, - <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>, - <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>; - }; - - /* Avoid backfeeding with removed card power */ - pinctrl_usdhc2_sleep: usdhc2slpgrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>, - <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>, - <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>, - <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>, - <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>, - <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>, - <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>; - }; - - /* - * On-module Wi-Fi/BT or type specific SDHC interface - * (e.g. on X52 extension slot of Verdin Development Board) - */ - pinctrl_usdhc3: usdhc3grp { - fsl,pins = - <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>, - <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>, - <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>, - <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>, - <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>, - <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = - <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>, - <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>, - <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>, - <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>, - <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>, - <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = - <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>, - <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>, - <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>, - <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>, - <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>, - <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */ - }; - - pinctrl_wifi_ctrl: wifictrlgrp { - fsl,pins = - <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */ - <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */ - <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */ - }; - - pinctrl_wifi_i2s: bti2sgrp { - fsl,pins = - <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */ - <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */ - <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */ - <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */ - }; - - pinctrl_wifi_pwr_en: wifipwrengrp { - fsl,pins = - <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */ - }; -}; diff --git a/arch/arm/dts/imx8mn-beacon-kit.dts b/arch/arm/dts/imx8mn-beacon-kit.dts deleted file mode 100644 index 1392ce02587..00000000000 --- a/arch/arm/dts/imx8mn-beacon-kit.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2020 Compass Electronics Group, LLC - */ - -/dts-v1/; - -#include "imx8mn.dtsi" -#include "imx8mn-beacon-som.dtsi" -#include "imx8mn-beacon-baseboard.dtsi" - -/ { - model = "Beacon EmbeddedWorks i.MX8M Nano Development Kit"; - compatible = "beacon,imx8mn-beacon-kit", "fsl,imx8mn"; - - chosen { - stdout-path = &uart2; - }; -}; diff --git a/arch/arm/dts/imx8mn-beacon-som.dtsi b/arch/arm/dts/imx8mn-beacon-som.dtsi deleted file mode 100644 index 1133cded9be..00000000000 --- a/arch/arm/dts/imx8mn-beacon-som.dtsi +++ /dev/null @@ -1,472 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2020 Compass Electronics Group, LLC - */ - -/ { - aliases { - rtc0 = &rtc; - rtc1 = &snvs_rtc; - spi0 = &flexspi; - }; - - usdhc1_pwrseq: usdhc1_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_gpio>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - clocks = <&osc_32k>; - clock-names = "ext_clock"; - post-power-on-delay-ms = <80>; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -/* DDR controller is running LPDDR at 800MHz which requires 0.95V */ -&a53_opp_table { - opp-1200000000 { - opp-microvolt = <950000>; - }; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-800M { - opp-hz = /bits/ 64 <800000000>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - phy-supply = <&buck6_reg>; - phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi>; - status = "okay"; - - flash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - eeprom@50 { - compatible = "microchip,24c64", "atmel,24c64"; - pagesize = <32>; - read-only; /* Manufacturing EEPROM programmed at factory */ - reg = <0x50>; - }; - - rtc: rtc@51 { - compatible = "nxp,pcf85263"; - reg = <0x51>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MN_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; - clocks = <&osc_32k>; - max-speed = <4000000>; - clock-names = "extclk"; - }; -}; - -&usdhc1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - vmmc-supply = <&buck4_reg>; - vqmmc-supply = <&buck5_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - mmc-pwrseq = <&usdhc1_pwrseq>; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan>; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_flexspi: flexspigrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 - MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 - MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 - MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 - MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 - MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 - MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 - >; - }; - - pinctrl_usdhc1_gpio: usdhc1gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; - - pinctrl_wlan: wlangrp { - fsl,pins = < - MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 - >; - }; -}; diff --git a/arch/arm/dts/imx8mn-ddr4-evk.dts b/arch/arm/dts/imx8mn-ddr4-evk.dts deleted file mode 100644 index d8ce217c601..00000000000 --- a/arch/arm/dts/imx8mn-ddr4-evk.dts +++ /dev/null @@ -1,160 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -/dts-v1/; - -#include "imx8mn.dtsi" -#include "imx8mn-evk.dtsi" - -/ { - model = "NXP i.MX8MNano DDR4 EVK board"; - compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn"; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-600M { - opp-hz = /bits/ 64 <600000000>; - }; - }; -}; - -&i2c1 { - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - }; - - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx8mn-evk.dts b/arch/arm/dts/imx8mn-evk.dts deleted file mode 100644 index 4eb467df5ba..00000000000 --- a/arch/arm/dts/imx8mn-evk.dts +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -/dts-v1/; - -#include "imx8mn.dtsi" -#include "imx8mn-evk.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "NXP i.MX8MNano EVK board"; - compatible = "fsl,imx8mn-evk", "fsl,imx8mn"; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&i2c1 { - pmic: pmic@25 { - compatible = "nxp,pca9450b"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - regulators { - buck1: BUCK1{ - regulator-name = "VDD_SOC"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <950000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "VDD_ARM_0V9"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - buck4: BUCK4{ - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5{ - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "NVCC_DRAM_1V1"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "NVCC_SNVS_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-name = "VDD_SNVS_0V8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "VDDA_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "VDD_PHY_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "NVCC_SD2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx8mn-venice-gw7902.dts b/arch/arm/dts/imx8mn-venice-gw7902.dts deleted file mode 100644 index 97582db71ca..00000000000 --- a/arch/arm/dts/imx8mn-venice-gw7902.dts +++ /dev/null @@ -1,980 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2021 Gateworks Corporation - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/net/ti-dp83867.h> - -#include "imx8mn.dtsi" - -/ { - model = "Gateworks Venice GW7902 i.MX8MN board"; - compatible = "gw,imx8mn-gw7902", "fsl,imx8mn"; - - aliases { - usb0 = &usbotg1; - }; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - can20m: can20m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <20000000>; - clock-output-names = "can20m"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-user-pb { - label = "user_pb"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = <BTN_0>; - }; - - key-user-pb1x { - label = "user_pb1x"; - linux,code = <BTN_1>; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key_erased"; - linux,code = <BTN_2>; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - key-eeprom-wp { - label = "eeprom_wp"; - linux,code = <BTN_3>; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - key-tamper { - label = "tamper"; - linux,code = <BTN_4>; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = <BTN_5>; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel1"; - gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel2"; - gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-2 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel3"; - gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-3 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel4"; - gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-4 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel5"; - gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb1_vbus: regulator-usb1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1>; - regulator-name = "usb_usb1_vbus"; - gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_wifi: regulator-wifi { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wl>; - regulator-name = "wifi"; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&can20m>; - interrupt-parent = <&gpio2>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - spi-max-frequency = <10000000>; - }; -}; - -&disp_blk_ctrl { - status = "disabled"; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - local-mac-address = [00 00 00 00 00 00]; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; - }; -}; - -&gpio1 { - gpio-line-names = "", "", "", "", "", "", "", "", - "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = "", "", "", "", "", "", "", "", - "uart2_en#", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485", - "", "uart1_term", "uart1_half", "app_gpio2", - "mipi_gpio1", "", "", ""; -}; - -&gpio5 { - gpio-line-names = "", "", "", "mipi_gpio4", - "mipi_gpio3", "mipi_gpio2", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpu { - status = "disabled"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - pinctrl-0 = <&pinctrl_gsc>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <1>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vin"; - gw,voltage-divider-ohms = <22100 1000>; - gw,voltage-offset-microvolt = <700000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vin_4p0"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_0p9"; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_soc"; - }; - - channel@8e { - gw,mode = <2>; - reg = <0x8e>; - label = "vdd_arm"; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_1p8"; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_dram"; - }; - - channel@98 { - gw,mode = <2>; - reg = <0x98>; - label = "vdd_1p0"; - }; - - channel@9a { - gw,mode = <2>; - reg = <0x9a>; - label = "vdd_2p5"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@9c { - gw,mode = <2>; - reg = <0x9c>; - label = "vdd_5p0"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - }; - - gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - /* vdd_soc: 0.805-0.900V (typ=0.8V) */ - BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - /* vdd_arm: 0.805-1.0V (typ=0.9V) */ - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ - BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_3p3 */ - BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_1p8 */ - BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_dram */ - BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - /* nvcc_snvs_1p8 */ - LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_snvs_0p8 */ - LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdda_1p8 */ - LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - accelerometer@19 { - compatible = "st,lis2de12"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio1>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -/* off-board header */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -/* off-board header */ -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&pgc_gpumix { - status = "disabled"; -}; - -/* off-board header */ -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MN_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -/* RS232/RS485/RS422 selectable */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; - status = "okay"; -}; - -/* RS232 console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* bluetooth HCI */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; - rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - }; -}; - -/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "host"; - vbus-supply = <®_usb1_vbus>; - disable-over-current; - status = "okay"; -}; - -/* SDIO WiFi */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wifi>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ - MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ - MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ - MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ - MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ - MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ - MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ - MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ - MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ - MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ - MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */ - MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */ - MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ - MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ - >; - }; - - pinctrl_gsc: gscgrp { - fsl,pins = < - MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 - MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 - MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 - MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 - MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 - MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 - MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 - MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */ - >; - }; - - pinctrl_reg_wl: regwlgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */ - >; - }; - - pinctrl_reg_usb1: regusb1grp { - fsl,pins = < - MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - >; - }; - - pinctrl_spi1: spi1grp { - fsl,pins = < - MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 - MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 - MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 - MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 - MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */ - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 - MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 - MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 - MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart1_gpio: uart1gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */ - MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */ - MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3_gpio: uart3_gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */ - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */ - MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */ - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 - MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 - MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mn-venice.dts b/arch/arm/dts/imx8mn-venice.dts deleted file mode 100644 index 9e31b37f249..00000000000 --- a/arch/arm/dts/imx8mn-venice.dts +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2022 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mn.dtsi" - -/ { - model = "Gateworks Venice i.MX8MM board"; - compatible = "gw,imx8mn-venice", "fsl,imx8mn"; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; - pagesize = <32>; - }; -}; - -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1grp-gpio-grp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-beacon-kit.dts b/arch/arm/dts/imx8mp-beacon-kit.dts deleted file mode 100644 index a08057410bd..00000000000 --- a/arch/arm/dts/imx8mp-beacon-kit.dts +++ /dev/null @@ -1,783 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks - */ - -/dts-v1/; - -#include <dt-bindings/usb/pd.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> -#include "imx8mp.dtsi" -#include "imx8mp-beacon-som.dtsi" - -/ { - model = "Beacon EmbeddedWorks i.MX8MPlus Development kit"; - compatible = "beacon,imx8mp-beacon-kit", "fsl,imx8mp"; - - aliases { - ethernet0 = &eqos; - ethernet1 = &fec; - }; - - chosen { - stdout-path = &uart2; - }; - - clk_xtal25: clock-xtal25 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hs_ep: endpoint { - remote-endpoint = <&usb3_hs_ep>; - }; - }; - port@1 { - reg = <1>; - - ss_ep: endpoint { - remote-endpoint = <&hd3ss3220_in_ep>; - }; - }; - }; - }; - - dmic_codec: dmic-codec { - compatible = "dmic-codec"; - num-channels = <1>; - #sound-dai-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - button-0 { - label = "btn0"; - linux,code = <BTN_0>; - gpios = <&pca6416_1 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - wakeup-source; - }; - - button-1 { - label = "btn1"; - linux,code = <BTN_1>; - gpios = <&pca6416_1 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - wakeup-source; - }; - - button-2 { - label = "btn2"; - linux,code = <BTN_2>; - gpios = <&pca6416_1 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - wakeup-source; - }; - - button-3 { - label = "btn3"; - linux,code = <BTN_3>; - gpios = <&pca6416_1 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - wakeup-source; - }; - }; - - bridge-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7535_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led3>; - - led-0 { - label = "gen_led0"; - gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-1 { - label = "gen_led1"; - gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-2 { - label = "gen_led2"; - gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-3 { - label = "heartbeat"; - gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_audio: regulator-wm8962 { - compatible = "regulator-fixed"; - regulator-name = "3v3_aud"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - off-on-delay-us = <20000>; - }; - - reg_usb1_host_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1_host_vbus"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound-adv7535 { - compatible = "simple-audio-card"; - simple-audio-card,name = "sound-adv7535"; - simple-audio-card,format = "i2s"; - - simple-audio-card,cpu { - sound-dai = <&sai5>; - system-clock-direction-out; - }; - - simple-audio-card,codec { - sound-dai = <&adv_bridge>; - }; - }; - - sound-dmic { - compatible = "simple-audio-card"; - simple-audio-card,name = "sound-pdm"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - - dailink_master: simple-audio-card,cpu { - sound-dai = <&micfil>; - }; - - simple-audio-card,codec { - sound-dai = <&dmic_codec>; - }; - }; - - sound-wm8962 { - compatible = "simple-audio-card"; - simple-audio-card,name = "wm8962"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = "Headphone", "Headphones", - "Microphone", "Headset Mic", - "Speaker", "Speaker"; - simple-audio-card,routing = "Headphones", "HPOUTL", - "Headphones", "HPOUTR", - "Speaker", "SPKOUTL", - "Speaker", "SPKOUTR", - "Headset Mic", "MICBIAS", - "IN3R", "Headset Mic"; - - simple-audio-card,cpu { - sound-dai = <&sai3>; - }; - - simple-audio-card,codec { - sound-dai = <&wm8962>; - clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; - frame-master; - bitclock-master; - }; - }; -}; - -&audio_blk_ctrl { - assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>; - assigned-clock-rates = <393216000>, <135475200>; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; - - tpm: tpm@0 { - compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpm>; - reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; - spi-max-frequency = <18500000>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@3 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; - reg = <3>; - reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <150000>; - interrupt-parent = <&gpio4>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&gpio2 { - usb-mux-hog { - gpio-hog; - gpios = <20 0>; - output-low; - line-name = "USB-C Mux En"; - }; -}; - -&i2c2 { - clock-frequency = <384000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pca6416_3: gpio@20 { - compatible = "nxp,pcal6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - adv_bridge: hdmi@3d { - compatible = "adi,adv7535"; - reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; - reg-names = "main", "cec", "edid", "packet"; - adi,dsi-lanes = <4>; - #sound-dai-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adv7535_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - - port@1 { - reg = <1>; - - adv7535_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; - - pcieclk: clock-generator@68 { - compatible = "renesas,9fgv0241"; - reg = <0x68>; - clocks = <&clk_xtal25>; - #clock-cells = <1>; - }; -}; - -&i2c3 { - /* Connected to USB Hub */ - usb-typec@52 { - compatible = "nxp,ptn5110"; - reg = <0x52>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec>; - interrupt-parent = <&gpio4>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "source"; - data-role = "host"; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - }; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clock-frequency = <384000>; - status = "okay"; - - wm8962: audio-codec@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wm8962>; - clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; - assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; - assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; - assigned-clock-rates = <22576000>; - DCVDD-supply = <®_audio>; - DBVDD-supply = <®_audio>; - AVDD-supply = <®_audio>; - CPVDD-supply = <®_audio>; - MICVDD-supply = <®_audio>; - PLLVDD-supply = <®_audio>; - SPKVDD1-supply = <®_audio>; - SPKVDD2-supply = <®_audio>; - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0000 /* 2:FN_DMICCLK */ - 0x0000 /* 3:Default */ - 0x0000 /* 4:FN_DMICCDAT */ - 0x0000 /* 5:Default */ - >; - #sound-dai-cells = <0>; - }; - - pca6416: gpio@20 { - compatible = "nxp,pcal6416"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcal6414>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pca6416_1: gpio@21 { - compatible = "nxp,pcal6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - - usb-hub-hog { - gpio-hog; - gpios = <7 0>; - output-low; - line-name = "USB Hub Enable"; - }; - }; - - usb-typec@47 { - compatible = "ti,hd3ss3220"; - reg = <0x47>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hd3ss3220>; - interrupt-parent = <&gpio4>; - interrupts = <19 IRQ_TYPE_LEVEL_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hd3ss3220_in_ep: endpoint { - remote-endpoint = <&ss_ep>; - }; - }; - - port@1 { - reg = <1>; - - hd3ss3220_out_ep: endpoint { - remote-endpoint = <&usb3_role_switch>; - }; - }; - }; - }; -}; - -&lcdif1 { - status = "okay"; -}; - -&micfil { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pdm>; - assigned-clocks = <&clk IMX8MP_CLK_PDM>; - assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; - assigned-clock-rates = <49152000>; - status = "okay"; -}; - -&mipi_dsi { - samsung,esc-clock-frequency = <10000000>; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - dsi_out: endpoint { - remote-endpoint = <&adv7535_in>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pcie_phy { - fsl,clkreq-unsupported; - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - clocks = <&pcieclk 1>; - clock-names = "ref"; - status = "okay"; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MP_CLK_SAI3>, - <&clk IMX8MP_AUDIO_PLL2> ; - assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; - assigned-clock-rates = <12288000>, <361267200>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&sai5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai5>; - assigned-clocks = <&clk IMX8MP_CLK_SAI5>; - assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; - assigned-clock-rates = <12288000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clk IMX8MP_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usb3_hs_ep: endpoint { - remote-endpoint = <&hs_ep>; - }; - }; - port@1 { - reg = <1>; - usb3_role_switch: endpoint { - remote-endpoint = <&hd3ss3220_out_ep>; - }; - }; - }; -}; - -&usb3_phy0 { - vbus-supply = <®_usb1_host_vbus>; - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 - MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x140 - MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x10 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 - MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 - >; - }; - - pinctrl_hd3ss3220: hd3ss3220grp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x140 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 - MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 - >; - }; - - pinctrl_led3: led3grp { - fsl,pins = < - MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x41 - >; - }; - - pinctrl_pcal6414: pcal6414-gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x10 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 /* PCIe_nDIS */ - MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x10 /* PCIe_nRST */ - >; - }; - - pinctrl_pdm: pdmgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 - MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 - MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 - MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 - MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 - MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 - >; - }; - - pinctrl_sai5: sai5grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0xd6 - MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0xd6 - MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0xd6 - >; - }; - - pinctrl_tpm: tpmgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* Reset */ - MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1d6 /* IRQ */ - >; - }; - - pinctrl_typec: typec1grp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0xc4 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 - MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 - MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 - MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; - - pinctrl_wm8962: wm8962grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x59 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-beacon-som.dtsi b/arch/arm/dts/imx8mp-beacon-som.dtsi deleted file mode 100644 index 8be251b6937..00000000000 --- a/arch/arm/dts/imx8mp-beacon-som.dtsi +++ /dev/null @@ -1,487 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 LogicPD, Inc. dba Beacon EmbeddedWorks - */ - -/ { - aliases { - rtc0 = &rtc; - rtc1 = &snvs_rtc; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0xc0000000>, - <0x1 0x00000000 0 0xc0000000>; - }; - - reg_wl_bt: regulator-wifi-bt { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wl_bt>; - regulator-name = "wl-bt-pow-dwn"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; - startup-delay-us = <70000>; - regulator-always-on; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - snps,force_thresh_dma_mode; - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@3 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; - reg = <3>; - reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio1>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - }; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <5>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,priority = <0x1>; - snps,map-to-dma-channel = <0>; - }; - - queue1 { - snps,dcb-algorithm; - snps,priority = <0x2>; - snps,map-to-dma-channel = <1>; - }; - - queue2 { - snps,dcb-algorithm; - snps,priority = <0x4>; - snps,map-to-dma-channel = <2>; - }; - - queue3 { - snps,dcb-algorithm; - snps,priority = <0x8>; - snps,map-to-dma-channel = <3>; - }; - - queue4 { - snps,dcb-algorithm; - snps,priority = <0xf0>; - snps,map-to-dma-channel = <4>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <5>; - snps,tx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,priority = <0x2>; - }; - - queue2 { - snps,dcb-algorithm; - snps,priority = <0x4>; - }; - - queue3 { - snps,dcb-algorithm; - snps,priority = <0x8>; - }; - - queue4 { - snps,dcb-algorithm; - snps,priority = <0xf0>; - }; - }; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; - status = "okay"; - - flash0: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <384000>; - status = "okay"; - - pmic@25 { - compatible = "nxp,pca9450c"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - regulators { - buck1: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - buck4: BUCK4 { - regulator-name = "BUCK4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5 { - regulator-name = "BUCK5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <384000>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - read-only; /* Manufacturing EEPROM programmed at factory */ - }; - - rtc: rtc@51 { - compatible = "nxp,pcf85263"; - reg = <0x51>; - }; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MP_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "nxp,88w8997-bt"; - }; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <4>; - vmmc-supply = <®_wl_bt>; - cap-sd-highspeed; - sd-uhs-sdr50; - sd-uhs-sdr104; - keep-power-in-suspend; - wakeup-source; - non-removable; - cap-power-off-card; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - mwifiex: wifi@1 { - compatible = "marvell,sd8997"; - reg = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan>; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 - MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10 - >; - }; - - pinctrl_flexspi0: flexspi0grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 - MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 - MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 - MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 - MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 - MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 - >; - }; - - pinctrl_reg_wl_bt: reg-wl-btgrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 - MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 - >; - }; - - pinctrl_wlan: wlangrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x140 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts deleted file mode 100644 index 9f1469db554..00000000000 --- a/arch/arm/dts/imx8mp-evk.dts +++ /dev/null @@ -1,684 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -/dts-v1/; - -#include <dt-bindings/phy/phy-imx8-pcie.h> -#include "imx8mp.dtsi" - -/ { - model = "NXP i.MX8MPlus EVK board"; - compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; - - chosen { - stdout-path = &uart2; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - status { - label = "yellow:status"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0xc0000000>, - <0x1 0x00000000 0 0xc0000000>; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - regulator-name = "can1-stby"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - regulator-name = "can2-stby"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_pcie0: regulator-pcie { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0_reg>; - regulator-name = "MPCIE_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&A53_0 { - cpu-supply = <®_arm>; -}; - -&A53_1 { - cpu-supply = <®_arm>; -}; - -&A53_2 { - cpu-supply = <®_arm>; -}; - -&A53_3 { - cpu-supply = <®_arm>; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - snps,force_thresh_dma_mode; - snps,mtl-tx-config = <&mtl_tx_setup>; - snps,mtl-rx-config = <&mtl_rx_setup>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - eee-broken-1000t; - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - realtek,clkout-disable; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <5>; - snps,tx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,priority = <0x2>; - }; - - queue2 { - snps,dcb-algorithm; - snps,priority = <0x4>; - }; - - queue3 { - snps,dcb-algorithm; - snps,priority = <0x8>; - }; - - queue4 { - snps,dcb-algorithm; - snps,priority = <0xf0>; - }; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <5>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,priority = <0x1>; - snps,map-to-dma-channel = <0>; - }; - - queue1 { - snps,dcb-algorithm; - snps,priority = <0x2>; - snps,map-to-dma-channel = <1>; - }; - - queue2 { - snps,dcb-algorithm; - snps,priority = <0x4>; - snps,map-to-dma-channel = <2>; - }; - - queue3 { - snps,dcb-algorithm; - snps,priority = <0x8>; - snps,map-to-dma-channel = <3>; - }; - - queue4 { - snps,dcb-algorithm; - snps,priority = <0xf0>; - snps,map-to-dma-channel = <4>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - eee-broken-1000t; - reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - realtek,clkout-disable; - }; - }; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_stby>; - status = "disabled";/* can2 pin conflict with pdm */ -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@25 { - compatible = "nxp,pca9450c"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - regulators { - BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - reg_arm: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1025000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - BUCK4 { - regulator-name = "BUCK4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3600000>; - regulator-boot-on; - regulator-always-on; - }; - - BUCK5 { - regulator-name = "BUCK5"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - regulator-boot-on; - regulator-always-on; - }; - - BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <1045000>; - regulator-max-microvolt = <1155000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <1890000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca6416_int>; - interrupt-parent = <&gpio1>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - gpio-line-names = "EXT_PWREN1", - "EXT_PWREN2", - "CAN1/I2C5_SEL", - "PDM/CAN2_SEL", - "FAN_EN", - "PWR_MEAS_IO1", - "PWR_MEAS_IO2", - "EXP_P0_7", - "EXP_P1_0", - "EXP_P1_1", - "EXP_P1_2", - "EXP_P1_3", - "EXP_P1_4", - "EXP_P1_5", - "EXP_P1_6", - "EXP_P1_7"; - }; -}; - -/* I2C on expansion connector J22. */ -&i2c5 { - clock-frequency = <100000>; /* Lower clock speed for external bus. */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c5>; - status = "disabled"; /* can1 pins conflict with i2c5 */ - - /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions: - * LOW: CAN1 (default, pull-down) - * HIGH: I2C5 - * You need to set it to high to enable I2C5 (for example, add gpio-hog - * in pca6416 node). - */ -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, - <&clk IMX8MP_CLK_PCIE_ROOT>, - <&clk IMX8MP_CLK_HSIO_AXI>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; - assigned-clock-rates = <10000000>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; - vpcie-supply = <®_pcie0>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { - /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&usb_dwc3_1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; -}; - -&usdhc3 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 - MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 - MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 - MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 - >; - }; - - pinctrl_flexcan1_reg: flexcan1reggrp { - fsl,pins = < - MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ - >; - }; - - pinctrl_flexcan2_reg: flexcan2reggrp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_i2c5: i2c5grp { - fsl,pins = < - MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 - MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */ - MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 - >; - }; - - pinctrl_pcie0_reg: pcie0reggrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 - >; - }; - - pinctrl_pca6416_int: pca6416_int_grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */ - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usb1_vbus: usb1grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw702x.dtsi b/arch/arm/dts/imx8mp-venice-gw702x.dtsi deleted file mode 100644 index 560c68e4da6..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw702x.dtsi +++ /dev/null @@ -1,587 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/net/ti-dp83867.h> - -/ { - aliases { - ethernet0 = &eqos; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-user-pb { - label = "user_pb"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = <BTN_0>; - }; - - key-user-pb1x { - label = "user_pb1x"; - linux,code = <BTN_1>; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key_erased"; - linux,code = <BTN_2>; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - key-eeprom-wp { - label = "eeprom_wp"; - linux,code = <BTN_3>; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - key-tamper { - label = "tamper"; - linux,code = <BTN_4>; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = <BTN_5>; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; -}; - -&A53_0 { - cpu-supply = <&buck3_reg>; -}; - -&A53_1 { - cpu-supply = <&buck3_reg>; -}; - -&A53_2 { - cpu-supply = <&buck3_reg>; -}; - -&A53_3 { - cpu-supply = <&buck3_reg>; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - pinctrl-0 = <&pinctrl_ethphy0>; - pinctrl-names = "default"; - reg = <0x0>; - interrupt-parent = <&gpio3>; - interrupts = <16 IRQ_TYPE_EDGE_FALLING>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - pinctrl-0 = <&pinctrl_gsc>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@8 { - gw,mode = <3>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@16 { - gw,mode = <4>; - reg = <0x16>; - label = "fan_tach"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vdd_vin"; - gw,voltage-divider-ohms = <22100 1000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vdd_adc1"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_adc2"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_1p0"; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_1p8"; - }; - - channel@8e { - gw,mode = <2>; - reg = <0x8e>; - label = "vdd_2p5"; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_dram"; - }; - - channel@98 { - gw,mode = <2>; - reg = <0x98>; - label = "vdd_soc"; - }; - - channel@9a { - gw,mode = <2>; - reg = <0x9a>; - label = "vdd_arm"; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - - fan-controller@0 { - compatible = "gw,gsc-fan"; - reg = <0x0a>; - }; - }; - - gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; - - pmic@69 { - compatible = "mps,mp5416"; - reg = <0x69>; - - regulators { - /* vdd_soc */ - buck1 { - regulator-name = "buck1"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* vdd_dram */ - buck2 { - regulator-name = "buck2"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - /* vdd_arm */ - buck3_reg: buck3 { - regulator-name = "buck3"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* vdd_1p8 */ - buck4 { - regulator-name = "buck4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - /* OUT2: nvcc_snvs_1p8 */ - ldo1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - /* OUT3: vdd_1p0 */ - ldo2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* OUT4: vdd_2p5 */ - ldo3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - regulator-boot-on; - }; - - /* OUT5: vdd_3p3 */ - ldo4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -/* off-board header */ -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; - pagesize = <32>; - }; -}; - -/* off-board header */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -/* off-board header */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* off-board header */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* off-board */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - non-removable; - status = "okay"; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 - >; - }; - - pinctrl_ethphy0: ethphy0grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x140 /* RST# */ - MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x150 /* IRQ# */ - >; - }; - - pinctrl_gsc: gscgrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x150 /* IRQ# */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 - MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 - MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi index 5c33f8c9cdc..216a7a0d8d7 100644 --- a/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi @@ -4,6 +4,15 @@ */ #include "imx8mp-venice-gw702x-u-boot.dtsi" +&gpio1 { + tpm_rst { + gpio-hog; + output-high; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "tpm_rst#"; + }; +}; + &gpio4 { dio_1 { gpio-hog; diff --git a/arch/arm/dts/imx8mp-venice-gw71xx-2x.dts b/arch/arm/dts/imx8mp-venice-gw71xx-2x.dts deleted file mode 100644 index 53120fc9cd7..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw71xx-2x.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mp.dtsi" -#include "imx8mp-venice-gw702x.dtsi" -#include "imx8mp-venice-gw71xx.dtsi" - -/ { - model = "Gateworks Venice GW71xx-2x i.MX8MP Development Kit"; - compatible = "gateworks,imx8mp-gw71xx-2x", "fsl,imx8mp"; - - chosen { - stdout-path = &uart2; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw71xx.dtsi b/arch/arm/dts/imx8mp-venice-gw71xx.dtsi deleted file mode 100644 index 86999f52d4b..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw71xx.dtsi +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "dio1", "", "", "dio0", - "", "", "pci_usb_sel", "", - "", "", "", "", - "", "", "", "", - "dio3", "", "dio2", "", - "pci_wdis#", "", "", ""; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - accelerometer@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio4>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* off-board header */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* USB1 Type-C front panel */ -&usb3_0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - fsl,over-current-active-low; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb_dwc3_0 { - /* dual role is implemented but not a full featured OTG */ - adp-disable; - hnp-disable; - srp-disable; - dr_mode = "otg"; - usb-role-switch; - role-switch-default-mode = "peripheral"; - status = "okay"; - - connector { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbcon1>; - compatible = "gpio-usb-b-connector", "usb-b-connector"; - type = "micro"; - label = "Type-C"; - id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - }; -}; - -/* USB2 - MiniPCIe socket */ -&usb3_1 { - fsl,permanently-attached; - fsl,disable-port-power-control; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ - MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ - MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ - MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000146 /* DIO2 */ - MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x40000146 /* DIO3 */ - MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ - MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 - >; - }; - - pinctrl_usb1: usb1grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ - >; - }; - - pinctrl_usbcon1: usbcon1grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 - MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw72xx-2x.dts b/arch/arm/dts/imx8mp-venice-gw72xx-2x.dts deleted file mode 100644 index 255e36f66b0..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw72xx-2x.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mp.dtsi" -#include "imx8mp-venice-gw702x.dtsi" -#include "imx8mp-venice-gw72xx.dtsi" - -/ { - model = "Gateworks Venice GW72xx-2x i.MX8MP Development Kit"; - compatible = "gateworks,imx8mp-gw72xx-2x", "fsl,imx8mp"; - - chosen { - stdout-path = &uart2; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw72xx.dtsi b/arch/arm/dts/imx8mp-venice-gw72xx.dtsi deleted file mode 100644 index 4e726128ccf..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw72xx.dtsi +++ /dev/null @@ -1,378 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_usb1_vbus: regulator-usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_en>; - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb2_vbus: regulator-usb2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2_en>; - compatible = "regulator-fixed"; - regulator-name = "usb2_vbus"; - gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_vmmc>; - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3_SD"; - enable-active-high; - gpio = <&gpio2 19 0>; /* SD2_RESET */ - off-on-delay-us = <12000>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - startup-delay-us = <100>; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, - <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; - tpm@1 { - compatible = "tcg,tpm_tis-spi"; - reg = <0x1>; - spi-max-frequency = <36000000>; - }; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "dio1", "", "", "dio0", - "", "", "pci_usb_sel", "", - "", "", "", "", - "", "", "rs485_en", "rs485_term", - "", "", "", "rs485_half", - "pci_wdis#", "", "", ""; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - accelerometer@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio4>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* off-board header */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* RS232 */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -/* USB1 - OTG */ -&usb3_0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - fsl,over-current-active-low; - status = "okay"; -}; - -&usb3_phy0 { - vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usb_dwc3_0 { - /* dual role is implemented but not a full featured OTG */ - adp-disable; - hnp-disable; - srp-disable; - dr_mode = "otg"; - usb-role-switch; - role-switch-default-mode = "peripheral"; - status = "okay"; - - connector { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbcon1>; - compatible = "gpio-usb-b-connector", "usb-b-connector"; - type = "micro"; - label = "otg"; - id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - }; -}; - -/* USB2 - USB3.0 Hub */ -&usb3_1 { - fsl,permanently-attached; - fsl,disable-port-power-control; - status = "okay"; -}; - -&usb3_phy1 { - vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ - MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ - MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ - MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ - MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ - MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ - MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 - >; - }; - - pinctrl_reg_usb1_en: regusb1grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */ - >; - }; - - pinctrl_usb1: usb1grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ - >; - }; - - pinctrl_usbcon1: usbcon1grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ - >; - }; - - pinctrl_reg_usb2_en: regusb2grp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 - MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 - MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 - MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw73xx-2x.dts b/arch/arm/dts/imx8mp-venice-gw73xx-2x.dts deleted file mode 100644 index 000fd15e0c0..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw73xx-2x.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mp.dtsi" -#include "imx8mp-venice-gw702x.dtsi" -#include "imx8mp-venice-gw73xx.dtsi" - -/ { - model = "Gateworks Venice GW73xx-2x i.MX8MP Development Kit"; - compatible = "gateworks,imx8mp-gw73xx-2x", "fsl,imx8mp"; - - chosen { - stdout-path = &uart2; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw73xx.dtsi b/arch/arm/dts/imx8mp-venice-gw73xx.dtsi deleted file mode 100644 index 88c3c006fa2..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw73xx.dtsi +++ /dev/null @@ -1,421 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_usb1_vbus: regulator-usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_en>; - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb2_vbus: regulator-usb2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2_en>; - compatible = "regulator-fixed"; - regulator-name = "usb2_vbus"; - gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_wifi_en: regulator-wifi-en { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wl>; - compatible = "regulator-fixed"; - regulator-name = "wl"; - gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100>; - enable-active-high; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_vmmc>; - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3_SD"; - enable-active-high; - gpio = <&gpio2 19 0>; /* SD2_RESET */ - off-on-delay-us = <12000>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - startup-delay-us = <100>; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, - <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; - tpm@1 { - compatible = "tcg,tpm_tis-spi"; - reg = <0x1>; - spi-max-frequency = <36000000>; - }; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "dio1", "", "", "dio0", - "", "", "pci_usb_sel", "", - "", "", "", "", - "", "", "rs485_en", "rs485_term", - "", "", "", "rs485_half", - "pci_wdis#", "", "", ""; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - accelerometer@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio4>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* bluetooth HCI */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>; - cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - shutdown-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; - }; -}; - -/* RS232 */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -/* USB1 - OTG */ -&usb3_0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - fsl,over-current-active-low; - status = "okay"; -}; - -&usb3_phy0 { - vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usb_dwc3_0 { - /* dual role is implemented but not a full featured OTG */ - adp-disable; - hnp-disable; - srp-disable; - dr_mode = "otg"; - usb-role-switch; - role-switch-default-mode = "peripheral"; - status = "okay"; - - connector { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbcon1>; - compatible = "gpio-usb-b-connector", "usb-b-connector"; - type = "micro"; - label = "otg"; - id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - }; -}; - -/* USB2 - USB3.0 Hub */ -&usb3_1 { - fsl,permanently-attached; - fsl,disable-port-power-control; - status = "okay"; -}; - -&usb3_phy1 { - vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -/* SDIO WiFi */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wifi_en>; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ - MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ - MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ - MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ - MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ - MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ - >; - }; - - pinctrl_bten: btengrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x146 - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ - MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 - >; - }; - - pinctrl_reg_wl: regwlgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x146 - >; - }; - - pinctrl_reg_usb1_en: regusb1grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */ - >; - }; - - pinctrl_usb1: usb1grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ - >; - }; - - pinctrl_usbcon1: usbcon1grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ - >; - }; - - pinctrl_reg_usb2_en: regusb2grp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 - MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 - MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 - MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x140 - MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 - MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw74xx.dts b/arch/arm/dts/imx8mp-venice-gw74xx.dts deleted file mode 100644 index 7eb28531573..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw74xx.dts +++ /dev/null @@ -1,1125 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2021 Gateworks Corporation - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -#include "imx8mp.dtsi" - -/ { - model = "Gateworks Venice GW74xx i.MX8MP board"; - compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp"; - - aliases { - ethernet0 = &eqos; - ethernet1 = &fec; - ethernet2 = &lan1; - ethernet3 = &lan2; - ethernet4 = &lan3; - ethernet5 = &lan4; - ethernet6 = &lan5; - }; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-0 { - label = "user_pb"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = <BTN_0>; - }; - - key-1 { - label = "user_pb1x"; - linux,code = <BTN_1>; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-2 { - label = "key_erased"; - linux,code = <BTN_2>; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - key-3 { - label = "eeprom_wp"; - linux,code = <BTN_3>; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - key-4 { - label = "tamper"; - linux,code = <BTN_4>; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - key-5 { - label = "switch_hold"; - linux,code = <BTN_5>; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_HEARTBEAT; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - reg_usb2_vbus: regulator-usb2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2>; - compatible = "regulator-fixed"; - regulator-name = "usb_usb2_vbus"; - gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_can1>; - regulator-name = "can1_stby"; - gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_can2>; - regulator-name = "can2_stby"; - gpio = <&gpio5 5 GPIO_ACTIVE_LOW>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_wifi_en: regulator-wifi-en { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wifi>; - compatible = "regulator-fixed"; - regulator-name = "wl"; - gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&A53_0 { - cpu-supply = <®_arm>; -}; - -&A53_1 { - cpu-supply = <®_arm>; -}; - -&A53_2 { - cpu-supply = <®_arm>; -}; - -&A53_3 { - cpu-supply = <®_arm>; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - tpm@0 { - compatible = "tcg,tpm_tis-spi"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x0>; - spi-max-frequency = <36000000>; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; - local-mac-address = [00 00 00 00 00 00]; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_stby>; - status = "okay"; -}; - -&gpio1 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "dio0", "", "dio1", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - "", "", "", "", "", "", "m2_pin20", "", - "", "", "", "", "", "pcie1_wdis#", "pcie3_wdis#", "", - "", "", "pcie2_wdis#", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "m2_rst", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "", "m2_off#", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "m2_wdis#", "", "", "", "", "", - "", "", "", "", "", "", "", "rs485_en"; -}; - -&gpio5 { - gpio-line-names = - "rs485_hd", "rs485_term", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - pinctrl-0 = <&pinctrl_gsc>; - interrupt-parent = <&gpio4>; - interrupts = <20 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@16 { - gw,mode = <4>; - reg = <0x16>; - label = "fan_tach"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vdd_adc1"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vdd_adc2"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_vin"; - gw,voltage-divider-ohms = <22100 1000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_2p5"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_soc"; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_arm"; - }; - - channel@98 { - gw,mode = <2>; - reg = <0x98>; - label = "vdd_1p8"; - }; - - channel@9a { - gw,mode = <2>; - reg = <0x9a>; - label = "vdd_1p2"; - }; - - channel@9c { - gw,mode = <2>; - reg = <0x9c>; - label = "vdd_dram"; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - - fan-controller@a { - compatible = "gw,gsc-fan"; - reg = <0x0a>; - }; - }; - - gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - accelerometer@19 { - compatible = "st,lis2de12"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; - - switch: switch@5f { - compatible = "microchip,ksz9897"; - reg = <0x5f>; - pinctrl-0 = <&pinctrl_ksz>; - interrupt-parent = <&gpio4>; - interrupts = <29 IRQ_TYPE_EDGE_FALLING>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - lan1: port@0 { - reg = <0>; - label = "lan1"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - lan2: port@1 { - reg = <1>; - label = "lan2"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - lan3: port@2 { - reg = <2>; - label = "lan3"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - lan4: port@3 { - reg = <3>; - label = "lan4"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - lan5: port@4 { - reg = <4>; - label = "lan5"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&fec>; - phy-mode = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic@25 { - compatible = "nxp,pca9450c"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio3>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - regulators { - BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - reg_arm: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1025000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - BUCK4 { - regulator-name = "BUCK4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3600000>; - regulator-boot-on; - regulator-always-on; - }; - - BUCK5 { - regulator-name = "BUCK5"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - regulator-boot-on; - regulator-always-on; - }; - - BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <1045000>; - regulator-max-microvolt = <1155000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <1890000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -/* off-board header */ -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, - <&clk IMX8MP_CLK_PCIE_ROOT>, - <&clk IMX8MP_CLK_HSIO_AXI>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; - assigned-clock-rates = <10000000>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; - status = "okay"; -}; - -/* GPS / off-board header */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* RS232 console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* bluetooth HCI */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; - cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -/* USB1 - Type C front panel */ -&usb3_0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - fsl,over-current-active-low; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb_dwc3_0 { - /* dual role is implemented but not a full featured OTG */ - adp-disable; - hnp-disable; - srp-disable; - dr_mode = "otg"; - usb-role-switch; - role-switch-default-mode = "peripheral"; - status = "okay"; - - connector { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbcon1>; - compatible = "gpio-usb-b-connector", "usb-b-connector"; - type = "micro"; - label = "Type-C"; - id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; -}; - -/* USB2 - USB3.0 Hub */ -&usb3_phy1 { - vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -&usb3_1 { - fsl,permanently-attached; - fsl,disable-port-power-control; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -/* SDIO WiFi */ -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wifi_en>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wifi@0 { - compatible = "cypress,cyw4373-fmac"; - reg = <0>; - }; -}; - -/* eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */ - MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */ - MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40000040 /* M2SKT_OFF# */ - MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */ - MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40000040 /* M2SKT_PIN20 */ - MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000040 /* M2SKT_PIN22 */ - MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x40000150 /* PCIE1_WDIS# */ - MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ - MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ - MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ - MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ - MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ - MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150 - >; - }; - - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 - MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */ - MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */ - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 - MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140 - MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 - MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 - MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 - >; - }; - - pinctrl_gsc: gscgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 - MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3 - MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3 - MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 - MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 - >; - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3 - MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3 - >; - }; - - pinctrl_ksz: kszgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */ - MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */ - >; - }; - - pinctrl_gpio_leds: ledgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10 - MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10 - >; - }; - - pinctrl_pcie0: pciegrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x106 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 - >; - }; - - pinctrl_reg_can1: regcan1grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154 - >; - }; - - pinctrl_reg_can2: regcan2grp { - fsl,pins = < - MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 - >; - }; - - pinctrl_reg_usb2: regusb2grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140 - >; - }; - - pinctrl_reg_wifi: regwifigrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110 - >; - }; - - pinctrl_spi1: spi1grp { - fsl,pins = < - MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 - MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 - MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 - MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140 - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 - MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 - MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 - MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140 - >; - }; - - pinctrl_uart3_gpio: uart3gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 - MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 - >; - }; - - pinctrl_usb1: usb1grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 - >; - }; - - pinctrl_usbcon1: usb1congrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw7905-2x.dts b/arch/arm/dts/imx8mp-venice-gw7905-2x.dts deleted file mode 100644 index 4a1bbbbe19e..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw7905-2x.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mp.dtsi" -#include "imx8mp-venice-gw702x.dtsi" -#include "imx8mp-venice-gw7905.dtsi" - -/ { - model = "Gateworks Venice GW7905-2x i.MX8MP Development Kit"; - compatible = "gateworks,imx8mp-gw7905-2x", "fsl,imx8mp"; - - chosen { - stdout-path = &uart2; - }; -}; - -/* Disable SOM interfaces not used on baseboard */ -&eqos { - status = "disabled"; -}; - -&usdhc1 { - status = "disabled"; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw7905.dtsi b/arch/arm/dts/imx8mp-venice-gw7905.dtsi deleted file mode 100644 index 0d40cb0f05f..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw7905.dtsi +++ /dev/null @@ -1,309 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_usb2_vbus: regulator-usb2-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2_en>; - compatible = "regulator-fixed"; - regulator-name = "usb2_vbus"; - gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - compatible = "regulator-fixed"; - regulator-name = "SD2_3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "gpioa", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "gpiod", "", "", - "gpiob", "gpioc", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "pci_usb_sel", "", - "pci_wdis#", "", "", ""; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; - pagesize = <32>; - }; -}; - -/* off-board header */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* USB1 - Type C front panel SINK port J14 */ -&usb3_0 { - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "peripheral"; - status = "okay"; -}; - -/* USB2 4-port USB3.0 HUB: - * P1 - USBC connector (host only) - * P2 - USB2 test connector - * P3 - miniPCIe full card - * P4 - miniPCIe half card - */ -&usb3_phy1 { - vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -&usb3_1 { - fsl,permanently-attached; - fsl,disable-port-power-control; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40000040 /* GPIOA */ - MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000040 /* GPIOD */ - MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x40000040 /* GPIOB */ - MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x40000040 /* GPIOC */ - MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000106 /* PCI_USBSEL */ - MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */ - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */ - MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6 /* LEDR */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_pcie0: pciegrp { - fsl,pins = < - MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106 - >; - }; - - pinctrl_reg_usb2_en: regusb2grp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x6 /* USBHUB_RST# (ext p/u) */ - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice.dts b/arch/arm/dts/imx8mp-venice.dts deleted file mode 100644 index 372db26cc09..00000000000 --- a/arch/arm/dts/imx8mp-venice.dts +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mp.dtsi" - -/ { - model = "Gateworks Venice i.MX8MP board"; - compatible = "gateworks,imx8mp-venice", "fsl,imx8mp"; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; - pagesize = <32>; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1grp-gpio-grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c3 - MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-verdin-dev.dtsi b/arch/arm/dts/imx8mp-verdin-dev.dtsi deleted file mode 100644 index bdfdd4c782f..00000000000 --- a/arch/arm/dts/imx8mp-verdin-dev.dtsi +++ /dev/null @@ -1,165 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/ { - /* TODO: Audio Codec */ - - reg_eth2phy: regulator-eth2phy { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio_expander_21 4 GPIO_ACTIVE_HIGH>; /* ETH_PWR_EN */ - off-on-delay-us = <500000>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_ETH"; - startup-delay-us = <200000>; - vin-supply = <®_3p3v>; - }; -}; - -&backlight { - power-supply = <®_3p3v>; -}; - -/* Verdin SPI_1 */ -&ecspi1 { - status = "okay"; -}; - -/* EEPROM on display adapter boards */ -&eeprom_display_adapter { - status = "okay"; -}; - -/* EEPROM on Verdin Development board */ -&eeprom_carrier_board { - status = "okay"; -}; - -&eqos { - status = "okay"; -}; - -&fec { - phy-supply = <®_eth2phy>; - status = "okay"; -}; - -&flexcan1 { - status = "okay"; -}; - -&flexcan2 { - status = "okay"; -}; - -/* Verdin QSPI_1 */ -&flexspi { - status = "okay"; -}; - -&gpio_expander_21 { - status = "okay"; - vcc-supply = <®_1p8v>; -}; - -/* Current measurement into module VCC */ -&hwmon { - status = "okay"; -}; - -&hwmon_temp { - vs-supply = <®_1p8v>; - status = "okay"; -}; - -/* Verdin I2C_2_DSI */ -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -/* Verdin I2C_1 */ -&i2c4 { - status = "okay"; - - /* TODO: Audio Codec */ -}; - -/* Verdin PCIE_1 */ -&pcie { - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -/* Verdin PWM_1 */ -&pwm1 { - status = "okay"; -}; - -/* Verdin PWM_2 */ -&pwm2 { - status = "okay"; -}; - -/* Verdin PWM_3_DSI */ -&pwm3 { - status = "okay"; -}; - -®_usdhc2_vmmc { - vin-supply = <®_3p3v>; -}; - -/* TODO: Verdin I2C_1 with Audio Codec */ - -/* Verdin UART_1, connector X50 through RS485 transceiver */ -&uart1 { - linux,rs485-enabled-at-boot-time; - rs485-rts-active-low; - rs485-rx-during-tx; - status = "okay"; -}; - -/* Verdin UART_2 */ -&uart2 { - status = "okay"; -}; - -/* Verdin UART_3, used as the Linux Console */ -&uart3 { - status = "okay"; -}; - -/* Verdin USB_1 */ -&usb3_0 { - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -/* Verdin USB_2 */ -&usb3_1 { - fsl,permanently-attached; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -/* Limit frequency on dev board due to long traces and bad signal integrity */ -&usdhc2 { - max-frequency = <100000000>; - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi index 03f211d5f7d..7b45a87450b 100644 --- a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi @@ -58,6 +58,10 @@ ctrl-sleep-moci-hog { bootph-pre-ram; + gpio-hog; + output-high; + gpios = <29 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; }; }; diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev.dts b/arch/arm/dts/imx8mp-verdin-wifi-dev.dts deleted file mode 100644 index c1713c28cdc..00000000000 --- a/arch/arm/dts/imx8mp-verdin-wifi-dev.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/dts-v1/; - -#include "imx8mp-verdin.dtsi" -#include "imx8mp-verdin-wifi.dtsi" -#include "imx8mp-verdin-dev.dtsi" - -/ { - model = "Toradex Verdin iMX8M Plus WB on Verdin Development Board"; - compatible = "toradex,verdin-imx8mp-wifi-dev", - "toradex,verdin-imx8mp-wifi", - "toradex,verdin-imx8mp", - "fsl,imx8mp"; -}; diff --git a/arch/arm/dts/imx8mp-verdin-wifi.dtsi b/arch/arm/dts/imx8mp-verdin-wifi.dtsi deleted file mode 100644 index ef94f9a57e2..00000000000 --- a/arch/arm/dts/imx8mp-verdin-wifi.dtsi +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/ { - reg_wifi_en: regulator-wifi-en { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_pwr_en>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "PDn_AW-CM276NF"; - startup-delay-us = <2000>; - }; -}; - -&gpio5 { - gpio-line-names = "SODIMM_42", - "SODIMM_46", - "SODIMM_187", - "SODIMM_20", - "SODIMM_22", - "SODIMM_15", - "SODIMM_196", - "SODIMM_200", - "SODIMM_198", - "SODIMM_202", - "", - "", - "", - "", - "", - "", - "SODIMM_55", - "SODIMM_53", - "SODIMM_95", - "SODIMM_93", - "SODIMM_14", - "SODIMM_12", - "SODIMM_129", - "SODIMM_131", - "SODIMM_137", - "SODIMM_139", - "SODIMM_147", - "SODIMM_149", - "SODIMM_151", - "SODIMM_153"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, - <&pinctrl_gpio3>, <&pinctrl_gpio4>, - <&pinctrl_gpio7>, <&pinctrl_gpio8>, - <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hog4>, - <&pinctrl_hdmi_hog>; -}; - -/* On-module Bluetooth */ -&uart4 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_uart>; - status = "okay"; - - bluetooth { - compatible = "mrvl,88w8997"; - max-speed = <921600>; - }; -}; - -/* On-module Wi-Fi */ -&usdhc1 { - bus-width = <4>; - keep-power-in-suspend; - max-frequency = <100000000>; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi_ctrl>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi_ctrl>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi_ctrl>; - vmmc-supply = <®_wifi_en>; - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mp-verdin.dtsi b/arch/arm/dts/imx8mp-verdin.dtsi deleted file mode 100644 index e9e4fcb562f..00000000000 --- a/arch/arm/dts/imx8mp-verdin.dtsi +++ /dev/null @@ -1,1438 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -#include <dt-bindings/phy/phy-imx8-pcie.h> -#include <dt-bindings/pwm/pwm.h> -#include "imx8mp.dtsi" - -/ { - chosen { - stdout-path = &uart3; - }; - - aliases { - /* Ethernet aliases to ensure correct MAC addresses */ - ethernet0 = &eqos; - ethernet1 = &fec; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 45 63 88 119 158 203 255>; - default-brightness-level = <4>; - /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ - enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; - power-supply = <®_3p3v>; - /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ - pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>; - status = "disabled"; - }; - - backlight_mezzanine: backlight-mezzanine { - compatible = "pwm-backlight"; - brightness-levels = <0 45 63 88 119 158 203 255>; - default-brightness-level = <4>; - /* Verdin GPIO 4 (SODIMM 212) */ - enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - /* Verdin PWM_2 (SODIMM 16) */ - pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>; - status = "disabled"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - key-wakeup { - debounce-interval = <10>; - /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ - gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; - label = "Wake-Up"; - linux,code = <KEY_WAKEUP>; - wakeup-source; - }; - }; - - /* Carrier Board Supplies */ - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8_SW"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_SW"; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "+V5_SW"; - }; - - /* Non PMIC On-module Supplies */ - reg_module_eth1phy: regulator-module-eth1phy { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ - off-on-delay-us = <500000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_eth>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "On-module +V3.3_ETH"; - startup-delay-us = <200000>; - vin-supply = <®_vdd_3v3>; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - /* Verdin USB_1_EN (SODIMM 155) */ - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1_vbus>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "USB_1_EN"; - }; - - reg_usb2_vbus: regulator-usb2-vbus { - compatible = "regulator-fixed"; - enable-active-high; - /* Verdin USB_2_EN (SODIMM 185) */ - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2_vbus>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "USB_2_EN"; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - enable-active-high; - /* Verdin SD_1_PWR_EN (SODIMM 76) */ - gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; - off-on-delay-us = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_SD"; - startup-delay-us = <2000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Use the kernel configuration settings instead */ - /delete-node/ linux,cma; - }; -}; - -&A53_0 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_1 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_2 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_3 { - cpu-supply = <®_vdd_arm>; -}; - -&cpu_alert0 { - temperature = <95000>; -}; - -&cpu_crit0 { - temperature = <105000>; -}; - -/* Verdin SPI_1 */ -&ecspi1 { - #address-cells = <1>; - #size-cells = <0>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; -}; - -/* Verdin ETH_1 (On-module PHY) */ -&eqos { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; - phy-supply = <®_module_eth1phy>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - snps,force_thresh_dma_mode; - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - eee-broken-100tx; - eee-broken-1000t; - interrupt-parent = <&gpio1>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <0>; - reg = <7>; - }; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <5>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,priority = <0x1>; - snps,map-to-dma-channel = <0>; - }; - - queue1 { - snps,dcb-algorithm; - snps,priority = <0x2>; - snps,map-to-dma-channel = <1>; - }; - - queue2 { - snps,dcb-algorithm; - snps,priority = <0x4>; - snps,map-to-dma-channel = <2>; - }; - - queue3 { - snps,dcb-algorithm; - snps,priority = <0x8>; - snps,map-to-dma-channel = <3>; - }; - - queue4 { - snps,dcb-algorithm; - snps,priority = <0xf0>; - snps,map-to-dma-channel = <4>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <5>; - snps,tx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,priority = <0x2>; - }; - - queue2 { - snps,dcb-algorithm; - snps,priority = <0x4>; - }; - - queue3 { - snps,dcb-algorithm; - snps,priority = <0x8>; - }; - - queue4 { - snps,dcb-algorithm; - snps,priority = <0xf0>; - }; - }; -}; - -/* Verdin ETH_2_RGMII */ -&fec { - fsl,magic-packet; - phy-handle = <ðphy1>; - phy-mode = "rgmii-id"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_fec>; - pinctrl-1 = <&pinctrl_fec_sleep>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - interrupt-parent = <&gpio4>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <0>; - reg = <7>; - }; - }; -}; - -/* Verdin CAN_1 */ -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -/* Verdin CAN_2 */ -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "disabled"; -}; - -/* Verdin QSPI_1 */ -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; -}; - -&gpio1 { - gpio-line-names = "SODIMM_206", - "SODIMM_208", - "", - "", - "", - "SODIMM_210", - "SODIMM_212", - "SODIMM_216", - "SODIMM_218", - "", - "", - "SODIMM_16", - "SODIMM_155", - "SODIMM_157", - "SODIMM_185", - "SODIMM_91"; -}; - -&gpio2 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "SODIMM_143", - "SODIMM_141", - "", - "", - "SODIMM_161", - "", - "SODIMM_84", - "SODIMM_78", - "SODIMM_74", - "SODIMM_80", - "SODIMM_82", - "SODIMM_70", - "SODIMM_72"; -}; - -&gpio3 { - gpio-line-names = "SODIMM_52", - "SODIMM_54", - "", - "", - "", - "", - "SODIMM_56", - "SODIMM_58", - "SODIMM_60", - "SODIMM_62", - "", - "", - "", - "", - "SODIMM_66", - "", - "SODIMM_64", - "", - "", - "SODIMM_34", - "SODIMM_19", - "", - "SODIMM_32", - "", - "", - "SODIMM_30", - "SODIMM_59", - "SODIMM_57", - "SODIMM_63", - "SODIMM_61"; -}; - -&gpio4 { - gpio-line-names = "SODIMM_252", - "SODIMM_222", - "SODIMM_36", - "SODIMM_220", - "SODIMM_193", - "SODIMM_191", - "SODIMM_201", - "SODIMM_203", - "SODIMM_205", - "SODIMM_207", - "SODIMM_199", - "SODIMM_197", - "SODIMM_221", - "SODIMM_219", - "SODIMM_217", - "SODIMM_215", - "SODIMM_211", - "SODIMM_213", - "SODIMM_189", - "SODIMM_244", - "SODIMM_38", - "", - "SODIMM_76", - "SODIMM_135", - "SODIMM_133", - "SODIMM_17", - "SODIMM_24", - "SODIMM_26", - "SODIMM_21", - "SODIMM_256", - "SODIMM_48", - "SODIMM_44"; - - ctrl-sleep-moci-hog { - gpio-hog; - /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ - gpios = <29 GPIO_ACTIVE_HIGH>; - line-name = "CTRL_SLEEP_MOCI#"; - output-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; - }; -}; - -/* On-module I2C */ -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pca9450: pmic@25 { - compatible = "nxp,pca9450c"; - interrupt-parent = <&gpio1>; - /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0x25>; - - /* - * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the - * I2C level shifter for the TLA2024 ADC behind this PMIC. - */ - - regulators { - BUCK1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1000000>; - regulator-min-microvolt = <720000>; - regulator-name = "On-module +VDD_SOC (BUCK1)"; - regulator-ramp-delay = <3125>; - }; - - reg_vdd_arm: BUCK2 { - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1025000>; - regulator-min-microvolt = <720000>; - regulator-name = "On-module +VDD_ARM (BUCK2)"; - regulator-ramp-delay = <3125>; - }; - - reg_vdd_3v3: BUCK4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "On-module +V3.3 (BUCK4)"; - }; - - reg_vdd_1v8: BUCK5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "PWR_1V8_MOCI (BUCK5)"; - }; - - BUCK6 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1155000>; - regulator-min-microvolt = <1045000>; - regulator-name = "On-module +VDD_DDR (BUCK6)"; - }; - - LDO1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1950000>; - regulator-min-microvolt = <1650000>; - regulator-name = "On-module +V1.8_SNVS (LDO1)"; - }; - - LDO2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1150000>; - regulator-min-microvolt = <800000>; - regulator-name = "On-module +V0.8_SNVS (LDO2)"; - }; - - LDO3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-module +V1.8A (LDO3)"; - }; - - LDO4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "On-module +V3.3_ADC (LDO4)"; - }; - - LDO5 { - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; - }; - }; - }; - - rtc_i2c: rtc@32 { - compatible = "epson,rx8130"; - reg = <0x32>; - }; - - /* On-module temperature sensor */ - hwmon_temp_module: sensor@48 { - compatible = "ti,tmp1075"; - reg = <0x48>; - vs-supply = <®_vdd_1v8>; - }; - - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - /* Verdin I2C_1 (ADC_4 - ADC_3) */ - channel@0 { - reg = <0>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 (ADC_4 - ADC_1) */ - channel@1 { - reg = <1>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 (ADC_3 - ADC_1) */ - channel@2 { - reg = <2>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 (ADC_2 - ADC_1) */ - channel@3 { - reg = <3>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 ADC_4 */ - channel@4 { - reg = <4>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 ADC_3 */ - channel@5 { - reg = <5>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 ADC_2 */ - channel@6 { - reg = <6>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 ADC_1 */ - channel@7 { - reg = <7>; - ti,datarate = <4>; - ti,gain = <2>; - }; - }; - - eeprom@50 { - compatible = "st,24c02"; - pagesize = <16>; - reg = <0x50>; - }; -}; - -/* Verdin I2C_2_DSI */ -&i2c2 { - /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */ - clock-frequency = <10000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - - atmel_mxt_ts_mezzanine: touch-mezzanine@4a { - compatible = "atmel,maxtouch"; - /* Verdin GPIO_3 (SODIMM 210) */ - interrupt-parent = <&gpio1>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - reg = <0x4a>; - /* Verdin GPIO_2 (SODIMM 208) */ - reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - status = "disabled"; - }; -}; - -/* TODO: Verdin I2C_3_HDMI */ - -/* Verdin I2C_4_CSI */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -/* Verdin I2C_1 */ -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - - gpio_expander_21: gpio-expander@21 { - compatible = "nxp,pcal6416"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x21>; - vcc-supply = <®_3p3v>; - status = "disabled"; - }; - - lvds_ti_sn65dsi84: bridge@2c { - compatible = "ti,sn65dsi84"; - /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ - /* Verdin GPIO_10_DSI (SODIMM 21) */ - enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_10_dsi>; - reg = <0x2c>; - status = "disabled"; - }; - - /* Current measurement into module VCC */ - hwmon: hwmon@40 { - compatible = "ti,ina219"; - reg = <0x40>; - shunt-resistor = <10000>; - status = "disabled"; - }; - - hdmi_lontium_lt8912: hdmi@48 { - compatible = "lontium,lt8912b"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>; - reg = <0x48>; - /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ - /* Verdin GPIO_10_DSI (SODIMM 21) */ - reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - status = "disabled"; - }; - - atmel_mxt_ts: touch@4a { - compatible = "atmel,maxtouch"; - /* - * Verdin GPIO_9_DSI - * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) - */ - interrupt-parent = <&gpio4>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; - reg = <0x4a>; - /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ - reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - status = "disabled"; - }; - - /* Temperature sensor on carrier board */ - hwmon_temp: sensor@4f { - compatible = "ti,tmp75c"; - reg = <0x4f>; - status = "disabled"; - }; - - /* EEPROM on display adapter (MIPI DSI Display Adapter) */ - eeprom_display_adapter: eeprom@50 { - compatible = "st,24c02"; - pagesize = <16>; - reg = <0x50>; - status = "disabled"; - }; - - /* EEPROM on carrier board */ - eeprom_carrier_board: eeprom@57 { - compatible = "st,24c02"; - pagesize = <16>; - reg = <0x57>; - status = "disabled"; - }; -}; - -/* Verdin PCIE_1 */ -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - /* PCIE_1_RESET# (SODIMM 244) */ - reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; -}; - -&pcie_phy { - clocks = <&hsio_blk_ctrl>; - clock-names = "ref"; - fsl,clkreq-unsupported; - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; -}; - -/* Verdin PWM_1 */ -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_1>; - #pwm-cells = <3>; -}; - -/* Verdin PWM_2 */ -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_2>; - #pwm-cells = <3>; -}; - -/* Verdin PWM_3_DSI */ -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_3>; - #pwm-cells = <3>; -}; - -/* TODO: Verdin I2S_1 */ - -/* TODO: Verdin I2S_2 */ - -&snvs_pwrkey { - status = "okay"; -}; - -/* Verdin UART_1 */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; -}; - -/* Verdin UART_2 */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; -}; - -/* Verdin UART_3, used as the Linux Console */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; -}; - -/* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; -}; - -/* Verdin USB_1 */ -&usb3_0 { - fsl,disable-port-power-control; - fsl,over-current-active-low; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_1_oc_n>; -}; - -&usb_dwc3_0 { - /* dual role only, not full featured OTG */ - adp-disable; - dr_mode = "otg"; - hnp-disable; - maximum-speed = "high-speed"; - role-switch-default-mode = "peripheral"; - srp-disable; - usb-role-switch; - - connector { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - label = "Type-C"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_1_id>; - self-powered; - type = "micro"; - vbus-supply = <®_usb1_vbus>; - }; -}; - -/* Verdin USB_2 */ -&usb3_1 { - fsl,disable-port-power-control; -}; - -&usb3_phy1 { - vbus-supply = <®_usb2_vbus>; -}; - -&usb_dwc3_1 { - dr_mode = "host"; -}; - -/* Verdin SD_1 */ -&usdhc2 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; - assigned-clock-rates = <400000000>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; - vmmc-supply = <®_usdhc2_vmmc>; -}; - -/* On-module eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - status = "okay"; -}; - -&wdog1 { - fsl,ext-reset-output; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - status = "okay"; -}; - -&iomuxc { - pinctrl_bt_uart: btuartgrp { - fsl,pins = - <MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1c4>, - <MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1c4>, - <MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1c4>, - <MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1c4>; - }; - - pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { - fsl,pins = - <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4>; /* SODIMM 256 */ - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = - <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SODIMM 198 */ - <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SODIMM 200 */ - <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SODIMM 196 */ - <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>; /* SODIMM 202 */ - }; - - /* Connection On Board PHY */ - pinctrl_eqos: eqosgrp { - fsl,pins = - <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>, - <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>, - <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>, - <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>, - <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>, - <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>, - <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>, - <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>, - <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>, - <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>, - <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>, - <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>, - <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>, - <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>; - }; - - /* ETH_INT# shared with TPM_INT# (usually N/A) */ - pinctrl_eth_tpm_int: ethtpmintgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4>; - }; - - /* Connection Carrier Board PHY ETH_2 */ - pinctrl_fec: fecgrp { - fsl,pins = - <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */ - <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */ - <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */ - <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */ - <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */ - <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */ - <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */ - <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */ - <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, /* SODIMM 221 */ - <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, /* SODIMM 219 */ - <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, /* SODIMM 217 */ - <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, /* SODIMM 215 */ - <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, /* SODIMM 211 */ - <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>, /* SODIMM 213 */ - <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1c4>; /* SODIMM 189 */ - }; - - pinctrl_fec_sleep: fecsleepgrp { - fsl,pins = - <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */ - <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */ - <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */ - <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */ - <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */ - <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */ - <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */ - <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */ - <MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x1f>, /* SODIMM 221 */ - <MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x1f>, /* SODIMM 219 */ - <MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1f>, /* SODIMM 217 */ - <MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x1f>, /* SODIMM 215 */ - <MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x1f>, /* SODIMM 211 */ - <MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x1f>, /* SODIMM 213 */ - <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x184>; /* SODIMM 189 */ - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = - <MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154>, /* SODIMM 22 */ - <MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154>; /* SODIMM 20 */ - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = - <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SODIMM 26 */ - <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SODIMM 24 */ - }; - - pinctrl_flexspi0: flexspi0grp { - fsl,pins = - <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, /* SODIMM 52 */ - <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, /* SODIMM 54 */ - <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82>, /* SODIMM 66 */ - <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, /* SODIMM 56 */ - <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, /* SODIMM 58 */ - <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, /* SODIMM 60 */ - <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, /* SODIMM 62 */ - <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */ - }; - - pinctrl_gpio1: gpio1grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184>; /* SODIMM 206 */ - }; - - pinctrl_gpio2: gpio2grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x1c4>; /* SODIMM 208 */ - }; - - pinctrl_gpio3: gpio3grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184>; /* SODIMM 210 */ - }; - - pinctrl_gpio4: gpio4grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184>; /* SODIMM 212 */ - }; - - pinctrl_gpio5: gpio5grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184>; /* SODIMM 216 */ - }; - - pinctrl_gpio6: gpio6grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184>; /* SODIMM 218 */ - }; - - pinctrl_gpio7: gpio7grp { - fsl,pins = - <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184>; /* SODIMM 220 */ - }; - - pinctrl_gpio8: gpio8grp { - fsl,pins = - <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184>; /* SODIMM 222 */ - }; - - /* Verdin GPIO_9_DSI (pulled-up as active-low) */ - pinctrl_gpio_9_dsi: gpio9dsigrp { - fsl,pins = - <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1c4>; /* SODIMM 17 */ - }; - - /* Verdin GPIO_10_DSI */ - pinctrl_gpio_10_dsi: gpio10dsigrp { - fsl,pins = - <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SODIMM 21 */ - }; - - /* Non-wifi MSP usage only */ - pinctrl_gpio_hog1: gpiohog1grp { - fsl,pins = - <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c4>, /* SODIMM 116 */ - <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1c4>, /* SODIMM 152 */ - <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1c4>, /* SODIMM 164 */ - <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>; /* SODIMM 128 */ - }; - - /* USB_2_OC# */ - pinctrl_gpio_hog2: gpiohog2grp { - fsl,pins = - <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SODIMM 187 */ - }; - - pinctrl_gpio_hog3: gpiohog3grp { - fsl,pins = - /* CSI_1_MCLK */ - <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */ - }; - - /* Wifi usage only */ - pinctrl_gpio_hog4: gpiohog4grp { - fsl,pins = - <MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x1c4>, /* SODIMM 151 */ - <MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x1c4>; /* SODIMM 153 */ - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = - <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c4>; /* SODIMM 252 */ - }; - - pinctrl_hdmi_hog: hdmihoggrp { - fsl,pins = - <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */ - <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3>, /* SODIMM 59 */ - <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3>, /* SODIMM 57 */ - <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */ - }; - - /* On-module I2C */ - pinctrl_i2c1: i2c1grp { - fsl,pins = - <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */ - <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */ - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = - <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */ - <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */ - }; - - /* Verdin I2C_2_DSI */ - pinctrl_i2c2: i2c2grp { - fsl,pins = - <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SODIMM 55 */ - <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SODIMM 53 */ - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = - <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SODIMM 55 */ - <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SODIMM 53 */ - }; - - /* Verdin I2C_4_CSI */ - pinctrl_i2c3: i2c3grp { - fsl,pins = - <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SODIMM 95 */ - <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SODIMM 93 */ - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = - <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SODIMM 95 */ - <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SODIMM 93 */ - }; - - /* Verdin I2C_1 */ - pinctrl_i2c4: i2c4grp { - fsl,pins = - <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SODIMM 14 */ - <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SODIMM 12 */ - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = - <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SODIMM 14 */ - <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */ - }; - - /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ - pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { - fsl,pins = - <MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x184>; /* SODIMM 42 */ - }; - - /* Verdin I2S_2_D_OUT shared with SAI3 */ - pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { - fsl,pins = - <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x184>; /* SODIMM 46 */ - }; - - pinctrl_pcie: pciegrp { - fsl,pins = - <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x4>, /* SODIMM 244 */ - <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* PMIC_EN_PCIe_CLK, unused */ - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */ - }; - - pinctrl_pwm_1: pwm1grp { - fsl,pins = - <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6>; /* SODIMM 15 */ - }; - - pinctrl_pwm_2: pwm2grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x6>; /* SODIMM 16 */ - }; - - /* Verdin PWM_3_DSI shared with GPIO3_IO20 */ - pinctrl_pwm_3: pwm3grp { - fsl,pins = - <MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x6>; /* SODIMM 19 */ - }; - - /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */ - pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp { - fsl,pins = - <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x184>; /* SODIMM 19 */ - }; - - pinctrl_reg_eth: regethgrp { - fsl,pins = - <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184>; /* PMIC_EN_ETH */ - }; - - pinctrl_sai1: sai1grp { - fsl,pins = - <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>, /* SODIMM 38 */ - <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x1d6>, /* SODIMM 36 */ - <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x1d6>, /* SODIMM 30 */ - <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x1d6>, /* SODIMM 32 */ - <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x96>; /* SODIMM 34 */ - }; - - pinctrl_sai3: sai3grp { - fsl,pins = - <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1d6>, /* SODIMM 48 */ - <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1d6>, /* SODIMM 42 */ - <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x96>, /* SODIMM 46 */ - <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1d6>; /* SODIMM 44 */ - }; - - pinctrl_uart1: uart1grp { - fsl,pins = - <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SODIMM 135 */ - <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SODIMM 133 */ - <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SODIMM 129 */ - <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SODIMM 131 */ - }; - - pinctrl_uart2: uart2grp { - fsl,pins = - <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SODIMM 143 */ - <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SODIMM 141 */ - <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SODIMM 137 */ - <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SODIMM 139 */ - }; - - pinctrl_uart3: uart3grp { - fsl,pins = - <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SODIMM 147 */ - <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SODIMM 149 */ - }; - - /* Non-wifi usage only */ - pinctrl_uart4: uart4grp { - fsl,pins = - <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SODIMM 151 */ - <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SODIMM 153 */ - }; - - pinctrl_usb1_vbus: usb1vbusgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x106>; /* SODIMM 155 */ - }; - - /* USB_1_ID */ - pinctrl_usb_1_id: usb1idgrp { - fsl,pins = - <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */ - }; - - /* USB_1_OC# */ - pinctrl_usb_1_oc_n: usb1ocngrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c4>; /* SODIMM 157 */ - }; - - pinctrl_usb2_vbus: usb2vbusgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x106>; /* SODIMM 185 */ - }; - - /* On-module Wi-Fi */ - pinctrl_usdhc1: usdhc1grp { - fsl,pins = - <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>, - <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>, - <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>, - <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>, - <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>, - <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = - <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>, - <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>, - <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>, - <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>, - <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>, - <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = - <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>, - <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>, - <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>, - <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>, - <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>, - <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>; - }; - - pinctrl_usdhc2_cd: usdhc2cdgrp { - fsl,pins = - <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SODIMM 84 */ - }; - - pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { - fsl,pins = - <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SODIMM 84 */ - }; - - pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { - fsl,pins = - <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x4>; /* SODIMM 76 */ - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, /* PMIC_USDHC_VSELECT */ - <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SODIMM 78 */ - <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SODIMM 74 */ - <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SODIMM 80 */ - <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SODIMM 82 */ - <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SODIMM 70 */ - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SODIMM 72 */ - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, - <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, - <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, - <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, - <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, - <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, - <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>, - <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>, - <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>, - <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>, - <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>, - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>; - }; - - /* Avoid backfeeding with removed card power */ - pinctrl_usdhc2_sleep: usdhc2slpgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0>, - <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>, - <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>, - <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>, - <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>, - <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>, - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, - <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>, - <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>, - <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>, - <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>, - <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>, - <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>, - <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>, - <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>, - <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>, - <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>, - <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, - <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>, - <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, - <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, - <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, - <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, - <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, - <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, - <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, - <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, - <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, - <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, - <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>, - <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>, - <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>, - <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>, - <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>, - <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>, - <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>, - <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>, - <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>, - <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>, - <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */ - }; - - pinctrl_bluetooth_ctrl: bluetoothctrlgrp { - fsl,pins = - <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x1c4>; /* WIFI_WKUP_BT */ - }; - - pinctrl_wifi_ctrl: wifictrlgrp { - fsl,pins = - <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4>; /* WIFI_WKUP_WLAN */ - }; - - pinctrl_wifi_i2s: wifii2sgrp { - fsl,pins = - <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x1d6>, /* WIFI_TX_SYNC */ - <MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x96>, /* WIFI_RX_DATA0 */ - <MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x1d6>, /* WIFI_TX_BCLK */ - <MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1d6>; /* WIFI_TX_DATA0 */ - }; - - pinctrl_wifi_pwr_en: wifipwrengrp { - fsl,pins = - <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x184>; /* PMIC_EN_WIFI */ - }; -}; diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts deleted file mode 100644 index 82387b9cb80..00000000000 --- a/arch/arm/dts/imx8mq-evk.dts +++ /dev/null @@ -1,712 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2017 NXP - * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> - */ - -/dts-v1/; - -#include "imx8mq.dtsi" - -/ { - model = "NXP i.MX8MQ EVK"; - compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x00000000 0x40000000 0 0xc0000000>; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_pcie1: regulator-pcie { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie1_reg>; - regulator-name = "MPCIE_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vmmc: regulator-vsd-3v3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2>; - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - buck2_reg: regulator-buck2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_buck2>; - compatible = "regulator-gpio"; - regulator-name = "vdd_arm"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1000000>; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - states = <1000000 0x0 - 900000 0x1>; - regulator-boot-on; - regulator-always-on; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - linux,autosuspend-period = <125>; - }; - - audio_codec_bt_sco: audio-codec-bt-sco { - compatible = "linux,bt-sco"; - #sound-dai-cells = <1>; - }; - - wm8524: audio-codec { - #sound-dai-cells = <0>; - compatible = "wlf,wm8524"; - wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - }; - - sound-bt-sco { - compatible = "simple-audio-card"; - simple-audio-card,name = "bt-sco-audio"; - simple-audio-card,format = "dsp_a"; - simple-audio-card,bitclock-inversion; - simple-audio-card,frame-master = <&btcpu>; - simple-audio-card,bitclock-master = <&btcpu>; - - btcpu: simple-audio-card,cpu { - sound-dai = <&sai3>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - - simple-audio-card,codec { - sound-dai = <&audio_codec_bt_sco 1>; - }; - }; - - sound-wm8524 { - compatible = "simple-audio-card"; - simple-audio-card,name = "wm8524-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&cpudai>; - simple-audio-card,bitclock-master = <&cpudai>; - simple-audio-card,widgets = - "Line", "Left Line Out Jack", - "Line", "Right Line Out Jack"; - simple-audio-card,routing = - "Left Line Out Jack", "LINEVOUTL", - "Right Line Out Jack", "LINEVOUTR"; - - cpudai: simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - link_codec: simple-audio-card,codec { - sound-dai = <&wm8524>; - clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; - }; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif1>; - spdif-out; - spdif-in; - }; - - sound-hdmi-arc { - compatible = "fsl,imx-audio-spdif"; - model = "imx-hdmi-arc"; - spdif-controller = <&spdif2>; - spdif-in; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - status = "okay"; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - /* - * On imx8mq B0 PLL can't be bypassed so low bus is 166M - */ - opp-166M { - opp-hz = /bits/ 64 <166935483>; - }; - - opp-800M { - opp-hz = /bits/ 64 <800000000>; - }; - }; -}; - -&dphy { - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - qca,disable-smarteee; - vddio-supply = <&vddh>; - - vddh: vddh-regulator { - }; - }; - }; -}; - -&gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_reset>; - - wl-reg-on-hog { - gpio-hog; - gpios = <29 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x8>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw3a_reg: sw3ab { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <975000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1675000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1625000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3625000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; -}; - -&lcdif { - status = "okay"; -}; - -&mipi_dsi { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - panel@0 { - pinctrl-0 = <&pinctrl_mipi_dsi>; - pinctrl-names = "default"; - compatible = "raydium,rm67191"; - reg = <0>; - reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; - dsi-lanes = <4>; - - port { - panel_in: endpoint { - remote-endpoint = <&mipi_dsi_out>; - }; - }; - }; - - ports { - port@1 { - reg = <1>; - mipi_dsi_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&clk IMX8MQ_CLK_PCIE1_AUX>, - <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - vph-supply = <&vgen5_reg>; - status = "okay"; -}; - -&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie1>; - reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, - <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - vpcie-supply = <®_pcie1>; - vph-supply = <&vgen5_reg>; - status = "okay"; -}; - -&pgc_gpu { - power-supply = <&sw1a_reg>; -}; - -&pgc_vpu { - power-supply = <&sw1c_reg>; -}; - -&qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - n25q256a: flash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - }; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <0>, <24576000>; - status = "okay"; -}; - -&sai3 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&spdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif1>; - assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&spdif2 { - assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - vqmmc-supply = <&sw4_reg>; - bus-width = <8>; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_buck2: vddarmgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_ir: irgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f - >; - }; - - pinctrl_mipi_dsi: mipidsigrp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 - MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 - >; - }; - - pinctrl_pcie1: pcie1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 - MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 - >; - }; - - pinctrl_pcie1_reg: pcie1reggrp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 - MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_reg_usdhc2: regusdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 - MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - >; - }; - - pinctrl_spdif1: spdif1grp { - fsl,pins = < - MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 - MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_wdog: wdog1grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; - - pinctrl_wifi_reset: wifiresetgrp { - fsl,pins = < - MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 - >; - }; -}; diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi index 8bf28c2de87..6897c91f4d9 100644 --- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi +++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi @@ -121,6 +121,21 @@ bootph-some-ram; }; +/* + * Remove once USB support is added to imx93-phyboard-segin.dts upstream. + */ +&usbotg1 { + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + &usdhc1 { bootph-pre-ram; bootph-some-ram; diff --git a/arch/arm/dts/k3-am62-verdin-dev.dtsi b/arch/arm/dts/k3-am62-verdin-dev.dtsi deleted file mode 100644 index 6701cb8974b..00000000000 --- a/arch/arm/dts/k3-am62-verdin-dev.dtsi +++ /dev/null @@ -1,240 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2023 Toradex - * - * Common dtsi for Verdin AM62 SoM on Development carrier board - * - * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 - * https://www.toradex.com/products/carrier-board/verdin-development-board-kit - */ - -/ { - sound { - compatible = "simple-audio-card"; - simple-audio-card,bitclock-master = <&codec_dai>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&codec_dai>; - simple-audio-card,name = "verdin-nau8822"; - simple-audio-card,routing = - "Headphones", "LHP", - "Headphones", "RHP", - "Speaker", "LSPK", - "Speaker", "RSPK", - "Line Out", "AUXOUT1", - "Line Out", "AUXOUT2", - "LAUX", "Line In", - "RAUX", "Line In", - "LMICP", "Mic In", - "RMICP", "Mic In"; - simple-audio-card,widgets = - "Headphones", "Headphones", - "Line Out", "Line Out", - "Speaker", "Speaker", - "Microphone", "Mic In", - "Line", "Line In"; - - codec_dai: simple-audio-card,codec { - clocks = <&audio_refclk1>; - sound-dai = <&nau8822_1a>; - }; - - simple-audio-card,cpu { - sound-dai = <&mcasp0>; - }; - }; -}; - -/* Verdin ETHs */ -&cpsw3g { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>; - status = "okay"; -}; - -/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ -&cpsw3g_mdio { - status = "okay"; - - cpsw3g_phy1: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <7>; - interrupt-parent = <&main_gpio0>; - interrupts = <38 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eth2_rgmii_int>; - micrel,led-mode = <0>; - }; -}; - -/* Verdin ETH_1 (On-module PHY) */ -&cpsw_port1 { - status = "okay"; -}; - -/* Verdin ETH_2_RGMII */ -&cpsw_port2 { - phy-handle = <&cpsw3g_phy1>; - phy-mode = "rgmii-rxid"; - status = "okay"; -}; - -/* Verdin PWM_1, PWM_2 */ -&epwm0 { - status = "okay"; -}; - -/* Verdin PWM_3_DSI */ -&epwm1 { - status = "okay"; -}; - -&main_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ctrl_sleep_moci>, - <&pinctrl_gpio_5>, - <&pinctrl_gpio_6>, - <&pinctrl_gpio_7>, - <&pinctrl_gpio_8>; -}; - -/* Verdin I2C_1 */ -&main_i2c1 { - status = "okay"; - - /* Audio Codec */ - nau8822_1a: audio-codec@1a { - compatible = "nuvoton,nau8822"; - reg = <0x1a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s1_mclk>; - #sound-dai-cells = <0>; - }; - - /* IO Expander */ - gpio_expander_21: gpio@21 { - compatible = "nxp,pcal6416"; - reg = <0x21>; - #gpio-cells = <2>; - gpio-controller; - }; - - /* Current measurement into module VCC */ - hwmon@40 { - compatible = "ti,ina219"; - reg = <0x40>; - shunt-resistor = <10000>; - }; - - /* Temperature sensor */ - sensor@4f { - compatible = "ti,tmp75c"; - reg = <0x4f>; - }; - - /* EEPROM */ - eeprom@57 { - compatible = "st,24c02", "atmel,24c02"; - reg = <0x57>; - pagesize = <16>; - }; -}; - -/* Verdin I2C_2_DSI */ -&main_i2c2 { - status = "okay"; -}; - -/* Verdin I2C_4_CSI */ -&main_i2c3 { - status = "okay"; -}; - -/* Verdin CAN_1 */ -&main_mcan0 { - status = "okay"; -}; - -/* Verdin SPI_1 */ -&main_spi1 { - status = "okay"; -}; - -/* Verdin UART_3 */ -&main_uart0 { - status = "okay"; -}; - -/* Verdin UART_1, connector X50 through RS485 transceiver. */ -&main_uart1 { - linux,rs485-enabled-at-boot-time; - rs485-rx-during-tx; - status = "okay"; -}; - -/* Verdin I2S_1 */ -&mcasp0 { - status = "okay"; -}; - -&mcu_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_1>, - <&pinctrl_gpio_2>, - <&pinctrl_gpio_3>, - <&pinctrl_gpio_4>; -}; - -/* Verdin I2C_3_HDMI */ -&mcu_i2c0 { - status = "okay"; -}; - -/* Verdin CAN_2 */ -&mcu_mcan0 { - status = "okay"; -}; - -/* Verdin UART_4 */ -&mcu_uart0 { - status = "okay"; -}; - -/* Verdin QSPI_1 */ -&ospi0 { - status = "okay"; -}; - -/* Verdin SD_1 */ -&sdhci1 { - ti,driver-strength-ohm = <33>; - status = "okay"; -}; - -/* Verdin USB_1 */ -&usbss0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -/* Verdin USB_2 */ -&usbss1 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -/* Verdin CTRL_WAKE1_MICO# */ -&verdin_gpio_keys { - status = "okay"; -}; - -/* Verdin UART_2 */ -&wkup_uart0 { - /* FIXME: WKUP UART0 is used by DM firmware */ - status = "reserved"; -}; diff --git a/arch/arm/dts/k3-am62-verdin-wifi.dtsi b/arch/arm/dts/k3-am62-verdin-wifi.dtsi deleted file mode 100644 index a6808b10c7b..00000000000 --- a/arch/arm/dts/k3-am62-verdin-wifi.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2023 Toradex - * - * Common dtsi for Verdin AM62 SoM WB variant - * - * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 - */ - -/ { - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_en>; - reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_LOW>; - }; -}; - -/* On-module Wi-Fi */ -&sdhci2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci2>; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - mmc-pwrseq = <&wifi_pwrseq>; - non-removable; - ti,fails-without-test-cd; - ti,driver-strength-ohm = <50>; - vmmc-supply = <®_3v3>; - status = "okay"; -}; - -/* On-module Bluetooth */ -&main_uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "nxp,88w8987-bt"; - fw-init-baudrate = <3000000>; - }; -}; diff --git a/arch/arm/dts/k3-am62-verdin.dtsi b/arch/arm/dts/k3-am62-verdin.dtsi deleted file mode 100644 index 5db52f23725..00000000000 --- a/arch/arm/dts/k3-am62-verdin.dtsi +++ /dev/null @@ -1,1443 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2023 Toradex - * - * Common dtsi for Verdin AM62 SoM - * - * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/net/ti-dp83867.h> - -/ { - chosen { - stdout-path = "serial2:115200n8"; - }; - - aliases { - can0 = &main_mcan0; - can1 = &mcu_mcan0; - ethernet0 = &cpsw_port1; - ethernet1 = &cpsw_port2; - i2c0 = &main_i2c0; - i2c1 = &main_i2c1; - i2c2 = &main_i2c2; - i2c3 = &mcu_i2c0; - i2c4 = &main_i2c3; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - mmc2 = &sdhci2; - rtc0 = &rtc_i2c; - rtc1 = &wkup_rtc0; - serial0 = &main_uart1; - serial1 = &wkup_uart0; - serial2 = &main_uart0; - serial3 = &mcu_uart0; - serial4 = &main_uart5; - usb0 = &usb0; - usb1 = &usb1; - }; - - verdin_gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; - status = "disabled"; - - verdin_key_wakeup: key-wakeup { - debounce-interval = <10>; - /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ - gpios = <&main_gpio0 32 GPIO_ACTIVE_LOW>; - label = "Wake-Up"; - linux,code = <KEY_WAKEUP>; - wakeup-source; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0x00000000 0x40000000>; /* 1G RAM */ - }; - - opp-table { - /* Add 1.4GHz OPP. Requires VDD_CORE to be at 0.85V */ - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-supported-hw = <0x01 0x0004>; - clock-latency-ns = <6000000>; - }; - }; - - /* Module Power Supply */ - reg_vsodimm: regulator-vsodimm { - compatible = "regulator-fixed"; - regulator-name = "+V_SODIMM"; - }; - - /* Non PMIC On-module Supplies */ - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "On-module +V3.3"; - vin-supply = <®_vsodimm>; - }; - - reg_1v2_dsi: regulator-1v2-dsi { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1200000>; - regulator-min-microvolt = <1200000>; - regulator-name = "On-module +V1.2_DSI"; - vin-supply = <®_1v8>; - }; - - /* Enabled by +V1.2_DSI */ - reg_1v8_dsi: regulator-1v8-dsi { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-module +V1.8_DSI"; - vin-supply = <®_1v8>; - }; - - /* Enabled by +V2.5_ETH */ - reg_1v0_eth: regulator-1v0-eth { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1000000>; - regulator-min-microvolt = <1000000>; - regulator-name = "On-module +V1.0_ETH"; - vin-supply = <®_1v8>; - }; - - /* Enabled by +V2.5_ETH */ - reg_1v8_eth: regulator-1v8-eth { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-module +V1.8_ETH"; - vin-supply = <®_1v8>; - }; - - /* Verdin SD_1 Power Supply */ - reg_sdhc1_vmmc: regulator-sdhci1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1_pwr_en>; - enable-active-high; - /* Verdin SD_1_PWR_EN (SODIMM 76) */ - gpio = <&main_gpio0 29 GPIO_ACTIVE_HIGH>; - off-on-delay-us = <100000>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_SD"; - startup-delay-us = <2000>; - }; - - reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vsel_sd>; - /* PMIC_VSEL_SD */ - gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; - regulator-name = "LDO1-VSEL-SD (PMIC)"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - states = <1800000 0x0>, - <3300000 0x1>; - vin-supply = <®_sd_3v3_1v8>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_tfa_ddr: tfa@9e780000 { - reg = <0x00 0x9e780000 0x00 0x80000>; - alignment = <0x1000>; - no-map; - }; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ - alignment = <0x1000>; - no-map; - }; - - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9db00000 0x00 0xc00000>; - no-map; - }; - }; -}; - -&main_pmx0 { - /* Verdin PWM_1 */ - pinctrl_epwm0_a: main-epwm0a-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01b4, PIN_OUTPUT, 2) /* (A13) SPI0_CS0.EHRPWM0_A */ /* SODIMM 15 */ - >; - }; - - /* Verdin PWM_2 */ - pinctrl_epwm0_b: main-epwm0b-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (C13) SPI0_CS1.EHRPWM0_B */ /* SODIMM 16 */ - >; - }; - - /* Verdin PWM_3_DSI */ - pinctrl_epwm1_a: main-epwm1a-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01bc, PIN_OUTPUT, 2) /* (A14) SPI0_CLK.EHRPWM1_A */ /* SODIMM 19 */ - >; - }; - - /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_clk_gpio: main-gpio0-0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0000, PIN_INPUT, 7) /* (H24) OSPI0_CLK.GPIO0_0 */ /* SODIMM 52 */ - >; - }; - - /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io0_gpio: main-gpio0-3-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */ /* SODIMM 56 */ - >; - }; - - /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io1_gpio: main-gpio0-4-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */ /* SODIMM 58 */ - >; - }; - - /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io2_gpio: main-gpio0-5-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */ /* SODIMM 60 */ - >; - }; - - /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io3_gpio: main-gpio0-6-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */ /* SODIMM 62 */ - >; - }; - - /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_cs_gpio: main-gpio0-11-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */ - >; - }; - - /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_cs2_gpio: main-gpio0-12-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */ /* SODIMM 64 */ - >; - }; - - /* WiFi_W_WKUP_HOST# */ - pinctrl_wifi_w_wkup_host: main-gpio0-15-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x003c, PIN_INPUT, 7) /* (M25) GPMC0_AD0.GPIO0_15 */ /* SODIMM 174 */ - >; - }; - - /* WiFi_BT_WKUP_HOST# */ - pinctrl_bt_wkup_host: main-gpio0-16-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */ /* SODIMM 172 */ - >; - }; - - /* PMIC_ETH_RESET# */ - pinctrl_eth_reset: main-gpio0-17-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0044, PIN_INPUT, 7) /* (N24) GPMC0_AD2.GPIO0_17 */ - >; - }; - - /* PMIC_BRIDGE_RESET# */ - pinctrl_bridge_reset: main-gpio0-20-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0050, PIN_INPUT, 7) /* (P22) GPMC0_AD5.GPIO0_20 */ - >; - }; - - /* PMIC_VSEL_SD */ - pinctrl_vsel_sd: main-gpio0-21-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0054, PIN_INPUT, 7) /* (P21) GPMC0_AD6.GPIO0_21 */ - >; - }; - - /* PMIC_EN_WIFI */ - pinctrl_wifi_en: main-gpio0-22-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0058, PIN_INPUT, 7) /* (R23) GPMC0_AD7.GPIO0_22 */ - >; - }; - - /* PMIC_ETH_INT# */ - pinctrl_eth_int: main-gpio0-25-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0064, PIN_INPUT_PULLUP, 7) /* (T25) GPMC0_AD10.GPIO0_25 */ - >; - }; - - /* WiFi_WKUP_BT# */ - pinctrl_wifi_wkup_bt: main-gpio0-26-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0068, PIN_INPUT, 7) /* (R21) GPMC0_AD11.GPIO0_26 */ - >; - }; - - /* WiFi_WKUP_WLAN# */ - pinctrl_wifi_wkup_wlan: main-gpio0-27-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x006c, PIN_INPUT, 7) /* (T22) GPMC0_AD12.GPIO0_27 */ - >; - }; - - /* Verdin SD_1_PWR_EN */ - pinctrl_sd1_pwr_en: main-gpio0-29-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0074, PIN_INPUT, 7) /* (U25) GPMC0_AD14.GPIO0_29 */ /* SODIMM 76 */ - >; - }; - - /* Verdin DSI_1_BKL_EN */ - pinctrl_dsi1_bkl_en: main-gpio0-30-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0078, PIN_INPUT, 7) /* (U24) GPMC0_AD15.GPIO0_30 */ /* SODIMM 21 */ - >; - }; - - /* Verdin CTRL_SLEEP_MOCI# */ - pinctrl_ctrl_sleep_moci: main-gpio0-31-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x007c, PIN_INPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ /* SODIMM 256 */ - >; - }; - - /* Verdin CTRL_WAKE1_MICO# */ - pinctrl_ctrl_wake1_mico: main-gpio0-32-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ /* SODIMM 252 */ - >; - }; - - /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2 interface) */ - pinctrl_i2s_2_d_out_gpio: main-gpio0-34-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x008c, PIN_INPUT, 7) /* (L25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */ - >; - }; - - /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2 interface) */ - pinctrl_i2s_2_bclk_gpio: main-gpio0-35-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0090, PIN_INPUT, 7) /* (M24) GPMC0_BE0n_CLE.GPIO0_35 */ /* SODIMM 42 */ - >; - }; - - /* Verdin GPIO_6 */ - pinctrl_gpio_6: main-gpio0-36-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0094, PIN_INPUT, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */ /* SODIMM 218 */ - >; - }; - - /* Verdin ETH_2_RGMII_INT# */ - pinctrl_eth2_rgmii_int: main-gpio0-38-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x009c, PIN_INPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ /* SODIMM 189 */ - >; - }; - - /* Verdin GPIO_5 */ - pinctrl_gpio_5: main-gpio0-40-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ /* SODIMM 216 */ - >; - }; - - /* Verdin GPIO_7 */ - pinctrl_gpio_7: main-gpio0-41-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ /* SODIMM 220 */ - >; - }; - - /* Verdin GPIO_8 */ - pinctrl_gpio_8: main-gpio0-42-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ /* SODIMM 222 */ - >; - }; - - /* Verdin USB_1_OC# */ - pinctrl_usb1_oc: main-gpio0-71-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0124, PIN_INPUT, 7) /* (A23) MMC2_SDCD.GPIO0_71 */ /* SODIMM 157 */ - >; - }; - - /* Verdin USB_2_OC# */ - pinctrl_usb2_oc: main-gpio0-72-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0128, PIN_INPUT, 7) /* (B23) MMC2_SDWP.GPIO0_72 */ /* SODIMM 187 */ - >; - }; - - /* Verdin PWM_3_DSI as GPIO */ - pinctrl_pwm3_dsi_gpio: main-gpio1-17-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01bc, PIN_INPUT, 7) /* (A14) SPI0_CLK.GPIO1_17 */ /* SODIMM 19 */ - >; - }; - - /* Verdin QSPI_1_DQS as GPIO */ - pinctrl_qspi1_dqs_gpio: main-gpio1-18-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01c0, PIN_INPUT, 7) /* (B13) SPI0_D0.GPIO1_18 */ /* SODIMM 66 */ - >; - }; - - /* Verdin USB_1_ID */ - pinctrl_usb0_id: main-gpio1-19-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1.GPIO1_19 */ /* SODIMM 161 */ - >; - }; - - /* Verdin DSI_1_INT# (pulled-up as active-low) */ - pinctrl_dsi1_int: main-gpio1-49-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0244, PIN_INPUT_PULLUP, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ /* SODIMM 17 */ - >; - }; - - /* On-module I2C - PMIC_I2C */ - pinctrl_i2c0: main-i2c0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01e0, PIN_INPUT, 0) /* (B16) I2C0_SCL */ /* PMIC_I2C_SCL */ - AM62X_IOPAD(0x01e4, PIN_INPUT, 0) /* (A16) I2C0_SDA */ /* PMIC_I2C_SDA */ - >; - }; - - /* Verdin I2C_1 */ - pinctrl_i2c1: main-i2c1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ /* SODIMM 14 */ - AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ /* SODIMM 12 */ - >; - }; - - /* Verdin I2C_2_DSI */ - pinctrl_i2c2: main-i2c2-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x00b0, PIN_INPUT, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ /* SODIMM 55 */ - AM62X_IOPAD(0x00b4, PIN_INPUT, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ /* SODIMM 53 */ - >; - }; - - /* Verdin I2C_4_CSI */ - pinctrl_i2c3: main-i2c3-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01d0, PIN_INPUT, 2) /* (A15) UART0_CTSn.I2C3_SCL */ /* SODIMM 95 */ - AM62X_IOPAD(0x01d4, PIN_INPUT, 2) /* (B15) UART0_RTSn.I2C3_SDA */ /* SODIMM 93 */ - >; - }; - - /* I2S_1_MCLK */ - pinctrl_i2s1_mclk: main-system-audio-ext-reflock1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ /* SODIMM 38 */ - >; - }; - - /* Verdin I2S_1 */ - pinctrl_mcasp0: main-mcasp0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01a4, PIN_INPUT, 0) /* (B20) MCASP0_ACLKX */ /* SODIMM 30 */ - AM62X_IOPAD(0x01a8, PIN_INPUT, 0) /* (D20) MCASP0_AFSX */ /* SODIMM 32 */ - AM62X_IOPAD(0x01a0, PIN_OUTPUT, 0) /* (E18) MCASP0_AXR0 */ /* SODIMM 34 */ - AM62X_IOPAD(0x019c, PIN_INPUT, 0) /* (B18) MCASP0_AXR1 */ /* SODIMM 36 */ - >; - }; - - /* Verdin I2S_2 */ - pinctrl_mcasp1: main-mcasp1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ /* SODIMM 42 */ - AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ /* SODIMM 44 */ - AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEn.MCASP1_AXR0 */ /* SODIMM 46 */ - AM62X_IOPAD(0x0088, PIN_INPUT, 2) /* (L24) GPMC0_OEn_REn.MCASP1_AXR1 */ /* SODIMM 48 */ - >; - }; - - /* Verdin CAN_1 */ - pinctrl_mcan0: main-mcan0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ /* SODIMM 22 */ - AM62X_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ /* SODIMM 20 */ - >; - }; - - /* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ - pinctrl_mdio: main-mdio1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ /* ETH_1_MDC, SODIMM 193 */ - AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ /* ETH_1_MDIO, SODIMM 191 */ - >; - }; - - /* On-module eMMC */ - pinctrl_sdhci0: main-mmc0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ - AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ - AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ - AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ - AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ - AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ - AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ - AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ - AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ - AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ - >; - }; - - /* Verdin SD_1 */ - pinctrl_sdhci1: main-mmc1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ /* SODIMM 74 */ - AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ /* SODIMM 78 */ - AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ /* SODIMM 80 */ - AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ /* SODIMM 82 */ - AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ /* SODIMM 70 */ - AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ /* SODIMM 72 */ - AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ /* SODIMM 84 */ - >; - }; - - /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */ - pinctrl_sdhci2: main-mmc2-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ /* WiFi_SDIO_CMD */ - AM62X_IOPAD(0x118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ /* WiFi_SDIO_CLK */ - AM62X_IOPAD(0x114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */ /* WiFi_SDIO_DATA0 */ - AM62X_IOPAD(0x110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */ /* WiFi_SDIO_DATA1 */ - AM62X_IOPAD(0x10c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */ /* WiFi_SDIO_DATA2 */ - AM62X_IOPAD(0x108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */ /* WiFi_SDIO_DATA3 */ - AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */ - >; - }; - - /* Verdin QSPI_1 */ - pinctrl_ospi0: main-ospi0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ /* SODIMM 52 */ - AM62X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ /* SODIMM 54 */ - AM62X_IOPAD(0x0030, PIN_OUTPUT, 0) /* (G21) OSPI0_CSn1 */ /* SODIMM 64 */ - AM62X_IOPAD(0x000c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ /* SODIMM 56 */ - AM62X_IOPAD(0x0010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ /* SODIMM 58 */ - AM62X_IOPAD(0x0014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ /* SODIMM 60 */ - AM62X_IOPAD(0x0018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ /* SODIMM 62 */ - >; - }; - - /* Verdin ETH_1 RGMII (On-module PHY) */ - pinctrl_rgmii1: main-rgmii1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ - AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ - AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ - AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ - AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ - AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ - AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ - AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ - AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ - AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ - AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ - AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ - >; - }; - - /* Verdin ETH_2 RGMII */ - pinctrl_rgmii2: main-rgmii2-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ /* SODIMM 201 */ - AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ /* SODIMM 203 */ - AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ /* SODIMM 205 */ - AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ /* SODIMM 207 */ - AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ /* SODIMM 197 */ - AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ /* SODIMM 199 */ - AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ /* SODIMM 221 */ - AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ /* SODIMM 219 */ - AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ /* SODIMM 217 */ - AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ /* SODIMM 215 */ - AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ /* SODIMM 213 */ - AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ /* SODIMM 211 */ - >; - }; - - /* Verdin SPI_1 */ - pinctrl_spi1: main-spi1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0020, PIN_INPUT, 1) /* (J25) OSPI0_D5.SPI1_CLK */ /* SODIMM 196 */ - AM62X_IOPAD(0x001c, PIN_INPUT, 1) /* (J23) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */ - AM62X_IOPAD(0x0024, PIN_INPUT, 1) /* (H25) OSPI0_D6.SPI1_D0 */ /* SODIMM 200 */ - AM62X_IOPAD(0x0028, PIN_INPUT, 1) /* (J22) OSPI0_D7.SPI1_D1 */ /* SODIMM 198 */ - >; - }; - - /* ETH_25MHz_CLK */ - pinctrl_eth_clock: main-system-clkout0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01f0, PIN_OUTPUT_PULLUP, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */ - >; - }; - - /* PMIC_EXTINT# */ - pinctrl_pmic_extint: main-system-extint-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */ - >; - }; - - /* Verdin UART_3, used as the Linux console */ - pinctrl_uart0: main-uart0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x1c8, PIN_INPUT_PULLUP, 0) /* (D14) UART0_RXD */ /* SODIMM 147 */ - AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ /* SODIMM 149 */ - >; - }; - - /* Verdin UART_1 */ - pinctrl_uart1: main-uart1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0194, PIN_INPUT_PULLUP, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ /* SODIMM 135 */ - AM62X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ /* SODIMM 133 */ - AM62X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ /* SODIMM 129 */ - AM62X_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ /* SODIMM 131 */ - >; - }; - - /* Bluetooth on WB SKUs, module-specific UART otherwise */ - pinctrl_uart5: main-uart5-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0008, PIN_INPUT_PULLUP, 5) /* (J24) OSPI0_DQS.UART5_CTSn */ /* WiFi_UART_CTS */ - AM62X_IOPAD(0x0004, PIN_OUTPUT, 5) /* (G25) OSPI0_LBCLKO.UART5_RTSn */ /* WiFi_UART_RTS */ - AM62X_IOPAD(0x0034, PIN_INPUT_PULLUP, 5) /* (H21) OSPI0_CSn2.UART5_RXD */ /* WiFi_UART_RXD */ - AM62X_IOPAD(0x0038, PIN_OUTPUT, 5) /* (E24) OSPI0_CSn3.UART5_TXD */ /* WiFi_UART_TXD */ - >; - }; - - /* Verdin USB_1 */ - pinctrl_usb0: main-usb0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0254, PIN_OUTPUT, 0) /* (C20) USB0_DRVVBUS */ /* SODIMM 155 */ - >; - }; - - /* Verdin USB_2 */ - pinctrl_usb1: main-usb1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ /* SODIMM 185 */ - >; - }; - - /* DSS VOUT0 RGB */ - pinctrl_parallel_rgb: main-vout-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ - AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ - AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ - AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ - AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ - AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ - AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ - AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ - AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ - AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ - AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ - AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ - AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ - AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ - AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ - AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ - AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ - AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ - AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ - AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ - AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */ - AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ - >; - }; -}; - -&mcu_pmx0 { - /* Verdin PCIE_1_RESET# */ - pinctrl_pcie_1_reset: mcu-gpio0-0-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0000, PIN_INPUT, 7) /* (E8) MCU_SPI0_CS0.MCU_GPIO0_0 */ /* SODIMM 244 */ - >; - }; - - /* Verdin GPIO_1 */ - pinctrl_gpio_1: mcu-gpio0-1-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0004, PIN_INPUT, 7) /* (B8) MCU_SPI0_CS1.MCU_GPIO0_1 */ /* SODIMM 206 */ - >; - }; - - /* Verdin GPIO_2 */ - pinctrl_gpio_2: mcu-gpio0-2-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0008, PIN_INPUT, 7) /* (A7) MCU_SPI0_CLK.MCU_GPIO0_2 */ /* SODIMM 208 */ - >; - }; - - /* Verdin GPIO_3 */ - pinctrl_gpio_3: mcu-gpio0-3-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x000c, PIN_INPUT, 7) /* (D9) MCU_SPI0_D0.MCU_GPIO0_3 */ /* SODIMM 210 */ - >; - }; - - /* Verdin GPIO_4 */ - pinctrl_gpio_4: mcu-gpio0-4-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0010, PIN_INPUT, 7) /* (C9) MCU_SPI0_D1.MCU_GPIO0_4 */ /* SODIMM 212 */ - >; - }; - - /* Verdin I2C_3_HDMI */ - pinctrl_mcu_i2c0: mcu-i2c0-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */ /* SODIMM 59 */ - AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ /* SODIMM 57 */ - >; - }; - - /* Verdin CAN_2 */ - pinctrl_mcu_mcan0: mcu-mcan0-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ /* SODIMM 26 */ - AM62X_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ /* SODIMM 24 */ - >; - }; - - /* Verdin UART_4 - Reserved to Cortex-M4 */ - pinctrl_mcu_uart0: mcu-uart0-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0014, PIN_INPUT_PULLUP, 0) /* (B5) MCU_UART0_RXD */ /* SODIMM 151 */ - AM62X_MCU_IOPAD(0x0018, PIN_OUTPUT, 0) /* (A5) MCU_UART0_TXD */ /* SODIMM 153 */ - >; - }; - - /* Verdin CSI_1_MCLK */ - pinctrl_csi1_mclk: wkup-clkout0-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ /* SODIMM 91 */ - >; - }; - - /* Verdin UART_2 */ - pinctrl_wkup_uart0: wkup-uart0-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x002c, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_UART0_CTSn */ /* SODIMM 143 */ - AM62X_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ /* SODIMM 141 */ - AM62X_MCU_IOPAD(0x0024, PIN_INPUT_PULLUP, 0) /* (B4) WKUP_UART0_RXD */ /* SODIMM 137 */ - AM62X_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ /* SODIMM 139 */ - >; - }; -}; - -/* VERDIN I2S_1_MCLK */ -&audio_refclk1 { - assigned-clock-rates = <25000000>; -}; - -&cpsw3g { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1>; - status = "disabled"; -}; - -/* Verdin ETH_1 (On-module PHY) */ -&cpsw_port1 { - phy-handle = <&cpsw3g_phy0>; - phy-mode = "rgmii-rxid"; - status = "disabled"; -}; - -/* Verdin ETH_2_RGMII */ -&cpsw_port2 { - status = "disabled"; -}; - -/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ -&cpsw3g_mdio { - assigned-clocks = <&k3_clks 157 20>; - assigned-clock-parents = <&k3_clks 157 22>; - assigned-clock-rates = <25000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eth_clock>, <&pinctrl_mdio>; - status = "disabled"; - - cpsw3g_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id2000.a231"; - reg = <0>; - interrupt-parent = <&main_gpio0>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eth_int>, <&pinctrl_eth_reset>; - reset-gpios = <&main_gpio0 17 GPIO_ACTIVE_LOW>; - reset-assert-us = <10>; - reset-deassert-us = <1000>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - }; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_parallel_rgb>; - status = "disabled"; -}; - -&dss_ports { - #address-cells = <1>; - #size-cells = <0>; - - /* VP2: DPI Output */ - port@1 { - reg = <1>; - - dpi_out: endpoint { - remote-endpoint = <&rgb_in>; - }; - }; -}; - -/* Verdin PWM_1, PWM_2 */ -&epwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_epwm0_a>, <&pinctrl_epwm0_b>; - status = "disabled"; -}; - -/* Verdin PWM_3_DSI */ -&epwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_epwm1_a>; - status = "disabled"; -}; - -&main_gpio0 { - gpio-line-names = - "SODIMM_52", /* 0 */ - "", - "", - "SODIMM_56", - "SODIMM_58", - "SODIMM_60", - "SODIMM_62", - "", - "", - "", - "", /* 10 */ - "SODIMM_54", - "SODIMM_64", - "", - "", - "SODIMM_174", - "SODIMM_172", - "", - "", - "", - "", /* 20 */ - "", - "", - "", - "", - "", - "", - "", - "", - "SODIMM_76", - "SODIMM_21", /* 30 */ - "SODIMM_256", - "SODIMM_252", - "", - "SODIMM_46", - "SODIMM_42", - "SODIMM_218", - "", - "SODIMM_189", - "", - "SODIMM_216", /* 40 */ - "SODIMM_220", - "SODIMM_222", - "", - "", - "", - "", - "", - "", - "", - "", /* 50 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 60 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 70 */ - "SODIMM_157", - "SODIMM_187", - "", - "", - "", - "", - "", - "", - "", - "", /* 80 */ - "", - "", - "", - "", - "", - ""; - - verdin_ctrl_sleep_moci: ctrl-sleep-moci-hog { - gpio-hog; - /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ - gpios = <31 GPIO_ACTIVE_HIGH>; - line-name = "CTRL_SLEEP_MOCI#"; - output-high; - }; -}; - -&main_gpio1 { - gpio-line-names = - "", /* 0 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 10 */ - "", - "", - "", - "", - "SODIMM_15", - "SODIMM_16", - "SODIMM_19", - "SODIMM_66", - "SODIMM_161", - "", /* 20 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 30 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 40 */ - "", - "", - "", - "", - "", - "", - "", - "", - "SODIMM_17", - "", /* 50 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 60 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 70 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 80 */ - "", - "", - "", - "", - "", - "", - ""; -}; - -/* On-module I2C - PMIC_I2C */ -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clock-frequency = <400000>; - status = "okay"; - - dsi_bridge: dsi@e { - compatible = "toshiba,tc358778"; - reg = <0xe>; - assigned-clocks = <&k3_clks 157 20>; - assigned-clock-parents = <&k3_clks 157 22>; - assigned-clock-rates = <25000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bridge_reset>; - clocks = <&k3_clks 157 20>; - clock-names = "refclk"; - reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>; - vddc-supply = <®_1v2_dsi>; - vddmipi-supply = <®_1v2_dsi>; - vddio-supply = <®_1v8_dsi>; - status = "disabled"; - - dsi_bridge_ports: ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - rgb_in: endpoint { - data-lines = <18>; - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - }; - }; - }; - - pmic@30 { - compatible = "ti,tps65219"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic_extint>; - interrupt-parent = <&gic500>; - interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - - buck1-supply = <®_vsodimm>; - buck2-supply = <®_vsodimm>; - buck3-supply = <®_vsodimm>; - ldo1-supply = <®_3v3>; - ldo2-supply = <®_1v8>; - ldo3-supply = <®_3v3>; - ldo4-supply = <®_3v3>; - system-power-controller; - ti,power-button; - - regulators { - reg_vdd_core: buck1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <850000>; - regulator-min-microvolt = <850000>; - regulator-name = "+VDD_CORE (PMIC BUCK1)"; - }; - - reg_1v8: buck2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8 (PMIC BUCK2)"; /* On-module and SODIMM 214 */ - }; - - reg_vdd_ddr: buck3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1100000>; - regulator-min-microvolt = <1100000>; - regulator-name = "+VDD_DDR (PMIC BUCK3)"; - }; - - reg_sd_3v3_1v8: ldo1 { - regulator-allow-bypass; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_1.8_SD (PMIC LDO1)"; - }; - - reg_vddr_core: ldo2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <850000>; - regulator-min-microvolt = <850000>; - regulator-name = "+VDDR_CORE (PMIC LDO2)"; - }; - - reg_1v8a: ldo3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8A (PMIC LDO3)"; - }; - - reg_eth_2v5: ldo4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <2500000>; - regulator-min-microvolt = <2500000>; - regulator-name = "+V2.5_ETH (PMIC LDO4)"; - }; - }; - }; - - rtc_i2c: rtc@32 { - compatible = "epson,rx8130"; - reg = <0x32>; - }; - - sensor@48 { - compatible = "ti,tmp1075"; - reg = <0x48>; - }; - - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - /* Verdin PMIC_I2C (ADC_4 - ADC_3) */ - channel@0 { - reg = <0>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin PMIC_I2C (ADC_4 - ADC_1) */ - channel@1 { - reg = <1>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin PMIC_I2C (ADC_3 - ADC_1) */ - channel@2 { - reg = <2>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin PMIC_I2C (ADC_2 - ADC_1) */ - channel@3 { - reg = <3>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin PMIC_I2C ADC_4 */ - channel@4 { - reg = <4>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin PMIC_I2C ADC_3 */ - channel@5 { - reg = <5>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin PMIC_I2C ADC_2 */ - channel@6 { - reg = <6>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin PMIC_I2C ADC_1 */ - channel@7 { - reg = <7>; - ti,datarate = <4>; - ti,gain = <2>; - }; - }; - - eeprom@50 { - compatible = "st,24c02", "atmel,24c02"; - pagesize = <16>; - reg = <0x50>; - }; -}; - -/* Verdin I2C_1 */ -&main_i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "disabled"; -}; - -/* Verdin I2C_2_DSI */ -&main_i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "disabled"; -}; - -/* Verdin I2C_4_CSI */ -&main_i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "disabled"; -}; - -&mailbox0_cluster0 { - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -/* Verdin CAN_1 */ -&main_mcan0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcan0>; - status = "disabled"; -}; - -/* Verdin SPI_1 */ -&main_spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - ti,pindir-d0-out-d1-in; - status = "disabled"; -}; - -/* Verdin UART_3, used as the Linux console */ -&main_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "disabled"; -}; - -/* Verdin UART_1 */ -&main_uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "disabled"; -}; - -/* Verdin I2S_1 */ -&mcasp0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcasp0>; - op-mode = <0>; /* I2S mode */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; - tdm-slots = <2>; - rx-num-evt = <32>; - tx-num-evt = <32>; - #sound-dai-cells = <0>; - status = "disabled"; -}; - -/* Verdin I2S_2 */ -&mcasp1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcasp1>; - op-mode = <0>; /* I2S mode */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; - tdm-slots = <2>; - rx-num-evt = <32>; - tx-num-evt = <32>; - #sound-dai-cells = <0>; - status = "disabled"; -}; - -/* Verdin I2C_3_HDMI */ -&mcu_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_i2c0>; - status = "disabled"; -}; - -&mcu_gpio0 { - gpio-line-names = - "SODIMM_244", - "SODIMM_206", - "SODIMM_208", - "SODIMM_210", - "SODIMM_212", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - ""; -}; - -/* Verdin CAN_2 */ -&mcu_mcan0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_mcan0>; - status = "disabled"; -}; - -/* Verdin UART_4 - Cortex-M4 UART */ -&mcu_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_uart0>; - status = "disabled"; -}; - -/* Verdin QSPI_1 */ -&ospi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ospi0>; - status = "disabled"; -}; - -/* On-module eMMC */ -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci0>; - non-removable; - ti,driver-strength-ohm = <50>; - status = "okay"; -}; - -/* Verdin SD_1 */ -&sdhci1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci1>; - disable-wp; - ti,driver-strength-ohm = <50>; - vmmc-supply = <®_sdhc1_vmmc>; - vqmmc-supply = <®_sdhc1_vqmmc>; - status = "disabled"; -}; - -/* Verdin USB_1 */ -&usbss0 { - ti,vbus-divider; - status = "disabled"; -}; - -/* TODO: role swich using ID pin */ -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb0_id>; - status = "disabled"; -}; - -/* Verdin USB_2 */ -&usbss1 { - ti,vbus-divider; - status = "disabled"; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - dr_mode = "host"; - status = "disabled"; -}; - -/* Verdin UART_2 */ -&wkup_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wkup_uart0>; - status = "disabled"; -}; diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi index a723caa5805..fb2032068d1 100644 --- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi @@ -41,13 +41,6 @@ clock-frequency = <25000000>; }; -&dmsc { - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; -}; - &sd_pins_default { /* Force to use SDCD card detect pin */ pinctrl-single,pins = < @@ -105,8 +98,8 @@ arch = "arm64"; compression = "none"; os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; + load = <CONFIG_K3_OPTEE_LOAD_ADDR>; + entry = <CONFIG_K3_OPTEE_LOAD_ADDR>; tee-os { filename = "tee-raw.bin"; }; diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi index f6138f3058f..94162282068 100644 --- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi @@ -42,13 +42,6 @@ bootph-all; }; -&dmsc { - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; -}; - &fss { bootph-all; }; diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index 5b058bd03a0..dfd38d64f63 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -151,11 +151,107 @@ filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; + + tifsstub-hs { + filename = "tifsstub.bin_hs"; + ti-secure-rom { + content = <&tifsstub_hs_cert>; + core = "secure"; + load = <0x40000>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "custMpk.pem"; + countersign; + tifsstub; + }; + tifsstub_hs_cert: tifsstub-hs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_hs_enc: tifsstub-hs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + + tifsstub-fs { + filename = "tifsstub.bin_fs"; + tifsstub_fs_cert: tifsstub-fs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_fs_enc: tifsstub-fs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + + }; + + tifsstub-gp { + filename = "tifsstub.bin_gp"; + ti-secure-rom { + content = <&tifsstub_gp>; + core = "secure"; + load = <0x60000>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "ti-degenerate-key.pem"; + tifsstub; + }; + tifsstub_gp: tifsstub-gp.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-gp.bin"; + type = "blob-ext"; + optional; + }; + }; + ti-spl { insert-template = <&ti_spl_template>; fit { images { + + tifsstub-hs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-hs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_hs"; + }; + }; + + tifsstub-fs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-fs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_fs"; + }; + }; + + tifsstub-gp { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-gp"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_gp"; + }; + }; + dm { ti-secure { content = <&dm>; @@ -189,7 +285,8 @@ conf-0 { description = "k3-am625-sk"; firmware = "atf"; - loadables = "tee", "dm", "spl"; + loadables = "tee", "tifsstub-hs", "tifsstub-fs", + "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; @@ -247,6 +344,45 @@ fit { images { + tifsstub-hs { + description = "tifsstub"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-hs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_hs"; + }; + }; + + tifsstub-fs { + description = "tifsstub"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-fs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_fs"; + }; + }; + + tifsstub-gp { + description = "tifsstub"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-gp"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_gp"; + }; + }; + dm { ti-dm { filename = "ti-dm.bin"; @@ -270,7 +406,8 @@ conf-0 { description = "k3-am625-sk"; firmware = "atf"; - loadables = "tee", "dm", "spl"; + loadables = "tee", "tifsstub-hs", "tifsstub-fs", + "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi index 4e3704809a6..6f5845024f2 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi @@ -140,7 +140,7 @@ #ifdef CONFIG_TARGET_VERDIN_AM62_A53 -#define SPL_VERDIN_AM62_DTB "spl/dts/k3-am625-verdin-wifi-dev.dtb" +#define SPL_VERDIN_AM62_DTB "spl/dts/ti/k3-am625-verdin-wifi-dev.dtb" #define VERDIN_AM62_DTB "u-boot.dtb" &binman { diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi index 28b697b67ae..7fe7ae41543 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi @@ -85,13 +85,6 @@ bootph-all; }; -&dmsc { - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; -}; - &fss { bootph-all; }; diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev.dts b/arch/arm/dts/k3-am625-verdin-wifi-dev.dts deleted file mode 100644 index 4b657d6d3e0..00000000000 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2023 Toradex - * - * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 - * https://www.toradex.com/products/carrier-board/verdin-development-board-kit - */ - -/dts-v1/; - -#include "k3-am625.dtsi" -#include "k3-am62-verdin.dtsi" -#include "k3-am62-verdin-wifi.dtsi" -#include "k3-am62-verdin-dev.dtsi" - -/ { - model = "Toradex Verdin AM62 WB on Verdin Development Board"; - compatible = "toradex,verdin-am62-wifi-dev", - "toradex,verdin-am62-wifi", - "toradex,verdin-am62", - "ti,am625"; -}; diff --git a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi index 31b89b41748..c42dec16194 100644 --- a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi @@ -119,10 +119,6 @@ &dmsc { bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; }; &vdd_mmc1 { diff --git a/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi new file mode 100644 index 00000000000..f6643520153 --- /dev/null +++ b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi @@ -0,0 +1,2800 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This file was generated with the + * AM62Px SysConfig DDR Subsystem Register Configuration Tool v0.10.02 + * Thu Jan 25 2024 10:43:46 GMT-0600 (Central Standard Time) + * DDR Type: LPDDR4 + * F0 = 50MHz F1 = NA F2 = 1600MHz + * Density (per channel): 16Gb + * Number of Ranks: 2 + */ + +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS_PLL_FREQUENCY_1 800000000 +#define DDRSS_PLL_FREQUENCY_2 800000000 +#define DDRSS_SDRAM_IDX 17 +#define DDRSS_REGION_IDX 17 + +#define DDRSS_CTL_0_DATA 0x00000B00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x00002710 +#define DDRSS_CTL_8_DATA 0x000186A0 +#define DDRSS_CTL_9_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_11_DATA 0x0004E200 +#define DDRSS_CTL_12_DATA 0x0030D400 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000C80 +#define DDRSS_CTL_15_DATA 0x0004E200 +#define DDRSS_CTL_16_DATA 0x0030D400 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000C80 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01010100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x0000000A +#define DDRSS_CTL_24_DATA 0x000186A0 +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00020200 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00004040 +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x00000000 +#define DDRSS_CTL_39_DATA 0x00000000 +#define DDRSS_CTL_40_DATA 0x0000040C +#define DDRSS_CTL_41_DATA 0x00000000 +#define DDRSS_CTL_42_DATA 0x00000E38 +#define DDRSS_CTL_43_DATA 0x00000000 +#define DDRSS_CTL_44_DATA 0x00000E38 +#define DDRSS_CTL_45_DATA 0x00000000 +#define DDRSS_CTL_46_DATA 0x05000804 +#define DDRSS_CTL_47_DATA 0x00000700 +#define DDRSS_CTL_48_DATA 0x09090004 +#define DDRSS_CTL_49_DATA 0x00000303 +#define DDRSS_CTL_50_DATA 0x00620011 +#define DDRSS_CTL_51_DATA 0x09110045 +#define DDRSS_CTL_52_DATA 0x0000421D +#define DDRSS_CTL_53_DATA 0x00620011 +#define DDRSS_CTL_54_DATA 0x09110045 +#define DDRSS_CTL_55_DATA 0x0900421D +#define DDRSS_CTL_56_DATA 0x000A0A09 +#define DDRSS_CTL_57_DATA 0x040006DB +#define DDRSS_CTL_58_DATA 0x090D2005 +#define DDRSS_CTL_59_DATA 0x00001710 +#define DDRSS_CTL_60_DATA 0x0C00DB60 +#define DDRSS_CTL_61_DATA 0x090D200D +#define DDRSS_CTL_62_DATA 0x00001710 +#define DDRSS_CTL_63_DATA 0x0C00DB60 +#define DDRSS_CTL_64_DATA 0x0304200D +#define DDRSS_CTL_65_DATA 0x04050002 +#define DDRSS_CTL_66_DATA 0x1F1E1F1E +#define DDRSS_CTL_67_DATA 0x01010008 +#define DDRSS_CTL_68_DATA 0x043C3C07 +#define DDRSS_CTL_69_DATA 0x03222203 +#define DDRSS_CTL_70_DATA 0x00002222 +#define DDRSS_CTL_71_DATA 0x00000101 +#define DDRSS_CTL_72_DATA 0x00000000 +#define DDRSS_CTL_73_DATA 0x01000000 +#define DDRSS_CTL_74_DATA 0x00130803 +#define DDRSS_CTL_75_DATA 0x000000BB +#define DDRSS_CTL_76_DATA 0x00000260 +#define DDRSS_CTL_77_DATA 0x00001858 +#define DDRSS_CTL_78_DATA 0x00000260 +#define DDRSS_CTL_79_DATA 0x00001858 +#define DDRSS_CTL_80_DATA 0x00000005 +#define DDRSS_CTL_81_DATA 0x0000000A +#define DDRSS_CTL_82_DATA 0x00000010 +#define DDRSS_CTL_83_DATA 0x00000130 +#define DDRSS_CTL_84_DATA 0x00000304 +#define DDRSS_CTL_85_DATA 0x00000130 +#define DDRSS_CTL_86_DATA 0x00000304 +#define DDRSS_CTL_87_DATA 0x03004000 +#define DDRSS_CTL_88_DATA 0x00001201 +#define DDRSS_CTL_89_DATA 0x000C0005 +#define DDRSS_CTL_90_DATA 0x2108000C +#define DDRSS_CTL_91_DATA 0x0A050521 +#define DDRSS_CTL_92_DATA 0x170C0803 +#define DDRSS_CTL_93_DATA 0x170C0803 +#define DDRSS_CTL_94_DATA 0x03010103 +#define DDRSS_CTL_95_DATA 0x00010301 +#define DDRSS_CTL_96_DATA 0x00140014 +#define DDRSS_CTL_97_DATA 0x026C026C +#define DDRSS_CTL_98_DATA 0x026C026C +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x03030000 +#define DDRSS_CTL_101_DATA 0x05050501 +#define DDRSS_CTL_102_DATA 0x03031804 +#define DDRSS_CTL_103_DATA 0x0C080C08 +#define DDRSS_CTL_104_DATA 0x08030318 +#define DDRSS_CTL_105_DATA 0x030C080C +#define DDRSS_CTL_106_DATA 0x00000303 +#define DDRSS_CTL_107_DATA 0x00000301 +#define DDRSS_CTL_108_DATA 0x00000001 +#define DDRSS_CTL_109_DATA 0x00000000 +#define DDRSS_CTL_110_DATA 0x40020100 +#define DDRSS_CTL_111_DATA 0x00038010 +#define DDRSS_CTL_112_DATA 0x00050004 +#define DDRSS_CTL_113_DATA 0x00000004 +#define DDRSS_CTL_114_DATA 0x00040003 +#define DDRSS_CTL_115_DATA 0x00040005 +#define DDRSS_CTL_116_DATA 0x00030000 +#define DDRSS_CTL_117_DATA 0x00050004 +#define DDRSS_CTL_118_DATA 0x00000004 +#define DDRSS_CTL_119_DATA 0x00002EC0 +#define DDRSS_CTL_120_DATA 0x00002EC0 +#define DDRSS_CTL_121_DATA 0x00002EC0 +#define DDRSS_CTL_122_DATA 0x00002EC0 +#define DDRSS_CTL_123_DATA 0x00002EC0 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000051D +#define DDRSS_CTL_126_DATA 0x00061600 +#define DDRSS_CTL_127_DATA 0x00061600 +#define DDRSS_CTL_128_DATA 0x00061600 +#define DDRSS_CTL_129_DATA 0x00061600 +#define DDRSS_CTL_130_DATA 0x00061600 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x0000AA68 +#define DDRSS_CTL_133_DATA 0x00061600 +#define DDRSS_CTL_134_DATA 0x00061600 +#define DDRSS_CTL_135_DATA 0x00061600 +#define DDRSS_CTL_136_DATA 0x00061600 +#define DDRSS_CTL_137_DATA 0x00061600 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x0000AA68 +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x00000000 +#define DDRSS_CTL_157_DATA 0x00000000 +#define DDRSS_CTL_158_DATA 0x03050000 +#define DDRSS_CTL_159_DATA 0x03080308 +#define DDRSS_CTL_160_DATA 0x00000000 +#define DDRSS_CTL_161_DATA 0x08010000 +#define DDRSS_CTL_162_DATA 0x000E0808 +#define DDRSS_CTL_163_DATA 0x01000000 +#define DDRSS_CTL_164_DATA 0x0E080808 +#define DDRSS_CTL_165_DATA 0x00000000 +#define DDRSS_CTL_166_DATA 0x08080801 +#define DDRSS_CTL_167_DATA 0x0000080E +#define DDRSS_CTL_168_DATA 0x00040003 +#define DDRSS_CTL_169_DATA 0x00000007 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x00000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x01000000 +#define DDRSS_CTL_177_DATA 0x00000000 +#define DDRSS_CTL_178_DATA 0x00001700 +#define DDRSS_CTL_179_DATA 0x0000100E +#define DDRSS_CTL_180_DATA 0x00000002 +#define DDRSS_CTL_181_DATA 0x00000000 +#define DDRSS_CTL_182_DATA 0x00000001 +#define DDRSS_CTL_183_DATA 0x00000002 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00008000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00008000 +#define DDRSS_CTL_188_DATA 0x00000C00 +#define DDRSS_CTL_189_DATA 0x00008000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x00000000 +#define DDRSS_CTL_193_DATA 0x00000000 +#define DDRSS_CTL_194_DATA 0x00000000 +#define DDRSS_CTL_195_DATA 0x0005000A +#define DDRSS_CTL_196_DATA 0x0404000D +#define DDRSS_CTL_197_DATA 0x0000000D +#define DDRSS_CTL_198_DATA 0x00A00140 +#define DDRSS_CTL_199_DATA 0x0C0C0190 +#define DDRSS_CTL_200_DATA 0x00000190 +#define DDRSS_CTL_201_DATA 0x00A00140 +#define DDRSS_CTL_202_DATA 0x0C0C0190 +#define DDRSS_CTL_203_DATA 0x00000190 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000000 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000000 +#define DDRSS_CTL_208_DATA 0x00000004 +#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x00000054 +#define DDRSS_CTL_212_DATA 0x0000002D +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x00000054 +#define DDRSS_CTL_215_DATA 0x0000002D +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000004 +#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x00000054 +#define DDRSS_CTL_221_DATA 0x0000002D +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x00000054 +#define DDRSS_CTL_224_DATA 0x0000002D +#define DDRSS_CTL_225_DATA 0x00000000 +#define DDRSS_CTL_226_DATA 0x00000000 +#define DDRSS_CTL_227_DATA 0x00000029 +#define DDRSS_CTL_228_DATA 0x000000A9 +#define DDRSS_CTL_229_DATA 0x000000A9 +#define DDRSS_CTL_230_DATA 0x00000029 +#define DDRSS_CTL_231_DATA 0x000000A9 +#define DDRSS_CTL_232_DATA 0x000000A9 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0x00000000 +#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00000000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x00000000 +#define DDRSS_CTL_255_DATA 0x00000000 +#define DDRSS_CTL_256_DATA 0x00000000 +#define DDRSS_CTL_257_DATA 0x35003535 +#define DDRSS_CTL_258_DATA 0x00002735 +#define DDRSS_CTL_259_DATA 0x00000027 +#define DDRSS_CTL_260_DATA 0x00000027 +#define DDRSS_CTL_261_DATA 0x00000027 +#define DDRSS_CTL_262_DATA 0x00000027 +#define DDRSS_CTL_263_DATA 0x00000027 +#define DDRSS_CTL_264_DATA 0x00000000 +#define DDRSS_CTL_265_DATA 0x00000000 +#define DDRSS_CTL_266_DATA 0x0000002B +#define DDRSS_CTL_267_DATA 0x0000002B +#define DDRSS_CTL_268_DATA 0x0000002B +#define DDRSS_CTL_269_DATA 0x0000002B +#define DDRSS_CTL_270_DATA 0x0000002B +#define DDRSS_CTL_271_DATA 0x0000002B +#define DDRSS_CTL_272_DATA 0x00000000 +#define DDRSS_CTL_273_DATA 0x00000000 +#define DDRSS_CTL_274_DATA 0x00000015 +#define DDRSS_CTL_275_DATA 0x00000015 +#define DDRSS_CTL_276_DATA 0x00000000 +#define DDRSS_CTL_277_DATA 0x00000015 +#define DDRSS_CTL_278_DATA 0x00000015 +#define DDRSS_CTL_279_DATA 0x00000020 +#define DDRSS_CTL_280_DATA 0x00010000 +#define DDRSS_CTL_281_DATA 0x00000100 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000101 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x00000000 +#define DDRSS_CTL_291_DATA 0x00000000 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x0C181511 +#define DDRSS_CTL_297_DATA 0x00000304 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00000000 +#define DDRSS_CTL_306_DATA 0x00000000 +#define DDRSS_CTL_307_DATA 0x00000000 +#define DDRSS_CTL_308_DATA 0x00000000 +#define DDRSS_CTL_309_DATA 0x00000000 +#define DDRSS_CTL_310_DATA 0x00000000 +#define DDRSS_CTL_311_DATA 0x00020000 +#define DDRSS_CTL_312_DATA 0x00400100 +#define DDRSS_CTL_313_DATA 0x00080032 +#define DDRSS_CTL_314_DATA 0x01000200 +#define DDRSS_CTL_315_DATA 0x06400040 +#define DDRSS_CTL_316_DATA 0x00020030 +#define DDRSS_CTL_317_DATA 0x00400100 +#define DDRSS_CTL_318_DATA 0x00300640 +#define DDRSS_CTL_319_DATA 0x00030000 +#define DDRSS_CTL_320_DATA 0x00500050 +#define DDRSS_CTL_321_DATA 0x00000100 +#define DDRSS_CTL_322_DATA 0x01010000 +#define DDRSS_CTL_323_DATA 0x00000101 +#define DDRSS_CTL_324_DATA 0x1FFF0000 +#define DDRSS_CTL_325_DATA 0x000FFF00 +#define DDRSS_CTL_326_DATA 0x3FFF2000 +#define DDRSS_CTL_327_DATA 0x000FFF00 +#define DDRSS_CTL_328_DATA 0x0B000001 +#define DDRSS_CTL_329_DATA 0x0001FFFF +#define DDRSS_CTL_330_DATA 0x01010101 +#define DDRSS_CTL_331_DATA 0x01010101 +#define DDRSS_CTL_332_DATA 0x00000118 +#define DDRSS_CTL_333_DATA 0x00000C03 +#define DDRSS_CTL_334_DATA 0x00040100 +#define DDRSS_CTL_335_DATA 0x00040100 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x01030303 +#define DDRSS_CTL_339_DATA 0x00000001 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x00000000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x00000000 +#define DDRSS_CTL_361_DATA 0x00000000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0x00000000 +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00000000 +#define DDRSS_CTL_366_DATA 0x00000000 +#define DDRSS_CTL_367_DATA 0x00000000 +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x00000000 +#define DDRSS_CTL_372_DATA 0x00000000 +#define DDRSS_CTL_373_DATA 0x00000000 +#define DDRSS_CTL_374_DATA 0x00000000 +#define DDRSS_CTL_375_DATA 0x00000000 +#define DDRSS_CTL_376_DATA 0x00000000 +#define DDRSS_CTL_377_DATA 0x00000000 +#define DDRSS_CTL_378_DATA 0x00000000 +#define DDRSS_CTL_379_DATA 0x00000000 +#define DDRSS_CTL_380_DATA 0x00000000 +#define DDRSS_CTL_381_DATA 0x00000000 +#define DDRSS_CTL_382_DATA 0x00000000 +#define DDRSS_CTL_383_DATA 0x01000101 +#define DDRSS_CTL_384_DATA 0x01010001 +#define DDRSS_CTL_385_DATA 0x00010101 +#define DDRSS_CTL_386_DATA 0x01080803 +#define DDRSS_CTL_387_DATA 0x05020201 +#define DDRSS_CTL_388_DATA 0x0C081818 +#define DDRSS_CTL_389_DATA 0x0008040C +#define DDRSS_CTL_390_DATA 0x0B100406 +#define DDRSS_CTL_391_DATA 0x0B100406 +#define DDRSS_CTL_392_DATA 0x10100806 +#define DDRSS_CTL_393_DATA 0x01000000 +#define DDRSS_CTL_394_DATA 0x06030601 +#define DDRSS_CTL_395_DATA 0x04000103 +#define DDRSS_CTL_396_DATA 0x1B000004 +#define DDRSS_CTL_397_DATA 0x00000176 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00000200 +#define DDRSS_CTL_400_DATA 0x00000200 +#define DDRSS_CTL_401_DATA 0x00000200 +#define DDRSS_CTL_402_DATA 0x00000693 +#define DDRSS_CTL_403_DATA 0x00000E9C +#define DDRSS_CTL_404_DATA 0x03000202 +#define DDRSS_CTL_405_DATA 0x32200404 +#define DDRSS_CTL_406_DATA 0x000030B0 +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00000200 +#define DDRSS_CTL_409_DATA 0x00000200 +#define DDRSS_CTL_410_DATA 0x00000200 +#define DDRSS_CTL_411_DATA 0x0000DB18 +#define DDRSS_CTL_412_DATA 0x0001E6E0 +#define DDRSS_CTL_413_DATA 0x0F160402 +#define DDRSS_CTL_414_DATA 0x32200A07 +#define DDRSS_CTL_415_DATA 0x000030B0 +#define DDRSS_CTL_416_DATA 0x00000200 +#define DDRSS_CTL_417_DATA 0x00000200 +#define DDRSS_CTL_418_DATA 0x00000200 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x0000DB18 +#define DDRSS_CTL_421_DATA 0x0001E6E0 +#define DDRSS_CTL_422_DATA 0x0F160402 +#define DDRSS_CTL_423_DATA 0x00200A07 +#define DDRSS_CTL_424_DATA 0x00000000 +#define DDRSS_CTL_425_DATA 0x02000A00 +#define DDRSS_CTL_426_DATA 0x00050003 +#define DDRSS_CTL_427_DATA 0x00010101 +#define DDRSS_CTL_428_DATA 0x00010101 +#define DDRSS_CTL_429_DATA 0x00010001 +#define DDRSS_CTL_430_DATA 0x00000101 +#define DDRSS_CTL_431_DATA 0x02000201 +#define DDRSS_CTL_432_DATA 0x02010000 +#define DDRSS_CTL_433_DATA 0x06000200 +#define DDRSS_CTL_434_DATA 0x00001E1E +#define DDRSS_PI_0_DATA 0x00000B00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000002 +#define DDRSS_PI_12_DATA 0x00000005 +#define DDRSS_PI_13_DATA 0x000F0001 +#define DDRSS_PI_14_DATA 0x08000000 +#define DDRSS_PI_15_DATA 0x00010300 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00000000 +#define DDRSS_PI_24_DATA 0x00000000 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x01010000 +#define DDRSS_PI_27_DATA 0x0A000100 +#define DDRSS_PI_28_DATA 0x00000028 +#define DDRSS_PI_29_DATA 0x0F000000 +#define DDRSS_PI_30_DATA 0x00320000 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x01010102 +#define DDRSS_PI_34_DATA 0x00000000 +#define DDRSS_PI_35_DATA 0x00000000 +#define DDRSS_PI_36_DATA 0x00000000 +#define DDRSS_PI_37_DATA 0x00000001 +#define DDRSS_PI_38_DATA 0x000000AA +#define DDRSS_PI_39_DATA 0x00000055 +#define DDRSS_PI_40_DATA 0x000000B5 +#define DDRSS_PI_41_DATA 0x0000004A +#define DDRSS_PI_42_DATA 0x00000056 +#define DDRSS_PI_43_DATA 0x000000A9 +#define DDRSS_PI_44_DATA 0x000000A9 +#define DDRSS_PI_45_DATA 0x000000B5 +#define DDRSS_PI_46_DATA 0x00000000 +#define DDRSS_PI_47_DATA 0x00000000 +#define DDRSS_PI_48_DATA 0x000F0F00 +#define DDRSS_PI_49_DATA 0x00000019 +#define DDRSS_PI_50_DATA 0x000007D0 +#define DDRSS_PI_51_DATA 0x00000300 +#define DDRSS_PI_52_DATA 0x00000000 +#define DDRSS_PI_53_DATA 0x00000000 +#define DDRSS_PI_54_DATA 0x01000000 +#define DDRSS_PI_55_DATA 0x00010101 +#define DDRSS_PI_56_DATA 0x01000000 +#define DDRSS_PI_57_DATA 0x03000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x0000170F +#define DDRSS_PI_60_DATA 0x00000000 +#define DDRSS_PI_61_DATA 0x00000000 +#define DDRSS_PI_62_DATA 0x00000000 +#define DDRSS_PI_63_DATA 0x0A0A140A +#define DDRSS_PI_64_DATA 0x10020101 +#define DDRSS_PI_65_DATA 0x01000210 +#define DDRSS_PI_66_DATA 0x05000404 +#define DDRSS_PI_67_DATA 0x00010001 +#define DDRSS_PI_68_DATA 0x0001000E +#define DDRSS_PI_69_DATA 0x01010F00 +#define DDRSS_PI_70_DATA 0x00010000 +#define DDRSS_PI_71_DATA 0x00000034 +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x0000FFFF +#define DDRSS_PI_75_DATA 0x00000000 +#define DDRSS_PI_76_DATA 0x00000000 +#define DDRSS_PI_77_DATA 0x00000000 +#define DDRSS_PI_78_DATA 0x00000000 +#define DDRSS_PI_79_DATA 0x01000000 +#define DDRSS_PI_80_DATA 0x01010001 +#define DDRSS_PI_81_DATA 0x02000008 +#define DDRSS_PI_82_DATA 0x01000200 +#define DDRSS_PI_83_DATA 0x00000100 +#define DDRSS_PI_84_DATA 0x02000100 +#define DDRSS_PI_85_DATA 0x02000200 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000000 +#define DDRSS_PI_92_DATA 0x00000000 +#define DDRSS_PI_93_DATA 0x00000000 +#define DDRSS_PI_94_DATA 0x00000000 +#define DDRSS_PI_95_DATA 0x00000000 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00000000 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x01000400 +#define DDRSS_PI_100_DATA 0x0E0D0F10 +#define DDRSS_PI_101_DATA 0x080A1413 +#define DDRSS_PI_102_DATA 0x01000009 +#define DDRSS_PI_103_DATA 0x00000302 +#define DDRSS_PI_104_DATA 0x00000008 +#define DDRSS_PI_105_DATA 0x08000000 +#define DDRSS_PI_106_DATA 0x00000100 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x0000AA00 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00010000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000000 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00000000 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x00000008 +#define DDRSS_PI_137_DATA 0x00000000 +#define DDRSS_PI_138_DATA 0x00000000 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x00000000 +#define DDRSS_PI_145_DATA 0x00010000 +#define DDRSS_PI_146_DATA 0x00000000 +#define DDRSS_PI_147_DATA 0x00000000 +#define DDRSS_PI_148_DATA 0x0000000A +#define DDRSS_PI_149_DATA 0x000186A0 +#define DDRSS_PI_150_DATA 0x00000100 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00000000 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x01000000 +#define DDRSS_PI_157_DATA 0x00010003 +#define DDRSS_PI_158_DATA 0x02000101 +#define DDRSS_PI_159_DATA 0x01030001 +#define DDRSS_PI_160_DATA 0x00010400 +#define DDRSS_PI_161_DATA 0x06000105 +#define DDRSS_PI_162_DATA 0x01070001 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00000000 +#define DDRSS_PI_165_DATA 0x00000000 +#define DDRSS_PI_166_DATA 0x00010001 +#define DDRSS_PI_167_DATA 0x00000000 +#define DDRSS_PI_168_DATA 0x00000000 +#define DDRSS_PI_169_DATA 0x00000000 +#define DDRSS_PI_170_DATA 0x00000000 +#define DDRSS_PI_171_DATA 0x00010000 +#define DDRSS_PI_172_DATA 0x00000004 +#define DDRSS_PI_173_DATA 0x00000000 +#define DDRSS_PI_174_DATA 0x00010000 +#define DDRSS_PI_175_DATA 0x00000000 +#define DDRSS_PI_176_DATA 0x00080000 +#define DDRSS_PI_177_DATA 0x00F000F0 +#define DDRSS_PI_178_DATA 0x00202001 +#define DDRSS_PI_179_DATA 0x00000034 +#define DDRSS_PI_180_DATA 0x00000057 +#define DDRSS_PI_181_DATA 0x00020057 +#define DDRSS_PI_182_DATA 0x02000200 +#define DDRSS_PI_183_DATA 0x00000004 +#define DDRSS_PI_184_DATA 0x00000E0C +#define DDRSS_PI_185_DATA 0x000E3800 +#define DDRSS_PI_186_DATA 0x00380000 +#define DDRSS_PI_187_DATA 0x00000013 +#define DDRSS_PI_188_DATA 0x000000BB +#define DDRSS_PI_189_DATA 0x00000260 +#define DDRSS_PI_190_DATA 0x00001858 +#define DDRSS_PI_191_DATA 0x00000260 +#define DDRSS_PI_192_DATA 0x04001858 +#define DDRSS_PI_193_DATA 0x01010404 +#define DDRSS_PI_194_DATA 0x00001501 +#define DDRSS_PI_195_DATA 0x00250025 +#define DDRSS_PI_196_DATA 0x01000100 +#define DDRSS_PI_197_DATA 0x00000100 +#define DDRSS_PI_198_DATA 0x00000000 +#define DDRSS_PI_199_DATA 0x05080803 +#define DDRSS_PI_200_DATA 0x01011818 +#define DDRSS_PI_201_DATA 0x01010101 +#define DDRSS_PI_202_DATA 0x000C0C0A +#define DDRSS_PI_203_DATA 0x00000000 +#define DDRSS_PI_204_DATA 0x00000000 +#define DDRSS_PI_205_DATA 0x04000000 +#define DDRSS_PI_206_DATA 0x0A021010 +#define DDRSS_PI_207_DATA 0x0404020A +#define DDRSS_PI_208_DATA 0x00090031 +#define DDRSS_PI_209_DATA 0x00190041 +#define DDRSS_PI_210_DATA 0x00190041 +#define DDRSS_PI_211_DATA 0x01010101 +#define DDRSS_PI_212_DATA 0x0003000D +#define DDRSS_PI_213_DATA 0x00030190 +#define DDRSS_PI_214_DATA 0x01000190 +#define DDRSS_PI_215_DATA 0x000E000E +#define DDRSS_PI_216_DATA 0x01910100 +#define DDRSS_PI_217_DATA 0x01000191 +#define DDRSS_PI_218_DATA 0x01910191 +#define DDRSS_PI_219_DATA 0x32103200 +#define DDRSS_PI_220_DATA 0x01013210 +#define DDRSS_PI_221_DATA 0x0A070601 +#define DDRSS_PI_222_DATA 0x180F090D +#define DDRSS_PI_223_DATA 0x180F0911 +#define DDRSS_PI_224_DATA 0x000C0011 +#define DDRSS_PI_225_DATA 0x00001000 +#define DDRSS_PI_226_DATA 0x00000C00 +#define DDRSS_PI_227_DATA 0x00001000 +#define DDRSS_PI_228_DATA 0x00000C00 +#define DDRSS_PI_229_DATA 0x02001000 +#define DDRSS_PI_230_DATA 0x001E000D +#define DDRSS_PI_231_DATA 0x001E0190 +#define DDRSS_PI_232_DATA 0x00000190 +#define DDRSS_PI_233_DATA 0x00001900 +#define DDRSS_PI_234_DATA 0x32000056 +#define DDRSS_PI_235_DATA 0x06000101 +#define DDRSS_PI_236_DATA 0x00230204 +#define DDRSS_PI_237_DATA 0x3212005A +#define DDRSS_PI_238_DATA 0x13000101 +#define DDRSS_PI_239_DATA 0x00230A10 +#define DDRSS_PI_240_DATA 0x3212005A +#define DDRSS_PI_241_DATA 0x13000101 +#define DDRSS_PI_242_DATA 0x00000A10 +#define DDRSS_PI_243_DATA 0x05030900 +#define DDRSS_PI_244_DATA 0x00040900 +#define DDRSS_PI_245_DATA 0x0000062B +#define DDRSS_PI_246_DATA 0x20010004 +#define DDRSS_PI_247_DATA 0x0A0A0A03 +#define DDRSS_PI_248_DATA 0x220D0000 +#define DDRSS_PI_249_DATA 0x1F09001E +#define DDRSS_PI_250_DATA 0x0000C570 +#define DDRSS_PI_251_DATA 0x20060045 +#define DDRSS_PI_252_DATA 0x17101718 +#define DDRSS_PI_253_DATA 0x220D0000 +#define DDRSS_PI_254_DATA 0x1F09001E +#define DDRSS_PI_255_DATA 0x0000C570 +#define DDRSS_PI_256_DATA 0x20060045 +#define DDRSS_PI_257_DATA 0x17101718 +#define DDRSS_PI_258_DATA 0x00000000 +#define DDRSS_PI_259_DATA 0x00000176 +#define DDRSS_PI_260_DATA 0x00000E9C +#define DDRSS_PI_261_DATA 0x000030B0 +#define DDRSS_PI_262_DATA 0x0001E6E0 +#define DDRSS_PI_263_DATA 0x000030B0 +#define DDRSS_PI_264_DATA 0x0001E6E0 +#define DDRSS_PI_265_DATA 0x026C0014 +#define DDRSS_PI_266_DATA 0x0303026C +#define DDRSS_PI_267_DATA 0x00000003 +#define DDRSS_PI_268_DATA 0x00000000 +#define DDRSS_PI_269_DATA 0x08030503 +#define DDRSS_PI_270_DATA 0x00000803 +#define DDRSS_PI_271_DATA 0x00002710 +#define DDRSS_PI_272_DATA 0x000186A0 +#define DDRSS_PI_273_DATA 0x00000005 +#define DDRSS_PI_274_DATA 0x00000064 +#define DDRSS_PI_275_DATA 0x00000014 +#define DDRSS_PI_276_DATA 0x0004E200 +#define DDRSS_PI_277_DATA 0x000186A0 +#define DDRSS_PI_278_DATA 0x00000005 +#define DDRSS_PI_279_DATA 0x00000C80 +#define DDRSS_PI_280_DATA 0x0000026C +#define DDRSS_PI_281_DATA 0x0004E200 +#define DDRSS_PI_282_DATA 0x000186A0 +#define DDRSS_PI_283_DATA 0x00000005 +#define DDRSS_PI_284_DATA 0x00000C80 +#define DDRSS_PI_285_DATA 0x0100026C +#define DDRSS_PI_286_DATA 0x00320040 +#define DDRSS_PI_287_DATA 0x00010008 +#define DDRSS_PI_288_DATA 0x06400040 +#define DDRSS_PI_289_DATA 0x00010030 +#define DDRSS_PI_290_DATA 0x06400040 +#define DDRSS_PI_291_DATA 0x00000330 +#define DDRSS_PI_292_DATA 0x00280050 +#define DDRSS_PI_293_DATA 0x03040404 +#define DDRSS_PI_294_DATA 0x00000303 +#define DDRSS_PI_295_DATA 0x01010000 +#define DDRSS_PI_296_DATA 0x04040202 +#define DDRSS_PI_297_DATA 0x67670808 +#define DDRSS_PI_298_DATA 0x67676767 +#define DDRSS_PI_299_DATA 0x67676767 +#define DDRSS_PI_300_DATA 0x67676767 +#define DDRSS_PI_301_DATA 0x00006767 +#define DDRSS_PI_302_DATA 0x00000000 +#define DDRSS_PI_303_DATA 0x00000000 +#define DDRSS_PI_304_DATA 0x00000000 +#define DDRSS_PI_305_DATA 0x00000000 +#define DDRSS_PI_306_DATA 0x55000000 +#define DDRSS_PI_307_DATA 0x00000000 +#define DDRSS_PI_308_DATA 0x3C00005A +#define DDRSS_PI_309_DATA 0x00005500 +#define DDRSS_PI_310_DATA 0x00005A00 +#define DDRSS_PI_311_DATA 0x0055003C +#define DDRSS_PI_312_DATA 0x00000000 +#define DDRSS_PI_313_DATA 0x3C00005A +#define DDRSS_PI_314_DATA 0x00005500 +#define DDRSS_PI_315_DATA 0x00005A00 +#define DDRSS_PI_316_DATA 0x1716153C +#define DDRSS_PI_317_DATA 0x13121118 +#define DDRSS_PI_318_DATA 0x06050414 +#define DDRSS_PI_319_DATA 0x02010007 +#define DDRSS_PI_320_DATA 0x00000003 +#define DDRSS_PI_321_DATA 0x00000000 +#define DDRSS_PI_322_DATA 0x00000000 +#define DDRSS_PI_323_DATA 0x01000000 +#define DDRSS_PI_324_DATA 0x04020201 +#define DDRSS_PI_325_DATA 0x00080804 +#define DDRSS_PI_326_DATA 0x00000000 +#define DDRSS_PI_327_DATA 0x00000000 +#define DDRSS_PI_328_DATA 0x00000000 +#define DDRSS_PI_329_DATA 0x00000004 +#define DDRSS_PI_330_DATA 0x00000000 +#define DDRSS_PI_331_DATA 0x00000029 +#define DDRSS_PI_332_DATA 0x00000000 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x00000000 +#define DDRSS_PI_335_DATA 0x20002B27 +#define DDRSS_PI_336_DATA 0x00000000 +#define DDRSS_PI_337_DATA 0x00000054 +#define DDRSS_PI_338_DATA 0x0000002D +#define DDRSS_PI_339_DATA 0x000000A9 +#define DDRSS_PI_340_DATA 0x00000000 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x35000000 +#define DDRSS_PI_343_DATA 0x20152B27 +#define DDRSS_PI_344_DATA 0x00000000 +#define DDRSS_PI_345_DATA 0x00000054 +#define DDRSS_PI_346_DATA 0x0000002D +#define DDRSS_PI_347_DATA 0x000000A9 +#define DDRSS_PI_348_DATA 0x00000000 +#define DDRSS_PI_349_DATA 0x00000000 +#define DDRSS_PI_350_DATA 0x35000000 +#define DDRSS_PI_351_DATA 0x20152B27 +#define DDRSS_PI_352_DATA 0x00000000 +#define DDRSS_PI_353_DATA 0x00000004 +#define DDRSS_PI_354_DATA 0x00000000 +#define DDRSS_PI_355_DATA 0x00000029 +#define DDRSS_PI_356_DATA 0x00000000 +#define DDRSS_PI_357_DATA 0x00000000 +#define DDRSS_PI_358_DATA 0x00000000 +#define DDRSS_PI_359_DATA 0x20002B27 +#define DDRSS_PI_360_DATA 0x00000000 +#define DDRSS_PI_361_DATA 0x00000054 +#define DDRSS_PI_362_DATA 0x0000002D +#define DDRSS_PI_363_DATA 0x000000A9 +#define DDRSS_PI_364_DATA 0x00000000 +#define DDRSS_PI_365_DATA 0x00000000 +#define DDRSS_PI_366_DATA 0x35000000 +#define DDRSS_PI_367_DATA 0x20152B27 +#define DDRSS_PI_368_DATA 0x00000000 +#define DDRSS_PI_369_DATA 0x00000054 +#define DDRSS_PI_370_DATA 0x0000002D +#define DDRSS_PI_371_DATA 0x000000A9 +#define DDRSS_PI_372_DATA 0x00000000 +#define DDRSS_PI_373_DATA 0x00000000 +#define DDRSS_PI_374_DATA 0x35000000 +#define DDRSS_PI_375_DATA 0x20152B27 +#define DDRSS_PI_376_DATA 0x00000000 +#define DDRSS_PI_377_DATA 0x00000004 +#define DDRSS_PI_378_DATA 0x00000000 +#define DDRSS_PI_379_DATA 0x00000029 +#define DDRSS_PI_380_DATA 0x00000000 +#define DDRSS_PI_381_DATA 0x00000000 +#define DDRSS_PI_382_DATA 0x00000000 +#define DDRSS_PI_383_DATA 0x20002B27 +#define DDRSS_PI_384_DATA 0x00000000 +#define DDRSS_PI_385_DATA 0x00000054 +#define DDRSS_PI_386_DATA 0x0000002D +#define DDRSS_PI_387_DATA 0x000000A9 +#define DDRSS_PI_388_DATA 0x00000000 +#define DDRSS_PI_389_DATA 0x00000000 +#define DDRSS_PI_390_DATA 0x35000000 +#define DDRSS_PI_391_DATA 0x20152B27 +#define DDRSS_PI_392_DATA 0x00000000 +#define DDRSS_PI_393_DATA 0x00000054 +#define DDRSS_PI_394_DATA 0x0000002D +#define DDRSS_PI_395_DATA 0x000000A9 +#define DDRSS_PI_396_DATA 0x00000000 +#define DDRSS_PI_397_DATA 0x00000000 +#define DDRSS_PI_398_DATA 0x35000000 +#define DDRSS_PI_399_DATA 0x20152B27 +#define DDRSS_PI_400_DATA 0x00000000 +#define DDRSS_PI_401_DATA 0x00000004 +#define DDRSS_PI_402_DATA 0x00000000 +#define DDRSS_PI_403_DATA 0x00000029 +#define DDRSS_PI_404_DATA 0x00000000 +#define DDRSS_PI_405_DATA 0x00000000 +#define DDRSS_PI_406_DATA 0x00000000 +#define DDRSS_PI_407_DATA 0x20002B27 +#define DDRSS_PI_408_DATA 0x00000000 +#define DDRSS_PI_409_DATA 0x00000054 +#define DDRSS_PI_410_DATA 0x0000002D +#define DDRSS_PI_411_DATA 0x000000A9 +#define DDRSS_PI_412_DATA 0x00000000 +#define DDRSS_PI_413_DATA 0x00000000 +#define DDRSS_PI_414_DATA 0x35000000 +#define DDRSS_PI_415_DATA 0x20152B27 +#define DDRSS_PI_416_DATA 0x00000000 +#define DDRSS_PI_417_DATA 0x00000054 +#define DDRSS_PI_418_DATA 0x0000002D +#define DDRSS_PI_419_DATA 0x000000A9 +#define DDRSS_PI_420_DATA 0x00000000 +#define DDRSS_PI_421_DATA 0x00000000 +#define DDRSS_PI_422_DATA 0x35000000 +#define DDRSS_PI_423_DATA 0x20152B27 +#define DDRSS_PHY_0_DATA 0x04F00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00030200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x01030000 +#define DDRSS_PHY_6_DATA 0x00010000 +#define DDRSS_PHY_7_DATA 0x01030004 +#define DDRSS_PHY_8_DATA 0x01000000 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x00000000 +#define DDRSS_PHY_12_DATA 0x01010000 +#define DDRSS_PHY_13_DATA 0x00010000 +#define DDRSS_PHY_14_DATA 0x00C00001 +#define DDRSS_PHY_15_DATA 0x00CC0008 +#define DDRSS_PHY_16_DATA 0x00660601 +#define DDRSS_PHY_17_DATA 0x00000003 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x00000001 +#define DDRSS_PHY_20_DATA 0x0000AAAA +#define DDRSS_PHY_21_DATA 0x00005555 +#define DDRSS_PHY_22_DATA 0x0000B5B5 +#define DDRSS_PHY_23_DATA 0x00004A4A +#define DDRSS_PHY_24_DATA 0x00005656 +#define DDRSS_PHY_25_DATA 0x0000A9A9 +#define DDRSS_PHY_26_DATA 0x0000B7B7 +#define DDRSS_PHY_27_DATA 0x00004848 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x00000000 +#define DDRSS_PHY_30_DATA 0x08000000 +#define DDRSS_PHY_31_DATA 0x0F000008 +#define DDRSS_PHY_32_DATA 0x00000F0F +#define DDRSS_PHY_33_DATA 0x00E4E400 +#define DDRSS_PHY_34_DATA 0x00071020 +#define DDRSS_PHY_35_DATA 0x000C0020 +#define DDRSS_PHY_36_DATA 0x00062000 +#define DDRSS_PHY_37_DATA 0x00000000 +#define DDRSS_PHY_38_DATA 0x55555555 +#define DDRSS_PHY_39_DATA 0xAAAAAAAA +#define DDRSS_PHY_40_DATA 0x55555555 +#define DDRSS_PHY_41_DATA 0xAAAAAAAA +#define DDRSS_PHY_42_DATA 0x00005555 +#define DDRSS_PHY_43_DATA 0x01000100 +#define DDRSS_PHY_44_DATA 0x00800180 +#define DDRSS_PHY_45_DATA 0x00000001 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000000 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000004 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x00000000 +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x081F07FF +#define DDRSS_PHY_75_DATA 0x10200080 +#define DDRSS_PHY_76_DATA 0x00000008 +#define DDRSS_PHY_77_DATA 0x00000401 +#define DDRSS_PHY_78_DATA 0x00000000 +#define DDRSS_PHY_79_DATA 0x01CC0B01 +#define DDRSS_PHY_80_DATA 0x1003CC0B +#define DDRSS_PHY_81_DATA 0x20000140 +#define DDRSS_PHY_82_DATA 0x07FF0200 +#define DDRSS_PHY_83_DATA 0x0000DD01 +#define DDRSS_PHY_84_DATA 0x00100303 +#define DDRSS_PHY_85_DATA 0x00000000 +#define DDRSS_PHY_86_DATA 0x00000000 +#define DDRSS_PHY_87_DATA 0x00031000 +#define DDRSS_PHY_88_DATA 0x00100010 +#define DDRSS_PHY_89_DATA 0x00100010 +#define DDRSS_PHY_90_DATA 0x00100010 +#define DDRSS_PHY_91_DATA 0x00100010 +#define DDRSS_PHY_92_DATA 0x02000010 +#define DDRSS_PHY_93_DATA 0x00000004 +#define DDRSS_PHY_94_DATA 0x51516042 +#define DDRSS_PHY_95_DATA 0x31C06000 +#define DDRSS_PHY_96_DATA 0x07AB0340 +#define DDRSS_PHY_97_DATA 0x00C0C001 +#define DDRSS_PHY_98_DATA 0x0B000000 +#define DDRSS_PHY_99_DATA 0x000B0A0A +#define DDRSS_PHY_100_DATA 0x42100010 +#define DDRSS_PHY_101_DATA 0x010C073E +#define DDRSS_PHY_102_DATA 0x000F0C2D +#define DDRSS_PHY_103_DATA 0x01000140 +#define DDRSS_PHY_104_DATA 0x00F50120 +#define DDRSS_PHY_105_DATA 0x00000C00 +#define DDRSS_PHY_106_DATA 0x00000299 +#define DDRSS_PHY_107_DATA 0x00030200 +#define DDRSS_PHY_108_DATA 0x02800000 +#define DDRSS_PHY_109_DATA 0x80800000 +#define DDRSS_PHY_110_DATA 0x000B2010 +#define DDRSS_PHY_111_DATA 0x32570186 +#define DDRSS_PHY_112_DATA 0x00000004 +#define DDRSS_PHY_113_DATA 0x04190419 +#define DDRSS_PHY_114_DATA 0x04190419 +#define DDRSS_PHY_115_DATA 0x04190419 +#define DDRSS_PHY_116_DATA 0x04190419 +#define DDRSS_PHY_117_DATA 0x00000419 +#define DDRSS_PHY_118_DATA 0x0000A000 +#define DDRSS_PHY_119_DATA 0x00A000A0 +#define DDRSS_PHY_120_DATA 0x00A000A0 +#define DDRSS_PHY_121_DATA 0x00A000A0 +#define DDRSS_PHY_122_DATA 0x00A000A0 +#define DDRSS_PHY_123_DATA 0x00A000A0 +#define DDRSS_PHY_124_DATA 0x00A000A0 +#define DDRSS_PHY_125_DATA 0x00A000A0 +#define DDRSS_PHY_126_DATA 0x00A000A0 +#define DDRSS_PHY_127_DATA 0x01E600A0 +#define DDRSS_PHY_128_DATA 0x01000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00080200 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x20202020 +#define DDRSS_PHY_134_DATA 0x20202020 +#define DDRSS_PHY_135_DATA 0xF0F02020 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04F00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01030000 +#define DDRSS_PHY_262_DATA 0x00010000 +#define DDRSS_PHY_263_DATA 0x01030004 +#define DDRSS_PHY_264_DATA 0x01000000 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x00000000 +#define DDRSS_PHY_268_DATA 0x01010000 +#define DDRSS_PHY_269_DATA 0x00010000 +#define DDRSS_PHY_270_DATA 0x00C00001 +#define DDRSS_PHY_271_DATA 0x00CC0008 +#define DDRSS_PHY_272_DATA 0x00660601 +#define DDRSS_PHY_273_DATA 0x00000003 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x00000001 +#define DDRSS_PHY_276_DATA 0x0000AAAA +#define DDRSS_PHY_277_DATA 0x00005555 +#define DDRSS_PHY_278_DATA 0x0000B5B5 +#define DDRSS_PHY_279_DATA 0x00004A4A +#define DDRSS_PHY_280_DATA 0x00005656 +#define DDRSS_PHY_281_DATA 0x0000A9A9 +#define DDRSS_PHY_282_DATA 0x0000B7B7 +#define DDRSS_PHY_283_DATA 0x00004848 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x00000000 +#define DDRSS_PHY_286_DATA 0x08000000 +#define DDRSS_PHY_287_DATA 0x0F000008 +#define DDRSS_PHY_288_DATA 0x00000F0F +#define DDRSS_PHY_289_DATA 0x00E4E400 +#define DDRSS_PHY_290_DATA 0x00071020 +#define DDRSS_PHY_291_DATA 0x000C0020 +#define DDRSS_PHY_292_DATA 0x00062000 +#define DDRSS_PHY_293_DATA 0x00000000 +#define DDRSS_PHY_294_DATA 0x55555555 +#define DDRSS_PHY_295_DATA 0xAAAAAAAA +#define DDRSS_PHY_296_DATA 0x55555555 +#define DDRSS_PHY_297_DATA 0xAAAAAAAA +#define DDRSS_PHY_298_DATA 0x00005555 +#define DDRSS_PHY_299_DATA 0x01000100 +#define DDRSS_PHY_300_DATA 0x00800180 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000000 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000004 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x00000000 +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x081F07FF +#define DDRSS_PHY_331_DATA 0x10200080 +#define DDRSS_PHY_332_DATA 0x00000008 +#define DDRSS_PHY_333_DATA 0x00000401 +#define DDRSS_PHY_334_DATA 0x00000000 +#define DDRSS_PHY_335_DATA 0x01CC0B01 +#define DDRSS_PHY_336_DATA 0x1003CC0B +#define DDRSS_PHY_337_DATA 0x20000140 +#define DDRSS_PHY_338_DATA 0x07FF0200 +#define DDRSS_PHY_339_DATA 0x0000DD01 +#define DDRSS_PHY_340_DATA 0x00100303 +#define DDRSS_PHY_341_DATA 0x00000000 +#define DDRSS_PHY_342_DATA 0x00000000 +#define DDRSS_PHY_343_DATA 0x00031000 +#define DDRSS_PHY_344_DATA 0x00100010 +#define DDRSS_PHY_345_DATA 0x00100010 +#define DDRSS_PHY_346_DATA 0x00100010 +#define DDRSS_PHY_347_DATA 0x00100010 +#define DDRSS_PHY_348_DATA 0x02000010 +#define DDRSS_PHY_349_DATA 0x00000004 +#define DDRSS_PHY_350_DATA 0x51516042 +#define DDRSS_PHY_351_DATA 0x31C06000 +#define DDRSS_PHY_352_DATA 0x07AB0340 +#define DDRSS_PHY_353_DATA 0x00C0C001 +#define DDRSS_PHY_354_DATA 0x0B000000 +#define DDRSS_PHY_355_DATA 0x000B0A0A +#define DDRSS_PHY_356_DATA 0x42100010 +#define DDRSS_PHY_357_DATA 0x010C073E +#define DDRSS_PHY_358_DATA 0x000F0C2D +#define DDRSS_PHY_359_DATA 0x01000140 +#define DDRSS_PHY_360_DATA 0x00F50120 +#define DDRSS_PHY_361_DATA 0x00000C00 +#define DDRSS_PHY_362_DATA 0x00000299 +#define DDRSS_PHY_363_DATA 0x00030200 +#define DDRSS_PHY_364_DATA 0x02800000 +#define DDRSS_PHY_365_DATA 0x80800000 +#define DDRSS_PHY_366_DATA 0x000B2010 +#define DDRSS_PHY_367_DATA 0x17520684 +#define DDRSS_PHY_368_DATA 0x00000003 +#define DDRSS_PHY_369_DATA 0x04190419 +#define DDRSS_PHY_370_DATA 0x04190419 +#define DDRSS_PHY_371_DATA 0x04190419 +#define DDRSS_PHY_372_DATA 0x04190419 +#define DDRSS_PHY_373_DATA 0x00000419 +#define DDRSS_PHY_374_DATA 0x0000A000 +#define DDRSS_PHY_375_DATA 0x00A000A0 +#define DDRSS_PHY_376_DATA 0x00A000A0 +#define DDRSS_PHY_377_DATA 0x00A000A0 +#define DDRSS_PHY_378_DATA 0x00A000A0 +#define DDRSS_PHY_379_DATA 0x00A000A0 +#define DDRSS_PHY_380_DATA 0x00A000A0 +#define DDRSS_PHY_381_DATA 0x00A000A0 +#define DDRSS_PHY_382_DATA 0x00A000A0 +#define DDRSS_PHY_383_DATA 0x01E600A0 +#define DDRSS_PHY_384_DATA 0x01000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00080200 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x20202020 +#define DDRSS_PHY_390_DATA 0x20202020 +#define DDRSS_PHY_391_DATA 0xF0F02020 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x04F00000 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00030200 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x01030000 +#define DDRSS_PHY_518_DATA 0x00010000 +#define DDRSS_PHY_519_DATA 0x01030004 +#define DDRSS_PHY_520_DATA 0x01000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00000000 +#define DDRSS_PHY_524_DATA 0x01010000 +#define DDRSS_PHY_525_DATA 0x00010000 +#define DDRSS_PHY_526_DATA 0x00C00001 +#define DDRSS_PHY_527_DATA 0x00CC0008 +#define DDRSS_PHY_528_DATA 0x00660601 +#define DDRSS_PHY_529_DATA 0x00000003 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000001 +#define DDRSS_PHY_532_DATA 0x0000AAAA +#define DDRSS_PHY_533_DATA 0x00005555 +#define DDRSS_PHY_534_DATA 0x0000B5B5 +#define DDRSS_PHY_535_DATA 0x00004A4A +#define DDRSS_PHY_536_DATA 0x00005656 +#define DDRSS_PHY_537_DATA 0x0000A9A9 +#define DDRSS_PHY_538_DATA 0x0000B7B7 +#define DDRSS_PHY_539_DATA 0x00004848 +#define DDRSS_PHY_540_DATA 0x00000000 +#define DDRSS_PHY_541_DATA 0x00000000 +#define DDRSS_PHY_542_DATA 0x08000000 +#define DDRSS_PHY_543_DATA 0x0F000008 +#define DDRSS_PHY_544_DATA 0x00000F0F +#define DDRSS_PHY_545_DATA 0x00E4E400 +#define DDRSS_PHY_546_DATA 0x00071020 +#define DDRSS_PHY_547_DATA 0x000C0020 +#define DDRSS_PHY_548_DATA 0x00062000 +#define DDRSS_PHY_549_DATA 0x00000000 +#define DDRSS_PHY_550_DATA 0x55555555 +#define DDRSS_PHY_551_DATA 0xAAAAAAAA +#define DDRSS_PHY_552_DATA 0x55555555 +#define DDRSS_PHY_553_DATA 0xAAAAAAAA +#define DDRSS_PHY_554_DATA 0x00005555 +#define DDRSS_PHY_555_DATA 0x01000100 +#define DDRSS_PHY_556_DATA 0x00800180 +#define DDRSS_PHY_557_DATA 0x00000001 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000004 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x081F07FF +#define DDRSS_PHY_587_DATA 0x10200080 +#define DDRSS_PHY_588_DATA 0x00000008 +#define DDRSS_PHY_589_DATA 0x00000401 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x01CC0B01 +#define DDRSS_PHY_592_DATA 0x1003CC0B +#define DDRSS_PHY_593_DATA 0x20000140 +#define DDRSS_PHY_594_DATA 0x07FF0200 +#define DDRSS_PHY_595_DATA 0x0000DD01 +#define DDRSS_PHY_596_DATA 0x00100303 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00031000 +#define DDRSS_PHY_600_DATA 0x00100010 +#define DDRSS_PHY_601_DATA 0x00100010 +#define DDRSS_PHY_602_DATA 0x00100010 +#define DDRSS_PHY_603_DATA 0x00100010 +#define DDRSS_PHY_604_DATA 0x02000010 +#define DDRSS_PHY_605_DATA 0x00000004 +#define DDRSS_PHY_606_DATA 0x51516042 +#define DDRSS_PHY_607_DATA 0x31C06000 +#define DDRSS_PHY_608_DATA 0x07AB0340 +#define DDRSS_PHY_609_DATA 0x00C0C001 +#define DDRSS_PHY_610_DATA 0x0B000000 +#define DDRSS_PHY_611_DATA 0x000B0A0A +#define DDRSS_PHY_612_DATA 0x42100010 +#define DDRSS_PHY_613_DATA 0x010C073E +#define DDRSS_PHY_614_DATA 0x000F0C2D +#define DDRSS_PHY_615_DATA 0x01000140 +#define DDRSS_PHY_616_DATA 0x00F50120 +#define DDRSS_PHY_617_DATA 0x00000C00 +#define DDRSS_PHY_618_DATA 0x00000299 +#define DDRSS_PHY_619_DATA 0x00030200 +#define DDRSS_PHY_620_DATA 0x02800000 +#define DDRSS_PHY_621_DATA 0x80800000 +#define DDRSS_PHY_622_DATA 0x000B2010 +#define DDRSS_PHY_623_DATA 0x07684523 +#define DDRSS_PHY_624_DATA 0x00000001 +#define DDRSS_PHY_625_DATA 0x04190419 +#define DDRSS_PHY_626_DATA 0x04190419 +#define DDRSS_PHY_627_DATA 0x04190419 +#define DDRSS_PHY_628_DATA 0x04190419 +#define DDRSS_PHY_629_DATA 0x00000419 +#define DDRSS_PHY_630_DATA 0x0000A000 +#define DDRSS_PHY_631_DATA 0x00A000A0 +#define DDRSS_PHY_632_DATA 0x00A000A0 +#define DDRSS_PHY_633_DATA 0x00A000A0 +#define DDRSS_PHY_634_DATA 0x00A000A0 +#define DDRSS_PHY_635_DATA 0x00A000A0 +#define DDRSS_PHY_636_DATA 0x00A000A0 +#define DDRSS_PHY_637_DATA 0x00A000A0 +#define DDRSS_PHY_638_DATA 0x00A000A0 +#define DDRSS_PHY_639_DATA 0x01E600A0 +#define DDRSS_PHY_640_DATA 0x01000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00080200 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x20202020 +#define DDRSS_PHY_646_DATA 0x20202020 +#define DDRSS_PHY_647_DATA 0xF0F02020 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x04F00000 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00030200 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x01030000 +#define DDRSS_PHY_774_DATA 0x00010000 +#define DDRSS_PHY_775_DATA 0x01030004 +#define DDRSS_PHY_776_DATA 0x01000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00000000 +#define DDRSS_PHY_780_DATA 0x01010000 +#define DDRSS_PHY_781_DATA 0x00010000 +#define DDRSS_PHY_782_DATA 0x00C00001 +#define DDRSS_PHY_783_DATA 0x00CC0008 +#define DDRSS_PHY_784_DATA 0x00660601 +#define DDRSS_PHY_785_DATA 0x00000003 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000001 +#define DDRSS_PHY_788_DATA 0x0000AAAA +#define DDRSS_PHY_789_DATA 0x00005555 +#define DDRSS_PHY_790_DATA 0x0000B5B5 +#define DDRSS_PHY_791_DATA 0x00004A4A +#define DDRSS_PHY_792_DATA 0x00005656 +#define DDRSS_PHY_793_DATA 0x0000A9A9 +#define DDRSS_PHY_794_DATA 0x0000B7B7 +#define DDRSS_PHY_795_DATA 0x00004848 +#define DDRSS_PHY_796_DATA 0x00000000 +#define DDRSS_PHY_797_DATA 0x00000000 +#define DDRSS_PHY_798_DATA 0x08000000 +#define DDRSS_PHY_799_DATA 0x0F000008 +#define DDRSS_PHY_800_DATA 0x00000F0F +#define DDRSS_PHY_801_DATA 0x00E4E400 +#define DDRSS_PHY_802_DATA 0x00071020 +#define DDRSS_PHY_803_DATA 0x000C0020 +#define DDRSS_PHY_804_DATA 0x00062000 +#define DDRSS_PHY_805_DATA 0x00000000 +#define DDRSS_PHY_806_DATA 0x55555555 +#define DDRSS_PHY_807_DATA 0xAAAAAAAA +#define DDRSS_PHY_808_DATA 0x55555555 +#define DDRSS_PHY_809_DATA 0xAAAAAAAA +#define DDRSS_PHY_810_DATA 0x00005555 +#define DDRSS_PHY_811_DATA 0x01000100 +#define DDRSS_PHY_812_DATA 0x00800180 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000004 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x081F07FF +#define DDRSS_PHY_843_DATA 0x10200080 +#define DDRSS_PHY_844_DATA 0x00000008 +#define DDRSS_PHY_845_DATA 0x00000401 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x01CC0B01 +#define DDRSS_PHY_848_DATA 0x1003CC0B +#define DDRSS_PHY_849_DATA 0x20000140 +#define DDRSS_PHY_850_DATA 0x07FF0200 +#define DDRSS_PHY_851_DATA 0x0000DD01 +#define DDRSS_PHY_852_DATA 0x00100303 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00031000 +#define DDRSS_PHY_856_DATA 0x00100010 +#define DDRSS_PHY_857_DATA 0x00100010 +#define DDRSS_PHY_858_DATA 0x00100010 +#define DDRSS_PHY_859_DATA 0x00100010 +#define DDRSS_PHY_860_DATA 0x02000010 +#define DDRSS_PHY_861_DATA 0x00000004 +#define DDRSS_PHY_862_DATA 0x51516042 +#define DDRSS_PHY_863_DATA 0x31C06000 +#define DDRSS_PHY_864_DATA 0x07AB0340 +#define DDRSS_PHY_865_DATA 0x00C0C001 +#define DDRSS_PHY_866_DATA 0x0B000000 +#define DDRSS_PHY_867_DATA 0x000B0A0A +#define DDRSS_PHY_868_DATA 0x42100010 +#define DDRSS_PHY_869_DATA 0x010C073E +#define DDRSS_PHY_870_DATA 0x000F0C2D +#define DDRSS_PHY_871_DATA 0x01000140 +#define DDRSS_PHY_872_DATA 0x00F50120 +#define DDRSS_PHY_873_DATA 0x00000C00 +#define DDRSS_PHY_874_DATA 0x00000299 +#define DDRSS_PHY_875_DATA 0x00030200 +#define DDRSS_PHY_876_DATA 0x02800000 +#define DDRSS_PHY_877_DATA 0x80800000 +#define DDRSS_PHY_878_DATA 0x000B2010 +#define DDRSS_PHY_879_DATA 0x76158234 +#define DDRSS_PHY_880_DATA 0x00000000 +#define DDRSS_PHY_881_DATA 0x04190419 +#define DDRSS_PHY_882_DATA 0x04190419 +#define DDRSS_PHY_883_DATA 0x04190419 +#define DDRSS_PHY_884_DATA 0x04190419 +#define DDRSS_PHY_885_DATA 0x00000419 +#define DDRSS_PHY_886_DATA 0x0000A000 +#define DDRSS_PHY_887_DATA 0x00A000A0 +#define DDRSS_PHY_888_DATA 0x00A000A0 +#define DDRSS_PHY_889_DATA 0x00A000A0 +#define DDRSS_PHY_890_DATA 0x00A000A0 +#define DDRSS_PHY_891_DATA 0x00A000A0 +#define DDRSS_PHY_892_DATA 0x00A000A0 +#define DDRSS_PHY_893_DATA 0x00A000A0 +#define DDRSS_PHY_894_DATA 0x00A000A0 +#define DDRSS_PHY_895_DATA 0x01E600A0 +#define DDRSS_PHY_896_DATA 0x01000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00080200 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x20202020 +#define DDRSS_PHY_902_DATA 0x20202020 +#define DDRSS_PHY_903_DATA 0xF0F02020 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x00000000 +#define DDRSS_PHY_1045_DATA 0x0000002A +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x00000015 +#define DDRSS_PHY_1048_DATA 0x0000002A +#define DDRSS_PHY_1049_DATA 0x00000033 +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x0000000C +#define DDRSS_PHY_1052_DATA 0x00000033 +#define DDRSS_PHY_1053_DATA 0x0A418820 +#define DDRSS_PHY_1054_DATA 0x003F0000 +#define DDRSS_PHY_1055_DATA 0x000F013F +#define DDRSS_PHY_1056_DATA 0x20202003 +#define DDRSS_PHY_1057_DATA 0x00202020 +#define DDRSS_PHY_1058_DATA 0x20008008 +#define DDRSS_PHY_1059_DATA 0x00000810 +#define DDRSS_PHY_1060_DATA 0x00000F00 +#define DDRSS_PHY_1061_DATA 0x000304CC +#define DDRSS_PHY_1062_DATA 0x03000003 +#define DDRSS_PHY_1063_DATA 0x00030000 +#define DDRSS_PHY_1064_DATA 0x00000300 +#define DDRSS_PHY_1065_DATA 0x00000300 +#define DDRSS_PHY_1066_DATA 0x00000300 +#define DDRSS_PHY_1067_DATA 0x00000300 +#define DDRSS_PHY_1068_DATA 0x42080010 +#define DDRSS_PHY_1069_DATA 0x0000803E +#define DDRSS_PHY_1070_DATA 0x00000001 +#define DDRSS_PHY_1071_DATA 0x01000002 +#define DDRSS_PHY_1072_DATA 0x00008000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00000000 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000100 +#define DDRSS_PHY_1286_DATA 0x00000200 +#define DDRSS_PHY_1287_DATA 0x00000000 +#define DDRSS_PHY_1288_DATA 0x00000000 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00400000 +#define DDRSS_PHY_1292_DATA 0x00000080 +#define DDRSS_PHY_1293_DATA 0x00DCBA98 +#define DDRSS_PHY_1294_DATA 0x03000000 +#define DDRSS_PHY_1295_DATA 0x00200000 +#define DDRSS_PHY_1296_DATA 0x00000000 +#define DDRSS_PHY_1297_DATA 0x00000000 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x00000000 +#define DDRSS_PHY_1300_DATA 0x00000000 +#define DDRSS_PHY_1301_DATA 0x0000002A +#define DDRSS_PHY_1302_DATA 0x00000015 +#define DDRSS_PHY_1303_DATA 0x00000015 +#define DDRSS_PHY_1304_DATA 0x0000002A +#define DDRSS_PHY_1305_DATA 0x00000033 +#define DDRSS_PHY_1306_DATA 0x0000000C +#define DDRSS_PHY_1307_DATA 0x0000000C +#define DDRSS_PHY_1308_DATA 0x00000033 +#define DDRSS_PHY_1309_DATA 0x0A418820 +#define DDRSS_PHY_1310_DATA 0x00000000 +#define DDRSS_PHY_1311_DATA 0x000F0000 +#define DDRSS_PHY_1312_DATA 0x20202003 +#define DDRSS_PHY_1313_DATA 0x00202020 +#define DDRSS_PHY_1314_DATA 0x20008008 +#define DDRSS_PHY_1315_DATA 0x00000810 +#define DDRSS_PHY_1316_DATA 0x00000F00 +#define DDRSS_PHY_1317_DATA 0x000304CC +#define DDRSS_PHY_1318_DATA 0x03000003 +#define DDRSS_PHY_1319_DATA 0x00030000 +#define DDRSS_PHY_1320_DATA 0x00000300 +#define DDRSS_PHY_1321_DATA 0x00000300 +#define DDRSS_PHY_1322_DATA 0x00000300 +#define DDRSS_PHY_1323_DATA 0x00000300 +#define DDRSS_PHY_1324_DATA 0x42080010 +#define DDRSS_PHY_1325_DATA 0x0000803E +#define DDRSS_PHY_1326_DATA 0x00000001 +#define DDRSS_PHY_1327_DATA 0x01000002 +#define DDRSS_PHY_1328_DATA 0x00008000 +#define DDRSS_PHY_1329_DATA 0x00000000 +#define DDRSS_PHY_1330_DATA 0x00000000 +#define DDRSS_PHY_1331_DATA 0x00000000 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000000 +#define DDRSS_PHY_1334_DATA 0x00000000 +#define DDRSS_PHY_1335_DATA 0x00000000 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x00000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x00000000 +#define DDRSS_PHY_1346_DATA 0x00000000 +#define DDRSS_PHY_1347_DATA 0x00000000 +#define DDRSS_PHY_1348_DATA 0x00000000 +#define DDRSS_PHY_1349_DATA 0x00000000 +#define DDRSS_PHY_1350_DATA 0x00000000 +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000000 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x00000000 +#define DDRSS_PHY_1360_DATA 0x00000000 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00000000 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000000 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x00000000 +#define DDRSS_PHY_1372_DATA 0x00000000 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00000000 +#define DDRSS_PHY_1375_DATA 0x00000000 +#define DDRSS_PHY_1376_DATA 0x00000000 +#define DDRSS_PHY_1377_DATA 0x00000000 +#define DDRSS_PHY_1378_DATA 0x00000000 +#define DDRSS_PHY_1379_DATA 0x00000000 +#define DDRSS_PHY_1380_DATA 0x00000000 +#define DDRSS_PHY_1381_DATA 0x00000000 +#define DDRSS_PHY_1382_DATA 0x00000000 +#define DDRSS_PHY_1383_DATA 0x00000000 +#define DDRSS_PHY_1384_DATA 0x00000000 +#define DDRSS_PHY_1385_DATA 0x00000000 +#define DDRSS_PHY_1386_DATA 0x00000000 +#define DDRSS_PHY_1387_DATA 0x00000000 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x00000000 +#define DDRSS_PHY_1390_DATA 0x00000000 +#define DDRSS_PHY_1391_DATA 0x00000000 +#define DDRSS_PHY_1392_DATA 0x00000000 +#define DDRSS_PHY_1393_DATA 0x00000000 +#define DDRSS_PHY_1394_DATA 0x00000000 +#define DDRSS_PHY_1395_DATA 0x00000000 +#define DDRSS_PHY_1396_DATA 0x00000000 +#define DDRSS_PHY_1397_DATA 0x00000000 +#define DDRSS_PHY_1398_DATA 0x00000000 +#define DDRSS_PHY_1399_DATA 0x00000000 +#define DDRSS_PHY_1400_DATA 0x00000000 +#define DDRSS_PHY_1401_DATA 0x00000000 +#define DDRSS_PHY_1402_DATA 0x00000000 +#define DDRSS_PHY_1403_DATA 0x00000000 +#define DDRSS_PHY_1404_DATA 0x00000000 +#define DDRSS_PHY_1405_DATA 0x00000000 +#define DDRSS_PHY_1406_DATA 0x00000000 +#define DDRSS_PHY_1407_DATA 0x00000000 +#define DDRSS_PHY_1408_DATA 0x00000000 +#define DDRSS_PHY_1409_DATA 0x00000000 +#define DDRSS_PHY_1410_DATA 0x00000000 +#define DDRSS_PHY_1411_DATA 0x00000000 +#define DDRSS_PHY_1412_DATA 0x00000000 +#define DDRSS_PHY_1413_DATA 0x00000000 +#define DDRSS_PHY_1414_DATA 0x00000000 +#define DDRSS_PHY_1415_DATA 0x00000000 +#define DDRSS_PHY_1416_DATA 0x00000000 +#define DDRSS_PHY_1417_DATA 0x00000000 +#define DDRSS_PHY_1418_DATA 0x00000000 +#define DDRSS_PHY_1419_DATA 0x00000000 +#define DDRSS_PHY_1420_DATA 0x00000000 +#define DDRSS_PHY_1421_DATA 0x00000000 +#define DDRSS_PHY_1422_DATA 0x00000000 +#define DDRSS_PHY_1423_DATA 0x00000000 +#define DDRSS_PHY_1424_DATA 0x00000000 +#define DDRSS_PHY_1425_DATA 0x00000000 +#define DDRSS_PHY_1426_DATA 0x00000000 +#define DDRSS_PHY_1427_DATA 0x00000000 +#define DDRSS_PHY_1428_DATA 0x00000000 +#define DDRSS_PHY_1429_DATA 0x00000000 +#define DDRSS_PHY_1430_DATA 0x00000000 +#define DDRSS_PHY_1431_DATA 0x00000000 +#define DDRSS_PHY_1432_DATA 0x00000000 +#define DDRSS_PHY_1433_DATA 0x00000000 +#define DDRSS_PHY_1434_DATA 0x00000000 +#define DDRSS_PHY_1435_DATA 0x00000000 +#define DDRSS_PHY_1436_DATA 0x00000000 +#define DDRSS_PHY_1437_DATA 0x00000000 +#define DDRSS_PHY_1438_DATA 0x00000000 +#define DDRSS_PHY_1439_DATA 0x00000000 +#define DDRSS_PHY_1440_DATA 0x00000000 +#define DDRSS_PHY_1441_DATA 0x00000000 +#define DDRSS_PHY_1442_DATA 0x00000000 +#define DDRSS_PHY_1443_DATA 0x00000000 +#define DDRSS_PHY_1444_DATA 0x00000000 +#define DDRSS_PHY_1445_DATA 0x00000000 +#define DDRSS_PHY_1446_DATA 0x00000000 +#define DDRSS_PHY_1447_DATA 0x00000000 +#define DDRSS_PHY_1448_DATA 0x00000000 +#define DDRSS_PHY_1449_DATA 0x00000000 +#define DDRSS_PHY_1450_DATA 0x00000000 +#define DDRSS_PHY_1451_DATA 0x00000000 +#define DDRSS_PHY_1452_DATA 0x00000000 +#define DDRSS_PHY_1453_DATA 0x00000000 +#define DDRSS_PHY_1454_DATA 0x00000000 +#define DDRSS_PHY_1455_DATA 0x00000000 +#define DDRSS_PHY_1456_DATA 0x00000000 +#define DDRSS_PHY_1457_DATA 0x00000000 +#define DDRSS_PHY_1458_DATA 0x00000000 +#define DDRSS_PHY_1459_DATA 0x00000000 +#define DDRSS_PHY_1460_DATA 0x00000000 +#define DDRSS_PHY_1461_DATA 0x00000000 +#define DDRSS_PHY_1462_DATA 0x00000000 +#define DDRSS_PHY_1463_DATA 0x00000000 +#define DDRSS_PHY_1464_DATA 0x00000000 +#define DDRSS_PHY_1465_DATA 0x00000000 +#define DDRSS_PHY_1466_DATA 0x00000000 +#define DDRSS_PHY_1467_DATA 0x00000000 +#define DDRSS_PHY_1468_DATA 0x00000000 +#define DDRSS_PHY_1469_DATA 0x00000000 +#define DDRSS_PHY_1470_DATA 0x00000000 +#define DDRSS_PHY_1471_DATA 0x00000000 +#define DDRSS_PHY_1472_DATA 0x00000000 +#define DDRSS_PHY_1473_DATA 0x00000000 +#define DDRSS_PHY_1474_DATA 0x00000000 +#define DDRSS_PHY_1475_DATA 0x00000000 +#define DDRSS_PHY_1476_DATA 0x00000000 +#define DDRSS_PHY_1477_DATA 0x00000000 +#define DDRSS_PHY_1478_DATA 0x00000000 +#define DDRSS_PHY_1479_DATA 0x00000000 +#define DDRSS_PHY_1480_DATA 0x00000000 +#define DDRSS_PHY_1481_DATA 0x00000000 +#define DDRSS_PHY_1482_DATA 0x00000000 +#define DDRSS_PHY_1483_DATA 0x00000000 +#define DDRSS_PHY_1484_DATA 0x00000000 +#define DDRSS_PHY_1485_DATA 0x00000000 +#define DDRSS_PHY_1486_DATA 0x00000000 +#define DDRSS_PHY_1487_DATA 0x00000000 +#define DDRSS_PHY_1488_DATA 0x00000000 +#define DDRSS_PHY_1489_DATA 0x00000000 +#define DDRSS_PHY_1490_DATA 0x00000000 +#define DDRSS_PHY_1491_DATA 0x00000000 +#define DDRSS_PHY_1492_DATA 0x00000000 +#define DDRSS_PHY_1493_DATA 0x00000000 +#define DDRSS_PHY_1494_DATA 0x00000000 +#define DDRSS_PHY_1495_DATA 0x00000000 +#define DDRSS_PHY_1496_DATA 0x00000000 +#define DDRSS_PHY_1497_DATA 0x00000000 +#define DDRSS_PHY_1498_DATA 0x00000000 +#define DDRSS_PHY_1499_DATA 0x00000000 +#define DDRSS_PHY_1500_DATA 0x00000000 +#define DDRSS_PHY_1501_DATA 0x00000000 +#define DDRSS_PHY_1502_DATA 0x00000000 +#define DDRSS_PHY_1503_DATA 0x00000000 +#define DDRSS_PHY_1504_DATA 0x00000000 +#define DDRSS_PHY_1505_DATA 0x00000000 +#define DDRSS_PHY_1506_DATA 0x00000000 +#define DDRSS_PHY_1507_DATA 0x00000000 +#define DDRSS_PHY_1508_DATA 0x00000000 +#define DDRSS_PHY_1509_DATA 0x00000000 +#define DDRSS_PHY_1510_DATA 0x00000000 +#define DDRSS_PHY_1511_DATA 0x00000000 +#define DDRSS_PHY_1512_DATA 0x00000000 +#define DDRSS_PHY_1513_DATA 0x00000000 +#define DDRSS_PHY_1514_DATA 0x00000000 +#define DDRSS_PHY_1515_DATA 0x00000000 +#define DDRSS_PHY_1516_DATA 0x00000000 +#define DDRSS_PHY_1517_DATA 0x00000000 +#define DDRSS_PHY_1518_DATA 0x00000000 +#define DDRSS_PHY_1519_DATA 0x00000000 +#define DDRSS_PHY_1520_DATA 0x00000000 +#define DDRSS_PHY_1521_DATA 0x00000000 +#define DDRSS_PHY_1522_DATA 0x00000000 +#define DDRSS_PHY_1523_DATA 0x00000000 +#define DDRSS_PHY_1524_DATA 0x00000000 +#define DDRSS_PHY_1525_DATA 0x00000000 +#define DDRSS_PHY_1526_DATA 0x00000000 +#define DDRSS_PHY_1527_DATA 0x00000000 +#define DDRSS_PHY_1528_DATA 0x00000000 +#define DDRSS_PHY_1529_DATA 0x00000000 +#define DDRSS_PHY_1530_DATA 0x00000000 +#define DDRSS_PHY_1531_DATA 0x00000000 +#define DDRSS_PHY_1532_DATA 0x00000000 +#define DDRSS_PHY_1533_DATA 0x00000000 +#define DDRSS_PHY_1534_DATA 0x00000000 +#define DDRSS_PHY_1535_DATA 0x00000000 +#define DDRSS_PHY_1536_DATA 0x00000000 +#define DDRSS_PHY_1537_DATA 0x00000000 +#define DDRSS_PHY_1538_DATA 0x00000000 +#define DDRSS_PHY_1539_DATA 0x00000000 +#define DDRSS_PHY_1540_DATA 0x00000000 +#define DDRSS_PHY_1541_DATA 0x00000100 +#define DDRSS_PHY_1542_DATA 0x00000200 +#define DDRSS_PHY_1543_DATA 0x00000000 +#define DDRSS_PHY_1544_DATA 0x00000000 +#define DDRSS_PHY_1545_DATA 0x00000000 +#define DDRSS_PHY_1546_DATA 0x00000000 +#define DDRSS_PHY_1547_DATA 0x00400000 +#define DDRSS_PHY_1548_DATA 0x00000080 +#define DDRSS_PHY_1549_DATA 0x00DCBA98 +#define DDRSS_PHY_1550_DATA 0x03000000 +#define DDRSS_PHY_1551_DATA 0x00200000 +#define DDRSS_PHY_1552_DATA 0x00000000 +#define DDRSS_PHY_1553_DATA 0x00000000 +#define DDRSS_PHY_1554_DATA 0x00000000 +#define DDRSS_PHY_1555_DATA 0x00000000 +#define DDRSS_PHY_1556_DATA 0x00000000 +#define DDRSS_PHY_1557_DATA 0x0000002A +#define DDRSS_PHY_1558_DATA 0x00000015 +#define DDRSS_PHY_1559_DATA 0x00000015 +#define DDRSS_PHY_1560_DATA 0x0000002A +#define DDRSS_PHY_1561_DATA 0x00000033 +#define DDRSS_PHY_1562_DATA 0x0000000C +#define DDRSS_PHY_1563_DATA 0x0000000C +#define DDRSS_PHY_1564_DATA 0x00000033 +#define DDRSS_PHY_1565_DATA 0x0A418820 +#define DDRSS_PHY_1566_DATA 0x10000000 +#define DDRSS_PHY_1567_DATA 0x000F0000 +#define DDRSS_PHY_1568_DATA 0x20202003 +#define DDRSS_PHY_1569_DATA 0x00202020 +#define DDRSS_PHY_1570_DATA 0x20008008 +#define DDRSS_PHY_1571_DATA 0x00000810 +#define DDRSS_PHY_1572_DATA 0x00000F00 +#define DDRSS_PHY_1573_DATA 0x000304CC +#define DDRSS_PHY_1574_DATA 0x03000003 +#define DDRSS_PHY_1575_DATA 0x00030000 +#define DDRSS_PHY_1576_DATA 0x00000300 +#define DDRSS_PHY_1577_DATA 0x00000300 +#define DDRSS_PHY_1578_DATA 0x00000300 +#define DDRSS_PHY_1579_DATA 0x00000300 +#define DDRSS_PHY_1580_DATA 0x42080010 +#define DDRSS_PHY_1581_DATA 0x0000803E +#define DDRSS_PHY_1582_DATA 0x00000001 +#define DDRSS_PHY_1583_DATA 0x01000002 +#define DDRSS_PHY_1584_DATA 0x00008000 +#define DDRSS_PHY_1585_DATA 0x00000000 +#define DDRSS_PHY_1586_DATA 0x00000000 +#define DDRSS_PHY_1587_DATA 0x00000000 +#define DDRSS_PHY_1588_DATA 0x00000000 +#define DDRSS_PHY_1589_DATA 0x00000000 +#define DDRSS_PHY_1590_DATA 0x00000000 +#define DDRSS_PHY_1591_DATA 0x00000000 +#define DDRSS_PHY_1592_DATA 0x00000000 +#define DDRSS_PHY_1593_DATA 0x00000000 +#define DDRSS_PHY_1594_DATA 0x00000000 +#define DDRSS_PHY_1595_DATA 0x00000000 +#define DDRSS_PHY_1596_DATA 0x00000000 +#define DDRSS_PHY_1597_DATA 0x00000000 +#define DDRSS_PHY_1598_DATA 0x00000000 +#define DDRSS_PHY_1599_DATA 0x00000000 +#define DDRSS_PHY_1600_DATA 0x00000000 +#define DDRSS_PHY_1601_DATA 0x00000000 +#define DDRSS_PHY_1602_DATA 0x00000000 +#define DDRSS_PHY_1603_DATA 0x00000000 +#define DDRSS_PHY_1604_DATA 0x00000000 +#define DDRSS_PHY_1605_DATA 0x00000000 +#define DDRSS_PHY_1606_DATA 0x00000000 +#define DDRSS_PHY_1607_DATA 0x00000000 +#define DDRSS_PHY_1608_DATA 0x00000000 +#define DDRSS_PHY_1609_DATA 0x00000000 +#define DDRSS_PHY_1610_DATA 0x00000000 +#define DDRSS_PHY_1611_DATA 0x00000000 +#define DDRSS_PHY_1612_DATA 0x00000000 +#define DDRSS_PHY_1613_DATA 0x00000000 +#define DDRSS_PHY_1614_DATA 0x00000000 +#define DDRSS_PHY_1615_DATA 0x00000000 +#define DDRSS_PHY_1616_DATA 0x00000000 +#define DDRSS_PHY_1617_DATA 0x00000000 +#define DDRSS_PHY_1618_DATA 0x00000000 +#define DDRSS_PHY_1619_DATA 0x00000000 +#define DDRSS_PHY_1620_DATA 0x00000000 +#define DDRSS_PHY_1621_DATA 0x00000000 +#define DDRSS_PHY_1622_DATA 0x00000000 +#define DDRSS_PHY_1623_DATA 0x00000000 +#define DDRSS_PHY_1624_DATA 0x00000000 +#define DDRSS_PHY_1625_DATA 0x00000000 +#define DDRSS_PHY_1626_DATA 0x00000000 +#define DDRSS_PHY_1627_DATA 0x00000000 +#define DDRSS_PHY_1628_DATA 0x00000000 +#define DDRSS_PHY_1629_DATA 0x00000000 +#define DDRSS_PHY_1630_DATA 0x00000000 +#define DDRSS_PHY_1631_DATA 0x00000000 +#define DDRSS_PHY_1632_DATA 0x00000000 +#define DDRSS_PHY_1633_DATA 0x00000000 +#define DDRSS_PHY_1634_DATA 0x00000000 +#define DDRSS_PHY_1635_DATA 0x00000000 +#define DDRSS_PHY_1636_DATA 0x00000000 +#define DDRSS_PHY_1637_DATA 0x00000000 +#define DDRSS_PHY_1638_DATA 0x00000000 +#define DDRSS_PHY_1639_DATA 0x00000000 +#define DDRSS_PHY_1640_DATA 0x00000000 +#define DDRSS_PHY_1641_DATA 0x00000000 +#define DDRSS_PHY_1642_DATA 0x00000000 +#define DDRSS_PHY_1643_DATA 0x00000000 +#define DDRSS_PHY_1644_DATA 0x00000000 +#define DDRSS_PHY_1645_DATA 0x00000000 +#define DDRSS_PHY_1646_DATA 0x00000000 +#define DDRSS_PHY_1647_DATA 0x00000000 +#define DDRSS_PHY_1648_DATA 0x00000000 +#define DDRSS_PHY_1649_DATA 0x00000000 +#define DDRSS_PHY_1650_DATA 0x00000000 +#define DDRSS_PHY_1651_DATA 0x00000000 +#define DDRSS_PHY_1652_DATA 0x00000000 +#define DDRSS_PHY_1653_DATA 0x00000000 +#define DDRSS_PHY_1654_DATA 0x00000000 +#define DDRSS_PHY_1655_DATA 0x00000000 +#define DDRSS_PHY_1656_DATA 0x00000000 +#define DDRSS_PHY_1657_DATA 0x00000000 +#define DDRSS_PHY_1658_DATA 0x00000000 +#define DDRSS_PHY_1659_DATA 0x00000000 +#define DDRSS_PHY_1660_DATA 0x00000000 +#define DDRSS_PHY_1661_DATA 0x00000000 +#define DDRSS_PHY_1662_DATA 0x00000000 +#define DDRSS_PHY_1663_DATA 0x00000000 +#define DDRSS_PHY_1664_DATA 0x00000000 +#define DDRSS_PHY_1665_DATA 0x00000000 +#define DDRSS_PHY_1666_DATA 0x00000000 +#define DDRSS_PHY_1667_DATA 0x00000000 +#define DDRSS_PHY_1668_DATA 0x00000000 +#define DDRSS_PHY_1669_DATA 0x00000000 +#define DDRSS_PHY_1670_DATA 0x00000000 +#define DDRSS_PHY_1671_DATA 0x00000000 +#define DDRSS_PHY_1672_DATA 0x00000000 +#define DDRSS_PHY_1673_DATA 0x00000000 +#define DDRSS_PHY_1674_DATA 0x00000000 +#define DDRSS_PHY_1675_DATA 0x00000000 +#define DDRSS_PHY_1676_DATA 0x00000000 +#define DDRSS_PHY_1677_DATA 0x00000000 +#define DDRSS_PHY_1678_DATA 0x00000000 +#define DDRSS_PHY_1679_DATA 0x00000000 +#define DDRSS_PHY_1680_DATA 0x00000000 +#define DDRSS_PHY_1681_DATA 0x00000000 +#define DDRSS_PHY_1682_DATA 0x00000000 +#define DDRSS_PHY_1683_DATA 0x00000000 +#define DDRSS_PHY_1684_DATA 0x00000000 +#define DDRSS_PHY_1685_DATA 0x00000000 +#define DDRSS_PHY_1686_DATA 0x00000000 +#define DDRSS_PHY_1687_DATA 0x00000000 +#define DDRSS_PHY_1688_DATA 0x00000000 +#define DDRSS_PHY_1689_DATA 0x00000000 +#define DDRSS_PHY_1690_DATA 0x00000000 +#define DDRSS_PHY_1691_DATA 0x00000000 +#define DDRSS_PHY_1692_DATA 0x00000000 +#define DDRSS_PHY_1693_DATA 0x00000000 +#define DDRSS_PHY_1694_DATA 0x00000000 +#define DDRSS_PHY_1695_DATA 0x00000000 +#define DDRSS_PHY_1696_DATA 0x00000000 +#define DDRSS_PHY_1697_DATA 0x00000000 +#define DDRSS_PHY_1698_DATA 0x00000000 +#define DDRSS_PHY_1699_DATA 0x00000000 +#define DDRSS_PHY_1700_DATA 0x00000000 +#define DDRSS_PHY_1701_DATA 0x00000000 +#define DDRSS_PHY_1702_DATA 0x00000000 +#define DDRSS_PHY_1703_DATA 0x00000000 +#define DDRSS_PHY_1704_DATA 0x00000000 +#define DDRSS_PHY_1705_DATA 0x00000000 +#define DDRSS_PHY_1706_DATA 0x00000000 +#define DDRSS_PHY_1707_DATA 0x00000000 +#define DDRSS_PHY_1708_DATA 0x00000000 +#define DDRSS_PHY_1709_DATA 0x00000000 +#define DDRSS_PHY_1710_DATA 0x00000000 +#define DDRSS_PHY_1711_DATA 0x00000000 +#define DDRSS_PHY_1712_DATA 0x00000000 +#define DDRSS_PHY_1713_DATA 0x00000000 +#define DDRSS_PHY_1714_DATA 0x00000000 +#define DDRSS_PHY_1715_DATA 0x00000000 +#define DDRSS_PHY_1716_DATA 0x00000000 +#define DDRSS_PHY_1717_DATA 0x00000000 +#define DDRSS_PHY_1718_DATA 0x00000000 +#define DDRSS_PHY_1719_DATA 0x00000000 +#define DDRSS_PHY_1720_DATA 0x00000000 +#define DDRSS_PHY_1721_DATA 0x00000000 +#define DDRSS_PHY_1722_DATA 0x00000000 +#define DDRSS_PHY_1723_DATA 0x00000000 +#define DDRSS_PHY_1724_DATA 0x00000000 +#define DDRSS_PHY_1725_DATA 0x00000000 +#define DDRSS_PHY_1726_DATA 0x00000000 +#define DDRSS_PHY_1727_DATA 0x00000000 +#define DDRSS_PHY_1728_DATA 0x00000000 +#define DDRSS_PHY_1729_DATA 0x00000000 +#define DDRSS_PHY_1730_DATA 0x00000000 +#define DDRSS_PHY_1731_DATA 0x00000000 +#define DDRSS_PHY_1732_DATA 0x00000000 +#define DDRSS_PHY_1733_DATA 0x00000000 +#define DDRSS_PHY_1734_DATA 0x00000000 +#define DDRSS_PHY_1735_DATA 0x00000000 +#define DDRSS_PHY_1736_DATA 0x00000000 +#define DDRSS_PHY_1737_DATA 0x00000000 +#define DDRSS_PHY_1738_DATA 0x00000000 +#define DDRSS_PHY_1739_DATA 0x00000000 +#define DDRSS_PHY_1740_DATA 0x00000000 +#define DDRSS_PHY_1741_DATA 0x00000000 +#define DDRSS_PHY_1742_DATA 0x00000000 +#define DDRSS_PHY_1743_DATA 0x00000000 +#define DDRSS_PHY_1744_DATA 0x00000000 +#define DDRSS_PHY_1745_DATA 0x00000000 +#define DDRSS_PHY_1746_DATA 0x00000000 +#define DDRSS_PHY_1747_DATA 0x00000000 +#define DDRSS_PHY_1748_DATA 0x00000000 +#define DDRSS_PHY_1749_DATA 0x00000000 +#define DDRSS_PHY_1750_DATA 0x00000000 +#define DDRSS_PHY_1751_DATA 0x00000000 +#define DDRSS_PHY_1752_DATA 0x00000000 +#define DDRSS_PHY_1753_DATA 0x00000000 +#define DDRSS_PHY_1754_DATA 0x00000000 +#define DDRSS_PHY_1755_DATA 0x00000000 +#define DDRSS_PHY_1756_DATA 0x00000000 +#define DDRSS_PHY_1757_DATA 0x00000000 +#define DDRSS_PHY_1758_DATA 0x00000000 +#define DDRSS_PHY_1759_DATA 0x00000000 +#define DDRSS_PHY_1760_DATA 0x00000000 +#define DDRSS_PHY_1761_DATA 0x00000000 +#define DDRSS_PHY_1762_DATA 0x00000000 +#define DDRSS_PHY_1763_DATA 0x00000000 +#define DDRSS_PHY_1764_DATA 0x00000000 +#define DDRSS_PHY_1765_DATA 0x00000000 +#define DDRSS_PHY_1766_DATA 0x00000000 +#define DDRSS_PHY_1767_DATA 0x00000000 +#define DDRSS_PHY_1768_DATA 0x00000000 +#define DDRSS_PHY_1769_DATA 0x00000000 +#define DDRSS_PHY_1770_DATA 0x00000000 +#define DDRSS_PHY_1771_DATA 0x00000000 +#define DDRSS_PHY_1772_DATA 0x00000000 +#define DDRSS_PHY_1773_DATA 0x00000000 +#define DDRSS_PHY_1774_DATA 0x00000000 +#define DDRSS_PHY_1775_DATA 0x00000000 +#define DDRSS_PHY_1776_DATA 0x00000000 +#define DDRSS_PHY_1777_DATA 0x00000000 +#define DDRSS_PHY_1778_DATA 0x00000000 +#define DDRSS_PHY_1779_DATA 0x00000000 +#define DDRSS_PHY_1780_DATA 0x00000000 +#define DDRSS_PHY_1781_DATA 0x00000000 +#define DDRSS_PHY_1782_DATA 0x00000000 +#define DDRSS_PHY_1783_DATA 0x00000000 +#define DDRSS_PHY_1784_DATA 0x00000000 +#define DDRSS_PHY_1785_DATA 0x00000000 +#define DDRSS_PHY_1786_DATA 0x00000000 +#define DDRSS_PHY_1787_DATA 0x00000000 +#define DDRSS_PHY_1788_DATA 0x00000000 +#define DDRSS_PHY_1789_DATA 0x00000000 +#define DDRSS_PHY_1790_DATA 0x00000000 +#define DDRSS_PHY_1791_DATA 0x00000000 +#define DDRSS_PHY_1792_DATA 0x00000000 +#define DDRSS_PHY_1793_DATA 0x00010100 +#define DDRSS_PHY_1794_DATA 0x00000000 +#define DDRSS_PHY_1795_DATA 0x00000000 +#define DDRSS_PHY_1796_DATA 0x00000000 +#define DDRSS_PHY_1797_DATA 0x00000000 +#define DDRSS_PHY_1798_DATA 0x00050000 +#define DDRSS_PHY_1799_DATA 0x04000000 +#define DDRSS_PHY_1800_DATA 0x00000055 +#define DDRSS_PHY_1801_DATA 0x00000000 +#define DDRSS_PHY_1802_DATA 0x00000000 +#define DDRSS_PHY_1803_DATA 0x00000000 +#define DDRSS_PHY_1804_DATA 0x00000000 +#define DDRSS_PHY_1805_DATA 0x00002001 +#define DDRSS_PHY_1806_DATA 0x00004003 +#define DDRSS_PHY_1807_DATA 0x50020028 +#define DDRSS_PHY_1808_DATA 0x01010000 +#define DDRSS_PHY_1809_DATA 0x80080001 +#define DDRSS_PHY_1810_DATA 0x10200000 +#define DDRSS_PHY_1811_DATA 0x00000008 +#define DDRSS_PHY_1812_DATA 0x00000000 +#define DDRSS_PHY_1813_DATA 0x06000000 +#define DDRSS_PHY_1814_DATA 0x010F0F0E +#define DDRSS_PHY_1815_DATA 0x00040101 +#define DDRSS_PHY_1816_DATA 0x0000010F +#define DDRSS_PHY_1817_DATA 0x00000000 +#define DDRSS_PHY_1818_DATA 0x00000064 +#define DDRSS_PHY_1819_DATA 0x00000000 +#define DDRSS_PHY_1820_DATA 0x00000000 +#define DDRSS_PHY_1821_DATA 0x0F0F0F01 +#define DDRSS_PHY_1822_DATA 0x0F0F0F02 +#define DDRSS_PHY_1823_DATA 0x0F0F0F0F +#define DDRSS_PHY_1824_DATA 0x0F0F0804 +#define DDRSS_PHY_1825_DATA 0x00800120 +#define DDRSS_PHY_1826_DATA 0x00041B42 +#define DDRSS_PHY_1827_DATA 0x00004201 +#define DDRSS_PHY_1828_DATA 0x00000000 +#define DDRSS_PHY_1829_DATA 0x00000000 +#define DDRSS_PHY_1830_DATA 0x00000000 +#define DDRSS_PHY_1831_DATA 0x00000000 +#define DDRSS_PHY_1832_DATA 0x00000000 +#define DDRSS_PHY_1833_DATA 0x00000000 +#define DDRSS_PHY_1834_DATA 0x03010100 +#define DDRSS_PHY_1835_DATA 0x00540007 +#define DDRSS_PHY_1836_DATA 0x000040A2 +#define DDRSS_PHY_1837_DATA 0x00024410 +#define DDRSS_PHY_1838_DATA 0x00004410 +#define DDRSS_PHY_1839_DATA 0x00004410 +#define DDRSS_PHY_1840_DATA 0x00004410 +#define DDRSS_PHY_1841_DATA 0x00004410 +#define DDRSS_PHY_1842_DATA 0x00004410 +#define DDRSS_PHY_1843_DATA 0x00004410 +#define DDRSS_PHY_1844_DATA 0x00004410 +#define DDRSS_PHY_1845_DATA 0x00004410 +#define DDRSS_PHY_1846_DATA 0x00004410 +#define DDRSS_PHY_1847_DATA 0x00000000 +#define DDRSS_PHY_1848_DATA 0x00000076 +#define DDRSS_PHY_1849_DATA 0x00000400 +#define DDRSS_PHY_1850_DATA 0x00000008 +#define DDRSS_PHY_1851_DATA 0x00000000 +#define DDRSS_PHY_1852_DATA 0x00000000 +#define DDRSS_PHY_1853_DATA 0x00000000 +#define DDRSS_PHY_1854_DATA 0x00000000 +#define DDRSS_PHY_1855_DATA 0x00000000 +#define DDRSS_PHY_1856_DATA 0x03000000 +#define DDRSS_PHY_1857_DATA 0x00000000 +#define DDRSS_PHY_1858_DATA 0x00000000 +#define DDRSS_PHY_1859_DATA 0x00000000 +#define DDRSS_PHY_1860_DATA 0x04102006 +#define DDRSS_PHY_1861_DATA 0x00041020 +#define DDRSS_PHY_1862_DATA 0x01C98C98 +#define DDRSS_PHY_1863_DATA 0x3F400000 +#define DDRSS_PHY_1864_DATA 0x3F3F1F3F +#define DDRSS_PHY_1865_DATA 0x0000001F +#define DDRSS_PHY_1866_DATA 0x00000000 +#define DDRSS_PHY_1867_DATA 0x00000000 +#define DDRSS_PHY_1868_DATA 0x00000000 +#define DDRSS_PHY_1869_DATA 0x00000001 +#define DDRSS_PHY_1870_DATA 0x00000000 +#define DDRSS_PHY_1871_DATA 0x00000000 +#define DDRSS_PHY_1872_DATA 0x00000000 +#define DDRSS_PHY_1873_DATA 0x00000000 +#define DDRSS_PHY_1874_DATA 0x76543210 +#define DDRSS_PHY_1875_DATA 0x06010198 +#define DDRSS_PHY_1876_DATA 0x00000000 +#define DDRSS_PHY_1877_DATA 0x00000000 +#define DDRSS_PHY_1878_DATA 0x00000000 +#define DDRSS_PHY_1879_DATA 0x00040700 +#define DDRSS_PHY_1880_DATA 0x00000000 +#define DDRSS_PHY_1881_DATA 0x00000000 +#define DDRSS_PHY_1882_DATA 0x00000000 +#define DDRSS_PHY_1883_DATA 0x00000000 +#define DDRSS_PHY_1884_DATA 0x00000000 +#define DDRSS_PHY_1885_DATA 0x00000002 +#define DDRSS_PHY_1886_DATA 0x00000000 +#define DDRSS_PHY_1887_DATA 0x00000000 +#define DDRSS_PHY_1888_DATA 0x0001F7C3 +#define DDRSS_PHY_1889_DATA 0x03000003 +#define DDRSS_PHY_1890_DATA 0x00000000 +#define DDRSS_PHY_1891_DATA 0x00001142 +#define DDRSS_PHY_1892_DATA 0x01020000 +#define DDRSS_PHY_1893_DATA 0x00000080 +#define DDRSS_PHY_1894_DATA 0x03900390 +#define DDRSS_PHY_1895_DATA 0x03900390 +#define DDRSS_PHY_1896_DATA 0x03900390 +#define DDRSS_PHY_1897_DATA 0x03900390 +#define DDRSS_PHY_1898_DATA 0x03000300 +#define DDRSS_PHY_1899_DATA 0x03000300 +#define DDRSS_PHY_1900_DATA 0x00000300 +#define DDRSS_PHY_1901_DATA 0x00000300 +#define DDRSS_PHY_1902_DATA 0x00000300 +#define DDRSS_PHY_1903_DATA 0x00000300 +#define DDRSS_PHY_1904_DATA 0x00000004 +#define DDRSS_PHY_1905_DATA 0x3183BF77 +#define DDRSS_PHY_1906_DATA 0x00000000 +#define DDRSS_PHY_1907_DATA 0x0C000DFF +#define DDRSS_PHY_1908_DATA 0x30000DFF +#define DDRSS_PHY_1909_DATA 0x3F0DFF11 +#define DDRSS_PHY_1910_DATA 0x00EF0000 +#define DDRSS_PHY_1911_DATA 0x780DFFCC +#define DDRSS_PHY_1912_DATA 0x00000C11 +#define DDRSS_PHY_1913_DATA 0x00018011 +#define DDRSS_PHY_1914_DATA 0x0089FF00 +#define DDRSS_PHY_1915_DATA 0x000C3F11 +#define DDRSS_PHY_1916_DATA 0x01990000 +#define DDRSS_PHY_1917_DATA 0x000C3F91 +#define DDRSS_PHY_1918_DATA 0x01990000 +#define DDRSS_PHY_1919_DATA 0x3F0DFF11 +#define DDRSS_PHY_1920_DATA 0x00EF0000 +#define DDRSS_PHY_1921_DATA 0x00018011 +#define DDRSS_PHY_1922_DATA 0x0089FF00 +#define DDRSS_PHY_1923_DATA 0x20040005 diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi new file mode 100644 index 00000000000..dea14945bf5 --- /dev/null +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-binman.dtsi" + +#if IS_ENABLED(CONFIG_TARGET_AM62P5_R5_EVM) + +&binman { + tiboot3-am62px-hs-fs-evm.bin { + filename = "tiboot3-am62px-hs-fs-evm.bin"; + symlink = "tiboot3.bin"; + + ti-secure-rom { + content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>, + <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_fs>; + content-sysfw = <&ti_fs_enc_fs>; + content-sysfw-data = <&combined_tifs_cfg_fs>; + content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; + content-dm-data = <&combined_dm_cfg_fs>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c4a800>; + }; + + u_boot_spl_fs: u-boot-spl { + no-expanded; + }; + + ti_fs_enc_fs: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + + combined_tifs_cfg_fs: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + + sysfw_inner_cert_fs: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + + combined_dm_cfg_fs: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +#endif /* CONFIG_TARGET_AM62P5_R5_EVM */ + +#if IS_ENABLED(CONFIG_TARGET_AM62P5_A53_EVM) + +#define SPL_AM62PX_SK_DTB "spl/dts/ti/k3-am62p5-sk.dtb" +#define AM62PX_SK_DTB "u-boot.dtb" + +&binman { + ti-dm { + filename = "ti-dm.bin"; + + blob-ext { + filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + + ti-spl { + insert-template = <&ti_spl_template>; + + fit { + images { + dm { + ti-secure { + content = <&dm>; + keyfile = "custMpk.pem"; + }; + + dm: ti-dm { + filename = "ti-dm.bin"; + }; + }; + + fdt-0 { + description = "k3-am62p5-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + ti-secure { + content = <&spl_am62p5_sk_dtb>; + keyfile = "custMpk.pem"; + }; + + spl_am62p5_sk_dtb: blob-ext { + filename = SPL_AM62PX_SK_DTB; + }; + + }; + + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62px-sk"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot { + insert-template = <&u_boot_template>; + + fit { + images { + uboot { + description = "U-Boot for AM62P5 Boards"; + }; + + fdt-0 { + description = "k3-am62px-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + ti-secure { + content = <&am62px_sk_dtb>; + keyfile = "custMpk.pem"; + }; + + am62px_sk_dtb: blob-ext { + filename = AM62PX_SK_DTB; + }; + + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62px-sk"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + + }; + }; + }; +}; + +#endif /* CONFIG_TARGET_AM62P5_A53_EVM */ diff --git a/arch/arm/dts/k3-am62p5-r5-sk.dts b/arch/arm/dts/k3-am62p5-r5-sk.dts new file mode 100644 index 00000000000..658f2cf730a --- /dev/null +++ b/arch/arm/dts/k3-am62p5-r5-sk.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62P5 SK dts file for R5 SPL + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am62p5-sk.dts" +#include "k3-am62p5-sk-u-boot.dtsi" + +#include "k3-am62p-ddr-lp4-50-1600.dtsi" +#include "k3-am62a-ddr.dtsi" + +/ { + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + serial0 = &wkup_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + clocks = <&k3_clks 61 0>; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <1200000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-all; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <36>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 20>, + <&secure_proxy_main 21>; + bootph-all; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; + +&cbass_main { + sa3_secproxy: secproxy@44880000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg = <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>, + <0x00 0x43600000 0x00 0x10000>; + reg-names = "rt", "scfg", "target_data"; + bootph-all; + }; + + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_main 1>, + <&secure_proxy_main 0>, + <&sa3_secproxy 0>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-all; + }; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + status = "okay"; +}; + +/* Main UART1 is used for TIFS firmware logs */ +&main_uart1 { + status = "okay"; +}; + +&main_pktdma { + ti,sci = <&dm_tifs>; +}; + +&main_bcdma { + ti,sci = <&dm_tifs>; +}; + +&ospi0 { + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x00 0x60000000 0x00 0x08000000>; +}; diff --git a/arch/arm/dts/k3-am62p5-sk-u-boot.dtsi b/arch/arm/dts/k3-am62p5-sk-u-boot.dtsi new file mode 100644 index 00000000000..cf087c6e343 --- /dev/null +++ b/arch/arm/dts/k3-am62p5-sk-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common AM62Px EVM dts file for SPLs + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am62p-sk-binman.dtsi" + +/ { + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &main_timer0; + }; +}; + +&dmsc { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi deleted file mode 100644 index 0df54a74182..00000000000 --- a/arch/arm/dts/k3-am64-main.dtsi +++ /dev/null @@ -1,1546 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM642 SoC Family Main Domain peripherals - * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include <dt-bindings/phy/phy-cadence.h> -#include <dt-bindings/phy/phy-ti.h> - -/ { - serdes_refclk: clock-cmnrefclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; - -&cbass_main { - oc_sram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x00 0x70000000 0x00 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x70000000 0x200000>; - - tfa-sram@1c0000 { - reg = <0x1c0000 0x20000>; - }; - - dmsc-sram@1e0000 { - reg = <0x1e0000 0x1c000>; - }; - - sproxy-sram@1fc000 { - reg = <0x1fc000 0x4000>; - }; - }; - - main_conf: syscon@43000000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x0 0x43000000 0x0 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x43000000 0x20000>; - - chipid@14 { - compatible = "ti,am654-chipid"; - reg = <0x00000014 0x4>; - }; - - serdes_ln_ctrl: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ - }; - - phy_gmii_sel: phy@4044 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4044 0x8>; - #phy-cells = <1>; - }; - - epwm_tbclk: clock-controller@4140 { - compatible = "ti,am64-epwm-tbclk"; - reg = <0x4130 0x4>; - #clock-cells = <1>; - }; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01840000 0x00 0xC0000>, /* GICR */ - <0x01 0x00000000 0x00 0x2000>, /* GICC */ - <0x01 0x00010000 0x00 0x1000>, /* GICH */ - <0x01 0x00020000 0x00 0x2000>; /* GICV */ - /* - * vcpumntirq: - * virtual CPU interface maintenance interrupt - */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - gic_its: msi-controller@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - dmss: bus@48000000 { - compatible = "simple-mfd"; - #address-cells = <2>; - #size-cells = <2>; - dma-ranges; - ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; - - ti,sci-dev-id = <25>; - - secure_proxy_main: mailbox@4d000000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x4d000000 0x00 0x80000>, - <0x00 0x4a600000 0x00 0x80000>, - <0x00 0x4a400000 0x00 0x80000>; - interrupt-names = "rx_012"; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - }; - - inta_main_dmss: interrupt-controller@48000000 { - compatible = "ti,sci-inta"; - reg = <0x00 0x48000000 0x00 0x100000>; - #interrupt-cells = <0>; - interrupt-controller; - interrupt-parent = <&gic500>; - msi-controller; - ti,sci = <&dmsc>; - ti,sci-dev-id = <28>; - ti,interrupt-ranges = <4 68 36>; - ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; - }; - - main_bcdma: dma-controller@485c0100 { - compatible = "ti,am64-dmss-bcdma"; - reg = <0x00 0x485c0100 0x00 0x100>, - <0x00 0x4c000000 0x00 0x20000>, - <0x00 0x4a820000 0x00 0x20000>, - <0x00 0x4aa40000 0x00 0x20000>, - <0x00 0x4bc00000 0x00 0x100000>; - reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; - msi-parent = <&inta_main_dmss>; - #dma-cells = <3>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <26>; - ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ - ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ - ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ - }; - - main_pktdma: dma-controller@485c0000 { - compatible = "ti,am64-dmss-pktdma"; - reg = <0x00 0x485c0000 0x00 0x100>, - <0x00 0x4a800000 0x00 0x20000>, - <0x00 0x4aa00000 0x00 0x40000>, - <0x00 0x4b800000 0x00 0x400000>; - reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; - msi-parent = <&inta_main_dmss>; - #dma-cells = <2>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <30>; - ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ - <0x24>, /* CPSW_TX_CHAN */ - <0x25>, /* SAUL_TX_0_CHAN */ - <0x26>, /* SAUL_TX_1_CHAN */ - <0x27>, /* ICSSG_0_TX_CHAN */ - <0x28>; /* ICSSG_1_TX_CHAN */ - ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ - <0x11>, /* RING_CPSW_TX_CHAN */ - <0x12>, /* RING_SAUL_TX_0_CHAN */ - <0x13>, /* RING_SAUL_TX_1_CHAN */ - <0x14>, /* RING_ICSSG_0_TX_CHAN */ - <0x15>; /* RING_ICSSG_1_TX_CHAN */ - ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ - <0x2b>, /* CPSW_RX_CHAN */ - <0x2d>, /* SAUL_RX_0_CHAN */ - <0x2f>, /* SAUL_RX_1_CHAN */ - <0x31>, /* SAUL_RX_2_CHAN */ - <0x33>, /* SAUL_RX_3_CHAN */ - <0x35>, /* ICSSG_0_RX_CHAN */ - <0x37>; /* ICSSG_1_RX_CHAN */ - ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ - <0x2c>, /* FLOW_CPSW_RX_CHAN */ - <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ - <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ - <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ - <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ - }; - }; - - dmsc: system-controller@44043000 { - compatible = "ti,k2g-sci"; - ti,host-id = <12>; - mbox-names = "rx", "tx"; - mboxes = <&secure_proxy_main 12>, - <&secure_proxy_main 13>; - reg-names = "debug_messages"; - reg = <0x00 0x44043000 0x00 0xfe0>; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - }; - - k3_clks: clock-controller { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - main_pmx0: pinctrl@f4000 { - compatible = "pinctrl-single"; - reg = <0x00 0xf4000 0x00 0x2d0>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - main_timer0: timer@2400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2400000 0x00 0x400>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 36 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 36 1>; - assigned-clock-parents = <&k3_clks 36 2>; - power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer1: timer@2410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2410000 0x00 0x400>; - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 37 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 37 1>; - assigned-clock-parents = <&k3_clks 37 2>; - power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer2: timer@2420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2420000 0x00 0x400>; - interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 38 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 38 1>; - assigned-clock-parents = <&k3_clks 38 2>; - power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer3: timer@2430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2430000 0x00 0x400>; - interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 39 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 39 1>; - assigned-clock-parents = <&k3_clks 39 2>; - power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer4: timer@2440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2440000 0x00 0x400>; - interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 40 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 40 1>; - assigned-clock-parents = <&k3_clks 40 2>; - power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer5: timer@2450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2450000 0x00 0x400>; - interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 41 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 41 1>; - assigned-clock-parents = <&k3_clks 41 2>; - power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer6: timer@2460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2460000 0x00 0x400>; - interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 42 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 42 1>; - assigned-clock-parents = <&k3_clks 42 2>; - power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer7: timer@2470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2470000 0x00 0x400>; - interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 43 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 43 1>; - assigned-clock-parents = <&k3_clks 43 2>; - power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer8: timer@2480000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2480000 0x00 0x400>; - interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 44 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 44 1>; - assigned-clock-parents = <&k3_clks 44 2>; - power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer9: timer@2490000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2490000 0x00 0x400>; - interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 45 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 45 1>; - assigned-clock-parents = <&k3_clks 45 2>; - power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer10: timer@24a0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24a0000 0x00 0x400>; - interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 46 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 46 1>; - assigned-clock-parents = <&k3_clks 46 2>; - power-domains = <&k3_pds 46 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer11: timer@24b0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24b0000 0x00 0x400>; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 47 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 47 1>; - assigned-clock-parents = <&k3_clks 47 2>; - power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_esm: esm@420000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x420000 0x00 0x1000>; - ti,esm-pins = <160>, <161>; - }; - - main_uart0: serial@2800000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x100>; - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 146 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart1: serial@2810000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x100>; - interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 152 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart2: serial@2820000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x100>; - interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 153 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart3: serial@2830000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02830000 0x00 0x100>; - interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 154 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart4: serial@2840000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02840000 0x00 0x100>; - interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 155 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart5: serial@2850000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02850000 0x00 0x100>; - interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 156 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart6: serial@2860000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02860000 0x00 0x100>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 158 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_i2c0: i2c@20000000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20000000 0x00 0x100>; - interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 102 2>; - clock-names = "fck"; - status = "disabled"; - }; - - main_i2c1: i2c@20010000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20010000 0x00 0x100>; - interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 103 2>; - clock-names = "fck"; - status = "disabled"; - }; - - main_i2c2: i2c@20020000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20020000 0x00 0x100>; - interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 104 2>; - clock-names = "fck"; - status = "disabled"; - }; - - main_i2c3: i2c@20030000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20030000 0x00 0x100>; - interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 105 2>; - clock-names = "fck"; - status = "disabled"; - }; - - main_spi0: spi@20100000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x20100000 0x00 0x400>; - interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 141 0>; - dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; - dma-names = "tx0", "rx0"; - status = "disabled"; - }; - - main_spi1: spi@20110000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x20110000 0x00 0x400>; - interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 142 0>; - status = "disabled"; - }; - - main_spi2: spi@20120000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x20120000 0x00 0x400>; - interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 143 0>; - status = "disabled"; - }; - - main_spi3: spi@20130000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x20130000 0x00 0x400>; - interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 144 0>; - status = "disabled"; - }; - - main_spi4: spi@20140000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x20140000 0x00 0x400>; - interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 145 0>; - status = "disabled"; - }; - - main_gpio_intr: interrupt-controller@a00000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x00a00000 0x00 0x800>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <3>; - ti,interrupt-ranges = <0 32 16>; - }; - - main_gpio0: gpio@600000 { - compatible = "ti,am64-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00600000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <190>, <191>, <192>, - <193>, <194>, <195>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <87>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 77 0>; - clock-names = "gpio"; - }; - - main_gpio1: gpio@601000 { - compatible = "ti,am64-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00601000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <180>, <181>, <182>, - <183>, <184>, <185>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <88>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 78 0>; - clock-names = "gpio"; - }; - - sdhci0: mmc@fa10000 { - compatible = "ti,am64-sdhci-8bit"; - reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; - clock-names = "clk_ahb", "clk_xin"; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - ti,trm-icp = <0x2>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x6>; - ti,otap-del-sel-hs200 = <0x7>; - }; - - sdhci1: mmc@fa00000 { - compatible = "ti,am64-sdhci-4bit"; - reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; - interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; - clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x6>; - ti,otap-del-sel-ddr50 = <0x9>; - ti,clkbuf-sel = <0x7>; - }; - - cpsw3g: ethernet@8000000 { - compatible = "ti,am642-cpsw-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x8000000 0x0 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; - clocks = <&k3_clks 13 0>; - assigned-clocks = <&k3_clks 13 1>; - assigned-clock-parents = <&k3_clks 13 9>; - clock-names = "fck"; - power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&main_pktdma 0xC500 15>, - <&main_pktdma 0xC501 15>, - <&main_pktdma 0xC502 15>, - <&main_pktdma 0xC503 15>, - <&main_pktdma 0xC504 15>, - <&main_pktdma 0xC505 15>, - <&main_pktdma 0xC506 15>, - <&main_pktdma 0xC507 15>, - <&main_pktdma 0x4500 15>; - dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", - "tx7", "rx"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - phys = <&phy_gmii_sel 1>; - mac-address = [00 00 00 00 00 00]; - ti,syscon-efuse = <&main_conf 0x200>; - }; - - cpsw_port2: port@2 { - reg = <2>; - ti,mac-only; - label = "port2"; - phys = <&phy_gmii_sel 2>; - mac-address = [00 00 00 00 00 00]; - }; - }; - - cpsw3g_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x0 0xf00 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 13 0>; - clock-names = "fck"; - bus_freq = <1000000>; - status = "disabled"; - }; - - cpts@3d000 { - compatible = "ti,j721e-cpts"; - reg = <0x0 0x3d000 0x0 0x400>; - clocks = <&k3_clks 13 1>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - main_cpts0: cpts@39000000 { - compatible = "ti,j721e-cpts"; - reg = <0x0 0x39000000 0x0 0x400>; - reg-names = "cpts"; - power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 84 0>; - clock-names = "cpts"; - assigned-clocks = <&k3_clks 84 0>; - assigned-clock-parents = <&k3_clks 84 8>; - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-periodic-outputs = <6>; - ti,cpts-ext-ts-inputs = <8>; - }; - - timesync_router: pinctrl@a40000 { - compatible = "pinctrl-single"; - reg = <0x0 0xa40000 0x0 0x800>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x000107ff>; - }; - - usbss0: cdns-usb@f900000 { - compatible = "ti,am64-usb"; - reg = <0x00 0xf900000 0x00 0x100>; - power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */ - #address-cells = <2>; - #size-cells = <2>; - ranges; - usb0: usb@f400000 { - compatible = "cdns,usb3"; - reg = <0x00 0xf400000 0x00 0x10000>, - <0x00 0xf410000 0x00 0x10000>, - <0x00 0xf420000 0x00 0x10000>; - reg-names = "otg", - "xhci", - "dev"; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ - <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ - <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */ - interrupt-names = "host", - "peripheral", - "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - }; - }; - - tscadc0: tscadc@28001000 { - compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; - reg = <0x00 0x28001000 0x00 0x1000>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 0 0>; - assigned-clocks = <&k3_clks 0 0>; - assigned-clock-parents = <&k3_clks 0 3>; - assigned-clock-rates = <60000000>; - clock-names = "fck"; - status = "disabled"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am654-adc", "ti,am3359-adc"; - }; - }; - - fss: bus@fc00000 { - compatible = "simple-bus"; - reg = <0x00 0x0fc00000 0x00 0x70000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ospi0: spi@fc40000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x00 0x0fc40000 0x00 0x100>, - <0x05 0x00000000 0x01 0x00000000>; - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - #address-cells = <0x1>; - #size-cells = <0x0>; - clocks = <&k3_clks 75 6>; - assigned-clocks = <&k3_clks 75 6>; - assigned-clock-parents = <&k3_clks 75 7>; - assigned-clock-rates = <166666666>; - power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - }; - - hwspinlock: spinlock@2a000000 { - compatible = "ti,am64-hwspinlock"; - reg = <0x00 0x2a000000 0x00 0x1000>; - #hwlock-cells = <1>; - }; - - mailbox0_cluster2: mailbox@29020000 { - compatible = "ti,am64-mailbox"; - reg = <0x00 0x29020000 0x00 0x200>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - status = "disabled"; - }; - - mailbox0_cluster3: mailbox@29030000 { - compatible = "ti,am64-mailbox"; - reg = <0x00 0x29030000 0x00 0x200>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - status = "disabled"; - }; - - mailbox0_cluster4: mailbox@29040000 { - compatible = "ti,am64-mailbox"; - reg = <0x00 0x29040000 0x00 0x200>; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - status = "disabled"; - }; - - mailbox0_cluster5: mailbox@29050000 { - compatible = "ti,am64-mailbox"; - reg = <0x00 0x29050000 0x00 0x200>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - status = "disabled"; - }; - - mailbox0_cluster6: mailbox@29060000 { - compatible = "ti,am64-mailbox"; - reg = <0x00 0x29060000 0x00 0x200>; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - status = "disabled"; - }; - - mailbox0_cluster7: mailbox@29070000 { - compatible = "ti,am64-mailbox"; - reg = <0x00 0x29070000 0x00 0x200>; - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - status = "disabled"; - }; - - main_r5fss0: r5fss@78000000 { - compatible = "ti,am64-r5fss"; - ti,cluster-mode = <0>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x78000000 0x00 0x78000000 0x10000>, - <0x78100000 0x00 0x78100000 0x10000>, - <0x78200000 0x00 0x78200000 0x08000>, - <0x78300000 0x00 0x78300000 0x08000>; - power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; - - main_r5fss0_core0: r5f@78000000 { - compatible = "ti,am64-r5f"; - reg = <0x78000000 0x00010000>, - <0x78100000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <121>; - ti,sci-proc-ids = <0x01 0xff>; - resets = <&k3_reset 121 1>; - firmware-name = "am64-main-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - main_r5fss0_core1: r5f@78200000 { - compatible = "ti,am64-r5f"; - reg = <0x78200000 0x00008000>, - <0x78300000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <122>; - ti,sci-proc-ids = <0x02 0xff>; - resets = <&k3_reset 122 1>; - firmware-name = "am64-main-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - main_r5fss1: r5fss@78400000 { - compatible = "ti,am64-r5fss"; - ti,cluster-mode = <0>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x78400000 0x00 0x78400000 0x10000>, - <0x78500000 0x00 0x78500000 0x10000>, - <0x78600000 0x00 0x78600000 0x08000>, - <0x78700000 0x00 0x78700000 0x08000>; - power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - - main_r5fss1_core0: r5f@78400000 { - compatible = "ti,am64-r5f"; - reg = <0x78400000 0x00010000>, - <0x78500000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <123>; - ti,sci-proc-ids = <0x06 0xff>; - resets = <&k3_reset 123 1>; - firmware-name = "am64-main-r5f1_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - main_r5fss1_core1: r5f@78600000 { - compatible = "ti,am64-r5f"; - reg = <0x78600000 0x00008000>, - <0x78700000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <124>; - ti,sci-proc-ids = <0x07 0xff>; - resets = <&k3_reset 124 1>; - firmware-name = "am64-main-r5f1_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - serdes_wiz0: wiz@f000000 { - compatible = "ti,am64-wiz-10g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - num-lanes = <1>; - #reset-cells = <1>; - #clock-cells = <1>; - ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; - - assigned-clocks = <&k3_clks 162 1>; - assigned-clock-parents = <&k3_clks 162 5>; - - serdes0: serdes@f000000 { - compatible = "ti,j721e-serdes-10g"; - reg = <0x0f000000 0x00010000>; - reg-names = "torrent_phy"; - resets = <&serdes_wiz0 0>; - reset-names = "torrent_reset"; - clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, - <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; - clock-names = "refclk", "phy_en_refclk"; - assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, - <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, - <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; - assigned-clock-parents = <&k3_clks 162 1>, - <&k3_clks 162 1>, - <&k3_clks 162 1>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - }; - }; - - pcie0_rc: pcie@f102000 { - compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; - reg = <0x00 0x0f102000 0x00 0x1000>, - <0x00 0x0f100000 0x00 0x400>, - <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x68000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&main_conf 0x4070>; - max-link-speed = <2>; - num-lanes = <1>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; - clock-names = "fck", "pcie_refclk"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - cdns,no-bar-match-nbits = <64>; - vendor-id = <0x104c>; - device-id = <0xb010>; - msi-map = <0x0 &gic_its 0x0 0x10000>; - ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, - <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; - status = "disabled"; - }; - - pcie0_ep: pcie-ep@f102000 { - compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; - reg = <0x00 0x0f102000 0x00 0x1000>, - <0x00 0x0f100000 0x00 0x400>, - <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x68000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; - ti,syscon-pcie-ctrl = <&main_conf 0x4070>; - max-link-speed = <2>; - num-lanes = <1>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "fck"; - max-functions = /bits/ 8 <1>; - status = "disabled"; - }; - - epwm0: pwm@23000000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x0 0x23000000 0x0 0x100>; - power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - epwm1: pwm@23010000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x0 0x23010000 0x0 0x100>; - power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - epwm2: pwm@23020000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x0 0x23020000 0x0 0x100>; - power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - epwm3: pwm@23030000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x0 0x23030000 0x0 0x100>; - power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - epwm4: pwm@23040000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x0 0x23040000 0x0 0x100>; - power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - epwm5: pwm@23050000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x0 0x23050000 0x0 0x100>; - power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - epwm6: pwm@23060000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x0 0x23060000 0x0 0x100>; - power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - epwm7: pwm@23070000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x0 0x23070000 0x0 0x100>; - power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - epwm8: pwm@23080000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x0 0x23080000 0x0 0x100>; - power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - ecap0: pwm@23100000 { - compatible = "ti,am64-ecap", "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x0 0x23100000 0x0 0x60>; - power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 51 0>; - clock-names = "fck"; - status = "disabled"; - }; - - ecap1: pwm@23110000 { - compatible = "ti,am64-ecap", "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x0 0x23110000 0x0 0x60>; - power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 52 0>; - clock-names = "fck"; - status = "disabled"; - }; - - ecap2: pwm@23120000 { - compatible = "ti,am64-ecap", "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x0 0x23120000 0x0 0x60>; - power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 53 0>; - clock-names = "fck"; - status = "disabled"; - }; - - main_rti0: watchdog@e000000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0xe000000 0x00 0x100>; - clocks = <&k3_clks 125 0>; - power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 125 0>; - assigned-clock-parents = <&k3_clks 125 2>; - }; - - main_rti1: watchdog@e010000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0xe010000 0x00 0x100>; - clocks = <&k3_clks 126 0>; - power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 126 0>; - assigned-clock-parents = <&k3_clks 126 2>; - }; - - icssg0: icssg@30000000 { - compatible = "ti,am642-icssg"; - reg = <0x00 0x30000000 0x00 0x80000>; - power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x30000000 0x80000>; - - icssg0_mem: memories@0 { - reg = <0x0 0x2000>, - <0x2000 0x2000>, - <0x10000 0x10000>; - reg-names = "dram0", "dram1", "shrdram2"; - }; - - icssg0_cfg: cfg@26000 { - compatible = "ti,pruss-cfg", "syscon"; - reg = <0x26000 0x200>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x2000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - icssg0_coreclk_mux: coreclk-mux@3c { - reg = <0x3c>; - #clock-cells = <0>; - clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ - <&k3_clks 81 20>; /* icssg0_iclk */ - assigned-clocks = <&icssg0_coreclk_mux>; - assigned-clock-parents = <&k3_clks 81 20>; - }; - - icssg0_iepclk_mux: iepclk-mux@30 { - reg = <0x30>; - #clock-cells = <0>; - clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */ - <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */ - assigned-clocks = <&icssg0_iepclk_mux>; - assigned-clock-parents = <&icssg0_coreclk_mux>; - }; - }; - }; - - icssg0_mii_rt: mii-rt@32000 { - compatible = "ti,pruss-mii", "syscon"; - reg = <0x32000 0x100>; - }; - - icssg0_mii_g_rt: mii-g-rt@33000 { - compatible = "ti,pruss-mii-g", "syscon"; - reg = <0x33000 0x1000>; - }; - - icssg0_intc: interrupt-controller@20000 { - compatible = "ti,icssg-intc"; - reg = <0x20000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host_intr0", "host_intr1", - "host_intr2", "host_intr3", - "host_intr4", "host_intr5", - "host_intr6", "host_intr7"; - }; - - pru0_0: pru@34000 { - compatible = "ti,am642-pru"; - reg = <0x34000 0x3000>, - <0x22000 0x100>, - <0x22400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am64x-pru0_0-fw"; - }; - - rtu0_0: rtu@4000 { - compatible = "ti,am642-rtu"; - reg = <0x4000 0x2000>, - <0x23000 0x100>, - <0x23400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am64x-rtu0_0-fw"; - }; - - tx_pru0_0: txpru@a000 { - compatible = "ti,am642-tx-pru"; - reg = <0xa000 0x1800>, - <0x25000 0x100>, - <0x25400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am64x-txpru0_0-fw"; - }; - - pru0_1: pru@38000 { - compatible = "ti,am642-pru"; - reg = <0x38000 0x3000>, - <0x24000 0x100>, - <0x24400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am64x-pru0_1-fw"; - }; - - rtu0_1: rtu@6000 { - compatible = "ti,am642-rtu"; - reg = <0x6000 0x2000>, - <0x23800 0x100>, - <0x23c00 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am64x-rtu0_1-fw"; - }; - - tx_pru0_1: txpru@c000 { - compatible = "ti,am642-tx-pru"; - reg = <0xc000 0x1800>, - <0x25800 0x100>, - <0x25c00 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am64x-txpru0_1-fw"; - }; - - icssg0_mdio: mdio@32400 { - compatible = "ti,davinci_mdio"; - reg = <0x32400 0x100>; - clocks = <&k3_clks 62 3>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - status = "disabled"; - }; - }; - - icssg1: icssg@30080000 { - compatible = "ti,am642-icssg"; - reg = <0x00 0x30080000 0x00 0x80000>; - power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x30080000 0x80000>; - - icssg1_mem: memories@0 { - reg = <0x0 0x2000>, - <0x2000 0x2000>, - <0x10000 0x10000>; - reg-names = "dram0", "dram1", "shrdram2"; - }; - - icssg1_cfg: cfg@26000 { - compatible = "ti,pruss-cfg", "syscon"; - reg = <0x26000 0x200>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x2000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - icssg1_coreclk_mux: coreclk-mux@3c { - reg = <0x3c>; - #clock-cells = <0>; - clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ - <&k3_clks 82 20>; /* icssg1_iclk */ - assigned-clocks = <&icssg1_coreclk_mux>; - assigned-clock-parents = <&k3_clks 82 20>; - }; - - icssg1_iepclk_mux: iepclk-mux@30 { - reg = <0x30>; - #clock-cells = <0>; - clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */ - <&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */ - assigned-clocks = <&icssg1_iepclk_mux>; - assigned-clock-parents = <&icssg1_coreclk_mux>; - }; - }; - }; - - icssg1_mii_rt: mii-rt@32000 { - compatible = "ti,pruss-mii", "syscon"; - reg = <0x32000 0x100>; - }; - - icssg1_mii_g_rt: mii-g-rt@33000 { - compatible = "ti,pruss-mii-g", "syscon"; - reg = <0x33000 0x1000>; - }; - - icssg1_intc: interrupt-controller@20000 { - compatible = "ti,icssg-intc"; - reg = <0x20000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host_intr0", "host_intr1", - "host_intr2", "host_intr3", - "host_intr4", "host_intr5", - "host_intr6", "host_intr7"; - }; - - pru1_0: pru@34000 { - compatible = "ti,am642-pru"; - reg = <0x34000 0x4000>, - <0x22000 0x100>, - <0x22400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am64x-pru1_0-fw"; - }; - - rtu1_0: rtu@4000 { - compatible = "ti,am642-rtu"; - reg = <0x4000 0x2000>, - <0x23000 0x100>, - <0x23400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am64x-rtu1_0-fw"; - }; - - tx_pru1_0: txpru@a000 { - compatible = "ti,am642-tx-pru"; - reg = <0xa000 0x1800>, - <0x25000 0x100>, - <0x25400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am64x-txpru1_0-fw"; - }; - - pru1_1: pru@38000 { - compatible = "ti,am642-pru"; - reg = <0x38000 0x4000>, - <0x24000 0x100>, - <0x24400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am64x-pru1_1-fw"; - }; - - rtu1_1: rtu@6000 { - compatible = "ti,am642-rtu"; - reg = <0x6000 0x2000>, - <0x23800 0x100>, - <0x23c00 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am64x-rtu1_1-fw"; - }; - - tx_pru1_1: txpru@c000 { - compatible = "ti,am642-tx-pru"; - reg = <0xc000 0x1800>, - <0x25800 0x100>, - <0x25c00 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "am64x-txpru1_1-fw"; - }; - - icssg1_mdio: mdio@32400 { - compatible = "ti,davinci_mdio"; - reg = <0x32400 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 82 0>; - clock-names = "fck"; - bus_freq = <1000000>; - status = "disabled"; - }; - }; - - main_mcan0: can@20701000 { - compatible = "bosch,m_can"; - reg = <0x00 0x20701000 0x00 0x200>, - <0x00 0x20708000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 98 5>, <&k3_clks 98 0>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan1: can@20711000 { - compatible = "bosch,m_can"; - reg = <0x00 0x20711000 0x00 0x200>, - <0x00 0x20718000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 99 5>, <&k3_clks 99 0>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - crypto: crypto@40900000 { - compatible = "ti,am64-sa2ul"; - reg = <0x00 0x40900000 0x00 0x1200>; - power-domains = <&k3_pds 133 TI_SCI_PD_SHARED>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; - dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>, - <&main_pktdma 0x4003 0>; - dma-names = "tx", "rx1", "rx2"; - - rng: rng@40910000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0x00 0x40910000 0x00 0x7d>; - interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; /* Used by OP-TEE */ - }; - }; - - gpmc0: memory-controller@3b000000 { - compatible = "ti,am64-gpmc"; - power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 80 0>; - clock-names = "fck"; - reg = <0x00 0x3b000000 0x00 0x400>, - <0x00 0x50000000 0x00 0x8000000>; - reg-names = "cfg", "data"; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - gpmc,num-cs = <3>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - - elm0: ecc@25010000 { - compatible = "ti,am64-elm"; - reg = <0x00 0x25010000 0x00 0x2000>; - interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 54 0>; - clock-names = "fck"; - status = "disabled"; - }; - - main_vtm0: temperature-sensor@b00000 { - compatible = "ti,j7200-vtm"; - reg = <0x00 0xb00000 0x00 0x400>, - <0x00 0xb01000 0x00 0x400>; - power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; - #thermal-sensor-cells = <1>; - }; -}; diff --git a/arch/arm/dts/k3-am64-mcu.dtsi b/arch/arm/dts/k3-am64-mcu.dtsi deleted file mode 100644 index 686d4979072..00000000000 --- a/arch/arm/dts/k3-am64-mcu.dtsi +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM64 SoC Family MCU Domain peripherals - * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_mcu { - /* - * The MCU domain timer interrupts are routed only to the ESM module, - * and not currently available for Linux. The MCU domain timers are - * of limited use without interrupts, and likely reserved by the ESM. - */ - mcu_timer0: timer@4800000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x4800000 0x00 0x400>; - clocks = <&k3_clks 35 1>; - clock-names = "fck"; - power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - status = "reserved"; - }; - - mcu_timer1: timer@4810000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x4810000 0x00 0x400>; - clocks = <&k3_clks 48 1>; - clock-names = "fck"; - power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - status = "reserved"; - }; - - mcu_timer2: timer@4820000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x4820000 0x00 0x400>; - clocks = <&k3_clks 49 1>; - clock-names = "fck"; - power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - status = "reserved"; - }; - - mcu_timer3: timer@4830000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x4830000 0x00 0x400>; - clocks = <&k3_clks 50 1>; - clock-names = "fck"; - power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - status = "reserved"; - }; - - mcu_uart0: serial@4a00000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x04a00000 0x00 0x100>; - interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 149 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - mcu_uart1: serial@4a10000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x04a10000 0x00 0x100>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 160 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - mcu_i2c0: i2c@4900000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x04900000 0x00 0x100>; - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 106 2>; - clock-names = "fck"; - status = "disabled"; - }; - - mcu_i2c1: i2c@4910000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x04910000 0x00 0x100>; - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 107 2>; - clock-names = "fck"; - status = "disabled"; - }; - - mcu_spi0: spi@4b00000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x04b00000 0x00 0x400>; - interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 147 0>; - status = "disabled"; - }; - - mcu_spi1: spi@4b10000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x04b10000 0x00 0x400>; - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 148 0>; - status = "disabled"; - }; - - mcu_gpio_intr: interrupt-controller@4210000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x04210000 0x00 0x200>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <5>; - ti,interrupt-ranges = <0 104 4>; - }; - - mcu_gpio0: gpio@4201000 { - compatible = "ti,am64-gpio", "ti,keystone-gpio"; - reg = <0x0 0x4201000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&mcu_gpio_intr>; - interrupts = <30>, <31>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <23>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 79 0>; - clock-names = "gpio"; - }; - - mcu_pmx0: pinctrl@4084000 { - compatible = "pinctrl-single"; - reg = <0x00 0x4084000 0x00 0x84>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - mcu_esm: esm@4100000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x4100000 0x00 0x1000>; - ti,esm-pins = <0>, <1>; - }; -}; diff --git a/arch/arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi b/arch/arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi new file mode 100644 index 00000000000..14bccb7f390 --- /dev/null +++ b/arch/arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi @@ -0,0 +1,2189 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This file was generated with the + * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.10 + * Wed Dec 15 2021 14:35:01 GMT-0800 (Pacific Standard Time) + * DDR Type: DDR4 + * Frequency = 800MHz (1600MTs) + * Density: 16Gb + * Number of Ranks: 1 +*/ + +#define DDRSS_PLL_FHS_CNT 6 +#define DDRSS_PLL_FREQUENCY_1 400000000 +#define DDRSS_PLL_FREQUENCY_2 400000000 + +#define DDRSS_CTL_0_DATA 0x00000A00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x000890B8 +#define DDRSS_CTL_8_DATA 0x00000000 +#define DDRSS_CTL_9_DATA 0x00000000 +#define DDRSS_CTL_10_DATA 0x00000000 +#define DDRSS_CTL_11_DATA 0x000890B8 +#define DDRSS_CTL_12_DATA 0x00000000 +#define DDRSS_CTL_13_DATA 0x00000000 +#define DDRSS_CTL_14_DATA 0x00000000 +#define DDRSS_CTL_15_DATA 0x000890B8 +#define DDRSS_CTL_16_DATA 0x00000000 +#define DDRSS_CTL_17_DATA 0x00000000 +#define DDRSS_CTL_18_DATA 0x00000000 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01000100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x00027100 +#define DDRSS_CTL_24_DATA 0x00061A80 +#define DDRSS_CTL_25_DATA 0x02550255 +#define DDRSS_CTL_26_DATA 0x00000255 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00000000 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x00000000 +#define DDRSS_CTL_35_DATA 0x00000000 +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x0400091C +#define DDRSS_CTL_39_DATA 0x1C1C1C1C +#define DDRSS_CTL_40_DATA 0x0400091C +#define DDRSS_CTL_41_DATA 0x1C1C1C1C +#define DDRSS_CTL_42_DATA 0x0400091C +#define DDRSS_CTL_43_DATA 0x1C1C1C1C +#define DDRSS_CTL_44_DATA 0x05050404 +#define DDRSS_CTL_45_DATA 0x00002806 +#define DDRSS_CTL_46_DATA 0x0602001D +#define DDRSS_CTL_47_DATA 0x05001D0C +#define DDRSS_CTL_48_DATA 0x00280605 +#define DDRSS_CTL_49_DATA 0x0602001D +#define DDRSS_CTL_50_DATA 0x05001D0C +#define DDRSS_CTL_51_DATA 0x00280605 +#define DDRSS_CTL_52_DATA 0x0602001D +#define DDRSS_CTL_53_DATA 0x07001D0C +#define DDRSS_CTL_54_DATA 0x00180807 +#define DDRSS_CTL_55_DATA 0x0400DB60 +#define DDRSS_CTL_56_DATA 0x07070009 +#define DDRSS_CTL_57_DATA 0x00001808 +#define DDRSS_CTL_58_DATA 0x0400DB60 +#define DDRSS_CTL_59_DATA 0x07070009 +#define DDRSS_CTL_60_DATA 0x00001808 +#define DDRSS_CTL_61_DATA 0x0400DB60 +#define DDRSS_CTL_62_DATA 0x03000009 +#define DDRSS_CTL_63_DATA 0x0D0D0002 +#define DDRSS_CTL_64_DATA 0x0D0D0D0D +#define DDRSS_CTL_65_DATA 0x01010000 +#define DDRSS_CTL_66_DATA 0x031A1A1A +#define DDRSS_CTL_67_DATA 0x0C0C0C0C +#define DDRSS_CTL_68_DATA 0x00000C0C +#define DDRSS_CTL_69_DATA 0x00000101 +#define DDRSS_CTL_70_DATA 0x00000000 +#define DDRSS_CTL_71_DATA 0x01000000 +#define DDRSS_CTL_72_DATA 0x01180803 +#define DDRSS_CTL_73_DATA 0x00001860 +#define DDRSS_CTL_74_DATA 0x00000118 +#define DDRSS_CTL_75_DATA 0x00001860 +#define DDRSS_CTL_76_DATA 0x00000118 +#define DDRSS_CTL_77_DATA 0x00001860 +#define DDRSS_CTL_78_DATA 0x00000005 +#define DDRSS_CTL_79_DATA 0x00000000 +#define DDRSS_CTL_80_DATA 0x00000000 +#define DDRSS_CTL_81_DATA 0x00000000 +#define DDRSS_CTL_82_DATA 0x00000000 +#define DDRSS_CTL_83_DATA 0x00000000 +#define DDRSS_CTL_84_DATA 0x00000000 +#define DDRSS_CTL_85_DATA 0x00000000 +#define DDRSS_CTL_86_DATA 0x00000000 +#define DDRSS_CTL_87_DATA 0x00090009 +#define DDRSS_CTL_88_DATA 0x00000009 +#define DDRSS_CTL_89_DATA 0x00000000 +#define DDRSS_CTL_90_DATA 0x00000000 +#define DDRSS_CTL_91_DATA 0x00000000 +#define DDRSS_CTL_92_DATA 0x00000000 +#define DDRSS_CTL_93_DATA 0x00000000 +#define DDRSS_CTL_94_DATA 0x00010001 +#define DDRSS_CTL_95_DATA 0x00025501 +#define DDRSS_CTL_96_DATA 0x02550120 +#define DDRSS_CTL_97_DATA 0x02550120 +#define DDRSS_CTL_98_DATA 0x01200120 +#define DDRSS_CTL_99_DATA 0x01200120 +#define DDRSS_CTL_100_DATA 0x00000000 +#define DDRSS_CTL_101_DATA 0x00000000 +#define DDRSS_CTL_102_DATA 0x00000000 +#define DDRSS_CTL_103_DATA 0x00000000 +#define DDRSS_CTL_104_DATA 0x00000000 +#define DDRSS_CTL_105_DATA 0x00000000 +#define DDRSS_CTL_106_DATA 0x03010000 +#define DDRSS_CTL_107_DATA 0x00010000 +#define DDRSS_CTL_108_DATA 0x00000000 +#define DDRSS_CTL_109_DATA 0x01000000 +#define DDRSS_CTL_110_DATA 0x80104002 +#define DDRSS_CTL_111_DATA 0x00040003 +#define DDRSS_CTL_112_DATA 0x00040005 +#define DDRSS_CTL_113_DATA 0x00030000 +#define DDRSS_CTL_114_DATA 0x00050004 +#define DDRSS_CTL_115_DATA 0x00000004 +#define DDRSS_CTL_116_DATA 0x00040003 +#define DDRSS_CTL_117_DATA 0x00040005 +#define DDRSS_CTL_118_DATA 0x00000000 +#define DDRSS_CTL_119_DATA 0x00061800 +#define DDRSS_CTL_120_DATA 0x00061800 +#define DDRSS_CTL_121_DATA 0x00061800 +#define DDRSS_CTL_122_DATA 0x00061800 +#define DDRSS_CTL_123_DATA 0x00061800 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000AAA0 +#define DDRSS_CTL_126_DATA 0x00061800 +#define DDRSS_CTL_127_DATA 0x00061800 +#define DDRSS_CTL_128_DATA 0x00061800 +#define DDRSS_CTL_129_DATA 0x00061800 +#define DDRSS_CTL_130_DATA 0x00061800 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x0000AAA0 +#define DDRSS_CTL_133_DATA 0x00061800 +#define DDRSS_CTL_134_DATA 0x00061800 +#define DDRSS_CTL_135_DATA 0x00061800 +#define DDRSS_CTL_136_DATA 0x00061800 +#define DDRSS_CTL_137_DATA 0x00061800 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x0000AAA0 +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x080C0000 +#define DDRSS_CTL_157_DATA 0x080C080C +#define DDRSS_CTL_158_DATA 0x00000000 +#define DDRSS_CTL_159_DATA 0x07010A09 +#define DDRSS_CTL_160_DATA 0x000E0A09 +#define DDRSS_CTL_161_DATA 0x010A0900 +#define DDRSS_CTL_162_DATA 0x0E0A0907 +#define DDRSS_CTL_163_DATA 0x0A090000 +#define DDRSS_CTL_164_DATA 0x0A090701 +#define DDRSS_CTL_165_DATA 0x0000000E +#define DDRSS_CTL_166_DATA 0x00040003 +#define DDRSS_CTL_167_DATA 0x00000007 +#define DDRSS_CTL_168_DATA 0x00000000 +#define DDRSS_CTL_169_DATA 0x00000000 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x01000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x00001500 +#define DDRSS_CTL_177_DATA 0x0000100E +#define DDRSS_CTL_178_DATA 0x00000000 +#define DDRSS_CTL_179_DATA 0x00000000 +#define DDRSS_CTL_180_DATA 0x00000001 +#define DDRSS_CTL_181_DATA 0x00000002 +#define DDRSS_CTL_182_DATA 0x00000C00 +#define DDRSS_CTL_183_DATA 0x00001000 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00001000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00001000 +#define DDRSS_CTL_188_DATA 0x00000000 +#define DDRSS_CTL_189_DATA 0x00000000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x00000000 +#define DDRSS_CTL_193_DATA 0x00000000 +#define DDRSS_CTL_194_DATA 0x00000000 +#define DDRSS_CTL_195_DATA 0x00000000 +#define DDRSS_CTL_196_DATA 0x00000000 +#define DDRSS_CTL_197_DATA 0x00000000 +#define DDRSS_CTL_198_DATA 0x00000000 +#define DDRSS_CTL_199_DATA 0x00000000 +#define DDRSS_CTL_200_DATA 0x00000000 +#define DDRSS_CTL_201_DATA 0x00000000 +#define DDRSS_CTL_202_DATA 0x00000000 +#define DDRSS_CTL_203_DATA 0x00000000 +#define DDRSS_CTL_204_DATA 0x00042400 +#define DDRSS_CTL_205_DATA 0x00000301 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000424 +#define DDRSS_CTL_208_DATA 0x00000301 +#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_210_DATA 0x00000424 +#define DDRSS_CTL_211_DATA 0x00000301 +#define DDRSS_CTL_212_DATA 0x00000000 +#define DDRSS_CTL_213_DATA 0x00000424 +#define DDRSS_CTL_214_DATA 0x00000301 +#define DDRSS_CTL_215_DATA 0x00000000 +#define DDRSS_CTL_216_DATA 0x00000424 +#define DDRSS_CTL_217_DATA 0x00000301 +#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_219_DATA 0x00000424 +#define DDRSS_CTL_220_DATA 0x00000301 +#define DDRSS_CTL_221_DATA 0x00000000 +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x00000000 +#define DDRSS_CTL_224_DATA 0x00000000 +#define DDRSS_CTL_225_DATA 0x00000000 +#define DDRSS_CTL_226_DATA 0x00000000 +#define DDRSS_CTL_227_DATA 0x00000000 +#define DDRSS_CTL_228_DATA 0x00000000 +#define DDRSS_CTL_229_DATA 0x00000000 +#define DDRSS_CTL_230_DATA 0x00000000 +#define DDRSS_CTL_231_DATA 0x00000000 +#define DDRSS_CTL_232_DATA 0x00000000 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00001401 +#define DDRSS_CTL_237_DATA 0x00001401 +#define DDRSS_CTL_238_DATA 0x00001401 +#define DDRSS_CTL_239_DATA 0x00001401 +#define DDRSS_CTL_240_DATA 0x00001401 +#define DDRSS_CTL_241_DATA 0x00001401 +#define DDRSS_CTL_242_DATA 0x00000493 +#define DDRSS_CTL_243_DATA 0x00000493 +#define DDRSS_CTL_244_DATA 0x00000493 +#define DDRSS_CTL_245_DATA 0x00000493 +#define DDRSS_CTL_246_DATA 0x00000493 +#define DDRSS_CTL_247_DATA 0x00000493 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x00000000 +#define DDRSS_CTL_255_DATA 0x00000000 +#define DDRSS_CTL_256_DATA 0x00000000 +#define DDRSS_CTL_257_DATA 0x00000000 +#define DDRSS_CTL_258_DATA 0x00000000 +#define DDRSS_CTL_259_DATA 0x00000000 +#define DDRSS_CTL_260_DATA 0x00000000 +#define DDRSS_CTL_261_DATA 0x00000000 +#define DDRSS_CTL_262_DATA 0x00000000 +#define DDRSS_CTL_263_DATA 0x00000000 +#define DDRSS_CTL_264_DATA 0x00000000 +#define DDRSS_CTL_265_DATA 0x00000000 +#define DDRSS_CTL_266_DATA 0x00000000 +#define DDRSS_CTL_267_DATA 0x00000000 +#define DDRSS_CTL_268_DATA 0x00000000 +#define DDRSS_CTL_269_DATA 0x00000000 +#define DDRSS_CTL_270_DATA 0x00000000 +#define DDRSS_CTL_271_DATA 0x00000000 +#define DDRSS_CTL_272_DATA 0x00000000 +#define DDRSS_CTL_273_DATA 0x00000000 +#define DDRSS_CTL_274_DATA 0x00000000 +#define DDRSS_CTL_275_DATA 0x00000000 +#define DDRSS_CTL_276_DATA 0x00000000 +#define DDRSS_CTL_277_DATA 0x00010000 +#define DDRSS_CTL_278_DATA 0x00000000 +#define DDRSS_CTL_279_DATA 0x00000000 +#define DDRSS_CTL_280_DATA 0x00000000 +#define DDRSS_CTL_281_DATA 0x00000101 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000000 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x0C181511 +#define DDRSS_CTL_291_DATA 0x00000304 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x00000000 +#define DDRSS_CTL_297_DATA 0x00000000 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00040000 +#define DDRSS_CTL_306_DATA 0x00800200 +#define DDRSS_CTL_307_DATA 0x00000000 +#define DDRSS_CTL_308_DATA 0x02000400 +#define DDRSS_CTL_309_DATA 0x00000080 +#define DDRSS_CTL_310_DATA 0x00040000 +#define DDRSS_CTL_311_DATA 0x00800200 +#define DDRSS_CTL_312_DATA 0x00000000 +#define DDRSS_CTL_313_DATA 0x00000000 +#define DDRSS_CTL_314_DATA 0x00000000 +#define DDRSS_CTL_315_DATA 0x00000100 +#define DDRSS_CTL_316_DATA 0x01010000 +#define DDRSS_CTL_317_DATA 0x00000000 +#define DDRSS_CTL_318_DATA 0x3FFF0000 +#define DDRSS_CTL_319_DATA 0x000FFF00 +#define DDRSS_CTL_320_DATA 0xFFFFFFFF +#define DDRSS_CTL_321_DATA 0x000FFF00 +#define DDRSS_CTL_322_DATA 0x0A000000 +#define DDRSS_CTL_323_DATA 0x0001FFFF +#define DDRSS_CTL_324_DATA 0x01010101 +#define DDRSS_CTL_325_DATA 0x01010101 +#define DDRSS_CTL_326_DATA 0x00000118 +#define DDRSS_CTL_327_DATA 0x00000C01 +#define DDRSS_CTL_328_DATA 0x00000000 +#define DDRSS_CTL_329_DATA 0x00000000 +#define DDRSS_CTL_330_DATA 0x01000000 +#define DDRSS_CTL_331_DATA 0x01000000 +#define DDRSS_CTL_332_DATA 0x00000100 +#define DDRSS_CTL_333_DATA 0x00010000 +#define DDRSS_CTL_334_DATA 0x00000000 +#define DDRSS_CTL_335_DATA 0x00000000 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x00000000 +#define DDRSS_CTL_339_DATA 0x00000000 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x00000000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x00000000 +#define DDRSS_CTL_361_DATA 0x00000000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0x00000000 +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00000000 +#define DDRSS_CTL_366_DATA 0x00000000 +#define DDRSS_CTL_367_DATA 0x00000000 +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x0C000000 +#define DDRSS_CTL_371_DATA 0x060C0606 +#define DDRSS_CTL_372_DATA 0x06060C06 +#define DDRSS_CTL_373_DATA 0x00010101 +#define DDRSS_CTL_374_DATA 0x02000000 +#define DDRSS_CTL_375_DATA 0x05020101 +#define DDRSS_CTL_376_DATA 0x00000505 +#define DDRSS_CTL_377_DATA 0x02020200 +#define DDRSS_CTL_378_DATA 0x02020202 +#define DDRSS_CTL_379_DATA 0x02020202 +#define DDRSS_CTL_380_DATA 0x02020202 +#define DDRSS_CTL_381_DATA 0x00000000 +#define DDRSS_CTL_382_DATA 0x00000000 +#define DDRSS_CTL_383_DATA 0x04000100 +#define DDRSS_CTL_384_DATA 0x1E000004 +#define DDRSS_CTL_385_DATA 0x000030C0 +#define DDRSS_CTL_386_DATA 0x00000200 +#define DDRSS_CTL_387_DATA 0x00000200 +#define DDRSS_CTL_388_DATA 0x00000200 +#define DDRSS_CTL_389_DATA 0x00000200 +#define DDRSS_CTL_390_DATA 0x0000DB60 +#define DDRSS_CTL_391_DATA 0x0001E780 +#define DDRSS_CTL_392_DATA 0x0C0D0302 +#define DDRSS_CTL_393_DATA 0x001E090A +#define DDRSS_CTL_394_DATA 0x000030C0 +#define DDRSS_CTL_395_DATA 0x00000200 +#define DDRSS_CTL_396_DATA 0x00000200 +#define DDRSS_CTL_397_DATA 0x00000200 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x0000DB60 +#define DDRSS_CTL_400_DATA 0x0001E780 +#define DDRSS_CTL_401_DATA 0x0C0D0302 +#define DDRSS_CTL_402_DATA 0x001E090A +#define DDRSS_CTL_403_DATA 0x000030C0 +#define DDRSS_CTL_404_DATA 0x00000200 +#define DDRSS_CTL_405_DATA 0x00000200 +#define DDRSS_CTL_406_DATA 0x00000200 +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x0000DB60 +#define DDRSS_CTL_409_DATA 0x0001E780 +#define DDRSS_CTL_410_DATA 0x0C0D0302 +#define DDRSS_CTL_411_DATA 0x0000090A +#define DDRSS_CTL_412_DATA 0x00000000 +#define DDRSS_CTL_413_DATA 0x0302000A +#define DDRSS_CTL_414_DATA 0x01000500 +#define DDRSS_CTL_415_DATA 0x01010001 +#define DDRSS_CTL_416_DATA 0x00010001 +#define DDRSS_CTL_417_DATA 0x01010001 +#define DDRSS_CTL_418_DATA 0x02010000 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x02000201 +#define DDRSS_CTL_421_DATA 0x00000000 +#define DDRSS_CTL_422_DATA 0x00202020 +#define DDRSS_PI_0_DATA 0x00000A00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000000 +#define DDRSS_PI_12_DATA 0x00000000 +#define DDRSS_PI_13_DATA 0x00010001 +#define DDRSS_PI_14_DATA 0x00000000 +#define DDRSS_PI_15_DATA 0x00010001 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00000000 +#define DDRSS_PI_24_DATA 0x280D0001 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x00010000 +#define DDRSS_PI_27_DATA 0x00003200 +#define DDRSS_PI_28_DATA 0x00000000 +#define DDRSS_PI_29_DATA 0x00000000 +#define DDRSS_PI_30_DATA 0x00060602 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x00000000 +#define DDRSS_PI_34_DATA 0x00000001 +#define DDRSS_PI_35_DATA 0x00000055 +#define DDRSS_PI_36_DATA 0x000000AA +#define DDRSS_PI_37_DATA 0x000000AD +#define DDRSS_PI_38_DATA 0x00000052 +#define DDRSS_PI_39_DATA 0x0000006A +#define DDRSS_PI_40_DATA 0x00000095 +#define DDRSS_PI_41_DATA 0x00000095 +#define DDRSS_PI_42_DATA 0x000000AD +#define DDRSS_PI_43_DATA 0x00000000 +#define DDRSS_PI_44_DATA 0x00000000 +#define DDRSS_PI_45_DATA 0x00010100 +#define DDRSS_PI_46_DATA 0x00000014 +#define DDRSS_PI_47_DATA 0x000007D0 +#define DDRSS_PI_48_DATA 0x00000300 +#define DDRSS_PI_49_DATA 0x00000000 +#define DDRSS_PI_50_DATA 0x00000000 +#define DDRSS_PI_51_DATA 0x01000000 +#define DDRSS_PI_52_DATA 0x00010101 +#define DDRSS_PI_53_DATA 0x01000000 +#define DDRSS_PI_54_DATA 0x00000000 +#define DDRSS_PI_55_DATA 0x00010000 +#define DDRSS_PI_56_DATA 0x00000000 +#define DDRSS_PI_57_DATA 0x00000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x00000000 +#define DDRSS_PI_60_DATA 0x00001400 +#define DDRSS_PI_61_DATA 0x00000000 +#define DDRSS_PI_62_DATA 0x01000000 +#define DDRSS_PI_63_DATA 0x00000404 +#define DDRSS_PI_64_DATA 0x00000001 +#define DDRSS_PI_65_DATA 0x0001010E +#define DDRSS_PI_66_DATA 0x02040100 +#define DDRSS_PI_67_DATA 0x00010000 +#define DDRSS_PI_68_DATA 0x00000034 +#define DDRSS_PI_69_DATA 0x00000000 +#define DDRSS_PI_70_DATA 0x00000000 +#define DDRSS_PI_71_DATA 0x00000000 +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x00000000 +#define DDRSS_PI_75_DATA 0x00000005 +#define DDRSS_PI_76_DATA 0x01000000 +#define DDRSS_PI_77_DATA 0x04000100 +#define DDRSS_PI_78_DATA 0x00020000 +#define DDRSS_PI_79_DATA 0x00010002 +#define DDRSS_PI_80_DATA 0x00000001 +#define DDRSS_PI_81_DATA 0x00020001 +#define DDRSS_PI_82_DATA 0x00020002 +#define DDRSS_PI_83_DATA 0x00000000 +#define DDRSS_PI_84_DATA 0x00000000 +#define DDRSS_PI_85_DATA 0x00000000 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000300 +#define DDRSS_PI_92_DATA 0x0A090B0C +#define DDRSS_PI_93_DATA 0x04060708 +#define DDRSS_PI_94_DATA 0x01000005 +#define DDRSS_PI_95_DATA 0x00000800 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00010008 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x0000AA00 +#define DDRSS_PI_100_DATA 0x00000000 +#define DDRSS_PI_101_DATA 0x00010000 +#define DDRSS_PI_102_DATA 0x00000000 +#define DDRSS_PI_103_DATA 0x00000000 +#define DDRSS_PI_104_DATA 0x00000000 +#define DDRSS_PI_105_DATA 0x00000000 +#define DDRSS_PI_106_DATA 0x00000000 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x00000000 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00000000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000008 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00010100 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x00027100 +#define DDRSS_PI_137_DATA 0x00061A80 +#define DDRSS_PI_138_DATA 0x00000100 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x01000000 +#define DDRSS_PI_145_DATA 0x00010003 +#define DDRSS_PI_146_DATA 0x02000101 +#define DDRSS_PI_147_DATA 0x01030001 +#define DDRSS_PI_148_DATA 0x00010400 +#define DDRSS_PI_149_DATA 0x06000105 +#define DDRSS_PI_150_DATA 0x01070001 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00010000 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x00000000 +#define DDRSS_PI_157_DATA 0x00000000 +#define DDRSS_PI_158_DATA 0x00000000 +#define DDRSS_PI_159_DATA 0x00010000 +#define DDRSS_PI_160_DATA 0x00000004 +#define DDRSS_PI_161_DATA 0x00000000 +#define DDRSS_PI_162_DATA 0x00000000 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00007800 +#define DDRSS_PI_165_DATA 0x00780078 +#define DDRSS_PI_166_DATA 0x00141414 +#define DDRSS_PI_167_DATA 0x0000003A +#define DDRSS_PI_168_DATA 0x0000003A +#define DDRSS_PI_169_DATA 0x0004003A +#define DDRSS_PI_170_DATA 0x04000400 +#define DDRSS_PI_171_DATA 0x68040009 +#define DDRSS_PI_172_DATA 0x0400091C +#define DDRSS_PI_173_DATA 0x00091C68 +#define DDRSS_PI_174_DATA 0x001C6804 +#define DDRSS_PI_175_DATA 0x00000118 +#define DDRSS_PI_176_DATA 0x00001860 +#define DDRSS_PI_177_DATA 0x00000118 +#define DDRSS_PI_178_DATA 0x00001860 +#define DDRSS_PI_179_DATA 0x00000118 +#define DDRSS_PI_180_DATA 0x04001860 +#define DDRSS_PI_181_DATA 0x01010404 +#define DDRSS_PI_182_DATA 0x00001901 +#define DDRSS_PI_183_DATA 0x00190019 +#define DDRSS_PI_184_DATA 0x010C010C +#define DDRSS_PI_185_DATA 0x0000010C +#define DDRSS_PI_186_DATA 0x00000000 +#define DDRSS_PI_187_DATA 0x05000000 +#define DDRSS_PI_188_DATA 0x01010505 +#define DDRSS_PI_189_DATA 0x01010101 +#define DDRSS_PI_190_DATA 0x00181818 +#define DDRSS_PI_191_DATA 0x00000000 +#define DDRSS_PI_192_DATA 0x00000000 +#define DDRSS_PI_193_DATA 0x0D000000 +#define DDRSS_PI_194_DATA 0x0A0A0D0D +#define DDRSS_PI_195_DATA 0x0303030A +#define DDRSS_PI_196_DATA 0x00000000 +#define DDRSS_PI_197_DATA 0x00000000 +#define DDRSS_PI_198_DATA 0x00000000 +#define DDRSS_PI_199_DATA 0x00000000 +#define DDRSS_PI_200_DATA 0x00000000 +#define DDRSS_PI_201_DATA 0x00000000 +#define DDRSS_PI_202_DATA 0x00000000 +#define DDRSS_PI_203_DATA 0x00000000 +#define DDRSS_PI_204_DATA 0x00000000 +#define DDRSS_PI_205_DATA 0x00000000 +#define DDRSS_PI_206_DATA 0x00000000 +#define DDRSS_PI_207_DATA 0x00000000 +#define DDRSS_PI_208_DATA 0x00000000 +#define DDRSS_PI_209_DATA 0x0D090000 +#define DDRSS_PI_210_DATA 0x0D09000D +#define DDRSS_PI_211_DATA 0x0D09000D +#define DDRSS_PI_212_DATA 0x0000000D +#define DDRSS_PI_213_DATA 0x00000000 +#define DDRSS_PI_214_DATA 0x00000000 +#define DDRSS_PI_215_DATA 0x00000000 +#define DDRSS_PI_216_DATA 0x00000000 +#define DDRSS_PI_217_DATA 0x16000000 +#define DDRSS_PI_218_DATA 0x001600C8 +#define DDRSS_PI_219_DATA 0x001600C8 +#define DDRSS_PI_220_DATA 0x010100C8 +#define DDRSS_PI_221_DATA 0x00001B01 +#define DDRSS_PI_222_DATA 0x1F0F0053 +#define DDRSS_PI_223_DATA 0x05000001 +#define DDRSS_PI_224_DATA 0x001B0A0D +#define DDRSS_PI_225_DATA 0x1F0F0053 +#define DDRSS_PI_226_DATA 0x05000001 +#define DDRSS_PI_227_DATA 0x001B0A0D +#define DDRSS_PI_228_DATA 0x1F0F0053 +#define DDRSS_PI_229_DATA 0x05000001 +#define DDRSS_PI_230_DATA 0x00010A0D +#define DDRSS_PI_231_DATA 0x0D0C0700 +#define DDRSS_PI_232_DATA 0x000D0605 +#define DDRSS_PI_233_DATA 0x0000C570 +#define DDRSS_PI_234_DATA 0x0000001D +#define DDRSS_PI_235_DATA 0x180A0800 +#define DDRSS_PI_236_DATA 0x0C071C1C +#define DDRSS_PI_237_DATA 0x0D06050D +#define DDRSS_PI_238_DATA 0x0000C570 +#define DDRSS_PI_239_DATA 0x0000001D +#define DDRSS_PI_240_DATA 0x180A0800 +#define DDRSS_PI_241_DATA 0x0C071C1C +#define DDRSS_PI_242_DATA 0x0D06050D +#define DDRSS_PI_243_DATA 0x0000C570 +#define DDRSS_PI_244_DATA 0x0000001D +#define DDRSS_PI_245_DATA 0x180A0800 +#define DDRSS_PI_246_DATA 0x00001C1C +#define DDRSS_PI_247_DATA 0x000030C0 +#define DDRSS_PI_248_DATA 0x0001E780 +#define DDRSS_PI_249_DATA 0x000030C0 +#define DDRSS_PI_250_DATA 0x0001E780 +#define DDRSS_PI_251_DATA 0x000030C0 +#define DDRSS_PI_252_DATA 0x0001E780 +#define DDRSS_PI_253_DATA 0x02550255 +#define DDRSS_PI_254_DATA 0x03030255 +#define DDRSS_PI_255_DATA 0x00025503 +#define DDRSS_PI_256_DATA 0x02550255 +#define DDRSS_PI_257_DATA 0x0C080C08 +#define DDRSS_PI_258_DATA 0x00000C08 +#define DDRSS_PI_259_DATA 0x000890B8 +#define DDRSS_PI_260_DATA 0x00000000 +#define DDRSS_PI_261_DATA 0x00000000 +#define DDRSS_PI_262_DATA 0x00000000 +#define DDRSS_PI_263_DATA 0x00000120 +#define DDRSS_PI_264_DATA 0x000890B8 +#define DDRSS_PI_265_DATA 0x00000000 +#define DDRSS_PI_266_DATA 0x00000000 +#define DDRSS_PI_267_DATA 0x00000000 +#define DDRSS_PI_268_DATA 0x00000120 +#define DDRSS_PI_269_DATA 0x000890B8 +#define DDRSS_PI_270_DATA 0x00000000 +#define DDRSS_PI_271_DATA 0x00000000 +#define DDRSS_PI_272_DATA 0x00000000 +#define DDRSS_PI_273_DATA 0x02000120 +#define DDRSS_PI_274_DATA 0x00000080 +#define DDRSS_PI_275_DATA 0x00020000 +#define DDRSS_PI_276_DATA 0x00000080 +#define DDRSS_PI_277_DATA 0x00020000 +#define DDRSS_PI_278_DATA 0x00000080 +#define DDRSS_PI_279_DATA 0x00000000 +#define DDRSS_PI_280_DATA 0x00000000 +#define DDRSS_PI_281_DATA 0x00040404 +#define DDRSS_PI_282_DATA 0x00000000 +#define DDRSS_PI_283_DATA 0x02010102 +#define DDRSS_PI_284_DATA 0x67676767 +#define DDRSS_PI_285_DATA 0x00000202 +#define DDRSS_PI_286_DATA 0x00000000 +#define DDRSS_PI_287_DATA 0x00000000 +#define DDRSS_PI_288_DATA 0x00000000 +#define DDRSS_PI_289_DATA 0x00000000 +#define DDRSS_PI_290_DATA 0x00000000 +#define DDRSS_PI_291_DATA 0x0D100F00 +#define DDRSS_PI_292_DATA 0x0003020E +#define DDRSS_PI_293_DATA 0x00000001 +#define DDRSS_PI_294_DATA 0x01000000 +#define DDRSS_PI_295_DATA 0x00020201 +#define DDRSS_PI_296_DATA 0x00000000 +#define DDRSS_PI_297_DATA 0x00000424 +#define DDRSS_PI_298_DATA 0x00000301 +#define DDRSS_PI_299_DATA 0x00000000 +#define DDRSS_PI_300_DATA 0x00000000 +#define DDRSS_PI_301_DATA 0x00000000 +#define DDRSS_PI_302_DATA 0x00001401 +#define DDRSS_PI_303_DATA 0x00000493 +#define DDRSS_PI_304_DATA 0x00000000 +#define DDRSS_PI_305_DATA 0x00000424 +#define DDRSS_PI_306_DATA 0x00000301 +#define DDRSS_PI_307_DATA 0x00000000 +#define DDRSS_PI_308_DATA 0x00000000 +#define DDRSS_PI_309_DATA 0x00000000 +#define DDRSS_PI_310_DATA 0x00001401 +#define DDRSS_PI_311_DATA 0x00000493 +#define DDRSS_PI_312_DATA 0x00000000 +#define DDRSS_PI_313_DATA 0x00000424 +#define DDRSS_PI_314_DATA 0x00000301 +#define DDRSS_PI_315_DATA 0x00000000 +#define DDRSS_PI_316_DATA 0x00000000 +#define DDRSS_PI_317_DATA 0x00000000 +#define DDRSS_PI_318_DATA 0x00001401 +#define DDRSS_PI_319_DATA 0x00000493 +#define DDRSS_PI_320_DATA 0x00000000 +#define DDRSS_PI_321_DATA 0x00000424 +#define DDRSS_PI_322_DATA 0x00000301 +#define DDRSS_PI_323_DATA 0x00000000 +#define DDRSS_PI_324_DATA 0x00000000 +#define DDRSS_PI_325_DATA 0x00000000 +#define DDRSS_PI_326_DATA 0x00001401 +#define DDRSS_PI_327_DATA 0x00000493 +#define DDRSS_PI_328_DATA 0x00000000 +#define DDRSS_PI_329_DATA 0x00000424 +#define DDRSS_PI_330_DATA 0x00000301 +#define DDRSS_PI_331_DATA 0x00000000 +#define DDRSS_PI_332_DATA 0x00000000 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x00001401 +#define DDRSS_PI_335_DATA 0x00000493 +#define DDRSS_PI_336_DATA 0x00000000 +#define DDRSS_PI_337_DATA 0x00000424 +#define DDRSS_PI_338_DATA 0x00000301 +#define DDRSS_PI_339_DATA 0x00000000 +#define DDRSS_PI_340_DATA 0x00000000 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x00001401 +#define DDRSS_PI_343_DATA 0x00000493 +#define DDRSS_PI_344_DATA 0x00000000 +#define DDRSS_PHY_0_DATA 0x04C00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00000200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x00000000 +#define DDRSS_PHY_6_DATA 0x00000000 +#define DDRSS_PHY_7_DATA 0x00000000 +#define DDRSS_PHY_8_DATA 0x00000001 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x010101FF +#define DDRSS_PHY_12_DATA 0x00010000 +#define DDRSS_PHY_13_DATA 0x00C00004 +#define DDRSS_PHY_14_DATA 0x00CC0008 +#define DDRSS_PHY_15_DATA 0x00660201 +#define DDRSS_PHY_16_DATA 0x00000000 +#define DDRSS_PHY_17_DATA 0x00000000 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x0000AAAA +#define DDRSS_PHY_20_DATA 0x00005555 +#define DDRSS_PHY_21_DATA 0x0000B5B5 +#define DDRSS_PHY_22_DATA 0x00004A4A +#define DDRSS_PHY_23_DATA 0x00005656 +#define DDRSS_PHY_24_DATA 0x0000A9A9 +#define DDRSS_PHY_25_DATA 0x0000B7B7 +#define DDRSS_PHY_26_DATA 0x00004848 +#define DDRSS_PHY_27_DATA 0x00000000 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x08000000 +#define DDRSS_PHY_30_DATA 0x0F000008 +#define DDRSS_PHY_31_DATA 0x00000F0F +#define DDRSS_PHY_32_DATA 0x00E4E400 +#define DDRSS_PHY_33_DATA 0x00070820 +#define DDRSS_PHY_34_DATA 0x000C0020 +#define DDRSS_PHY_35_DATA 0x00062000 +#define DDRSS_PHY_36_DATA 0x00000000 +#define DDRSS_PHY_37_DATA 0x55555555 +#define DDRSS_PHY_38_DATA 0xAAAAAAAA +#define DDRSS_PHY_39_DATA 0x55555555 +#define DDRSS_PHY_40_DATA 0xAAAAAAAA +#define DDRSS_PHY_41_DATA 0x00005555 +#define DDRSS_PHY_42_DATA 0x01000100 +#define DDRSS_PHY_43_DATA 0x00800180 +#define DDRSS_PHY_44_DATA 0x00000000 +#define DDRSS_PHY_45_DATA 0x00000000 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000004 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000000 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x041F07FF +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x01CCB001 +#define DDRSS_PHY_75_DATA 0x2000CCB0 +#define DDRSS_PHY_76_DATA 0x20000140 +#define DDRSS_PHY_77_DATA 0x07FF0200 +#define DDRSS_PHY_78_DATA 0x0000DD01 +#define DDRSS_PHY_79_DATA 0x10100303 +#define DDRSS_PHY_80_DATA 0x10101010 +#define DDRSS_PHY_81_DATA 0x10101010 +#define DDRSS_PHY_82_DATA 0x00021010 +#define DDRSS_PHY_83_DATA 0x00100010 +#define DDRSS_PHY_84_DATA 0x00100010 +#define DDRSS_PHY_85_DATA 0x00100010 +#define DDRSS_PHY_86_DATA 0x00100010 +#define DDRSS_PHY_87_DATA 0x02020010 +#define DDRSS_PHY_88_DATA 0x51515041 +#define DDRSS_PHY_89_DATA 0x31804000 +#define DDRSS_PHY_90_DATA 0x04BF0340 +#define DDRSS_PHY_91_DATA 0x01008080 +#define DDRSS_PHY_92_DATA 0x04050001 +#define DDRSS_PHY_93_DATA 0x00000504 +#define DDRSS_PHY_94_DATA 0x42100010 +#define DDRSS_PHY_95_DATA 0x010C053E +#define DDRSS_PHY_96_DATA 0x000F0C14 +#define DDRSS_PHY_97_DATA 0x01000140 +#define DDRSS_PHY_98_DATA 0x007A0120 +#define DDRSS_PHY_99_DATA 0x00000C00 +#define DDRSS_PHY_100_DATA 0x000001CC +#define DDRSS_PHY_101_DATA 0x20100200 +#define DDRSS_PHY_102_DATA 0x00000005 +#define DDRSS_PHY_103_DATA 0x76543210 +#define DDRSS_PHY_104_DATA 0x00000008 +#define DDRSS_PHY_105_DATA 0x02800280 +#define DDRSS_PHY_106_DATA 0x02800280 +#define DDRSS_PHY_107_DATA 0x02800280 +#define DDRSS_PHY_108_DATA 0x02800280 +#define DDRSS_PHY_109_DATA 0x00000280 +#define DDRSS_PHY_110_DATA 0x00008000 +#define DDRSS_PHY_111_DATA 0x00800080 +#define DDRSS_PHY_112_DATA 0x00800080 +#define DDRSS_PHY_113_DATA 0x00800080 +#define DDRSS_PHY_114_DATA 0x00800080 +#define DDRSS_PHY_115_DATA 0x00800080 +#define DDRSS_PHY_116_DATA 0x00800080 +#define DDRSS_PHY_117_DATA 0x00800080 +#define DDRSS_PHY_118_DATA 0x00800080 +#define DDRSS_PHY_119_DATA 0x01000080 +#define DDRSS_PHY_120_DATA 0x01A00000 +#define DDRSS_PHY_121_DATA 0x00000000 +#define DDRSS_PHY_122_DATA 0x00000000 +#define DDRSS_PHY_123_DATA 0x00080200 +#define DDRSS_PHY_124_DATA 0x00000000 +#define DDRSS_PHY_125_DATA 0x00000000 +#define DDRSS_PHY_126_DATA 0x00000000 +#define DDRSS_PHY_127_DATA 0x00000000 +#define DDRSS_PHY_128_DATA 0x00000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00000000 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x00000000 +#define DDRSS_PHY_134_DATA 0x00000000 +#define DDRSS_PHY_135_DATA 0x00000000 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04C00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00000200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x00000000 +#define DDRSS_PHY_262_DATA 0x00000000 +#define DDRSS_PHY_263_DATA 0x00000000 +#define DDRSS_PHY_264_DATA 0x00000001 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x010101FF +#define DDRSS_PHY_268_DATA 0x00010000 +#define DDRSS_PHY_269_DATA 0x00C00004 +#define DDRSS_PHY_270_DATA 0x00CC0008 +#define DDRSS_PHY_271_DATA 0x00660201 +#define DDRSS_PHY_272_DATA 0x00000000 +#define DDRSS_PHY_273_DATA 0x00000000 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x0000AAAA +#define DDRSS_PHY_276_DATA 0x00005555 +#define DDRSS_PHY_277_DATA 0x0000B5B5 +#define DDRSS_PHY_278_DATA 0x00004A4A +#define DDRSS_PHY_279_DATA 0x00005656 +#define DDRSS_PHY_280_DATA 0x0000A9A9 +#define DDRSS_PHY_281_DATA 0x0000B7B7 +#define DDRSS_PHY_282_DATA 0x00004848 +#define DDRSS_PHY_283_DATA 0x00000000 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x08000000 +#define DDRSS_PHY_286_DATA 0x0F000008 +#define DDRSS_PHY_287_DATA 0x00000F0F +#define DDRSS_PHY_288_DATA 0x00E4E400 +#define DDRSS_PHY_289_DATA 0x00070820 +#define DDRSS_PHY_290_DATA 0x000C0020 +#define DDRSS_PHY_291_DATA 0x00062000 +#define DDRSS_PHY_292_DATA 0x00000000 +#define DDRSS_PHY_293_DATA 0x55555555 +#define DDRSS_PHY_294_DATA 0xAAAAAAAA +#define DDRSS_PHY_295_DATA 0x55555555 +#define DDRSS_PHY_296_DATA 0xAAAAAAAA +#define DDRSS_PHY_297_DATA 0x00005555 +#define DDRSS_PHY_298_DATA 0x01000100 +#define DDRSS_PHY_299_DATA 0x00800180 +#define DDRSS_PHY_300_DATA 0x00000000 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000004 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000000 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x041F07FF +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x01CCB001 +#define DDRSS_PHY_331_DATA 0x2000CCB0 +#define DDRSS_PHY_332_DATA 0x20000140 +#define DDRSS_PHY_333_DATA 0x07FF0200 +#define DDRSS_PHY_334_DATA 0x0000DD01 +#define DDRSS_PHY_335_DATA 0x10100303 +#define DDRSS_PHY_336_DATA 0x10101010 +#define DDRSS_PHY_337_DATA 0x10101010 +#define DDRSS_PHY_338_DATA 0x00021010 +#define DDRSS_PHY_339_DATA 0x00100010 +#define DDRSS_PHY_340_DATA 0x00100010 +#define DDRSS_PHY_341_DATA 0x00100010 +#define DDRSS_PHY_342_DATA 0x00100010 +#define DDRSS_PHY_343_DATA 0x02020010 +#define DDRSS_PHY_344_DATA 0x51515041 +#define DDRSS_PHY_345_DATA 0x31804000 +#define DDRSS_PHY_346_DATA 0x04BF0340 +#define DDRSS_PHY_347_DATA 0x01008080 +#define DDRSS_PHY_348_DATA 0x04050001 +#define DDRSS_PHY_349_DATA 0x00000504 +#define DDRSS_PHY_350_DATA 0x42100010 +#define DDRSS_PHY_351_DATA 0x010C053E +#define DDRSS_PHY_352_DATA 0x000F0C14 +#define DDRSS_PHY_353_DATA 0x01000140 +#define DDRSS_PHY_354_DATA 0x007A0120 +#define DDRSS_PHY_355_DATA 0x00000C00 +#define DDRSS_PHY_356_DATA 0x000001CC +#define DDRSS_PHY_357_DATA 0x20100200 +#define DDRSS_PHY_358_DATA 0x00000005 +#define DDRSS_PHY_359_DATA 0x76543210 +#define DDRSS_PHY_360_DATA 0x00000008 +#define DDRSS_PHY_361_DATA 0x02800280 +#define DDRSS_PHY_362_DATA 0x02800280 +#define DDRSS_PHY_363_DATA 0x02800280 +#define DDRSS_PHY_364_DATA 0x02800280 +#define DDRSS_PHY_365_DATA 0x00000280 +#define DDRSS_PHY_366_DATA 0x00008000 +#define DDRSS_PHY_367_DATA 0x00800080 +#define DDRSS_PHY_368_DATA 0x00800080 +#define DDRSS_PHY_369_DATA 0x00800080 +#define DDRSS_PHY_370_DATA 0x00800080 +#define DDRSS_PHY_371_DATA 0x00800080 +#define DDRSS_PHY_372_DATA 0x00800080 +#define DDRSS_PHY_373_DATA 0x00800080 +#define DDRSS_PHY_374_DATA 0x00800080 +#define DDRSS_PHY_375_DATA 0x01000080 +#define DDRSS_PHY_376_DATA 0x01A00000 +#define DDRSS_PHY_377_DATA 0x00000000 +#define DDRSS_PHY_378_DATA 0x00000000 +#define DDRSS_PHY_379_DATA 0x00080200 +#define DDRSS_PHY_380_DATA 0x00000000 +#define DDRSS_PHY_381_DATA 0x00000000 +#define DDRSS_PHY_382_DATA 0x00000000 +#define DDRSS_PHY_383_DATA 0x00000000 +#define DDRSS_PHY_384_DATA 0x00000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00000000 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x00000000 +#define DDRSS_PHY_390_DATA 0x00000000 +#define DDRSS_PHY_391_DATA 0x00000000 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x00000100 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00000000 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x00000100 +#define DDRSS_PHY_518_DATA 0x00000000 +#define DDRSS_PHY_519_DATA 0x00000000 +#define DDRSS_PHY_520_DATA 0x00000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00000000 +#define DDRSS_PHY_524_DATA 0x00000000 +#define DDRSS_PHY_525_DATA 0x00DCBA98 +#define DDRSS_PHY_526_DATA 0x00000000 +#define DDRSS_PHY_527_DATA 0x00000000 +#define DDRSS_PHY_528_DATA 0x00000000 +#define DDRSS_PHY_529_DATA 0x00000000 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000000 +#define DDRSS_PHY_532_DATA 0x00000000 +#define DDRSS_PHY_533_DATA 0x00000000 +#define DDRSS_PHY_534_DATA 0x00000000 +#define DDRSS_PHY_535_DATA 0x00000000 +#define DDRSS_PHY_536_DATA 0x00000000 +#define DDRSS_PHY_537_DATA 0x00000000 +#define DDRSS_PHY_538_DATA 0x00000000 +#define DDRSS_PHY_539_DATA 0x00000000 +#define DDRSS_PHY_540_DATA 0x0A418820 +#define DDRSS_PHY_541_DATA 0x103F0000 +#define DDRSS_PHY_542_DATA 0x000F0100 +#define DDRSS_PHY_543_DATA 0x0000000F +#define DDRSS_PHY_544_DATA 0x020002CC +#define DDRSS_PHY_545_DATA 0x00030000 +#define DDRSS_PHY_546_DATA 0x00000300 +#define DDRSS_PHY_547_DATA 0x00000300 +#define DDRSS_PHY_548_DATA 0x00000300 +#define DDRSS_PHY_549_DATA 0x00000300 +#define DDRSS_PHY_550_DATA 0x00000300 +#define DDRSS_PHY_551_DATA 0x42080010 +#define DDRSS_PHY_552_DATA 0x0000003E +#define DDRSS_PHY_553_DATA 0x00000000 +#define DDRSS_PHY_554_DATA 0x00000000 +#define DDRSS_PHY_555_DATA 0x00000000 +#define DDRSS_PHY_556_DATA 0x00000000 +#define DDRSS_PHY_557_DATA 0x00000000 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000000 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x00000000 +#define DDRSS_PHY_587_DATA 0x00000000 +#define DDRSS_PHY_588_DATA 0x00000000 +#define DDRSS_PHY_589_DATA 0x00000000 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x00000000 +#define DDRSS_PHY_592_DATA 0x00000000 +#define DDRSS_PHY_593_DATA 0x00000000 +#define DDRSS_PHY_594_DATA 0x00000000 +#define DDRSS_PHY_595_DATA 0x00000000 +#define DDRSS_PHY_596_DATA 0x00000000 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00000000 +#define DDRSS_PHY_600_DATA 0x00000000 +#define DDRSS_PHY_601_DATA 0x00000000 +#define DDRSS_PHY_602_DATA 0x00000000 +#define DDRSS_PHY_603_DATA 0x00000000 +#define DDRSS_PHY_604_DATA 0x00000000 +#define DDRSS_PHY_605_DATA 0x00000000 +#define DDRSS_PHY_606_DATA 0x00000000 +#define DDRSS_PHY_607_DATA 0x00000000 +#define DDRSS_PHY_608_DATA 0x00000000 +#define DDRSS_PHY_609_DATA 0x00000000 +#define DDRSS_PHY_610_DATA 0x00000000 +#define DDRSS_PHY_611_DATA 0x00000000 +#define DDRSS_PHY_612_DATA 0x00000000 +#define DDRSS_PHY_613_DATA 0x00000000 +#define DDRSS_PHY_614_DATA 0x00000000 +#define DDRSS_PHY_615_DATA 0x00000000 +#define DDRSS_PHY_616_DATA 0x00000000 +#define DDRSS_PHY_617_DATA 0x00000000 +#define DDRSS_PHY_618_DATA 0x00000000 +#define DDRSS_PHY_619_DATA 0x00000000 +#define DDRSS_PHY_620_DATA 0x00000000 +#define DDRSS_PHY_621_DATA 0x00000000 +#define DDRSS_PHY_622_DATA 0x00000000 +#define DDRSS_PHY_623_DATA 0x00000000 +#define DDRSS_PHY_624_DATA 0x00000000 +#define DDRSS_PHY_625_DATA 0x00000000 +#define DDRSS_PHY_626_DATA 0x00000000 +#define DDRSS_PHY_627_DATA 0x00000000 +#define DDRSS_PHY_628_DATA 0x00000000 +#define DDRSS_PHY_629_DATA 0x00000000 +#define DDRSS_PHY_630_DATA 0x00000000 +#define DDRSS_PHY_631_DATA 0x00000000 +#define DDRSS_PHY_632_DATA 0x00000000 +#define DDRSS_PHY_633_DATA 0x00000000 +#define DDRSS_PHY_634_DATA 0x00000000 +#define DDRSS_PHY_635_DATA 0x00000000 +#define DDRSS_PHY_636_DATA 0x00000000 +#define DDRSS_PHY_637_DATA 0x00000000 +#define DDRSS_PHY_638_DATA 0x00000000 +#define DDRSS_PHY_639_DATA 0x00000000 +#define DDRSS_PHY_640_DATA 0x00000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00000000 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x00000000 +#define DDRSS_PHY_646_DATA 0x00000000 +#define DDRSS_PHY_647_DATA 0x00000000 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x00000100 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00000000 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x00000100 +#define DDRSS_PHY_774_DATA 0x00000000 +#define DDRSS_PHY_775_DATA 0x00000000 +#define DDRSS_PHY_776_DATA 0x00000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00000000 +#define DDRSS_PHY_780_DATA 0x00000000 +#define DDRSS_PHY_781_DATA 0x00DCBA98 +#define DDRSS_PHY_782_DATA 0x00000000 +#define DDRSS_PHY_783_DATA 0x00000000 +#define DDRSS_PHY_784_DATA 0x00000000 +#define DDRSS_PHY_785_DATA 0x00000000 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000000 +#define DDRSS_PHY_788_DATA 0x00000000 +#define DDRSS_PHY_789_DATA 0x00000000 +#define DDRSS_PHY_790_DATA 0x00000000 +#define DDRSS_PHY_791_DATA 0x00000000 +#define DDRSS_PHY_792_DATA 0x00000000 +#define DDRSS_PHY_793_DATA 0x00000000 +#define DDRSS_PHY_794_DATA 0x00000000 +#define DDRSS_PHY_795_DATA 0x00000000 +#define DDRSS_PHY_796_DATA 0x16A4A0E6 +#define DDRSS_PHY_797_DATA 0x103F0000 +#define DDRSS_PHY_798_DATA 0x000F0000 +#define DDRSS_PHY_799_DATA 0x0000000F +#define DDRSS_PHY_800_DATA 0x020002CC +#define DDRSS_PHY_801_DATA 0x00030000 +#define DDRSS_PHY_802_DATA 0x00000300 +#define DDRSS_PHY_803_DATA 0x00000300 +#define DDRSS_PHY_804_DATA 0x00000300 +#define DDRSS_PHY_805_DATA 0x00000300 +#define DDRSS_PHY_806_DATA 0x00000300 +#define DDRSS_PHY_807_DATA 0x42080010 +#define DDRSS_PHY_808_DATA 0x0000003E +#define DDRSS_PHY_809_DATA 0x00000000 +#define DDRSS_PHY_810_DATA 0x00000000 +#define DDRSS_PHY_811_DATA 0x00000000 +#define DDRSS_PHY_812_DATA 0x00000000 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000000 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x00000000 +#define DDRSS_PHY_843_DATA 0x00000000 +#define DDRSS_PHY_844_DATA 0x00000000 +#define DDRSS_PHY_845_DATA 0x00000000 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x00000000 +#define DDRSS_PHY_848_DATA 0x00000000 +#define DDRSS_PHY_849_DATA 0x00000000 +#define DDRSS_PHY_850_DATA 0x00000000 +#define DDRSS_PHY_851_DATA 0x00000000 +#define DDRSS_PHY_852_DATA 0x00000000 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00000000 +#define DDRSS_PHY_856_DATA 0x00000000 +#define DDRSS_PHY_857_DATA 0x00000000 +#define DDRSS_PHY_858_DATA 0x00000000 +#define DDRSS_PHY_859_DATA 0x00000000 +#define DDRSS_PHY_860_DATA 0x00000000 +#define DDRSS_PHY_861_DATA 0x00000000 +#define DDRSS_PHY_862_DATA 0x00000000 +#define DDRSS_PHY_863_DATA 0x00000000 +#define DDRSS_PHY_864_DATA 0x00000000 +#define DDRSS_PHY_865_DATA 0x00000000 +#define DDRSS_PHY_866_DATA 0x00000000 +#define DDRSS_PHY_867_DATA 0x00000000 +#define DDRSS_PHY_868_DATA 0x00000000 +#define DDRSS_PHY_869_DATA 0x00000000 +#define DDRSS_PHY_870_DATA 0x00000000 +#define DDRSS_PHY_871_DATA 0x00000000 +#define DDRSS_PHY_872_DATA 0x00000000 +#define DDRSS_PHY_873_DATA 0x00000000 +#define DDRSS_PHY_874_DATA 0x00000000 +#define DDRSS_PHY_875_DATA 0x00000000 +#define DDRSS_PHY_876_DATA 0x00000000 +#define DDRSS_PHY_877_DATA 0x00000000 +#define DDRSS_PHY_878_DATA 0x00000000 +#define DDRSS_PHY_879_DATA 0x00000000 +#define DDRSS_PHY_880_DATA 0x00000000 +#define DDRSS_PHY_881_DATA 0x00000000 +#define DDRSS_PHY_882_DATA 0x00000000 +#define DDRSS_PHY_883_DATA 0x00000000 +#define DDRSS_PHY_884_DATA 0x00000000 +#define DDRSS_PHY_885_DATA 0x00000000 +#define DDRSS_PHY_886_DATA 0x00000000 +#define DDRSS_PHY_887_DATA 0x00000000 +#define DDRSS_PHY_888_DATA 0x00000000 +#define DDRSS_PHY_889_DATA 0x00000000 +#define DDRSS_PHY_890_DATA 0x00000000 +#define DDRSS_PHY_891_DATA 0x00000000 +#define DDRSS_PHY_892_DATA 0x00000000 +#define DDRSS_PHY_893_DATA 0x00000000 +#define DDRSS_PHY_894_DATA 0x00000000 +#define DDRSS_PHY_895_DATA 0x00000000 +#define DDRSS_PHY_896_DATA 0x00000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00000000 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x00000000 +#define DDRSS_PHY_902_DATA 0x00000000 +#define DDRSS_PHY_903_DATA 0x00000000 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000100 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000000 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00000000 +#define DDRSS_PHY_1036_DATA 0x00000000 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x00000000 +#define DDRSS_PHY_1039_DATA 0x00000000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x00000000 +#define DDRSS_PHY_1045_DATA 0x00000000 +#define DDRSS_PHY_1046_DATA 0x00000000 +#define DDRSS_PHY_1047_DATA 0x00000000 +#define DDRSS_PHY_1048_DATA 0x00000000 +#define DDRSS_PHY_1049_DATA 0x00000000 +#define DDRSS_PHY_1050_DATA 0x00000000 +#define DDRSS_PHY_1051_DATA 0x00000000 +#define DDRSS_PHY_1052_DATA 0x2307B9AC +#define DDRSS_PHY_1053_DATA 0x10030000 +#define DDRSS_PHY_1054_DATA 0x000F0000 +#define DDRSS_PHY_1055_DATA 0x0000000F +#define DDRSS_PHY_1056_DATA 0x020002CC +#define DDRSS_PHY_1057_DATA 0x00030000 +#define DDRSS_PHY_1058_DATA 0x00000300 +#define DDRSS_PHY_1059_DATA 0x00000300 +#define DDRSS_PHY_1060_DATA 0x00000300 +#define DDRSS_PHY_1061_DATA 0x00000300 +#define DDRSS_PHY_1062_DATA 0x00000300 +#define DDRSS_PHY_1063_DATA 0x42080010 +#define DDRSS_PHY_1064_DATA 0x0000003E +#define DDRSS_PHY_1065_DATA 0x00000000 +#define DDRSS_PHY_1066_DATA 0x00000000 +#define DDRSS_PHY_1067_DATA 0x00000000 +#define DDRSS_PHY_1068_DATA 0x00000000 +#define DDRSS_PHY_1069_DATA 0x00000000 +#define DDRSS_PHY_1070_DATA 0x00000000 +#define DDRSS_PHY_1071_DATA 0x00000000 +#define DDRSS_PHY_1072_DATA 0x00000000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00000100 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000000 +#define DDRSS_PHY_1286_DATA 0x00050000 +#define DDRSS_PHY_1287_DATA 0x04000100 +#define DDRSS_PHY_1288_DATA 0x00000055 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00000000 +#define DDRSS_PHY_1292_DATA 0x00000000 +#define DDRSS_PHY_1293_DATA 0x01002000 +#define DDRSS_PHY_1294_DATA 0x00004001 +#define DDRSS_PHY_1295_DATA 0x00020028 +#define DDRSS_PHY_1296_DATA 0x00010100 +#define DDRSS_PHY_1297_DATA 0x00000001 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x0F0F0E06 +#define DDRSS_PHY_1300_DATA 0x00010101 +#define DDRSS_PHY_1301_DATA 0x010F0004 +#define DDRSS_PHY_1302_DATA 0x00000000 +#define DDRSS_PHY_1303_DATA 0x00000000 +#define DDRSS_PHY_1304_DATA 0x00000064 +#define DDRSS_PHY_1305_DATA 0x00000000 +#define DDRSS_PHY_1306_DATA 0x00000000 +#define DDRSS_PHY_1307_DATA 0x01020103 +#define DDRSS_PHY_1308_DATA 0x0F020102 +#define DDRSS_PHY_1309_DATA 0x03030303 +#define DDRSS_PHY_1310_DATA 0x03030303 +#define DDRSS_PHY_1311_DATA 0x00040000 +#define DDRSS_PHY_1312_DATA 0x00005201 +#define DDRSS_PHY_1313_DATA 0x00000000 +#define DDRSS_PHY_1314_DATA 0x00000000 +#define DDRSS_PHY_1315_DATA 0x00000000 +#define DDRSS_PHY_1316_DATA 0x00000000 +#define DDRSS_PHY_1317_DATA 0x00000000 +#define DDRSS_PHY_1318_DATA 0x00000000 +#define DDRSS_PHY_1319_DATA 0x07070001 +#define DDRSS_PHY_1320_DATA 0x00005400 +#define DDRSS_PHY_1321_DATA 0x000040A2 +#define DDRSS_PHY_1322_DATA 0x00024410 +#define DDRSS_PHY_1323_DATA 0x00004410 +#define DDRSS_PHY_1324_DATA 0x00004410 +#define DDRSS_PHY_1325_DATA 0x00004410 +#define DDRSS_PHY_1326_DATA 0x00004410 +#define DDRSS_PHY_1327_DATA 0x00004410 +#define DDRSS_PHY_1328_DATA 0x00004410 +#define DDRSS_PHY_1329_DATA 0x00004410 +#define DDRSS_PHY_1330_DATA 0x00004410 +#define DDRSS_PHY_1331_DATA 0x00004410 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000046 +#define DDRSS_PHY_1334_DATA 0x00010000 +#define DDRSS_PHY_1335_DATA 0x00000008 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x03000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x04102006 +#define DDRSS_PHY_1346_DATA 0x00041020 +#define DDRSS_PHY_1347_DATA 0x01C98C98 +#define DDRSS_PHY_1348_DATA 0x3F400000 +#define DDRSS_PHY_1349_DATA 0x3F3F1F3F +#define DDRSS_PHY_1350_DATA 0x0000001F +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000001 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x76543210 +#define DDRSS_PHY_1360_DATA 0x00000098 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00040700 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000002 +#define DDRSS_PHY_1369_DATA 0x00000100 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x0001F7C0 +#define DDRSS_PHY_1372_DATA 0x00020002 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00001142 +#define DDRSS_PHY_1375_DATA 0x03020400 +#define DDRSS_PHY_1376_DATA 0x00000080 +#define DDRSS_PHY_1377_DATA 0x03900390 +#define DDRSS_PHY_1378_DATA 0x03900390 +#define DDRSS_PHY_1379_DATA 0x03900390 +#define DDRSS_PHY_1380_DATA 0x03900390 +#define DDRSS_PHY_1381_DATA 0x03900390 +#define DDRSS_PHY_1382_DATA 0x03900390 +#define DDRSS_PHY_1383_DATA 0x00000300 +#define DDRSS_PHY_1384_DATA 0x00000300 +#define DDRSS_PHY_1385_DATA 0x00000300 +#define DDRSS_PHY_1386_DATA 0x00000300 +#define DDRSS_PHY_1387_DATA 0x31823FC7 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x0C000D3F +#define DDRSS_PHY_1390_DATA 0x30000D3F +#define DDRSS_PHY_1391_DATA 0x300D3F11 +#define DDRSS_PHY_1392_DATA 0x01990000 +#define DDRSS_PHY_1393_DATA 0x000D3FCC +#define DDRSS_PHY_1394_DATA 0x00000C11 +#define DDRSS_PHY_1395_DATA 0x300D3F11 +#define DDRSS_PHY_1396_DATA 0x01990000 +#define DDRSS_PHY_1397_DATA 0x300C3F11 +#define DDRSS_PHY_1398_DATA 0x01990000 +#define DDRSS_PHY_1399_DATA 0x300C3F11 +#define DDRSS_PHY_1400_DATA 0x01990000 +#define DDRSS_PHY_1401_DATA 0x300D3F11 +#define DDRSS_PHY_1402_DATA 0x01990000 +#define DDRSS_PHY_1403_DATA 0x300D3F11 +#define DDRSS_PHY_1404_DATA 0x01990000 +#define DDRSS_PHY_1405_DATA 0x20040001 diff --git a/arch/arm/dts/k3-am64-phycore-som.dtsi b/arch/arm/dts/k3-am64-phycore-som.dtsi new file mode 100644 index 00000000000..1678e74cb75 --- /dev/null +++ b/arch/arm/dts/k3-am64-phycore-som.dtsi @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com + * Author: Matt McKee <mmckee@phytec.com> + * + * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + * + * Product homepage: + * https://www.phytec.com/product/phycore-am64x + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/net/ti-dp83867.h> + +/ { + model = "PHYTEC phyCORE-AM64x"; + compatible = "phytec,am64-phycore-som", "ti,am642"; + + aliases { + ethernet0 = &cpsw_port1; + mmc0 = &sdhci0; + rtc0 = &i2c_som_rtc; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_default>; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + }; + }; + + vcc_5v0_som: regulator-vcc-5v0-som { + /* VIN / VCC_5V0_SOM */ + compatible = "regulator-fixed"; + regulator-name = "VCC_5V0_SOM"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&main_pmx0 { + cpsw_mdio_pins_default: cpsw-mdio-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ + AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ + AM64X_IOPAD(0x0100, PIN_OUTPUT, 7) /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */ + >; + }; + + cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ + AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ + AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ + AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ + AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ + AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ + AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ + AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ + AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ + AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ + AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ + AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ + AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) PRG1_PRU1_GPO19.GPIO0_84 */ + >; + }; + + eeprom_wp_pins_default: eeprom-wp-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0208, PIN_OUTPUT, 7) /* (D12) SPI0_CS0.GPIO1_42 */ + >; + }; + + leds_pins_default: leds-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* (L18) OSPI0_CSn1.GPIO0_12 */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */ + AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ + AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ + AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ + AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ + AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ + AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ + AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ + AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ + AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ + AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ + AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ + >; + }; + + rtc_pins_default: rtc-defaults-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* (C19) EXTINTn.GPIO1_70 */ + >; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_rgmii1_pins_default>; +}; + +&cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_mdio_pins_default>; + + cpsw3g_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&main_gpio0>; + interrupts = <84 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "atmel,24c32"; + pinctrl-names = "default"; + pinctrl-0 = <&eeprom_wp_pins_default>; + pagesize = <32>; + reg = <0x50>; + }; + + i2c_som_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_pins_default>; + interrupt-parent = <&main_gpio1>; + interrupts = <70 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <0>; + }; +}; + +&sdhci0 { + status = "okay"; + bus-width = <8>; + non-removable; + ti,driver-strength-ohm = <50>; + disable-wp; + keep-power-in-suspend; +}; diff --git a/arch/arm/dts/k3-am64-thermal.dtsi b/arch/arm/dts/k3-am64-thermal.dtsi deleted file mode 100644 index 036db56ba79..00000000000 --- a/arch/arm/dts/k3-am64-thermal.dtsi +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include <dt-bindings/thermal/thermal.h> - -thermal_zones: thermal-zones { - main0_thermal: main0-thermal { - polling-delay-passive = <250>; /* milliSeconds */ - polling-delay = <500>; /* milliSeconds */ - thermal-sensors = <&main_vtm0 0>; - - trips { - main0_crit: main0-crit { - temperature = <105000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - main1_thermal: main1-thermal { - polling-delay-passive = <250>; /* milliSeconds */ - polling-delay = <500>; /* milliSeconds */ - thermal-sensors = <&main_vtm0 1>; - - trips { - main1_crit: main1-crit { - temperature = <105000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; -}; diff --git a/arch/arm/dts/k3-am64.dtsi b/arch/arm/dts/k3-am64.dtsi deleted file mode 100644 index 8e9c2bc70f4..00000000000 --- a/arch/arm/dts/k3-am64.dtsi +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM642 SoC Family - * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/soc/ti,sci_pm_domain.h> - -#include "k3-pinctrl.h" - -/ { - model = "Texas Instruments K3 AM642 SoC"; - compatible = "ti,am642"; - interrupt-parent = <&gic500>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - }; - - a53_timer0: timer-cl0-cpu0 { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ - }; - - pmu: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; - }; - - cbass_main: bus@f4000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */ - <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ - <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ - <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ - <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */ - <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */ - <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */ - <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */ - <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ - <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */ - <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */ - <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */ - <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */ - <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */ - <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */ - <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA2_UL0 */ - <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ - <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */ - <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */ - <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ - <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */ - <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */ - <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ - <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ - - /* MCU Domain Range */ - <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; - - cbass_mcu: bus@4000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ - }; - }; - - #include "k3-am64-thermal.dtsi" -}; - -/* Now include the peripherals for each bus segments */ -#include "k3-am64-main.dtsi" -#include "k3-am64-mcu.dtsi" diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi index b8430782436..705b3baa81c 100644 --- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi @@ -9,97 +9,20 @@ chosen { tick-timer = &main_timer0; }; - - memory@80000000 { - bootph-all; - }; -}; - -&cbass_main { - bootph-all; }; &main_timer0 { - bootph-all; clock-frequency = <200000000>; }; -&main_conf { - bootph-all; - chipid@14 { - bootph-all; - }; -}; - -&main_pmx0 { - bootph-all; -}; - -&main_i2c0_pins_default { - bootph-all; -}; - -&main_i2c0 { - bootph-all; -}; - -&main_uart0_pins_default { - bootph-all; -}; - -&main_uart0 { - bootph-all; -}; - -&main_usb0_pins_default { - bootph-all; -}; - &usb0 { dr_mode="peripheral"; - bootph-all; -}; - -&usbss0 { - bootph-all; }; &main_mmc1_pins_default { bootph-all; }; -&main_usb0_pins_default { - bootph-all; -}; - -&dmss { - bootph-all; -}; - -&secure_proxy_main { - bootph-all; -}; - -&dmsc { - bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; -}; - -&k3_pds { - bootph-all; -}; - -&k3_clks { - bootph-all; -}; - -&k3_reset { - bootph-all; -}; - &sdhci0 { bootph-all; }; @@ -108,10 +31,6 @@ bootph-all; }; -&sdhci1 { - bootph-all; -}; - &inta_main_dmss { bootph-all; }; @@ -143,42 +62,22 @@ bootph-all; }; -&mdio1_pins_default { - bootph-all; -}; - -&cpsw3g_mdio { - bootph-all; -}; - -&cpsw3g_phy0 { - bootph-all; +&cpsw_port2 { + status = "disabled"; }; -&rgmii1_pins_default { +&ospi0_pins_default { bootph-all; }; -&rgmii2_pins_default { +&fss { bootph-all; }; -&cpsw3g { +&ospi0 { bootph-all; - ethernet-ports { + flash@0 { bootph-all; }; }; - -&phy_gmii_sel { - bootph-all; -}; - -&cpsw_port1 { - bootph-all; -}; - -&cpsw_port2 { - status = "disabled"; -}; diff --git a/arch/arm/dts/k3-am642-evm.dts b/arch/arm/dts/k3-am642-evm.dts deleted file mode 100644 index b4a1f73d4fb..00000000000 --- a/arch/arm/dts/k3-am642-evm.dts +++ /dev/null @@ -1,690 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include <dt-bindings/phy/phy.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/net/ti-dp83867.h> -#include "k3-am642.dtsi" - -#include "k3-serdes.h" - -/ { - compatible = "ti,am642-evm", "ti,am642"; - model = "Texas Instruments AM642 EVM"; - - chosen { - stdout-path = &main_uart0; - }; - - aliases { - serial0 = &mcu_uart0; - serial1 = &main_uart1; - serial2 = &main_uart0; - serial3 = &main_uart3; - i2c0 = &main_i2c0; - i2c1 = &main_i2c1; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - ethernet0 = &cpsw_port1; - ethernet1 = &cpsw_port2; - }; - - memory@80000000 { - device_type = "memory"; - /* 2G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ - alignment = <0x1000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a5000000 { - reg = <0x00 0xa5000000 0x00 0x00800000>; - alignment = <0x1000>; - no-map; - }; - }; - - evm_12v0: regulator-0 { - /* main DC jack */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_5v0: regulator-1 { - /* output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: regulator-2 { - /* output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: regulator-3 { - /* TPS2051BD */ - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&exp1 6 GPIO_ACTIVE_HIGH>; - }; - - vddb: regulator-4 { - compatible = "regulator-fixed"; - regulator-name = "vddb_3v3_display"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - regulator-boot-on; - }; - - vtt_supply: regulator-5 { - compatible = "regulator-fixed"; - regulator-name = "vtt"; - pinctrl-names = "default"; - pinctrl-0 = <&ddr_vtt_pins_default>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>; - vin-supply = <&vsys_3v3>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "am64-evm:red:heartbeat"; - gpios = <&exp1 16 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - function = LED_FUNCTION_HEARTBEAT; - default-state = "off"; - }; - }; - - mdio_mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - - mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>; - }; - - mdio-mux-1 { - compatible = "mdio-mux-multiplexer"; - mux-controls = <&mdio_mux>; - mdio-parent-bus = <&cpsw3g_mdio>; - #address-cells = <1>; - #size-cells = <0>; - - mdio@1 { - reg = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - - cpsw3g_phy3: ethernet-phy@3 { - reg = <3>; - }; - }; - }; - - transceiver1: can-phy0 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>; - }; - - transceiver2: can-phy1 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; - }; -}; - -&main_pmx0 { - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ - AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ - AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ - AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ - AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ - AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ - AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ - AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */ - AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */ - >; - }; - - main_uart1_pins_default: main-uart1-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ - AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ - AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ - AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ - >; - }; - - main_uart0_pins_default: main-uart0-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ - AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ - AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ - AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ - >; - }; - - main_spi0_pins_default: main-spi0-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ - AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */ - AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */ - AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ - AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ - AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ - >; - }; - - mdio1_pins_default: mdio1-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ - AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ - >; - }; - - rgmii1_pins_default: rgmii1-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ - AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ - AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ - AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ - AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ - AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ - AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ - AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ - AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ - AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ - AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ - AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ - >; - }; - - rgmii2_pins_default: rgmii2-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ - AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ - AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ - AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ - AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ - AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ - AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ - AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ - AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ - AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ - AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ - AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ - >; - }; - - main_usb0_pins_default: main-usb0-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ - >; - }; - - ospi0_pins_default: ospi0-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ - AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ - AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ - AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ - AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ - AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ - AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ - AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ - AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ - AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ - AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ - >; - }; - - main_ecap0_pins_default: main-ecap0-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ - >; - }; - - main_mcan0_pins_default: main-mcan0-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */ - AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */ - >; - }; - - main_mcan1_pins_default: main-mcan1-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ - AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ - >; - }; - - ddr_vtt_pins_default: ddr-vtt-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ - >; - }; -}; - -&main_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; - current-speed = <115200>; -}; - -/* main_uart1 is reserved for firmware usage */ -&main_uart1 { - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@50 { - /* AT24CM01 */ - compatible = "atmel,24c1024"; - reg = <0x50>; - }; -}; - -&main_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; - - exp1: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL", - "GPIO_CPSW1_RST", "GPIO_RGMII1_RST", - "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT", - "MMC1_SD_EN", "FSI_FET_SEL", - "MCAN0_STB_3V3", "MCAN1_STB_3V3", - "CPSW_FET_SEL", "CPSW_FET2_SEL", - "PRG1_RGMII2_FET_SEL", "TEST_GPIO2", - "GPIO_OLED_RESETn", "VPP_LDO_EN", - "TEST_LED1", "TP92", "TP90", "TP88", - "TP87", "TP86", "TP89", "TP91"; - }; - - /* osd9616p0899-10 */ - display@3c { - compatible = "solomon,ssd1306fb-i2c"; - reg = <0x3c>; - reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>; - vbat-supply = <&vddb>; - solomon,height = <16>; - solomon,width = <96>; - solomon,com-seq; - solomon,com-invdir; - solomon,page-offset = <0>; - solomon,prechargep1 = <2>; - solomon,prechargep2 = <13>; - }; -}; - -/* mcu_gpio0 is reserved for mcu firmware usage */ -&mcu_gpio0 { - status = "reserved"; -}; - -&main_spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_spi0_pins_default>; - ti,pindir-d0-out-d1-in; - eeprom@0 { - compatible = "microchip,93lc46b"; - reg = <0>; - spi-max-frequency = <1000000>; - spi-cs-high; - data-size = <16>; - }; -}; - -&sdhci0 { - /* emmc */ - bus-width = <8>; - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&sdhci1 { - /* SD/MMC */ - vmmc-supply = <&vdd_mmc1>; - pinctrl-names = "default"; - bus-width = <4>; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&usbss0 { - ti,vbus-divider; - ti,usb2-only; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "high-speed"; - pinctrl-names = "default"; - pinctrl-0 = <&main_usb0_pins_default>; -}; - -&cpsw3g { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy0>; -}; - -&cpsw_port2 { - phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy3>; -}; - -&cpsw3g_mdio { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mdio1_pins_default>; - - cpsw3g_phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; -}; - -&tscadc0 { - /* ADC is reserved for R5 usage */ - status = "reserved"; -}; - -&ospi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ospi0_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ospi.tiboot3"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "ospi.tispl"; - reg = <0x100000 0x200000>; - }; - - partition@300000 { - label = "ospi.u-boot"; - reg = <0x300000 0x400000>; - }; - - partition@700000 { - label = "ospi.env"; - reg = <0x700000 0x40000>; - }; - - partition@740000 { - label = "ospi.env.backup"; - reg = <0x740000 0x40000>; - }; - - partition@800000 { - label = "ospi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fc0000 { - label = "ospi.phypattern"; - reg = <0x3fc0000 0x40000>; - }; - }; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status = "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&serdes_ln_ctrl { - idle-states = <AM64_SERDES0_LANE0_PCIE0>; -}; - -&serdes0 { - serdes0_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz0 1>; - }; -}; - -&pcie0_rc { - status = "okay"; - reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&pcie0_ep { - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&ecap0 { - status = "okay"; - /* PWM is available on Pin 1 of header J12 */ - pinctrl-names = "default"; - pinctrl-0 = <&main_ecap0_pins_default>; -}; - -&main_mcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan0_pins_default>; - phys = <&transceiver1>; -}; - -&main_mcan1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan1_pins_default>; - phys = <&transceiver2>; -}; diff --git a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi new file mode 100644 index 00000000000..4677c35e2d9 --- /dev/null +++ b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com + * Author: Matt McKee <mmckee@phytec.com> + * + * Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + * + * Product homepage: + * https://www.phytec.com/product/phycore-am64x + */ + +#include "k3-am642-phycore-som-binman.dtsi" + +/ { + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &main_timer0; + }; + + memory@80000000 { + bootph-all; + }; +}; + +&cbass_main { + bootph-all; +}; + +&dmsc { + bootph-all; +}; + +&dmss { + bootph-all; +}; + +&k3_clks { + bootph-all; +}; + +&k3_pds { + bootph-all; +}; + +&k3_reset { + bootph-all; +}; + +&main_bcdma { + bootph-all; + reg = <0x00 0x485c0100 0x00 0x100>, + <0x00 0x4c000000 0x00 0x20000>, + <0x00 0x4a820000 0x00 0x20000>, + <0x00 0x4aa40000 0x00 0x20000>, + <0x00 0x4bc00000 0x00 0x100000>, + <0x00 0x48600000 0x00 0x8000>, + <0x00 0x484a4000 0x00 0x2000>, + <0x00 0x484c2000 0x00 0x2000>; + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", + "cfg", "tchan", "rchan"; +}; + +&main_conf { + bootph-all; + chipid@14 { + bootph-all; + }; +}; + +&main_gpio0 { + bootph-all; +}; + +&main_mmc1_pins_default { + bootph-all; +}; + +&main_pktdma { + bootph-all; + reg = <0x00 0x485c0000 0x00 0x100>, + <0x00 0x4a800000 0x00 0x20000>, + <0x00 0x4aa00000 0x00 0x40000>, + <0x00 0x4b800000 0x00 0x400000>, + <0x00 0x485e0000 0x00 0x20000>, + <0x00 0x484a0000 0x00 0x4000>, + <0x00 0x484c0000 0x00 0x2000>, + <0x00 0x48430000 0x00 0x4000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg", + "tchan", "rchan", "rflow"; +}; + +&main_pmx0 { + bootph-all; +}; + +&main_timer0 { + bootph-all; + clock-frequency = <200000000>; +}; + +&main_uart0 { + bootph-all; +}; + +&main_uart0_pins_default { + bootph-all; +}; + +&main_usb0_pins_default { + bootph-all; +}; + +&ospi0 { + bootph-all; + flash@0 { + bootph-all; + }; +}; + +&ospi0_pins_default { + bootph-all; +}; + +&sdhci0 { + bootph-all; +}; + +&sdhci1 { + bootph-all; +}; + +&secure_proxy_main { + bootph-all; +}; + +&usbss0 { + bootph-all; +}; + +&usb0 { + bootph-all; +}; diff --git a/arch/arm/dts/k3-am642-phyboard-electra-rdk.dts b/arch/arm/dts/k3-am642-phyboard-electra-rdk.dts new file mode 100644 index 00000000000..53b64e55413 --- /dev/null +++ b/arch/arm/dts/k3-am642-phyboard-electra-rdk.dts @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com + * Author: Matt McKee <mmckee@phytec.com> + * + * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + * + * Product homepage: + * https://www.phytec.com/product/phyboard-am64x + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/leds/leds-pca9532.h> +#include <dt-bindings/phy/phy.h> +#include "k3-am642.dtsi" +#include "k3-am64-phycore-som.dtsi" + +#include "k3-serdes.h" + +/ { + compatible = "phytec,am642-phyboard-electra-rdk", + "phytec,am64-phycore-som", "ti,am642"; + model = "PHYTEC phyBOARD-Electra-AM64x RDK"; + + aliases { + mmc1 = &sdhci1; + serial2 = &main_uart0; + serial3 = &main_uart1; + }; + + chosen { + stdout-path = &main_uart0; + }; + + can_tc1: can-phy0 { + compatible = "ti,tcan1042"; + pinctrl-names = "default"; + pinctrl-0 = <&can_tc1_pins_default>; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>; + }; + + can_tc2: can-phy1 { + compatible = "ti,tcan1042"; + pinctrl-names = "default"; + pinctrl-0 = <&can_tc2_pins_default>; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&main_gpio0 35 GPIO_ACTIVE_HIGH>; + }; + + keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins_default>; + + key-home { + label = "home"; + linux,code = <KEY_HOME>; + gpios = <&main_gpio0 17 GPIO_ACTIVE_HIGH>; + }; + + key-menu { + label = "menu"; + linux,code = <KEY_MENU>; + gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>; + + led-1 { + color = <LED_COLOR_ID_RED>; + gpios = <&main_gpio0 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + function = LED_FUNCTION_DISK; + }; + + led-2 { + color = <LED_COLOR_ID_GREEN>; + gpios = <&main_gpio0 16 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + function = LED_FUNCTION_DISK; + }; + }; + + vcc_3v3_mmc: regulator-sd { + /* TPS22963C */ + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_MMC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&main_pmx0 { + can_tc1_pins_default: can-tc1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (P16) GPMC0_ADVn_ALE.GPIO0_32 */ + >; + }; + + can_tc2_pins_default: can-tc2-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0090, PIN_OUTPUT, 7) /* (P17) GPMC0_BE0n_CLE.GPIO0_35 */ + >; + }; + + gpio_keys_pins_default: gpio-keys-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0044, PIN_INPUT, 7) /* (T18) GPMC0_AD2.GPIO0_17 */ + AM64X_IOPAD(0x0054, PIN_INPUT, 7) /* (V20) GPMC0_AD6.GPIO0_21 */ + >; + }; + + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0268, PIN_INPUT, 0) /* (C18) I2C1_SCL */ + AM64X_IOPAD(0x026c, PIN_INPUT, 0) /* (B19) I2C1_SDA */ + >; + }; + + main_mcan0_pins_default: main-mcan0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */ + AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */ + >; + }; + + main_mcan1_pins_default: main-mcan1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ + AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ + >; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ + AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ + AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ + AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ + AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ + AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */ + AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ + AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ + >; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ + AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ + >; + }; + + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ + AM64X_IOPAD(0x024C, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ + AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ + AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ + >; + }; + + main_usb0_pins_default: main-usb0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ + >; + }; + + pcie_usb_sel_pins_default: pcie-usb-sel-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x017c, PIN_OUTPUT, 7) /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */ + >; + }; + + pcie0_pins_default: pcie0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (W19) GPMC0_WAIT0.GPIO0_37 */ + >; + }; + + user_leds_pins_default: user-leds-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x003c, PIN_OUTPUT, 7) /* (T20) GPMC0_AD0.GPIO0_15 */ + AM64X_IOPAD(0x0040, PIN_OUTPUT, 7) /* (U21) GPMC0_AD1.GPIO0_16 */ + >; + }; +}; + +&main_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + + eeprom@51 { + compatible = "atmel,24c02"; + pagesize = <16>; + reg = <0x51>; + }; + + led-controller@62 { + compatible = "nxp,pca9533"; + reg = <0x62>; + + led-3 { + label = "red:user"; + type = <PCA9532_TYPE_LED>; + }; + + led-4 { + label = "green:user"; + type = <PCA9532_TYPE_LED>; + }; + + led-5 { + label = "blue:user"; + type = <PCA9532_TYPE_LED>; + }; + }; +}; + +&main_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&can_tc1>; +}; + +&main_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan1_pins_default>; + phys = <&can_tc2>; +}; + +&main_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + current-speed = <115200>; +}; + +&main_uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + uart-has-rtscts; + current-speed = <115200>; +}; + +&sdhci1 { + status = "okay"; + vmmc-supply = <&vcc_3v3_mmc>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + bus-width = <4>; + ti,driver-strength-ohm = <50>; + disable-wp; + no-1-8-v; +}; + +&serdes0 { + serdes0_pcie_usb_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_USB3>; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes_ln_ctrl { + idle-states = <AM64_SERDES0_LANE0_USB>; +}; + +&usbss0 { + ti,vbus-divider; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usb0_pins_default>; + dr_mode = "host"; + maximum-speed = "super-speed"; + phys = <&serdes0_pcie_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; diff --git a/arch/arm/dts/k3-am642-phycore-som-binman.dtsi b/arch/arm/dts/k3-am642-phycore-som-binman.dtsi new file mode 100644 index 00000000000..79783aadbe2 --- /dev/null +++ b/arch/arm/dts/k3-am642-phycore-som-binman.dtsi @@ -0,0 +1,457 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Based on k3-am64x-binman.dtsi + * + * Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + */ + +#include "k3-binman.dtsi" + +#ifdef CONFIG_TARGET_PHYCORE_AM64X_R5 +&binman { + tiboot3-am64x_sr2-hs-phycore-som.bin { + filename = "tiboot3-am64x_sr2-hs-phycore-som.bin"; + ti-secure-rom { + content = <&u_boot_spl>, <&ti_sci_enc>, + <&combined_sysfw_cfg>, <&sysfw_inner_cert>; + combined; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl>; + content-sysfw = <&ti_sci_enc>; + content-sysfw-data = <&combined_sysfw_cfg>; + content-sysfw-inner-cert = <&sysfw_inner_cert>; + load = <0x70000000>; + load-sysfw = <0x44000>; + load-sysfw-data = <0x7b000>; + }; + u_boot_spl: u-boot-spl { + no-expanded; + }; + ti_sci_enc: ti-fs-enc.bin { + filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_sysfw_cfg: combined-sysfw-cfg.bin { + filename = "combined-sysfw-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert: sysfw-inner-cert { + filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + + }; +}; + +&binman { + tiboot3-am64x_sr2-hs-fs-phycore-som.bin { + filename = "tiboot3-am64x_sr2-hs-fs-phycore-som.bin"; + symlink = "tiboot3.bin"; + ti-secure-rom { + content = <&u_boot_spl_fs>, <&ti_sci_enc_fs>, + <&combined_sysfw_cfg_fs>, <&sysfw_inner_cert_fs>; + combined; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_fs>; + content-sysfw = <&ti_sci_enc_fs>; + content-sysfw-data = <&combined_sysfw_cfg_fs>; + content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; + load = <0x70000000>; + load-sysfw = <0x44000>; + load-sysfw-data = <0x7b000>; + }; + u_boot_spl_fs: u-boot-spl { + no-expanded; + }; + ti_sci_enc_fs: ti-fs-enc.bin { + filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_sysfw_cfg_fs: combined-sysfw-cfg.bin { + filename = "combined-sysfw-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert_fs: sysfw-inner-cert { + filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + + }; +}; + +&binman { + tiboot3-am64x-gp-phycore-som.bin { + filename = "tiboot3-am64x-gp-phycore-som.bin"; + ti-secure-rom { + content = <&u_boot_spl_unsigned>, <&ti_sci_gp>, <&combined_sysfw_cfg_gp>; + combined; + content-sbl = <&u_boot_spl_unsigned>; + load = <0x70000000>; + content-sysfw = <&ti_sci_gp>; + load-sysfw = <0x44000>; + content-sysfw-data = <&combined_sysfw_cfg_gp>; + load-sysfw-data = <0x7b000>; + sw-rev = <1>; + keyfile = "ti-degenerate-key.pem"; + }; + u_boot_spl_unsigned: u-boot-spl { + no-expanded; + }; + ti_sci_gp: ti-sci-gp.bin { + filename = "ti-sysfw/ti-sci-firmware-am64x-gp.bin"; + type = "blob-ext"; + optional; + }; + combined_sysfw_cfg_gp: combined-sysfw-cfg-gp.bin { + filename = "combined-sysfw-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +#endif + +#ifdef CONFIG_TARGET_PHYCORE_AM64X_A53 +#define SPL_AM642_PHYBOARD_ELECTRA_DTB "spl/dts/k3-am642-phyboard-electra-rdk.dtb" +#define AM642_PHYBOARD_ELECTRA_DTB "u-boot.dtb" + +&binman { + ti-spl { + insert-template = <&ti_spl_template>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + dm { + blob-ext { + filename = "/dev/null"; + }; + }; + + fdt-0 { + description = "k3-am642-phyboard-electra-rdk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_am642_phyboard_electra_dtb>; + keyfile = "custMpk.pem"; + }; + spl_am642_phyboard_electra_dtb: blob-ext { + filename = SPL_AM642_PHYBOARD_ELECTRA_DTB; + }; + + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am642-phyboard-electra-rdk"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot { + insert-template = <&u_boot_template>; + + fit { + images { + uboot { + description = "U-Boot for AM64 board"; + }; + + fdt-0 { + description = "k3-am642-phyboard-electra-rdk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&am642_phyboard_electra_dtb>; + keyfile = "custMpk.pem"; + }; + am642_phyboard_electra_dtb: blob-ext { + filename = AM642_PHYBOARD_ELECTRA_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am642-phyboard-electra-rdk"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + ti-spl_unsigned { + insert-template = <&ti_spl_unsigned_template>; + + fit { + images { + dm { + blob-ext { + filename = "/dev/null"; + }; + }; + + fdt-0 { + description = "k3-am642-phyboard-electra-rdk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = SPL_AM642_PHYBOARD_ELECTRA_DTB; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am642-phyboard-electra-rdk"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot_unsigned { + insert-template = <&u_boot_unsigned_template>; + + fit { + images { + uboot { + description = "U-Boot for AM64 board"; + }; + + fdt-0 { + description = "k3-am642-phyboard-electra-rdk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = AM642_PHYBOARD_ELECTRA_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am642-phyboard-electra-rdk"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; +#endif + +#ifdef CONFIG_TARGET_PHYCORE_AM64X_A53 + +#define SPL_AM642_PHYBOARD_ELECTRA_DTB "spl/dts/k3-am642-phyboard-electra-rdk.dtb" + +#define AM642_PHYBOARD_ELECTRA_DTB "u-boot.dtb" + +&binman { + ti-spl { + insert-template = <&ti_spl_template>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + dm { + blob-ext { + filename = "/dev/null"; + }; + }; + + fdt-0 { + description = "k3-am642-phyboard-electra-rdk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_am642_phyboard_electra_dtb>; + keyfile = "custMpk.pem"; + }; + spl_am642_phyboard_electra_dtb: blob-ext { + filename = SPL_AM642_PHYBOARD_ELECTRA_DTB; + }; + + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am642-phyboard-electra-rdk"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot { + insert-template = <&u_boot_template>; + + fit { + images { + uboot { + description = "U-Boot for AM64 board"; + }; + + fdt-0 { + description = "k3-am642-phyboard-electra-rdk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&am642_phyboard_electra_dtb>; + keyfile = "custMpk.pem"; + }; + am642_phyboard_electra_dtb: blob-ext { + filename = AM642_PHYBOARD_ELECTRA_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am642-phyboard-electra-rdk"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + ti-spl_unsigned { + insert-template = <&ti_spl_unsigned_template>; + + fit { + images { + dm { + blob-ext { + filename = "/dev/null"; + }; + }; + + fdt-0 { + description = "k3-am642-phyboard-electra-rdk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = SPL_AM642_PHYBOARD_ELECTRA_DTB; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am642-phyboard-electra-rdk"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot_unsigned { + insert-template = <&u_boot_unsigned_template>; + + fit { + images { + uboot { + description = "U-Boot for AM64 board"; + }; + + fdt-0 { + description = "k3-am642-phyboard-electra-rdk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = AM642_PHYBOARD_ELECTRA_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am642-phyboard-electra-rdk"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; +#endif /* CONFIG_TARGET_PHYCORE_AM64X_A53 */ diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts index 64b3c3af630..be8596987ba 100644 --- a/arch/arm/dts/k3-am642-r5-evm.dts +++ b/arch/arm/dts/k3-am642-r5-evm.dts @@ -40,10 +40,6 @@ }; }; -&vtt_supply { - bootph-pre-ram; -}; - &cbass_main { sysctrler: sysctrler { compatible = "ti,am654-system-controller"; @@ -53,18 +49,6 @@ }; }; -&main_esm { - bootph-pre-ram; -}; - -&cbass_mcu { - bootph-pre-ram; -}; - -&mcu_esm { - bootph-pre-ram; -}; - &dmsc { mboxes= <&secure_proxy_main 0>, <&secure_proxy_main 1>, @@ -74,10 +58,6 @@ ti,secure-host; }; -&vtt_supply { - bootph-pre-ram; -}; - &memorycontroller { vtt-supply = <&vtt_supply>; }; @@ -92,10 +72,6 @@ clock-names = "clk_xin"; }; -&main_gpio0 { - bootph-pre-ram; -}; - /* UART is initialized before SYSFW is started * so we can't do any power-domain/clock operations. * Delete clock/power-domain properties to avoid @@ -120,3 +96,8 @@ /delete-property/ assigned-clock-parents; /delete-property/ power-domains; }; + +&ospi0 { + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x00 0x60000000 0x00 0x8000000>; +}; diff --git a/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts new file mode 100644 index 00000000000..40c25d5dbb6 --- /dev/null +++ b/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com + * Author: Matt McKee <mmckee@phytec.com> + * + * Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + */ + +/dts-v1/; + +#include "k3-am642-phyboard-electra-rdk.dts" +#include "k3-am64-phycore-som-ddr4-2gb.dtsi" +#include "k3-am64-ddr.dtsi" + +#include "k3-am642-phyboard-electra-rdk-u-boot.dtsi" + +/ { + aliases { + ethernet0 = &cpsw3g; + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + clocks = <&k3_clks 61 0>; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <1000000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-pre-ram; + }; + + clk_200mhz: dummy-clock-200mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + bootph-pre-ram; + }; + + vtt_supply: vtt-supply { + compatible = "regulator-fixed"; + regulator-name = "vtt"; + pinctrl-names = "default"; + pinctrl-0 = <&ddr_vtt_pins_default>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&main_gpio0 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + bootph-pre-ram; + }; +}; + +&cbass_main { + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>; + mbox-names = "tx", "rx"; + bootph-pre-ram; + }; +}; + +&cbass_mcu { + bootph-pre-ram; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; + +&main_esm { + bootph-pre-ram; +}; + +&main_gpio0 { + bootph-pre-ram; +}; + +&main_pmx0 { + bootph-pre-ram; + ddr_vtt_pins_default: ddr-vtt-default-pins { + bootph-pre-ram; + pinctrl-single,pins = < + AM64X_IOPAD(0x0038, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN3.GPIO0_14 */ + >; + }; +}; + +/* timer init is called as part of rproc_start() while + * starting System Firmware, so any clock/power-domain + * operations will fail as SYSFW is not yet up and running. + * Delete all clock/power-domain properties to avoid + * timer init failure. + * This is an always on timer at 20MHz. + */ +&main_timer0 { + /delete-property/ clocks; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ power-domains; +}; + +/* UART is initialized before SYSFW is started + * so we can't do any power-domain/clock operations. + * Delete clock/power-domain properties to avoid + * UART init failure + */ +&main_uart0 { + /delete-property/ power-domains; + /delete-property/ clocks; + /delete-property/ clock-names; +}; + +&mcu_esm { + bootph-pre-ram; +}; + +&memorycontroller { + vtt-supply = <&vtt_supply>; +}; + +&ospi0 { + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x00 0x60000000 0x00 0x08000000>; +}; diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts index daa483a7811..2186152a0b8 100644 --- a/arch/arm/dts/k3-am642-r5-sk.dts +++ b/arch/arm/dts/k3-am642-r5-sk.dts @@ -49,18 +49,6 @@ }; }; -&main_esm { - bootph-pre-ram; -}; - -&cbass_mcu { - bootph-pre-ram; -}; - -&mcu_esm { - bootph-pre-ram; -}; - &dmsc { mboxes= <&secure_proxy_main 0>, <&secure_proxy_main 1>, @@ -103,3 +91,8 @@ /delete-property/ assigned-clock-parents; /delete-property/ power-domains; }; + +&ospi0 { + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x00 0x60000000 0x00 0x8000000>; +}; diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi index 2eb227c1d00..6fcb11bd04d 100644 --- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi @@ -9,87 +9,14 @@ chosen { tick-timer = &main_timer0; }; - - memory@80000000 { - bootph-all; - }; -}; - -&cbass_main{ - bootph-all; }; &main_timer0 { - bootph-all; clock-frequency = <200000000>; }; -&main_conf { - bootph-all; - chipid@14 { - bootph-all; - }; -}; - -&main_pmx0 { - bootph-all; -}; - -&main_i2c0_pins_default { - bootph-all; -}; - -&main_i2c0 { - bootph-all; -}; - -&main_uart0_pins_default { - bootph-all; -}; - -&main_uart0 { - bootph-all; -}; - -&dmss { - bootph-all; -}; - -&secure_proxy_main { - bootph-all; -}; - -&dmsc { - bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; -}; - -&k3_pds { - bootph-all; -}; - -&k3_clks { - bootph-all; -}; - -&k3_reset { - bootph-all; -}; - &sdhci0 { status = "disabled"; - bootph-all; -}; - -&sdhci1 { - bootph-all; -}; - -&main_mmc1_pins_default { - bootph-all; }; &inta_main_dmss { @@ -180,34 +107,22 @@ bootph-all; }; -&main_usb0_pins_default { - bootph-all; -}; - &serdes_ln_ctrl { - u-boot,mux-autoprobe; -}; - -&usbss0 { bootph-all; }; -&usb0 { +&ospi0_pins_default { bootph-all; }; -&serdes_wiz0 { +&fss { bootph-all; }; -&serdes0_usb_link { - bootph-all; -}; - -&serdes0 { - bootph-all; -}; +&ospi0 { + bootph-all; -&serdes_refclk { - bootph-all; + flash@0 { + bootph-all; + }; }; diff --git a/arch/arm/dts/k3-am642-sk.dts b/arch/arm/dts/k3-am642-sk.dts deleted file mode 100644 index 722fd285a34..00000000000 --- a/arch/arm/dts/k3-am642-sk.dts +++ /dev/null @@ -1,642 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include <dt-bindings/phy/phy.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/net/ti-dp83867.h> -#include <dt-bindings/leds/common.h> -#include "k3-am642.dtsi" - -#include "k3-serdes.h" - -/ { - compatible = "ti,am642-sk", "ti,am642"; - model = "Texas Instruments AM642 SK"; - - chosen { - stdout-path = &main_uart0; - }; - - aliases { - serial0 = &mcu_uart0; - serial1 = &main_uart1; - serial2 = &main_uart0; - i2c0 = &main_i2c0; - i2c1 = &main_i2c1; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - ethernet0 = &cpsw_port1; - ethernet1 = &cpsw_port2; - }; - - memory@80000000 { - device_type = "memory"; - /* 2G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ - alignment = <0x1000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a5000000 { - reg = <0x00 0xa5000000 0x00 0x00800000>; - alignment = <0x1000>; - no-map; - }; - }; - - vusb_main: regulator-0 { - /* USB MAIN INPUT 5V DC */ - compatible = "regulator-fixed"; - regulator-name = "vusb_main5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_3v3_sys: regulator-1 { - /* output of LP8733xx */ - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sys"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vusb_main>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: regulator-2 { - /* TPS2051BD */ - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vcc_3v3_sys>; - gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; - }; - - com8_ls_en: regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "com8_ls_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - pinctrl-0 = <&main_com8_ls_en_pins_default>; - pinctrl-names = "default"; - gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>; - }; - - wlan_en: regulator-4 { - /* output of SN74AVC4T245RSVR */ - compatible = "regulator-fixed"; - regulator-name = "wlan_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - pinctrl-0 = <&main_wlan_en_pins_default>; - pinctrl-names = "default"; - vin-supply = <&com8_ls_en>; - gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>; - }; - - led-controller { - compatible = "gpio-leds"; - - led-0 { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - gpios = <&exp2 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-1 { - color = <LED_COLOR_ID_RED>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <2>; - gpios = <&exp2 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-2 { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <3>; - gpios = <&exp2 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-3 { - color = <LED_COLOR_ID_AMBER>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <4>; - gpios = <&exp2 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-4 { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <5>; - gpios = <&exp2 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-5 { - color = <LED_COLOR_ID_RED>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <6>; - gpios = <&exp2 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-6 { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <7>; - gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-7 { - color = <LED_COLOR_ID_AMBER>; - function = LED_FUNCTION_HEARTBEAT; - function-enumerator = <8>; - linux,default-trigger = "heartbeat"; - gpios = <&exp2 7 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&main_pmx0 { - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */ - AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ - AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ - AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */ - AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ - AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ - AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ - AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ - AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ - >; - }; - - main_uart0_pins_default: main-uart0-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ - AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ - AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ - AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ - >; - }; - - main_uart1_pins_default: main-uart1-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ - AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ - AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ - AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ - >; - }; - - main_usb0_pins_default: main-usb0-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ - AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ - AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ - >; - }; - - mdio1_pins_default: mdio1-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ - AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ - >; - }; - - rgmii1_pins_default: rgmii1-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */ - AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */ - AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */ - AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */ - AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */ - AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */ - AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ - AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ - AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ - AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ - AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ - AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ - >; - }; - - rgmii2_pins_default: rgmii2-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ - AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ - AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ - AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ - AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ - AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ - AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ - AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ - AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ - AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ - AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ - AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ - >; - }; - - ospi0_pins_default: ospi0-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ - AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ - AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ - AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ - AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ - AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ - AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ - AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ - AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ - AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ - AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ - >; - }; - - main_ecap0_pins_default: main-ecap0-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ - >; - }; - main_wlan_en_pins_default: main-wlan-en-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */ - >; - }; - - main_com8_ls_en_pins_default: main-com8-ls-en-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */ - >; - }; - - main_wlan_pins_default: main-wlan-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ - >; - }; -}; - -&main_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; - current-speed = <115200>; -}; - -&main_uart1 { - /* main_uart1 is reserved for firmware usage */ - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@51 { - compatible = "atmel,24c512"; - reg = <0x51>; - }; -}; - -&main_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; - - exp1: gpio@70 { - compatible = "nxp,pca9538"; - reg = <0x70>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", - "PRU_DETECT", "MMC1_SD_EN", - "VPP_LDO_EN", "RPI_PS_3V3_En", - "RPI_PS_5V0_En", "RPI_HAT_DETECT"; - }; - - exp2: gpio@60 { - compatible = "ti,tpic2810"; - reg = <0x60>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8"; - }; -}; - -/* mcu_gpio0 is reserved for mcu firmware usage */ -&mcu_gpio0 { - status = "reserved"; -}; - -&sdhci0 { - vmmc-supply = <&wlan_en>; - bus-width = <4>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - ti,driver-strength-ohm = <50>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - pinctrl-0 = <&main_wlan_pins_default>; - pinctrl-names = "default"; - interrupt-parent = <&main_gpio0>; - interrupts = <46 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&sdhci1 { - /* SD/MMC */ - vmmc-supply = <&vdd_mmc1>; - pinctrl-names = "default"; - bus-width = <4>; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&serdes_ln_ctrl { - idle-states = <AM64_SERDES0_LANE0_USB>; -}; - -&serdes0 { - serdes0_usb_link: phy@0 { - reg = <0>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_USB3>; - resets = <&serdes_wiz0 1>; - }; -}; - -&usbss0 { - ti,vbus-divider; -}; - -&usb0 { - dr_mode = "host"; - maximum-speed = "super-speed"; - pinctrl-names = "default"; - pinctrl-0 = <&main_usb0_pins_default>; - phys = <&serdes0_usb_link>; - phy-names = "cdns3,usb3-phy"; -}; - -&cpsw3g { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy0>; -}; - -&cpsw_port2 { - phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy1>; -}; - -&cpsw3g_mdio { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mdio1_pins_default>; - - cpsw3g_phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; - - cpsw3g_phy1: ethernet-phy@1 { - reg = <1>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; -}; - -&ospi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ospi0_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ospi.tiboot3"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "ospi.tispl"; - reg = <0x100000 0x200000>; - }; - - partition@300000 { - label = "ospi.u-boot"; - reg = <0x300000 0x400000>; - }; - - partition@700000 { - label = "ospi.env"; - reg = <0x700000 0x40000>; - }; - - partition@740000 { - label = "ospi.env.backup"; - reg = <0x740000 0x40000>; - }; - - partition@800000 { - label = "ospi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fc0000 { - label = "ospi.phypattern"; - reg = <0x3fc0000 0x40000>; - }; - }; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status = "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&ecap0 { - status = "okay"; - /* PWM is available on Pin 1 of header J3 */ - pinctrl-names = "default"; - pinctrl-0 = <&main_ecap0_pins_default>; -}; diff --git a/arch/arm/dts/k3-am642.dtsi b/arch/arm/dts/k3-am642.dtsi deleted file mode 100644 index 7a6eedea3aa..00000000000 --- a/arch/arm/dts/k3-am642.dtsi +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM642 SoC family in Dual core configuration - * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-am64.dtsi" - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_0>; - }; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - cache-size = <0x40000>; - cache-line-size = <64>; - cache-sets = <256>; - }; -}; diff --git a/arch/arm/dts/k3-am64x-binman.dtsi b/arch/arm/dts/k3-am64x-binman.dtsi index 88df2149545..37817ba60d2 100644 --- a/arch/arm/dts/k3-am64x-binman.dtsi +++ b/arch/arm/dts/k3-am64x-binman.dtsi @@ -118,11 +118,11 @@ #ifdef CONFIG_TARGET_AM642_A53_EVM -#define SPL_AM642_EVM_DTB "spl/dts/k3-am642-evm.dtb" -#define SPL_AM642_SK_DTB "spl/dts/k3-am642-sk.dtb" +#define SPL_AM642_EVM_DTB "spl/dts/ti/k3-am642-evm.dtb" +#define SPL_AM642_SK_DTB "spl/dts/ti/k3-am642-sk.dtb" #define AM642_EVM_DTB "u-boot.dtb" -#define AM642_SK_DTB "arch/arm/dts/k3-am642-sk.dtb" +#define AM642_SK_DTB "dts/upstream/src/arm64/ti/k3-am642-sk.dtb" &binman { ti-spl { diff --git a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi index 64318d09cf0..3a6db91e132 100644 --- a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi @@ -51,8 +51,8 @@ arch = "arm64"; compression = "none"; os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; + load = <CONFIG_K3_OPTEE_LOAD_ADDR>; + entry = <CONFIG_K3_OPTEE_LOAD_ADDR>; tee-os { }; }; diff --git a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi index d53f133cd63..b6d2c816acc 100644 --- a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi @@ -99,10 +99,6 @@ &dmsc { bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; }; &k3_pds { diff --git a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi index 4f34347586e..b8fc62f0dd1 100644 --- a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi @@ -51,10 +51,6 @@ &sms { bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; }; &main_pmx0 { diff --git a/arch/arm/dts/k3-am69-r5-sk.dts b/arch/arm/dts/k3-am69-r5-sk.dts new file mode 100644 index 00000000000..f177f563527 --- /dev/null +++ b/arch/arm/dts/k3-am69-r5-sk.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am69-sk.dts" +#include "k3-j784s4-ddr-evm-lp4-4266.dtsi" +#include "k3-j784s4-ddr.dtsi" +#include "k3-am69-sk-u-boot.dtsi" + +/ { + chosen { + tick-timer = &mcu_timer0; + }; + + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a72_0; + }; + + a72_0: a72@0 { + compatible = "ti,am654-rproc"; + reg = <0x0 0x00a90000 0x0 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 202 0>; + clocks = <&k3_clks 61 0>; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 202 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <2000000000>; + ti,sci = <&sms>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-pre-ram; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_mcu 21>, <&secure_proxy_mcu 23>; + bootph-pre-ram; + }; +}; + +&mcu_timer0 { + status = "okay"; + clock-frequency = <250000000>; + bootph-pre-ram; +}; + +&secure_proxy_sa3 { + status = "okay"; + bootph-pre-ram; +}; + +&secure_proxy_mcu { + status = "okay"; + bootph-pre-ram; +}; + +&cbass_mcu_wakeup { + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_mcu 4>, + <&secure_proxy_mcu 5>, + <&secure_proxy_sa3 5>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-pre-ram; + }; +}; + +&sms { + mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; + mbox-names = "tx", "rx", "notify"; + ti,host-id = <4>; + ti,secure-host; + bootph-pre-ram; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + bootph-pre-ram; + status = "okay"; +}; + +&ospi0 { + reg = <0x0 0x47040000 0x0 0x100>, + <0x0 0x50000000 0x0 0x8000000>; +}; + +&ospi1 { + reg = <0x0 0x47050000 0x0 0x100>, + <0x0 0x58000000 0x0 0x8000000>; +}; + +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; diff --git a/arch/arm/dts/k3-am69-sk-u-boot.dtsi b/arch/arm/dts/k3-am69-sk-u-boot.dtsi new file mode 100644 index 00000000000..4a82d2fd222 --- /dev/null +++ b/arch/arm/dts/k3-am69-sk-u-boot.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-j784s4-binman.dtsi" + +/ { + memory@80000000 { + bootph-all; + }; +}; + +&mcu_udmap { + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x284c0000 0x0 0x4000>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x284a0000 0x0 0x4000>, + <0x0 0x2aa00000 0x0 0x40000>, + <0x0 0x28400000 0x0 0x2000>; + reg-names = "gcfg", "rchan", "rchanrt", "tchan", + "tchanrt", "rflow"; + bootph-pre-ram; +}; + +#ifdef CONFIG_TARGET_J784S4_A72_EVM + +#define SPL_AM69_SK_DTB "spl/dts/ti/k3-am69-sk.dtb" +#define AM69_SK_DTB "u-boot.dtb" + +&spl_j784s4_evm_dtb { + filename = SPL_AM69_SK_DTB; +}; + +&j784s4_evm_dtb { + filename = AM69_SK_DTB; +}; + +&spl_j784s4_evm_dtb_unsigned { + filename = SPL_AM69_SK_DTB; +}; + +&j784s4_evm_dtb_unsigned { + filename = AM69_SK_DTB; +}; + +#endif diff --git a/arch/arm/dts/k3-binman.dtsi b/arch/arm/dts/k3-binman.dtsi index 758c8bf6ea1..5163161b94d 100644 --- a/arch/arm/dts/k3-binman.dtsi +++ b/arch/arm/dts/k3-binman.dtsi @@ -286,13 +286,14 @@ arch = "arm64"; compression = "none"; os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; + load = <CONFIG_K3_OPTEE_LOAD_ADDR>; + entry = <CONFIG_K3_OPTEE_LOAD_ADDR>; ti-secure { content = <&tee>; keyfile = "custMpk.pem"; }; tee: tee-os { + optional; }; }; @@ -356,10 +357,11 @@ arch = "arm64"; compression = "none"; os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; + load = <CONFIG_K3_OPTEE_LOAD_ADDR>; + entry = <CONFIG_K3_OPTEE_LOAD_ADDR>; tee-os { filename = "tee-raw.bin"; + optional; }; }; diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 60ca6d21abb..485f17c5f06 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -57,10 +57,6 @@ &dmsc { bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; }; &k3_pds { @@ -195,6 +191,10 @@ &ospi0 { bootph-all; + + flash@0 { + bootph-all; + }; }; &serdes_ln_ctrl { diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index 018faaa13b6..fb7e2e50239 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -52,7 +52,7 @@ }; &mcu_timer0 { - clock-frequency = <25000000>; + clock-frequency = <250000000>; bootph-pre-ram; }; @@ -83,3 +83,16 @@ &wkup_vtm0 { bootph-pre-ram; }; + +&ospi0 { + reg = <0x0 0x47040000 0x0 0x100>, + <0x0 0x50000000 0x0 0x8000000>; +}; + +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; diff --git a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi index 017a5a722e0..e202ae16644 100644 --- a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi @@ -92,10 +92,6 @@ &dmsc { bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; }; &k3_pds { @@ -165,7 +161,6 @@ &serdes_ln_ctrl { bootph-all; - u-boot,mux-autoprobe; }; &serdes2_usb_link { @@ -174,7 +169,6 @@ &usb_serdes_mux { bootph-all; - u-boot,mux-autoprobe; }; &serdes_wiz2 { @@ -250,8 +244,8 @@ arch = "arm64"; compression = "none"; os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; + load = <CONFIG_K3_OPTEE_LOAD_ADDR>; + entry = <CONFIG_K3_OPTEE_LOAD_ADDR>; tee-os { filename = "tee-raw.bin"; }; diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 7ae7cf3d4c9..aa919b40702 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -47,10 +47,6 @@ &dmsc { bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; }; &k3_pds { @@ -94,11 +90,11 @@ }; &serdes_ln_ctrl { - u-boot,mux-autoprobe; + bootph-all; }; &usb_serdes_mux { - u-boot,mux-autoprobe; + bootph-all; }; &main_usbss0_pins_default { diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi index 479b7bcd6f8..8f4f944263e 100644 --- a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi @@ -47,10 +47,6 @@ &dmsc { bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; }; &k3_pds { @@ -90,11 +86,11 @@ }; &serdes_ln_ctrl { - u-boot,mux-autoprobe; + bootph-all; }; &usb_serdes_mux { - u-boot,mux-autoprobe; + bootph-all; }; &main_usbss0_pins_default { @@ -157,9 +153,5 @@ flash@0 { bootph-all; - - partition@3fc0000 { - bootph-all; - }; }; }; diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi index a3ebf5996ea..19b2d48c7f8 100644 --- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi @@ -51,10 +51,6 @@ &sms { bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; }; &main_pmx0 { diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi new file mode 100644 index 00000000000..e4dd6e14a66 --- /dev/null +++ b/arch/arm/dts/k3-j784s4-binman.dtsi @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-binman.dtsi" + +#ifdef CONFIG_TARGET_J784S4_R5_EVM + +&rcfg_yaml_tifs { + config = "tifs-rm-cfg.yaml"; +}; + +&binman { + tiboot3-j784s4-hs-evm.bin { + filename = "tiboot3-j784s4-hs-evm.bin"; + + ti-secure-rom { + content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>, + <&combined_dm_cfg>, <&sysfw_inner_cert>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl>; + content-sysfw = <&ti_fs_enc>; + content-sysfw-data = <&combined_tifs_cfg>; + content-sysfw-inner-cert = <&sysfw_inner_cert>; + content-dm-data = <&combined_dm_cfg>; + load = <0x41c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x66800>; + load-dm-data = <0x41c80000>; + }; + + u_boot_spl: u-boot-spl { + no-expanded; + }; + + ti_fs_enc: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + + combined_tifs_cfg: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + + sysfw_inner_cert: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + + combined_dm_cfg: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +&binman { + tiboot3-j784s4-hs-fs-evm.bin { + filename = "tiboot3-j784s4-hs-fs-evm.bin"; + + ti-secure-rom { + content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>, + <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_fs>; + content-sysfw = <&ti_fs_enc_fs>; + content-sysfw-data = <&combined_tifs_cfg_fs>; + content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; + content-dm-data = <&combined_dm_cfg_fs>; + load = <0x41c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x66800>; + load-dm-data = <0x41c80000>; + }; + + u_boot_spl_fs: u-boot-spl { + no-expanded; + }; + + ti_fs_enc_fs: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + + combined_tifs_cfg_fs: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + + sysfw_inner_cert_fs: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + + combined_dm_cfg_fs: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +&binman { + tiboot3-j784s4-gp-evm.bin { + filename = "tiboot3-j784s4-gp-evm.bin"; + symlink = "tiboot3.bin"; + + ti-secure-rom { + content = <&u_boot_spl_unsigned>, <&ti_fs_gp>, + <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; + combined; + dm-data; + content-sbl = <&u_boot_spl_unsigned>; + load = <0x41c00000>; + content-sysfw = <&ti_fs_gp>; + load-sysfw = <0x40000>; + content-sysfw-data = <&combined_tifs_cfg_gp>; + load-sysfw-data = < 0x66800>; + content-dm-data = <&combined_dm_cfg_gp>; + load-dm-data = <0x41c80000>; + sw-rev = <1>; + keyfile = "ti-degenerate-key.pem"; + }; + + u_boot_spl_unsigned: u-boot-spl { + no-expanded; + }; + + ti_fs_gp: ti-fs-gp.bin { + filename = "ti-sysfw/ti-fs-firmware-j784s4-gp.bin"; + type = "blob-ext"; + optional; + }; + + combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + + combined_dm_cfg_gp: combined-dm-cfg-gp.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + + }; +}; +#endif + +#ifdef CONFIG_TARGET_J784S4_A72_EVM + +#define SPL_J784S4_EVM_DTB "spl/dts/ti/k3-j784s4-evm.dtb" +#define J784S4_EVM_DTB "u-boot.dtb" + +&binman { + ti-dm { + filename = "ti-dm.bin"; + + blob-ext { + filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + + ti-spl { + insert-template = <&ti_spl_template>; + + fit { + images { + dm { + ti-secure { + content = <&dm>; + keyfile = "custMpk.pem"; + }; + + dm: blob-ext { + filename = "ti-dm.bin"; + }; + }; + + fdt-0 { + description = "k3-j784s4-evm"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + ti-secure { + content = <&spl_j784s4_evm_dtb>; + keyfile = "custMpk.pem"; + }; + + spl_j784s4_evm_dtb: blob-ext { + filename = SPL_J784S4_EVM_DTB; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j784s4-evm"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot { + insert-template = <&u_boot_template>; + + fit { + images { + uboot { + description = "U-Boot for J784S4 board"; + }; + + fdt-0 { + description = "k3-j784s4-evm"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + ti-secure { + content = <&j784s4_evm_dtb>; + keyfile = "custMpk.pem"; + }; + + j784s4_evm_dtb: blob-ext { + filename = J784S4_EVM_DTB; + }; + + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j784s4-evm"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + ti-spl_unsigned { + insert-template = <&ti_spl_unsigned_template>; + + fit { + images { + dm { + blob-ext { + filename = "ti-dm.bin"; + }; + }; + + fdt-0 { + description = "k3-j784s4-evm"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + spl_j784s4_evm_dtb_unsigned: blob { + filename = SPL_J784S4_EVM_DTB; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j784s4-evm"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot_unsigned { + insert-template = <&u_boot_unsigned_template>; + + fit { + images { + uboot { + description = "U-Boot for J784S4 board"; + }; + + fdt-0 { + description = "k3-j784s4-evm"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + j784s4_evm_dtb_unsigned: blob { + filename = J784S4_EVM_DTB; + }; + + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j784s4-evm"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; +#endif diff --git a/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi new file mode 100644 index 00000000000..0e16d2f201d --- /dev/null +++ b/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi @@ -0,0 +1,8757 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.10.0 + * This file was generated on 04/12/2023 + */ + +#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FREQUENCY_0 27500000 +#define DDRSS_PLL_FREQUENCY_1 1066500000 +#define DDRSS_PLL_FREQUENCY_2 1066500000 + +#define MULTI_DDR_CFG_INTRLV_GRAN 0 +#define MULTI_DDR_CFG_INTRLV_SIZE 12 +#define MULTI_DDR_CFG_ECC_ENABLE 0 +#define MULTI_DDR_CFG_HYBRID_SELECT 24 +#define MULTI_DDR_CFG_EMIFS_ACTIVE 15 + +#define DDRSS0_CTL_00_DATA 0x00000B00 +#define DDRSS0_CTL_01_DATA 0x00000000 +#define DDRSS0_CTL_02_DATA 0x00000000 +#define DDRSS0_CTL_03_DATA 0x00000000 +#define DDRSS0_CTL_04_DATA 0x00000000 +#define DDRSS0_CTL_05_DATA 0x00000000 +#define DDRSS0_CTL_06_DATA 0x00000000 +#define DDRSS0_CTL_07_DATA 0x00002AF8 +#define DDRSS0_CTL_08_DATA 0x0001ADAF +#define DDRSS0_CTL_09_DATA 0x00000005 +#define DDRSS0_CTL_10_DATA 0x0000006E +#define DDRSS0_CTL_11_DATA 0x000681C8 +#define DDRSS0_CTL_12_DATA 0x004111C9 +#define DDRSS0_CTL_13_DATA 0x00000005 +#define DDRSS0_CTL_14_DATA 0x000010A9 +#define DDRSS0_CTL_15_DATA 0x000681C8 +#define DDRSS0_CTL_16_DATA 0x004111C9 +#define DDRSS0_CTL_17_DATA 0x00000005 +#define DDRSS0_CTL_18_DATA 0x000010A9 +#define DDRSS0_CTL_19_DATA 0x01010000 +#define DDRSS0_CTL_20_DATA 0x02011001 +#define DDRSS0_CTL_21_DATA 0x02010000 +#define DDRSS0_CTL_22_DATA 0x00020100 +#define DDRSS0_CTL_23_DATA 0x0000000B +#define DDRSS0_CTL_24_DATA 0x0000001C +#define DDRSS0_CTL_25_DATA 0x00000000 +#define DDRSS0_CTL_26_DATA 0x00000000 +#define DDRSS0_CTL_27_DATA 0x03020200 +#define DDRSS0_CTL_28_DATA 0x00005656 +#define DDRSS0_CTL_29_DATA 0x00100000 +#define DDRSS0_CTL_30_DATA 0x00000000 +#define DDRSS0_CTL_31_DATA 0x00000000 +#define DDRSS0_CTL_32_DATA 0x00000000 +#define DDRSS0_CTL_33_DATA 0x00000000 +#define DDRSS0_CTL_34_DATA 0x040C0000 +#define DDRSS0_CTL_35_DATA 0x12481248 +#define DDRSS0_CTL_36_DATA 0x00050804 +#define DDRSS0_CTL_37_DATA 0x09040008 +#define DDRSS0_CTL_38_DATA 0x15000204 +#define DDRSS0_CTL_39_DATA 0x1760008B +#define DDRSS0_CTL_40_DATA 0x1500422B +#define DDRSS0_CTL_41_DATA 0x1760008B +#define DDRSS0_CTL_42_DATA 0x2000422B +#define DDRSS0_CTL_43_DATA 0x000A0A09 +#define DDRSS0_CTL_44_DATA 0x040003C5 +#define DDRSS0_CTL_45_DATA 0x1E161104 +#define DDRSS0_CTL_46_DATA 0x1000922C +#define DDRSS0_CTL_47_DATA 0x1E161110 +#define DDRSS0_CTL_48_DATA 0x1000922C +#define DDRSS0_CTL_49_DATA 0x02030410 +#define DDRSS0_CTL_50_DATA 0x2C040500 +#define DDRSS0_CTL_51_DATA 0x08292C29 +#define DDRSS0_CTL_52_DATA 0x14000E0A +#define DDRSS0_CTL_53_DATA 0x04010A0A +#define DDRSS0_CTL_54_DATA 0x01010004 +#define DDRSS0_CTL_55_DATA 0x04545408 +#define DDRSS0_CTL_56_DATA 0x04313104 +#define DDRSS0_CTL_57_DATA 0x00003131 +#define DDRSS0_CTL_58_DATA 0x00010100 +#define DDRSS0_CTL_59_DATA 0x03010000 +#define DDRSS0_CTL_60_DATA 0x00001508 +#define DDRSS0_CTL_61_DATA 0x00000063 +#define DDRSS0_CTL_62_DATA 0x0000032B +#define DDRSS0_CTL_63_DATA 0x00001035 +#define DDRSS0_CTL_64_DATA 0x0000032B +#define DDRSS0_CTL_65_DATA 0x00001035 +#define DDRSS0_CTL_66_DATA 0x00000005 +#define DDRSS0_CTL_67_DATA 0x00050000 +#define DDRSS0_CTL_68_DATA 0x00CB0012 +#define DDRSS0_CTL_69_DATA 0x00CB0408 +#define DDRSS0_CTL_70_DATA 0x00400408 +#define DDRSS0_CTL_71_DATA 0x00120103 +#define DDRSS0_CTL_72_DATA 0x00100005 +#define DDRSS0_CTL_73_DATA 0x2F080010 +#define DDRSS0_CTL_74_DATA 0x0505012F +#define DDRSS0_CTL_75_DATA 0x0401030A +#define DDRSS0_CTL_76_DATA 0x041E100B +#define DDRSS0_CTL_77_DATA 0x100B0401 +#define DDRSS0_CTL_78_DATA 0x0001041E +#define DDRSS0_CTL_79_DATA 0x00160016 +#define DDRSS0_CTL_80_DATA 0x033B033B +#define DDRSS0_CTL_81_DATA 0x033B033B +#define DDRSS0_CTL_82_DATA 0x03050505 +#define DDRSS0_CTL_83_DATA 0x03010303 +#define DDRSS0_CTL_84_DATA 0x200B100B +#define DDRSS0_CTL_85_DATA 0x04041004 +#define DDRSS0_CTL_86_DATA 0x200B100B +#define DDRSS0_CTL_87_DATA 0x04041004 +#define DDRSS0_CTL_88_DATA 0x03010000 +#define DDRSS0_CTL_89_DATA 0x00010000 +#define DDRSS0_CTL_90_DATA 0x00000000 +#define DDRSS0_CTL_91_DATA 0x00000000 +#define DDRSS0_CTL_92_DATA 0x01000000 +#define DDRSS0_CTL_93_DATA 0x80104002 +#define DDRSS0_CTL_94_DATA 0x00000000 +#define DDRSS0_CTL_95_DATA 0x00040005 +#define DDRSS0_CTL_96_DATA 0x00000000 +#define DDRSS0_CTL_97_DATA 0x00050000 +#define DDRSS0_CTL_98_DATA 0x00000004 +#define DDRSS0_CTL_99_DATA 0x00000000 +#define DDRSS0_CTL_100_DATA 0x00040005 +#define DDRSS0_CTL_101_DATA 0x00000000 +#define DDRSS0_CTL_102_DATA 0x000018C0 +#define DDRSS0_CTL_103_DATA 0x000018C0 +#define DDRSS0_CTL_104_DATA 0x000018C0 +#define DDRSS0_CTL_105_DATA 0x000018C0 +#define DDRSS0_CTL_106_DATA 0x000018C0 +#define DDRSS0_CTL_107_DATA 0x00000000 +#define DDRSS0_CTL_108_DATA 0x000002B5 +#define DDRSS0_CTL_109_DATA 0x00040D40 +#define DDRSS0_CTL_110_DATA 0x00040D40 +#define DDRSS0_CTL_111_DATA 0x00040D40 +#define DDRSS0_CTL_112_DATA 0x00040D40 +#define DDRSS0_CTL_113_DATA 0x00040D40 +#define DDRSS0_CTL_114_DATA 0x00000000 +#define DDRSS0_CTL_115_DATA 0x00007173 +#define DDRSS0_CTL_116_DATA 0x00040D40 +#define DDRSS0_CTL_117_DATA 0x00040D40 +#define DDRSS0_CTL_118_DATA 0x00040D40 +#define DDRSS0_CTL_119_DATA 0x00040D40 +#define DDRSS0_CTL_120_DATA 0x00040D40 +#define DDRSS0_CTL_121_DATA 0x00000000 +#define DDRSS0_CTL_122_DATA 0x00007173 +#define DDRSS0_CTL_123_DATA 0x00000000 +#define DDRSS0_CTL_124_DATA 0x00000000 +#define DDRSS0_CTL_125_DATA 0x00000000 +#define DDRSS0_CTL_126_DATA 0x00000000 +#define DDRSS0_CTL_127_DATA 0x00000000 +#define DDRSS0_CTL_128_DATA 0x00000000 +#define DDRSS0_CTL_129_DATA 0x00000000 +#define DDRSS0_CTL_130_DATA 0x00000000 +#define DDRSS0_CTL_131_DATA 0x0B030500 +#define DDRSS0_CTL_132_DATA 0x00040B04 +#define DDRSS0_CTL_133_DATA 0x0A090000 +#define DDRSS0_CTL_134_DATA 0x0A090701 +#define DDRSS0_CTL_135_DATA 0x0900000E +#define DDRSS0_CTL_136_DATA 0x0907010A +#define DDRSS0_CTL_137_DATA 0x00000E0A +#define DDRSS0_CTL_138_DATA 0x07010A09 +#define DDRSS0_CTL_139_DATA 0x000E0A09 +#define DDRSS0_CTL_140_DATA 0x07000401 +#define DDRSS0_CTL_141_DATA 0x00000000 +#define DDRSS0_CTL_142_DATA 0x00000000 +#define DDRSS0_CTL_143_DATA 0x00000000 +#define DDRSS0_CTL_144_DATA 0x00000000 +#define DDRSS0_CTL_145_DATA 0x00000000 +#define DDRSS0_CTL_146_DATA 0x00000000 +#define DDRSS0_CTL_147_DATA 0x00000000 +#define DDRSS0_CTL_148_DATA 0x08080000 +#define DDRSS0_CTL_149_DATA 0x01000000 +#define DDRSS0_CTL_150_DATA 0x800000C0 +#define DDRSS0_CTL_151_DATA 0x800000C0 +#define DDRSS0_CTL_152_DATA 0x800000C0 +#define DDRSS0_CTL_153_DATA 0x00000000 +#define DDRSS0_CTL_154_DATA 0x00001500 +#define DDRSS0_CTL_155_DATA 0x00000000 +#define DDRSS0_CTL_156_DATA 0x00000001 +#define DDRSS0_CTL_157_DATA 0x00000002 +#define DDRSS0_CTL_158_DATA 0x0000100E +#define DDRSS0_CTL_159_DATA 0x00000000 +#define DDRSS0_CTL_160_DATA 0x00000000 +#define DDRSS0_CTL_161_DATA 0x00000000 +#define DDRSS0_CTL_162_DATA 0x00000000 +#define DDRSS0_CTL_163_DATA 0x00000000 +#define DDRSS0_CTL_164_DATA 0x000B0000 +#define DDRSS0_CTL_165_DATA 0x000E0006 +#define DDRSS0_CTL_166_DATA 0x000E0404 +#define DDRSS0_CTL_167_DATA 0x00D601AB +#define DDRSS0_CTL_168_DATA 0x10100216 +#define DDRSS0_CTL_169_DATA 0x01AB0216 +#define DDRSS0_CTL_170_DATA 0x021600D6 +#define DDRSS0_CTL_171_DATA 0x02161010 +#define DDRSS0_CTL_172_DATA 0x00000000 +#define DDRSS0_CTL_173_DATA 0x00000000 +#define DDRSS0_CTL_174_DATA 0x00000000 +#define DDRSS0_CTL_175_DATA 0x3FF40084 +#define DDRSS0_CTL_176_DATA 0x33003FF4 +#define DDRSS0_CTL_177_DATA 0x00003333 +#define DDRSS0_CTL_178_DATA 0x35000000 +#define DDRSS0_CTL_179_DATA 0x27270035 +#define DDRSS0_CTL_180_DATA 0x0F0F0000 +#define DDRSS0_CTL_181_DATA 0x16000000 +#define DDRSS0_CTL_182_DATA 0x00841616 +#define DDRSS0_CTL_183_DATA 0x3FF43FF4 +#define DDRSS0_CTL_184_DATA 0x33333300 +#define DDRSS0_CTL_185_DATA 0x00000000 +#define DDRSS0_CTL_186_DATA 0x00353500 +#define DDRSS0_CTL_187_DATA 0x00002727 +#define DDRSS0_CTL_188_DATA 0x00000F0F +#define DDRSS0_CTL_189_DATA 0x16161600 +#define DDRSS0_CTL_190_DATA 0x00000020 +#define DDRSS0_CTL_191_DATA 0x00000000 +#define DDRSS0_CTL_192_DATA 0x00000001 +#define DDRSS0_CTL_193_DATA 0x00000000 +#define DDRSS0_CTL_194_DATA 0x01000000 +#define DDRSS0_CTL_195_DATA 0x00000001 +#define DDRSS0_CTL_196_DATA 0x00000000 +#define DDRSS0_CTL_197_DATA 0x00000000 +#define DDRSS0_CTL_198_DATA 0x00000000 +#define DDRSS0_CTL_199_DATA 0x00000000 +#define DDRSS0_CTL_200_DATA 0x00000000 +#define DDRSS0_CTL_201_DATA 0x00000000 +#define DDRSS0_CTL_202_DATA 0x00000000 +#define DDRSS0_CTL_203_DATA 0x00000000 +#define DDRSS0_CTL_204_DATA 0x00000000 +#define DDRSS0_CTL_205_DATA 0x00000000 +#define DDRSS0_CTL_206_DATA 0x02000000 +#define DDRSS0_CTL_207_DATA 0x01080101 +#define DDRSS0_CTL_208_DATA 0x00000000 +#define DDRSS0_CTL_209_DATA 0x00000000 +#define DDRSS0_CTL_210_DATA 0x00000000 +#define DDRSS0_CTL_211_DATA 0x00000000 +#define DDRSS0_CTL_212_DATA 0x00000000 +#define DDRSS0_CTL_213_DATA 0x00000000 +#define DDRSS0_CTL_214_DATA 0x00000000 +#define DDRSS0_CTL_215_DATA 0x00000000 +#define DDRSS0_CTL_216_DATA 0x00000000 +#define DDRSS0_CTL_217_DATA 0x00000000 +#define DDRSS0_CTL_218_DATA 0x00000000 +#define DDRSS0_CTL_219_DATA 0x00000000 +#define DDRSS0_CTL_220_DATA 0x00000000 +#define DDRSS0_CTL_221_DATA 0x00000000 +#define DDRSS0_CTL_222_DATA 0x00001000 +#define DDRSS0_CTL_223_DATA 0x006403E8 +#define DDRSS0_CTL_224_DATA 0x00000000 +#define DDRSS0_CTL_225_DATA 0x00000000 +#define DDRSS0_CTL_226_DATA 0x00000000 +#define DDRSS0_CTL_227_DATA 0x15110000 +#define DDRSS0_CTL_228_DATA 0x00040C18 +#define DDRSS0_CTL_229_DATA 0xF000C000 +#define DDRSS0_CTL_230_DATA 0x0000F000 +#define DDRSS0_CTL_231_DATA 0x00000000 +#define DDRSS0_CTL_232_DATA 0x00000000 +#define DDRSS0_CTL_233_DATA 0xC0000000 +#define DDRSS0_CTL_234_DATA 0xF000F000 +#define DDRSS0_CTL_235_DATA 0x00000000 +#define DDRSS0_CTL_236_DATA 0x00000000 +#define DDRSS0_CTL_237_DATA 0x00000000 +#define DDRSS0_CTL_238_DATA 0xF000C000 +#define DDRSS0_CTL_239_DATA 0x0000F000 +#define DDRSS0_CTL_240_DATA 0x00000000 +#define DDRSS0_CTL_241_DATA 0x00000000 +#define DDRSS0_CTL_242_DATA 0x00030000 +#define DDRSS0_CTL_243_DATA 0x00000000 +#define DDRSS0_CTL_244_DATA 0x00000000 +#define DDRSS0_CTL_245_DATA 0x00000000 +#define DDRSS0_CTL_246_DATA 0x00000000 +#define DDRSS0_CTL_247_DATA 0x00000000 +#define DDRSS0_CTL_248_DATA 0x00000000 +#define DDRSS0_CTL_249_DATA 0x00000000 +#define DDRSS0_CTL_250_DATA 0x00000000 +#define DDRSS0_CTL_251_DATA 0x00000000 +#define DDRSS0_CTL_252_DATA 0x00000000 +#define DDRSS0_CTL_253_DATA 0x00000000 +#define DDRSS0_CTL_254_DATA 0x00000000 +#define DDRSS0_CTL_255_DATA 0x00000000 +#define DDRSS0_CTL_256_DATA 0x00000000 +#define DDRSS0_CTL_257_DATA 0x01000200 +#define DDRSS0_CTL_258_DATA 0x00370040 +#define DDRSS0_CTL_259_DATA 0x00020008 +#define DDRSS0_CTL_260_DATA 0x00400100 +#define DDRSS0_CTL_261_DATA 0x00400855 +#define DDRSS0_CTL_262_DATA 0x01000200 +#define DDRSS0_CTL_263_DATA 0x08550040 +#define DDRSS0_CTL_264_DATA 0x00000040 +#define DDRSS0_CTL_265_DATA 0x006B0003 +#define DDRSS0_CTL_266_DATA 0x0100006B +#define DDRSS0_CTL_267_DATA 0x03030303 +#define DDRSS0_CTL_268_DATA 0x00000000 +#define DDRSS0_CTL_269_DATA 0x00000202 +#define DDRSS0_CTL_270_DATA 0x00001FFF +#define DDRSS0_CTL_271_DATA 0x3FFF2000 +#define DDRSS0_CTL_272_DATA 0x03FF0000 +#define DDRSS0_CTL_273_DATA 0x000103FF +#define DDRSS0_CTL_274_DATA 0x0FFF0B00 +#define DDRSS0_CTL_275_DATA 0x01010001 +#define DDRSS0_CTL_276_DATA 0x01010101 +#define DDRSS0_CTL_277_DATA 0x01180101 +#define DDRSS0_CTL_278_DATA 0x00030000 +#define DDRSS0_CTL_279_DATA 0x00000000 +#define DDRSS0_CTL_280_DATA 0x00000000 +#define DDRSS0_CTL_281_DATA 0x00000000 +#define DDRSS0_CTL_282_DATA 0x00000000 +#define DDRSS0_CTL_283_DATA 0x00000000 +#define DDRSS0_CTL_284_DATA 0x00000000 +#define DDRSS0_CTL_285_DATA 0x00000000 +#define DDRSS0_CTL_286_DATA 0x00040101 +#define DDRSS0_CTL_287_DATA 0x04010100 +#define DDRSS0_CTL_288_DATA 0x00000000 +#define DDRSS0_CTL_289_DATA 0x00000000 +#define DDRSS0_CTL_290_DATA 0x03030300 +#define DDRSS0_CTL_291_DATA 0x00000001 +#define DDRSS0_CTL_292_DATA 0x00000000 +#define DDRSS0_CTL_293_DATA 0x00000000 +#define DDRSS0_CTL_294_DATA 0x00000000 +#define DDRSS0_CTL_295_DATA 0x00000000 +#define DDRSS0_CTL_296_DATA 0x00000000 +#define DDRSS0_CTL_297_DATA 0x00000000 +#define DDRSS0_CTL_298_DATA 0x00000000 +#define DDRSS0_CTL_299_DATA 0x00000000 +#define DDRSS0_CTL_300_DATA 0x00000000 +#define DDRSS0_CTL_301_DATA 0x00000000 +#define DDRSS0_CTL_302_DATA 0x00000000 +#define DDRSS0_CTL_303_DATA 0x00000000 +#define DDRSS0_CTL_304_DATA 0x00000000 +#define DDRSS0_CTL_305_DATA 0x00000000 +#define DDRSS0_CTL_306_DATA 0x00000000 +#define DDRSS0_CTL_307_DATA 0x00000000 +#define DDRSS0_CTL_308_DATA 0x00000000 +#define DDRSS0_CTL_309_DATA 0x00000000 +#define DDRSS0_CTL_310_DATA 0x00000000 +#define DDRSS0_CTL_311_DATA 0x00000000 +#define DDRSS0_CTL_312_DATA 0x00000000 +#define DDRSS0_CTL_313_DATA 0x01000000 +#define DDRSS0_CTL_314_DATA 0x00020201 +#define DDRSS0_CTL_315_DATA 0x01000101 +#define DDRSS0_CTL_316_DATA 0x01010001 +#define DDRSS0_CTL_317_DATA 0x00010101 +#define DDRSS0_CTL_318_DATA 0x050A0A03 +#define DDRSS0_CTL_319_DATA 0x10081F1F +#define DDRSS0_CTL_320_DATA 0x00090310 +#define DDRSS0_CTL_321_DATA 0x0B0C030F +#define DDRSS0_CTL_322_DATA 0x0B0C0306 +#define DDRSS0_CTL_323_DATA 0x0C090006 +#define DDRSS0_CTL_324_DATA 0x0100000C +#define DDRSS0_CTL_325_DATA 0x08040801 +#define DDRSS0_CTL_326_DATA 0x00000004 +#define DDRSS0_CTL_327_DATA 0x00000000 +#define DDRSS0_CTL_328_DATA 0x00010000 +#define DDRSS0_CTL_329_DATA 0x00280D00 +#define DDRSS0_CTL_330_DATA 0x00000001 +#define DDRSS0_CTL_331_DATA 0x00030001 +#define DDRSS0_CTL_332_DATA 0x00000000 +#define DDRSS0_CTL_333_DATA 0x00000000 +#define DDRSS0_CTL_334_DATA 0x00000000 +#define DDRSS0_CTL_335_DATA 0x00000000 +#define DDRSS0_CTL_336_DATA 0x00000000 +#define DDRSS0_CTL_337_DATA 0x00000000 +#define DDRSS0_CTL_338_DATA 0x00000000 +#define DDRSS0_CTL_339_DATA 0x00000000 +#define DDRSS0_CTL_340_DATA 0x01000000 +#define DDRSS0_CTL_341_DATA 0x00000001 +#define DDRSS0_CTL_342_DATA 0x00010100 +#define DDRSS0_CTL_343_DATA 0x03030000 +#define DDRSS0_CTL_344_DATA 0x00000000 +#define DDRSS0_CTL_345_DATA 0x00000000 +#define DDRSS0_CTL_346_DATA 0x00000000 +#define DDRSS0_CTL_347_DATA 0x00000000 +#define DDRSS0_CTL_348_DATA 0x00000000 +#define DDRSS0_CTL_349_DATA 0x00000000 +#define DDRSS0_CTL_350_DATA 0x00000000 +#define DDRSS0_CTL_351_DATA 0x00000000 +#define DDRSS0_CTL_352_DATA 0x00000000 +#define DDRSS0_CTL_353_DATA 0x00000000 +#define DDRSS0_CTL_354_DATA 0x00000000 +#define DDRSS0_CTL_355_DATA 0x00000000 +#define DDRSS0_CTL_356_DATA 0x00000000 +#define DDRSS0_CTL_357_DATA 0x00000000 +#define DDRSS0_CTL_358_DATA 0x00000000 +#define DDRSS0_CTL_359_DATA 0x00000000 +#define DDRSS0_CTL_360_DATA 0x000556AA +#define DDRSS0_CTL_361_DATA 0x000AAAAA +#define DDRSS0_CTL_362_DATA 0x000AA955 +#define DDRSS0_CTL_363_DATA 0x00055555 +#define DDRSS0_CTL_364_DATA 0x000B3133 +#define DDRSS0_CTL_365_DATA 0x0004CD33 +#define DDRSS0_CTL_366_DATA 0x0004CECC +#define DDRSS0_CTL_367_DATA 0x000B32CC +#define DDRSS0_CTL_368_DATA 0x00010300 +#define DDRSS0_CTL_369_DATA 0x03000100 +#define DDRSS0_CTL_370_DATA 0x00000000 +#define DDRSS0_CTL_371_DATA 0x00000000 +#define DDRSS0_CTL_372_DATA 0x00000000 +#define DDRSS0_CTL_373_DATA 0x00000000 +#define DDRSS0_CTL_374_DATA 0x00000000 +#define DDRSS0_CTL_375_DATA 0x00000000 +#define DDRSS0_CTL_376_DATA 0x00000000 +#define DDRSS0_CTL_377_DATA 0x00010000 +#define DDRSS0_CTL_378_DATA 0x00000404 +#define DDRSS0_CTL_379_DATA 0x00000000 +#define DDRSS0_CTL_380_DATA 0x00000000 +#define DDRSS0_CTL_381_DATA 0x00000000 +#define DDRSS0_CTL_382_DATA 0x00000000 +#define DDRSS0_CTL_383_DATA 0x00000000 +#define DDRSS0_CTL_384_DATA 0x00000000 +#define DDRSS0_CTL_385_DATA 0x00000000 +#define DDRSS0_CTL_386_DATA 0x00000000 +#define DDRSS0_CTL_387_DATA 0x3A3A1B00 +#define DDRSS0_CTL_388_DATA 0x000A0000 +#define DDRSS0_CTL_389_DATA 0x000000C6 +#define DDRSS0_CTL_390_DATA 0x00000200 +#define DDRSS0_CTL_391_DATA 0x00000200 +#define DDRSS0_CTL_392_DATA 0x00000200 +#define DDRSS0_CTL_393_DATA 0x00000200 +#define DDRSS0_CTL_394_DATA 0x00000252 +#define DDRSS0_CTL_395_DATA 0x000007BC +#define DDRSS0_CTL_396_DATA 0x00000204 +#define DDRSS0_CTL_397_DATA 0x0000206A +#define DDRSS0_CTL_398_DATA 0x00000200 +#define DDRSS0_CTL_399_DATA 0x00000200 +#define DDRSS0_CTL_400_DATA 0x00000200 +#define DDRSS0_CTL_401_DATA 0x00000200 +#define DDRSS0_CTL_402_DATA 0x0000613E +#define DDRSS0_CTL_403_DATA 0x00014424 +#define DDRSS0_CTL_404_DATA 0x00000E15 +#define DDRSS0_CTL_405_DATA 0x0000206A +#define DDRSS0_CTL_406_DATA 0x00000200 +#define DDRSS0_CTL_407_DATA 0x00000200 +#define DDRSS0_CTL_408_DATA 0x00000200 +#define DDRSS0_CTL_409_DATA 0x00000200 +#define DDRSS0_CTL_410_DATA 0x0000613E +#define DDRSS0_CTL_411_DATA 0x00014424 +#define DDRSS0_CTL_412_DATA 0x02020E15 +#define DDRSS0_CTL_413_DATA 0x03030202 +#define DDRSS0_CTL_414_DATA 0x00000022 +#define DDRSS0_CTL_415_DATA 0x00000000 +#define DDRSS0_CTL_416_DATA 0x00000000 +#define DDRSS0_CTL_417_DATA 0x00001403 +#define DDRSS0_CTL_418_DATA 0x000007D0 +#define DDRSS0_CTL_419_DATA 0x00000000 +#define DDRSS0_CTL_420_DATA 0x00000000 +#define DDRSS0_CTL_421_DATA 0x00030000 +#define DDRSS0_CTL_422_DATA 0x0007001F +#define DDRSS0_CTL_423_DATA 0x001B0033 +#define DDRSS0_CTL_424_DATA 0x001B0033 +#define DDRSS0_CTL_425_DATA 0x00000000 +#define DDRSS0_CTL_426_DATA 0x00000000 +#define DDRSS0_CTL_427_DATA 0x02000000 +#define DDRSS0_CTL_428_DATA 0x01000404 +#define DDRSS0_CTL_429_DATA 0x0B1E0B1E +#define DDRSS0_CTL_430_DATA 0x00000105 +#define DDRSS0_CTL_431_DATA 0x00010101 +#define DDRSS0_CTL_432_DATA 0x00010101 +#define DDRSS0_CTL_433_DATA 0x00010001 +#define DDRSS0_CTL_434_DATA 0x00000101 +#define DDRSS0_CTL_435_DATA 0x02000201 +#define DDRSS0_CTL_436_DATA 0x02010000 +#define DDRSS0_CTL_437_DATA 0x00000200 +#define DDRSS0_CTL_438_DATA 0x28060000 +#define DDRSS0_CTL_439_DATA 0x00000128 +#define DDRSS0_CTL_440_DATA 0xFFFFFFFF +#define DDRSS0_CTL_441_DATA 0xFFFFFFFF +#define DDRSS0_CTL_442_DATA 0x00000000 +#define DDRSS0_CTL_443_DATA 0x00000000 +#define DDRSS0_CTL_444_DATA 0x00000000 +#define DDRSS0_CTL_445_DATA 0x00000000 +#define DDRSS0_CTL_446_DATA 0x00000000 +#define DDRSS0_CTL_447_DATA 0x00000000 +#define DDRSS0_CTL_448_DATA 0x00000000 +#define DDRSS0_CTL_449_DATA 0x00000000 +#define DDRSS0_CTL_450_DATA 0x00000000 +#define DDRSS0_CTL_451_DATA 0x00000000 +#define DDRSS0_CTL_452_DATA 0x00000000 +#define DDRSS0_CTL_453_DATA 0x00000000 +#define DDRSS0_CTL_454_DATA 0x00000000 +#define DDRSS0_CTL_455_DATA 0x00000000 +#define DDRSS0_CTL_456_DATA 0x00000000 +#define DDRSS0_CTL_457_DATA 0x00000000 +#define DDRSS0_CTL_458_DATA 0x00000000 + +#define DDRSS0_PI_00_DATA 0x00000B00 +#define DDRSS0_PI_01_DATA 0x00000000 +#define DDRSS0_PI_02_DATA 0x00000000 +#define DDRSS0_PI_03_DATA 0x00000000 +#define DDRSS0_PI_04_DATA 0x00000000 +#define DDRSS0_PI_05_DATA 0x00000101 +#define DDRSS0_PI_06_DATA 0x00640000 +#define DDRSS0_PI_07_DATA 0x00000001 +#define DDRSS0_PI_08_DATA 0x00000000 +#define DDRSS0_PI_09_DATA 0x00000000 +#define DDRSS0_PI_10_DATA 0x00000000 +#define DDRSS0_PI_11_DATA 0x00000000 +#define DDRSS0_PI_12_DATA 0x00000007 +#define DDRSS0_PI_13_DATA 0x00010002 +#define DDRSS0_PI_14_DATA 0x0800000F +#define DDRSS0_PI_15_DATA 0x00000103 +#define DDRSS0_PI_16_DATA 0x00000005 +#define DDRSS0_PI_17_DATA 0x00000000 +#define DDRSS0_PI_18_DATA 0x00000000 +#define DDRSS0_PI_19_DATA 0x00000000 +#define DDRSS0_PI_20_DATA 0x00000000 +#define DDRSS0_PI_21_DATA 0x00000000 +#define DDRSS0_PI_22_DATA 0x00000000 +#define DDRSS0_PI_23_DATA 0x00000000 +#define DDRSS0_PI_24_DATA 0x00000000 +#define DDRSS0_PI_25_DATA 0x00000000 +#define DDRSS0_PI_26_DATA 0x00010100 +#define DDRSS0_PI_27_DATA 0x00280A00 +#define DDRSS0_PI_28_DATA 0x00000000 +#define DDRSS0_PI_29_DATA 0x0F000000 +#define DDRSS0_PI_30_DATA 0x00003200 +#define DDRSS0_PI_31_DATA 0x00000000 +#define DDRSS0_PI_32_DATA 0x00000000 +#define DDRSS0_PI_33_DATA 0x01010102 +#define DDRSS0_PI_34_DATA 0x00000000 +#define DDRSS0_PI_35_DATA 0x000000AA +#define DDRSS0_PI_36_DATA 0x00000055 +#define DDRSS0_PI_37_DATA 0x000000B5 +#define DDRSS0_PI_38_DATA 0x0000004A +#define DDRSS0_PI_39_DATA 0x00000056 +#define DDRSS0_PI_40_DATA 0x000000A9 +#define DDRSS0_PI_41_DATA 0x000000A9 +#define DDRSS0_PI_42_DATA 0x000000B5 +#define DDRSS0_PI_43_DATA 0x00000000 +#define DDRSS0_PI_44_DATA 0x00000000 +#define DDRSS0_PI_45_DATA 0x000F0F00 +#define DDRSS0_PI_46_DATA 0x0000001B +#define DDRSS0_PI_47_DATA 0x000007D0 +#define DDRSS0_PI_48_DATA 0x00000300 +#define DDRSS0_PI_49_DATA 0x00000000 +#define DDRSS0_PI_50_DATA 0x00000000 +#define DDRSS0_PI_51_DATA 0x01000000 +#define DDRSS0_PI_52_DATA 0x00010101 +#define DDRSS0_PI_53_DATA 0x00000000 +#define DDRSS0_PI_54_DATA 0x00030000 +#define DDRSS0_PI_55_DATA 0x0F000000 +#define DDRSS0_PI_56_DATA 0x00000017 +#define DDRSS0_PI_57_DATA 0x00000000 +#define DDRSS0_PI_58_DATA 0x00000000 +#define DDRSS0_PI_59_DATA 0x00000000 +#define DDRSS0_PI_60_DATA 0x0A0A140A +#define DDRSS0_PI_61_DATA 0x10020101 +#define DDRSS0_PI_62_DATA 0x00020805 +#define DDRSS0_PI_63_DATA 0x01000404 +#define DDRSS0_PI_64_DATA 0x00000000 +#define DDRSS0_PI_65_DATA 0x00000000 +#define DDRSS0_PI_66_DATA 0x00000100 +#define DDRSS0_PI_67_DATA 0x0001010F +#define DDRSS0_PI_68_DATA 0x00340000 +#define DDRSS0_PI_69_DATA 0x00000000 +#define DDRSS0_PI_70_DATA 0x00000000 +#define DDRSS0_PI_71_DATA 0x0000FFFF +#define DDRSS0_PI_72_DATA 0x00000000 +#define DDRSS0_PI_73_DATA 0x00080000 +#define DDRSS0_PI_74_DATA 0x02000200 +#define DDRSS0_PI_75_DATA 0x01000100 +#define DDRSS0_PI_76_DATA 0x01000000 +#define DDRSS0_PI_77_DATA 0x02000200 +#define DDRSS0_PI_78_DATA 0x00000200 +#define DDRSS0_PI_79_DATA 0x00000000 +#define DDRSS0_PI_80_DATA 0x00000000 +#define DDRSS0_PI_81_DATA 0x00000000 +#define DDRSS0_PI_82_DATA 0x00000000 +#define DDRSS0_PI_83_DATA 0x00000000 +#define DDRSS0_PI_84_DATA 0x00000000 +#define DDRSS0_PI_85_DATA 0x00000000 +#define DDRSS0_PI_86_DATA 0x00000000 +#define DDRSS0_PI_87_DATA 0x00000000 +#define DDRSS0_PI_88_DATA 0x00000000 +#define DDRSS0_PI_89_DATA 0x00000000 +#define DDRSS0_PI_90_DATA 0x00000000 +#define DDRSS0_PI_91_DATA 0x00000400 +#define DDRSS0_PI_92_DATA 0x02010000 +#define DDRSS0_PI_93_DATA 0x00080003 +#define DDRSS0_PI_94_DATA 0x00080000 +#define DDRSS0_PI_95_DATA 0x00000001 +#define DDRSS0_PI_96_DATA 0x00000000 +#define DDRSS0_PI_97_DATA 0x0000AA00 +#define DDRSS0_PI_98_DATA 0x00000000 +#define DDRSS0_PI_99_DATA 0x00000000 +#define DDRSS0_PI_100_DATA 0x00010000 +#define DDRSS0_PI_101_DATA 0x00000000 +#define DDRSS0_PI_102_DATA 0x00000000 +#define DDRSS0_PI_103_DATA 0x00000000 +#define DDRSS0_PI_104_DATA 0x00000000 +#define DDRSS0_PI_105_DATA 0x00000000 +#define DDRSS0_PI_106_DATA 0x00000000 +#define DDRSS0_PI_107_DATA 0x00000000 +#define DDRSS0_PI_108_DATA 0x00000000 +#define DDRSS0_PI_109_DATA 0x00000000 +#define DDRSS0_PI_110_DATA 0x00000000 +#define DDRSS0_PI_111_DATA 0x00000000 +#define DDRSS0_PI_112_DATA 0x00000000 +#define DDRSS0_PI_113_DATA 0x00000000 +#define DDRSS0_PI_114_DATA 0x00000000 +#define DDRSS0_PI_115_DATA 0x00000000 +#define DDRSS0_PI_116_DATA 0x00000000 +#define DDRSS0_PI_117_DATA 0x00000000 +#define DDRSS0_PI_118_DATA 0x00000000 +#define DDRSS0_PI_119_DATA 0x00000000 +#define DDRSS0_PI_120_DATA 0x00000000 +#define DDRSS0_PI_121_DATA 0x00000000 +#define DDRSS0_PI_122_DATA 0x00000000 +#define DDRSS0_PI_123_DATA 0x00000000 +#define DDRSS0_PI_124_DATA 0x00000000 +#define DDRSS0_PI_125_DATA 0x00000008 +#define DDRSS0_PI_126_DATA 0x00000000 +#define DDRSS0_PI_127_DATA 0x00000000 +#define DDRSS0_PI_128_DATA 0x00000000 +#define DDRSS0_PI_129_DATA 0x00000000 +#define DDRSS0_PI_130_DATA 0x00000000 +#define DDRSS0_PI_131_DATA 0x00000000 +#define DDRSS0_PI_132_DATA 0x00000000 +#define DDRSS0_PI_133_DATA 0x00000000 +#define DDRSS0_PI_134_DATA 0x00000002 +#define DDRSS0_PI_135_DATA 0x00000000 +#define DDRSS0_PI_136_DATA 0x00000000 +#define DDRSS0_PI_137_DATA 0x0000000A +#define DDRSS0_PI_138_DATA 0x00000019 +#define DDRSS0_PI_139_DATA 0x00000100 +#define DDRSS0_PI_140_DATA 0x00000000 +#define DDRSS0_PI_141_DATA 0x00000000 +#define DDRSS0_PI_142_DATA 0x00000000 +#define DDRSS0_PI_143_DATA 0x00000000 +#define DDRSS0_PI_144_DATA 0x01000000 +#define DDRSS0_PI_145_DATA 0x00010003 +#define DDRSS0_PI_146_DATA 0x02000101 +#define DDRSS0_PI_147_DATA 0x01030001 +#define DDRSS0_PI_148_DATA 0x00010400 +#define DDRSS0_PI_149_DATA 0x06000105 +#define DDRSS0_PI_150_DATA 0x01070001 +#define DDRSS0_PI_151_DATA 0x00000000 +#define DDRSS0_PI_152_DATA 0x00000000 +#define DDRSS0_PI_153_DATA 0x00000000 +#define DDRSS0_PI_154_DATA 0x00010001 +#define DDRSS0_PI_155_DATA 0x00000000 +#define DDRSS0_PI_156_DATA 0x00000000 +#define DDRSS0_PI_157_DATA 0x00000000 +#define DDRSS0_PI_158_DATA 0x00000000 +#define DDRSS0_PI_159_DATA 0x00000401 +#define DDRSS0_PI_160_DATA 0x00000000 +#define DDRSS0_PI_161_DATA 0x00010000 +#define DDRSS0_PI_162_DATA 0x00000000 +#define DDRSS0_PI_163_DATA 0x2B2B0200 +#define DDRSS0_PI_164_DATA 0x00000034 +#define DDRSS0_PI_165_DATA 0x00000064 +#define DDRSS0_PI_166_DATA 0x00020064 +#define DDRSS0_PI_167_DATA 0x02000200 +#define DDRSS0_PI_168_DATA 0x48120C04 +#define DDRSS0_PI_169_DATA 0x00154812 +#define DDRSS0_PI_170_DATA 0x00000063 +#define DDRSS0_PI_171_DATA 0x0000032B +#define DDRSS0_PI_172_DATA 0x00001035 +#define DDRSS0_PI_173_DATA 0x0000032B +#define DDRSS0_PI_174_DATA 0x04001035 +#define DDRSS0_PI_175_DATA 0x01010404 +#define DDRSS0_PI_176_DATA 0x00001501 +#define DDRSS0_PI_177_DATA 0x00150015 +#define DDRSS0_PI_178_DATA 0x01000100 +#define DDRSS0_PI_179_DATA 0x00000100 +#define DDRSS0_PI_180_DATA 0x00000000 +#define DDRSS0_PI_181_DATA 0x01010101 +#define DDRSS0_PI_182_DATA 0x00000101 +#define DDRSS0_PI_183_DATA 0x00000000 +#define DDRSS0_PI_184_DATA 0x00000000 +#define DDRSS0_PI_185_DATA 0x15040000 +#define DDRSS0_PI_186_DATA 0x0E0E0215 +#define DDRSS0_PI_187_DATA 0x00040402 +#define DDRSS0_PI_188_DATA 0x000D0035 +#define DDRSS0_PI_189_DATA 0x00218049 +#define DDRSS0_PI_190_DATA 0x00218049 +#define DDRSS0_PI_191_DATA 0x01010101 +#define DDRSS0_PI_192_DATA 0x0004000E +#define DDRSS0_PI_193_DATA 0x00040216 +#define DDRSS0_PI_194_DATA 0x01000216 +#define DDRSS0_PI_195_DATA 0x000F000F +#define DDRSS0_PI_196_DATA 0x02170100 +#define DDRSS0_PI_197_DATA 0x01000217 +#define DDRSS0_PI_198_DATA 0x02170217 +#define DDRSS0_PI_199_DATA 0x32103200 +#define DDRSS0_PI_200_DATA 0x01013210 +#define DDRSS0_PI_201_DATA 0x0A070601 +#define DDRSS0_PI_202_DATA 0x1F130A0D +#define DDRSS0_PI_203_DATA 0x1F130A14 +#define DDRSS0_PI_204_DATA 0x0000C014 +#define DDRSS0_PI_205_DATA 0x00C01000 +#define DDRSS0_PI_206_DATA 0x00C01000 +#define DDRSS0_PI_207_DATA 0x00021000 +#define DDRSS0_PI_208_DATA 0x0024000E +#define DDRSS0_PI_209_DATA 0x00240216 +#define DDRSS0_PI_210_DATA 0x00110216 +#define DDRSS0_PI_211_DATA 0x32000056 +#define DDRSS0_PI_212_DATA 0x00000301 +#define DDRSS0_PI_213_DATA 0x005B0036 +#define DDRSS0_PI_214_DATA 0x03013212 +#define DDRSS0_PI_215_DATA 0x00003600 +#define DDRSS0_PI_216_DATA 0x3212005B +#define DDRSS0_PI_217_DATA 0x09000301 +#define DDRSS0_PI_218_DATA 0x04010504 +#define DDRSS0_PI_219_DATA 0x04000364 +#define DDRSS0_PI_220_DATA 0x0A032001 +#define DDRSS0_PI_221_DATA 0x2C31110A +#define DDRSS0_PI_222_DATA 0x00002918 +#define DDRSS0_PI_223_DATA 0x6000838E +#define DDRSS0_PI_224_DATA 0x1E202008 +#define DDRSS0_PI_225_DATA 0x2C311116 +#define DDRSS0_PI_226_DATA 0x00002918 +#define DDRSS0_PI_227_DATA 0x6000838E +#define DDRSS0_PI_228_DATA 0x1E202008 +#define DDRSS0_PI_229_DATA 0x0000C616 +#define DDRSS0_PI_230_DATA 0x000007BC +#define DDRSS0_PI_231_DATA 0x0000206A +#define DDRSS0_PI_232_DATA 0x00014424 +#define DDRSS0_PI_233_DATA 0x0000206A +#define DDRSS0_PI_234_DATA 0x00014424 +#define DDRSS0_PI_235_DATA 0x033B0016 +#define DDRSS0_PI_236_DATA 0x0303033B +#define DDRSS0_PI_237_DATA 0x002AF803 +#define DDRSS0_PI_238_DATA 0x0001ADAF +#define DDRSS0_PI_239_DATA 0x00000005 +#define DDRSS0_PI_240_DATA 0x0000006E +#define DDRSS0_PI_241_DATA 0x00000016 +#define DDRSS0_PI_242_DATA 0x000681C8 +#define DDRSS0_PI_243_DATA 0x0001ADAF +#define DDRSS0_PI_244_DATA 0x00000005 +#define DDRSS0_PI_245_DATA 0x000010A9 +#define DDRSS0_PI_246_DATA 0x0000033B +#define DDRSS0_PI_247_DATA 0x000681C8 +#define DDRSS0_PI_248_DATA 0x0001ADAF +#define DDRSS0_PI_249_DATA 0x00000005 +#define DDRSS0_PI_250_DATA 0x000010A9 +#define DDRSS0_PI_251_DATA 0x0100033B +#define DDRSS0_PI_252_DATA 0x00370040 +#define DDRSS0_PI_253_DATA 0x00010008 +#define DDRSS0_PI_254_DATA 0x08550040 +#define DDRSS0_PI_255_DATA 0x00010040 +#define DDRSS0_PI_256_DATA 0x08550040 +#define DDRSS0_PI_257_DATA 0x00000340 +#define DDRSS0_PI_258_DATA 0x006B006B +#define DDRSS0_PI_259_DATA 0x08040404 +#define DDRSS0_PI_260_DATA 0x00000055 +#define DDRSS0_PI_261_DATA 0x55083C5A +#define DDRSS0_PI_262_DATA 0x5A000000 +#define DDRSS0_PI_263_DATA 0x0055083C +#define DDRSS0_PI_264_DATA 0x3C5A0000 +#define DDRSS0_PI_265_DATA 0x00005508 +#define DDRSS0_PI_266_DATA 0x0C3C5A00 +#define DDRSS0_PI_267_DATA 0x080F0E0D +#define DDRSS0_PI_268_DATA 0x000B0A09 +#define DDRSS0_PI_269_DATA 0x00030201 +#define DDRSS0_PI_270_DATA 0x01000000 +#define DDRSS0_PI_271_DATA 0x04020201 +#define DDRSS0_PI_272_DATA 0x00080804 +#define DDRSS0_PI_273_DATA 0x00000000 +#define DDRSS0_PI_274_DATA 0x00000000 +#define DDRSS0_PI_275_DATA 0x00330084 +#define DDRSS0_PI_276_DATA 0x00160000 +#define DDRSS0_PI_277_DATA 0x35333FF4 +#define DDRSS0_PI_278_DATA 0x00160F27 +#define DDRSS0_PI_279_DATA 0x35333FF4 +#define DDRSS0_PI_280_DATA 0x00160F27 +#define DDRSS0_PI_281_DATA 0x00330084 +#define DDRSS0_PI_282_DATA 0x00160000 +#define DDRSS0_PI_283_DATA 0x35333FF4 +#define DDRSS0_PI_284_DATA 0x00160F27 +#define DDRSS0_PI_285_DATA 0x35333FF4 +#define DDRSS0_PI_286_DATA 0x00160F27 +#define DDRSS0_PI_287_DATA 0x00330084 +#define DDRSS0_PI_288_DATA 0x00160000 +#define DDRSS0_PI_289_DATA 0x35333FF4 +#define DDRSS0_PI_290_DATA 0x00160F27 +#define DDRSS0_PI_291_DATA 0x35333FF4 +#define DDRSS0_PI_292_DATA 0x00160F27 +#define DDRSS0_PI_293_DATA 0x00330084 +#define DDRSS0_PI_294_DATA 0x00160000 +#define DDRSS0_PI_295_DATA 0x35333FF4 +#define DDRSS0_PI_296_DATA 0x00160F27 +#define DDRSS0_PI_297_DATA 0x35333FF4 +#define DDRSS0_PI_298_DATA 0x00160F27 +#define DDRSS0_PI_299_DATA 0x00000000 + +#define DDRSS0_PHY_00_DATA 0x000004F0 +#define DDRSS0_PHY_01_DATA 0x00000000 +#define DDRSS0_PHY_02_DATA 0x00030200 +#define DDRSS0_PHY_03_DATA 0x00000000 +#define DDRSS0_PHY_04_DATA 0x00000000 +#define DDRSS0_PHY_05_DATA 0x01030000 +#define DDRSS0_PHY_06_DATA 0x00010000 +#define DDRSS0_PHY_07_DATA 0x01030004 +#define DDRSS0_PHY_08_DATA 0x01000000 +#define DDRSS0_PHY_09_DATA 0x00000000 +#define DDRSS0_PHY_10_DATA 0x00000000 +#define DDRSS0_PHY_11_DATA 0x01000001 +#define DDRSS0_PHY_12_DATA 0x00000100 +#define DDRSS0_PHY_13_DATA 0x000800C0 +#define DDRSS0_PHY_14_DATA 0x060100CC +#define DDRSS0_PHY_15_DATA 0x00030066 +#define DDRSS0_PHY_16_DATA 0x00000000 +#define DDRSS0_PHY_17_DATA 0x00000301 +#define DDRSS0_PHY_18_DATA 0x0000AAAA +#define DDRSS0_PHY_19_DATA 0x00005555 +#define DDRSS0_PHY_20_DATA 0x0000B5B5 +#define DDRSS0_PHY_21_DATA 0x00004A4A +#define DDRSS0_PHY_22_DATA 0x00005656 +#define DDRSS0_PHY_23_DATA 0x0000A9A9 +#define DDRSS0_PHY_24_DATA 0x0000A9A9 +#define DDRSS0_PHY_25_DATA 0x0000B5B5 +#define DDRSS0_PHY_26_DATA 0x00000000 +#define DDRSS0_PHY_27_DATA 0x00000000 +#define DDRSS0_PHY_28_DATA 0x2A000000 +#define DDRSS0_PHY_29_DATA 0x00000808 +#define DDRSS0_PHY_30_DATA 0x0F000000 +#define DDRSS0_PHY_31_DATA 0x00000F0F +#define DDRSS0_PHY_32_DATA 0x10400000 +#define DDRSS0_PHY_33_DATA 0x0C002006 +#define DDRSS0_PHY_34_DATA 0x00000000 +#define DDRSS0_PHY_35_DATA 0x00000000 +#define DDRSS0_PHY_36_DATA 0x55555555 +#define DDRSS0_PHY_37_DATA 0xAAAAAAAA +#define DDRSS0_PHY_38_DATA 0x55555555 +#define DDRSS0_PHY_39_DATA 0xAAAAAAAA +#define DDRSS0_PHY_40_DATA 0x00005555 +#define DDRSS0_PHY_41_DATA 0x01000100 +#define DDRSS0_PHY_42_DATA 0x00800180 +#define DDRSS0_PHY_43_DATA 0x00000001 +#define DDRSS0_PHY_44_DATA 0x00000000 +#define DDRSS0_PHY_45_DATA 0x00000000 +#define DDRSS0_PHY_46_DATA 0x00000000 +#define DDRSS0_PHY_47_DATA 0x00000000 +#define DDRSS0_PHY_48_DATA 0x00000000 +#define DDRSS0_PHY_49_DATA 0x00000000 +#define DDRSS0_PHY_50_DATA 0x00000000 +#define DDRSS0_PHY_51_DATA 0x00000000 +#define DDRSS0_PHY_52_DATA 0x00000000 +#define DDRSS0_PHY_53_DATA 0x00000000 +#define DDRSS0_PHY_54_DATA 0x00000000 +#define DDRSS0_PHY_55_DATA 0x00000000 +#define DDRSS0_PHY_56_DATA 0x00000000 +#define DDRSS0_PHY_57_DATA 0x00000000 +#define DDRSS0_PHY_58_DATA 0x00000000 +#define DDRSS0_PHY_59_DATA 0x00000000 +#define DDRSS0_PHY_60_DATA 0x00000000 +#define DDRSS0_PHY_61_DATA 0x00000000 +#define DDRSS0_PHY_62_DATA 0x00000000 +#define DDRSS0_PHY_63_DATA 0x00000000 +#define DDRSS0_PHY_64_DATA 0x00000000 +#define DDRSS0_PHY_65_DATA 0x00000000 +#define DDRSS0_PHY_66_DATA 0x00000104 +#define DDRSS0_PHY_67_DATA 0x00000120 +#define DDRSS0_PHY_68_DATA 0x00000000 +#define DDRSS0_PHY_69_DATA 0x00000000 +#define DDRSS0_PHY_70_DATA 0x00000000 +#define DDRSS0_PHY_71_DATA 0x00000000 +#define DDRSS0_PHY_72_DATA 0x00000000 +#define DDRSS0_PHY_73_DATA 0x00000000 +#define DDRSS0_PHY_74_DATA 0x00000000 +#define DDRSS0_PHY_75_DATA 0x00000001 +#define DDRSS0_PHY_76_DATA 0x07FF0000 +#define DDRSS0_PHY_77_DATA 0x0080081F +#define DDRSS0_PHY_78_DATA 0x00081020 +#define DDRSS0_PHY_79_DATA 0x04010000 +#define DDRSS0_PHY_80_DATA 0x00000000 +#define DDRSS0_PHY_81_DATA 0x00000000 +#define DDRSS0_PHY_82_DATA 0x00000000 +#define DDRSS0_PHY_83_DATA 0x00000100 +#define DDRSS0_PHY_84_DATA 0x01CC0C01 +#define DDRSS0_PHY_85_DATA 0x1003CC0C +#define DDRSS0_PHY_86_DATA 0x20000140 +#define DDRSS0_PHY_87_DATA 0x07FF0200 +#define DDRSS0_PHY_88_DATA 0x0000DD01 +#define DDRSS0_PHY_89_DATA 0x10100303 +#define DDRSS0_PHY_90_DATA 0x10101010 +#define DDRSS0_PHY_91_DATA 0x10101010 +#define DDRSS0_PHY_92_DATA 0x00021010 +#define DDRSS0_PHY_93_DATA 0x00100010 +#define DDRSS0_PHY_94_DATA 0x00100010 +#define DDRSS0_PHY_95_DATA 0x00100010 +#define DDRSS0_PHY_96_DATA 0x00100010 +#define DDRSS0_PHY_97_DATA 0x00050010 +#define DDRSS0_PHY_98_DATA 0x51517041 +#define DDRSS0_PHY_99_DATA 0x31C06001 +#define DDRSS0_PHY_100_DATA 0x07AB0340 +#define DDRSS0_PHY_101_DATA 0x00C0C001 +#define DDRSS0_PHY_102_DATA 0x0E0D0001 +#define DDRSS0_PHY_103_DATA 0x10001000 +#define DDRSS0_PHY_104_DATA 0x0C083E42 +#define DDRSS0_PHY_105_DATA 0x0F0C3701 +#define DDRSS0_PHY_106_DATA 0x01000140 +#define DDRSS0_PHY_107_DATA 0x0C000420 +#define DDRSS0_PHY_108_DATA 0x00000198 +#define DDRSS0_PHY_109_DATA 0x0A0000D0 +#define DDRSS0_PHY_110_DATA 0x00030200 +#define DDRSS0_PHY_111_DATA 0x02800000 +#define DDRSS0_PHY_112_DATA 0x80800000 +#define DDRSS0_PHY_113_DATA 0x000E2010 +#define DDRSS0_PHY_114_DATA 0x76543210 +#define DDRSS0_PHY_115_DATA 0x00000008 +#define DDRSS0_PHY_116_DATA 0x02800280 +#define DDRSS0_PHY_117_DATA 0x02800280 +#define DDRSS0_PHY_118_DATA 0x02800280 +#define DDRSS0_PHY_119_DATA 0x02800280 +#define DDRSS0_PHY_120_DATA 0x00000280 +#define DDRSS0_PHY_121_DATA 0x0000A000 +#define DDRSS0_PHY_122_DATA 0x00A000A0 +#define DDRSS0_PHY_123_DATA 0x00A000A0 +#define DDRSS0_PHY_124_DATA 0x00A000A0 +#define DDRSS0_PHY_125_DATA 0x00A000A0 +#define DDRSS0_PHY_126_DATA 0x00A000A0 +#define DDRSS0_PHY_127_DATA 0x00A000A0 +#define DDRSS0_PHY_128_DATA 0x00A000A0 +#define DDRSS0_PHY_129_DATA 0x00A000A0 +#define DDRSS0_PHY_130_DATA 0x01C200A0 +#define DDRSS0_PHY_131_DATA 0x01A00005 +#define DDRSS0_PHY_132_DATA 0x00000000 +#define DDRSS0_PHY_133_DATA 0x00000000 +#define DDRSS0_PHY_134_DATA 0x00080200 +#define DDRSS0_PHY_135_DATA 0x00000000 +#define DDRSS0_PHY_136_DATA 0x20202000 +#define DDRSS0_PHY_137_DATA 0x20202020 +#define DDRSS0_PHY_138_DATA 0xF0F02020 +#define DDRSS0_PHY_139_DATA 0x00000000 +#define DDRSS0_PHY_140_DATA 0x00000000 +#define DDRSS0_PHY_141_DATA 0x00000000 +#define DDRSS0_PHY_142_DATA 0x00000000 +#define DDRSS0_PHY_143_DATA 0x00000000 +#define DDRSS0_PHY_144_DATA 0x00000000 +#define DDRSS0_PHY_145_DATA 0x00000000 +#define DDRSS0_PHY_146_DATA 0x00000000 +#define DDRSS0_PHY_147_DATA 0x00000000 +#define DDRSS0_PHY_148_DATA 0x00000000 +#define DDRSS0_PHY_149_DATA 0x00000000 +#define DDRSS0_PHY_150_DATA 0x00000000 +#define DDRSS0_PHY_151_DATA 0x00000000 +#define DDRSS0_PHY_152_DATA 0x00000000 +#define DDRSS0_PHY_153_DATA 0x00000000 +#define DDRSS0_PHY_154_DATA 0x00000000 +#define DDRSS0_PHY_155_DATA 0x00000000 +#define DDRSS0_PHY_156_DATA 0x00000000 +#define DDRSS0_PHY_157_DATA 0x00000000 +#define DDRSS0_PHY_158_DATA 0x00000000 +#define DDRSS0_PHY_159_DATA 0x00000000 +#define DDRSS0_PHY_160_DATA 0x00000000 +#define DDRSS0_PHY_161_DATA 0x00000000 +#define DDRSS0_PHY_162_DATA 0x00000000 +#define DDRSS0_PHY_163_DATA 0x00000000 +#define DDRSS0_PHY_164_DATA 0x00000000 +#define DDRSS0_PHY_165_DATA 0x00000000 +#define DDRSS0_PHY_166_DATA 0x00000000 +#define DDRSS0_PHY_167_DATA 0x00000000 +#define DDRSS0_PHY_168_DATA 0x00000000 +#define DDRSS0_PHY_169_DATA 0x00000000 +#define DDRSS0_PHY_170_DATA 0x00000000 +#define DDRSS0_PHY_171_DATA 0x00000000 +#define DDRSS0_PHY_172_DATA 0x00000000 +#define DDRSS0_PHY_173_DATA 0x00000000 +#define DDRSS0_PHY_174_DATA 0x00000000 +#define DDRSS0_PHY_175_DATA 0x00000000 +#define DDRSS0_PHY_176_DATA 0x00000000 +#define DDRSS0_PHY_177_DATA 0x00000000 +#define DDRSS0_PHY_178_DATA 0x00000000 +#define DDRSS0_PHY_179_DATA 0x00000000 +#define DDRSS0_PHY_180_DATA 0x00000000 +#define DDRSS0_PHY_181_DATA 0x00000000 +#define DDRSS0_PHY_182_DATA 0x00000000 +#define DDRSS0_PHY_183_DATA 0x00000000 +#define DDRSS0_PHY_184_DATA 0x00000000 +#define DDRSS0_PHY_185_DATA 0x00000000 +#define DDRSS0_PHY_186_DATA 0x00000000 +#define DDRSS0_PHY_187_DATA 0x00000000 +#define DDRSS0_PHY_188_DATA 0x00000000 +#define DDRSS0_PHY_189_DATA 0x00000000 +#define DDRSS0_PHY_190_DATA 0x00000000 +#define DDRSS0_PHY_191_DATA 0x00000000 +#define DDRSS0_PHY_192_DATA 0x00000000 +#define DDRSS0_PHY_193_DATA 0x00000000 +#define DDRSS0_PHY_194_DATA 0x00000000 +#define DDRSS0_PHY_195_DATA 0x00000000 +#define DDRSS0_PHY_196_DATA 0x00000000 +#define DDRSS0_PHY_197_DATA 0x00000000 +#define DDRSS0_PHY_198_DATA 0x00000000 +#define DDRSS0_PHY_199_DATA 0x00000000 +#define DDRSS0_PHY_200_DATA 0x00000000 +#define DDRSS0_PHY_201_DATA 0x00000000 +#define DDRSS0_PHY_202_DATA 0x00000000 +#define DDRSS0_PHY_203_DATA 0x00000000 +#define DDRSS0_PHY_204_DATA 0x00000000 +#define DDRSS0_PHY_205_DATA 0x00000000 +#define DDRSS0_PHY_206_DATA 0x00000000 +#define DDRSS0_PHY_207_DATA 0x00000000 +#define DDRSS0_PHY_208_DATA 0x00000000 +#define DDRSS0_PHY_209_DATA 0x00000000 +#define DDRSS0_PHY_210_DATA 0x00000000 +#define DDRSS0_PHY_211_DATA 0x00000000 +#define DDRSS0_PHY_212_DATA 0x00000000 +#define DDRSS0_PHY_213_DATA 0x00000000 +#define DDRSS0_PHY_214_DATA 0x00000000 +#define DDRSS0_PHY_215_DATA 0x00000000 +#define DDRSS0_PHY_216_DATA 0x00000000 +#define DDRSS0_PHY_217_DATA 0x00000000 +#define DDRSS0_PHY_218_DATA 0x00000000 +#define DDRSS0_PHY_219_DATA 0x00000000 +#define DDRSS0_PHY_220_DATA 0x00000000 +#define DDRSS0_PHY_221_DATA 0x00000000 +#define DDRSS0_PHY_222_DATA 0x00000000 +#define DDRSS0_PHY_223_DATA 0x00000000 +#define DDRSS0_PHY_224_DATA 0x00000000 +#define DDRSS0_PHY_225_DATA 0x00000000 +#define DDRSS0_PHY_226_DATA 0x00000000 +#define DDRSS0_PHY_227_DATA 0x00000000 +#define DDRSS0_PHY_228_DATA 0x00000000 +#define DDRSS0_PHY_229_DATA 0x00000000 +#define DDRSS0_PHY_230_DATA 0x00000000 +#define DDRSS0_PHY_231_DATA 0x00000000 +#define DDRSS0_PHY_232_DATA 0x00000000 +#define DDRSS0_PHY_233_DATA 0x00000000 +#define DDRSS0_PHY_234_DATA 0x00000000 +#define DDRSS0_PHY_235_DATA 0x00000000 +#define DDRSS0_PHY_236_DATA 0x00000000 +#define DDRSS0_PHY_237_DATA 0x00000000 +#define DDRSS0_PHY_238_DATA 0x00000000 +#define DDRSS0_PHY_239_DATA 0x00000000 +#define DDRSS0_PHY_240_DATA 0x00000000 +#define DDRSS0_PHY_241_DATA 0x00000000 +#define DDRSS0_PHY_242_DATA 0x00000000 +#define DDRSS0_PHY_243_DATA 0x00000000 +#define DDRSS0_PHY_244_DATA 0x00000000 +#define DDRSS0_PHY_245_DATA 0x00000000 +#define DDRSS0_PHY_246_DATA 0x00000000 +#define DDRSS0_PHY_247_DATA 0x00000000 +#define DDRSS0_PHY_248_DATA 0x00000000 +#define DDRSS0_PHY_249_DATA 0x00000000 +#define DDRSS0_PHY_250_DATA 0x00000000 +#define DDRSS0_PHY_251_DATA 0x00000000 +#define DDRSS0_PHY_252_DATA 0x00000000 +#define DDRSS0_PHY_253_DATA 0x00000000 +#define DDRSS0_PHY_254_DATA 0x00000000 +#define DDRSS0_PHY_255_DATA 0x00000000 +#define DDRSS0_PHY_256_DATA 0x000004F0 +#define DDRSS0_PHY_257_DATA 0x00000000 +#define DDRSS0_PHY_258_DATA 0x00030200 +#define DDRSS0_PHY_259_DATA 0x00000000 +#define DDRSS0_PHY_260_DATA 0x00000000 +#define DDRSS0_PHY_261_DATA 0x01030000 +#define DDRSS0_PHY_262_DATA 0x00010000 +#define DDRSS0_PHY_263_DATA 0x01030004 +#define DDRSS0_PHY_264_DATA 0x01000000 +#define DDRSS0_PHY_265_DATA 0x00000000 +#define DDRSS0_PHY_266_DATA 0x00000000 +#define DDRSS0_PHY_267_DATA 0x01000001 +#define DDRSS0_PHY_268_DATA 0x00000100 +#define DDRSS0_PHY_269_DATA 0x000800C0 +#define DDRSS0_PHY_270_DATA 0x060100CC +#define DDRSS0_PHY_271_DATA 0x00030066 +#define DDRSS0_PHY_272_DATA 0x00000000 +#define DDRSS0_PHY_273_DATA 0x00000301 +#define DDRSS0_PHY_274_DATA 0x0000AAAA +#define DDRSS0_PHY_275_DATA 0x00005555 +#define DDRSS0_PHY_276_DATA 0x0000B5B5 +#define DDRSS0_PHY_277_DATA 0x00004A4A +#define DDRSS0_PHY_278_DATA 0x00005656 +#define DDRSS0_PHY_279_DATA 0x0000A9A9 +#define DDRSS0_PHY_280_DATA 0x0000A9A9 +#define DDRSS0_PHY_281_DATA 0x0000B5B5 +#define DDRSS0_PHY_282_DATA 0x00000000 +#define DDRSS0_PHY_283_DATA 0x00000000 +#define DDRSS0_PHY_284_DATA 0x2A000000 +#define DDRSS0_PHY_285_DATA 0x00000808 +#define DDRSS0_PHY_286_DATA 0x0F000000 +#define DDRSS0_PHY_287_DATA 0x00000F0F +#define DDRSS0_PHY_288_DATA 0x10400000 +#define DDRSS0_PHY_289_DATA 0x0C002006 +#define DDRSS0_PHY_290_DATA 0x00000000 +#define DDRSS0_PHY_291_DATA 0x00000000 +#define DDRSS0_PHY_292_DATA 0x55555555 +#define DDRSS0_PHY_293_DATA 0xAAAAAAAA +#define DDRSS0_PHY_294_DATA 0x55555555 +#define DDRSS0_PHY_295_DATA 0xAAAAAAAA +#define DDRSS0_PHY_296_DATA 0x00005555 +#define DDRSS0_PHY_297_DATA 0x01000100 +#define DDRSS0_PHY_298_DATA 0x00800180 +#define DDRSS0_PHY_299_DATA 0x00000000 +#define DDRSS0_PHY_300_DATA 0x00000000 +#define DDRSS0_PHY_301_DATA 0x00000000 +#define DDRSS0_PHY_302_DATA 0x00000000 +#define DDRSS0_PHY_303_DATA 0x00000000 +#define DDRSS0_PHY_304_DATA 0x00000000 +#define DDRSS0_PHY_305_DATA 0x00000000 +#define DDRSS0_PHY_306_DATA 0x00000000 +#define DDRSS0_PHY_307_DATA 0x00000000 +#define DDRSS0_PHY_308_DATA 0x00000000 +#define DDRSS0_PHY_309_DATA 0x00000000 +#define DDRSS0_PHY_310_DATA 0x00000000 +#define DDRSS0_PHY_311_DATA 0x00000000 +#define DDRSS0_PHY_312_DATA 0x00000000 +#define DDRSS0_PHY_313_DATA 0x00000000 +#define DDRSS0_PHY_314_DATA 0x00000000 +#define DDRSS0_PHY_315_DATA 0x00000000 +#define DDRSS0_PHY_316_DATA 0x00000000 +#define DDRSS0_PHY_317_DATA 0x00000000 +#define DDRSS0_PHY_318_DATA 0x00000000 +#define DDRSS0_PHY_319_DATA 0x00000000 +#define DDRSS0_PHY_320_DATA 0x00000000 +#define DDRSS0_PHY_321_DATA 0x00000000 +#define DDRSS0_PHY_322_DATA 0x00000104 +#define DDRSS0_PHY_323_DATA 0x00000120 +#define DDRSS0_PHY_324_DATA 0x00000000 +#define DDRSS0_PHY_325_DATA 0x00000000 +#define DDRSS0_PHY_326_DATA 0x00000000 +#define DDRSS0_PHY_327_DATA 0x00000000 +#define DDRSS0_PHY_328_DATA 0x00000000 +#define DDRSS0_PHY_329_DATA 0x00000000 +#define DDRSS0_PHY_330_DATA 0x00000000 +#define DDRSS0_PHY_331_DATA 0x00000001 +#define DDRSS0_PHY_332_DATA 0x07FF0000 +#define DDRSS0_PHY_333_DATA 0x0080081F +#define DDRSS0_PHY_334_DATA 0x00081020 +#define DDRSS0_PHY_335_DATA 0x04010000 +#define DDRSS0_PHY_336_DATA 0x00000000 +#define DDRSS0_PHY_337_DATA 0x00000000 +#define DDRSS0_PHY_338_DATA 0x00000000 +#define DDRSS0_PHY_339_DATA 0x00000100 +#define DDRSS0_PHY_340_DATA 0x01CC0C01 +#define DDRSS0_PHY_341_DATA 0x1003CC0C +#define DDRSS0_PHY_342_DATA 0x20000140 +#define DDRSS0_PHY_343_DATA 0x07FF0200 +#define DDRSS0_PHY_344_DATA 0x0000DD01 +#define DDRSS0_PHY_345_DATA 0x10100303 +#define DDRSS0_PHY_346_DATA 0x10101010 +#define DDRSS0_PHY_347_DATA 0x10101010 +#define DDRSS0_PHY_348_DATA 0x00021010 +#define DDRSS0_PHY_349_DATA 0x00100010 +#define DDRSS0_PHY_350_DATA 0x00100010 +#define DDRSS0_PHY_351_DATA 0x00100010 +#define DDRSS0_PHY_352_DATA 0x00100010 +#define DDRSS0_PHY_353_DATA 0x00050010 +#define DDRSS0_PHY_354_DATA 0x51517041 +#define DDRSS0_PHY_355_DATA 0x31C06001 +#define DDRSS0_PHY_356_DATA 0x07AB0340 +#define DDRSS0_PHY_357_DATA 0x00C0C001 +#define DDRSS0_PHY_358_DATA 0x0E0D0001 +#define DDRSS0_PHY_359_DATA 0x10001000 +#define DDRSS0_PHY_360_DATA 0x0C083E42 +#define DDRSS0_PHY_361_DATA 0x0F0C3701 +#define DDRSS0_PHY_362_DATA 0x01000140 +#define DDRSS0_PHY_363_DATA 0x0C000420 +#define DDRSS0_PHY_364_DATA 0x00000198 +#define DDRSS0_PHY_365_DATA 0x0A0000D0 +#define DDRSS0_PHY_366_DATA 0x00030200 +#define DDRSS0_PHY_367_DATA 0x02800000 +#define DDRSS0_PHY_368_DATA 0x80800000 +#define DDRSS0_PHY_369_DATA 0x000E2010 +#define DDRSS0_PHY_370_DATA 0x76543210 +#define DDRSS0_PHY_371_DATA 0x00000008 +#define DDRSS0_PHY_372_DATA 0x02800280 +#define DDRSS0_PHY_373_DATA 0x02800280 +#define DDRSS0_PHY_374_DATA 0x02800280 +#define DDRSS0_PHY_375_DATA 0x02800280 +#define DDRSS0_PHY_376_DATA 0x00000280 +#define DDRSS0_PHY_377_DATA 0x0000A000 +#define DDRSS0_PHY_378_DATA 0x00A000A0 +#define DDRSS0_PHY_379_DATA 0x00A000A0 +#define DDRSS0_PHY_380_DATA 0x00A000A0 +#define DDRSS0_PHY_381_DATA 0x00A000A0 +#define DDRSS0_PHY_382_DATA 0x00A000A0 +#define DDRSS0_PHY_383_DATA 0x00A000A0 +#define DDRSS0_PHY_384_DATA 0x00A000A0 +#define DDRSS0_PHY_385_DATA 0x00A000A0 +#define DDRSS0_PHY_386_DATA 0x01C200A0 +#define DDRSS0_PHY_387_DATA 0x01A00005 +#define DDRSS0_PHY_388_DATA 0x00000000 +#define DDRSS0_PHY_389_DATA 0x00000000 +#define DDRSS0_PHY_390_DATA 0x00080200 +#define DDRSS0_PHY_391_DATA 0x00000000 +#define DDRSS0_PHY_392_DATA 0x20202000 +#define DDRSS0_PHY_393_DATA 0x20202020 +#define DDRSS0_PHY_394_DATA 0xF0F02020 +#define DDRSS0_PHY_395_DATA 0x00000000 +#define DDRSS0_PHY_396_DATA 0x00000000 +#define DDRSS0_PHY_397_DATA 0x00000000 +#define DDRSS0_PHY_398_DATA 0x00000000 +#define DDRSS0_PHY_399_DATA 0x00000000 +#define DDRSS0_PHY_400_DATA 0x00000000 +#define DDRSS0_PHY_401_DATA 0x00000000 +#define DDRSS0_PHY_402_DATA 0x00000000 +#define DDRSS0_PHY_403_DATA 0x00000000 +#define DDRSS0_PHY_404_DATA 0x00000000 +#define DDRSS0_PHY_405_DATA 0x00000000 +#define DDRSS0_PHY_406_DATA 0x00000000 +#define DDRSS0_PHY_407_DATA 0x00000000 +#define DDRSS0_PHY_408_DATA 0x00000000 +#define DDRSS0_PHY_409_DATA 0x00000000 +#define DDRSS0_PHY_410_DATA 0x00000000 +#define DDRSS0_PHY_411_DATA 0x00000000 +#define DDRSS0_PHY_412_DATA 0x00000000 +#define DDRSS0_PHY_413_DATA 0x00000000 +#define DDRSS0_PHY_414_DATA 0x00000000 +#define DDRSS0_PHY_415_DATA 0x00000000 +#define DDRSS0_PHY_416_DATA 0x00000000 +#define DDRSS0_PHY_417_DATA 0x00000000 +#define DDRSS0_PHY_418_DATA 0x00000000 +#define DDRSS0_PHY_419_DATA 0x00000000 +#define DDRSS0_PHY_420_DATA 0x00000000 +#define DDRSS0_PHY_421_DATA 0x00000000 +#define DDRSS0_PHY_422_DATA 0x00000000 +#define DDRSS0_PHY_423_DATA 0x00000000 +#define DDRSS0_PHY_424_DATA 0x00000000 +#define DDRSS0_PHY_425_DATA 0x00000000 +#define DDRSS0_PHY_426_DATA 0x00000000 +#define DDRSS0_PHY_427_DATA 0x00000000 +#define DDRSS0_PHY_428_DATA 0x00000000 +#define DDRSS0_PHY_429_DATA 0x00000000 +#define DDRSS0_PHY_430_DATA 0x00000000 +#define DDRSS0_PHY_431_DATA 0x00000000 +#define DDRSS0_PHY_432_DATA 0x00000000 +#define DDRSS0_PHY_433_DATA 0x00000000 +#define DDRSS0_PHY_434_DATA 0x00000000 +#define DDRSS0_PHY_435_DATA 0x00000000 +#define DDRSS0_PHY_436_DATA 0x00000000 +#define DDRSS0_PHY_437_DATA 0x00000000 +#define DDRSS0_PHY_438_DATA 0x00000000 +#define DDRSS0_PHY_439_DATA 0x00000000 +#define DDRSS0_PHY_440_DATA 0x00000000 +#define DDRSS0_PHY_441_DATA 0x00000000 +#define DDRSS0_PHY_442_DATA 0x00000000 +#define DDRSS0_PHY_443_DATA 0x00000000 +#define DDRSS0_PHY_444_DATA 0x00000000 +#define DDRSS0_PHY_445_DATA 0x00000000 +#define DDRSS0_PHY_446_DATA 0x00000000 +#define DDRSS0_PHY_447_DATA 0x00000000 +#define DDRSS0_PHY_448_DATA 0x00000000 +#define DDRSS0_PHY_449_DATA 0x00000000 +#define DDRSS0_PHY_450_DATA 0x00000000 +#define DDRSS0_PHY_451_DATA 0x00000000 +#define DDRSS0_PHY_452_DATA 0x00000000 +#define DDRSS0_PHY_453_DATA 0x00000000 +#define DDRSS0_PHY_454_DATA 0x00000000 +#define DDRSS0_PHY_455_DATA 0x00000000 +#define DDRSS0_PHY_456_DATA 0x00000000 +#define DDRSS0_PHY_457_DATA 0x00000000 +#define DDRSS0_PHY_458_DATA 0x00000000 +#define DDRSS0_PHY_459_DATA 0x00000000 +#define DDRSS0_PHY_460_DATA 0x00000000 +#define DDRSS0_PHY_461_DATA 0x00000000 +#define DDRSS0_PHY_462_DATA 0x00000000 +#define DDRSS0_PHY_463_DATA 0x00000000 +#define DDRSS0_PHY_464_DATA 0x00000000 +#define DDRSS0_PHY_465_DATA 0x00000000 +#define DDRSS0_PHY_466_DATA 0x00000000 +#define DDRSS0_PHY_467_DATA 0x00000000 +#define DDRSS0_PHY_468_DATA 0x00000000 +#define DDRSS0_PHY_469_DATA 0x00000000 +#define DDRSS0_PHY_470_DATA 0x00000000 +#define DDRSS0_PHY_471_DATA 0x00000000 +#define DDRSS0_PHY_472_DATA 0x00000000 +#define DDRSS0_PHY_473_DATA 0x00000000 +#define DDRSS0_PHY_474_DATA 0x00000000 +#define DDRSS0_PHY_475_DATA 0x00000000 +#define DDRSS0_PHY_476_DATA 0x00000000 +#define DDRSS0_PHY_477_DATA 0x00000000 +#define DDRSS0_PHY_478_DATA 0x00000000 +#define DDRSS0_PHY_479_DATA 0x00000000 +#define DDRSS0_PHY_480_DATA 0x00000000 +#define DDRSS0_PHY_481_DATA 0x00000000 +#define DDRSS0_PHY_482_DATA 0x00000000 +#define DDRSS0_PHY_483_DATA 0x00000000 +#define DDRSS0_PHY_484_DATA 0x00000000 +#define DDRSS0_PHY_485_DATA 0x00000000 +#define DDRSS0_PHY_486_DATA 0x00000000 +#define DDRSS0_PHY_487_DATA 0x00000000 +#define DDRSS0_PHY_488_DATA 0x00000000 +#define DDRSS0_PHY_489_DATA 0x00000000 +#define DDRSS0_PHY_490_DATA 0x00000000 +#define DDRSS0_PHY_491_DATA 0x00000000 +#define DDRSS0_PHY_492_DATA 0x00000000 +#define DDRSS0_PHY_493_DATA 0x00000000 +#define DDRSS0_PHY_494_DATA 0x00000000 +#define DDRSS0_PHY_495_DATA 0x00000000 +#define DDRSS0_PHY_496_DATA 0x00000000 +#define DDRSS0_PHY_497_DATA 0x00000000 +#define DDRSS0_PHY_498_DATA 0x00000000 +#define DDRSS0_PHY_499_DATA 0x00000000 +#define DDRSS0_PHY_500_DATA 0x00000000 +#define DDRSS0_PHY_501_DATA 0x00000000 +#define DDRSS0_PHY_502_DATA 0x00000000 +#define DDRSS0_PHY_503_DATA 0x00000000 +#define DDRSS0_PHY_504_DATA 0x00000000 +#define DDRSS0_PHY_505_DATA 0x00000000 +#define DDRSS0_PHY_506_DATA 0x00000000 +#define DDRSS0_PHY_507_DATA 0x00000000 +#define DDRSS0_PHY_508_DATA 0x00000000 +#define DDRSS0_PHY_509_DATA 0x00000000 +#define DDRSS0_PHY_510_DATA 0x00000000 +#define DDRSS0_PHY_511_DATA 0x00000000 +#define DDRSS0_PHY_512_DATA 0x000004F0 +#define DDRSS0_PHY_513_DATA 0x00000000 +#define DDRSS0_PHY_514_DATA 0x00030200 +#define DDRSS0_PHY_515_DATA 0x00000000 +#define DDRSS0_PHY_516_DATA 0x00000000 +#define DDRSS0_PHY_517_DATA 0x01030000 +#define DDRSS0_PHY_518_DATA 0x00010000 +#define DDRSS0_PHY_519_DATA 0x01030004 +#define DDRSS0_PHY_520_DATA 0x01000000 +#define DDRSS0_PHY_521_DATA 0x00000000 +#define DDRSS0_PHY_522_DATA 0x00000000 +#define DDRSS0_PHY_523_DATA 0x01000001 +#define DDRSS0_PHY_524_DATA 0x00000100 +#define DDRSS0_PHY_525_DATA 0x000800C0 +#define DDRSS0_PHY_526_DATA 0x060100CC +#define DDRSS0_PHY_527_DATA 0x00030066 +#define DDRSS0_PHY_528_DATA 0x00000000 +#define DDRSS0_PHY_529_DATA 0x00000301 +#define DDRSS0_PHY_530_DATA 0x0000AAAA +#define DDRSS0_PHY_531_DATA 0x00005555 +#define DDRSS0_PHY_532_DATA 0x0000B5B5 +#define DDRSS0_PHY_533_DATA 0x00004A4A +#define DDRSS0_PHY_534_DATA 0x00005656 +#define DDRSS0_PHY_535_DATA 0x0000A9A9 +#define DDRSS0_PHY_536_DATA 0x0000A9A9 +#define DDRSS0_PHY_537_DATA 0x0000B5B5 +#define DDRSS0_PHY_538_DATA 0x00000000 +#define DDRSS0_PHY_539_DATA 0x00000000 +#define DDRSS0_PHY_540_DATA 0x2A000000 +#define DDRSS0_PHY_541_DATA 0x00000808 +#define DDRSS0_PHY_542_DATA 0x0F000000 +#define DDRSS0_PHY_543_DATA 0x00000F0F +#define DDRSS0_PHY_544_DATA 0x10400000 +#define DDRSS0_PHY_545_DATA 0x0C002006 +#define DDRSS0_PHY_546_DATA 0x00000000 +#define DDRSS0_PHY_547_DATA 0x00000000 +#define DDRSS0_PHY_548_DATA 0x55555555 +#define DDRSS0_PHY_549_DATA 0xAAAAAAAA +#define DDRSS0_PHY_550_DATA 0x55555555 +#define DDRSS0_PHY_551_DATA 0xAAAAAAAA +#define DDRSS0_PHY_552_DATA 0x00005555 +#define DDRSS0_PHY_553_DATA 0x01000100 +#define DDRSS0_PHY_554_DATA 0x00800180 +#define DDRSS0_PHY_555_DATA 0x00000001 +#define DDRSS0_PHY_556_DATA 0x00000000 +#define DDRSS0_PHY_557_DATA 0x00000000 +#define DDRSS0_PHY_558_DATA 0x00000000 +#define DDRSS0_PHY_559_DATA 0x00000000 +#define DDRSS0_PHY_560_DATA 0x00000000 +#define DDRSS0_PHY_561_DATA 0x00000000 +#define DDRSS0_PHY_562_DATA 0x00000000 +#define DDRSS0_PHY_563_DATA 0x00000000 +#define DDRSS0_PHY_564_DATA 0x00000000 +#define DDRSS0_PHY_565_DATA 0x00000000 +#define DDRSS0_PHY_566_DATA 0x00000000 +#define DDRSS0_PHY_567_DATA 0x00000000 +#define DDRSS0_PHY_568_DATA 0x00000000 +#define DDRSS0_PHY_569_DATA 0x00000000 +#define DDRSS0_PHY_570_DATA 0x00000000 +#define DDRSS0_PHY_571_DATA 0x00000000 +#define DDRSS0_PHY_572_DATA 0x00000000 +#define DDRSS0_PHY_573_DATA 0x00000000 +#define DDRSS0_PHY_574_DATA 0x00000000 +#define DDRSS0_PHY_575_DATA 0x00000000 +#define DDRSS0_PHY_576_DATA 0x00000000 +#define DDRSS0_PHY_577_DATA 0x00000000 +#define DDRSS0_PHY_578_DATA 0x00000104 +#define DDRSS0_PHY_579_DATA 0x00000120 +#define DDRSS0_PHY_580_DATA 0x00000000 +#define DDRSS0_PHY_581_DATA 0x00000000 +#define DDRSS0_PHY_582_DATA 0x00000000 +#define DDRSS0_PHY_583_DATA 0x00000000 +#define DDRSS0_PHY_584_DATA 0x00000000 +#define DDRSS0_PHY_585_DATA 0x00000000 +#define DDRSS0_PHY_586_DATA 0x00000000 +#define DDRSS0_PHY_587_DATA 0x00000001 +#define DDRSS0_PHY_588_DATA 0x07FF0000 +#define DDRSS0_PHY_589_DATA 0x0080081F +#define DDRSS0_PHY_590_DATA 0x00081020 +#define DDRSS0_PHY_591_DATA 0x04010000 +#define DDRSS0_PHY_592_DATA 0x00000000 +#define DDRSS0_PHY_593_DATA 0x00000000 +#define DDRSS0_PHY_594_DATA 0x00000000 +#define DDRSS0_PHY_595_DATA 0x00000100 +#define DDRSS0_PHY_596_DATA 0x01CC0C01 +#define DDRSS0_PHY_597_DATA 0x1003CC0C +#define DDRSS0_PHY_598_DATA 0x20000140 +#define DDRSS0_PHY_599_DATA 0x07FF0200 +#define DDRSS0_PHY_600_DATA 0x0000DD01 +#define DDRSS0_PHY_601_DATA 0x10100303 +#define DDRSS0_PHY_602_DATA 0x10101010 +#define DDRSS0_PHY_603_DATA 0x10101010 +#define DDRSS0_PHY_604_DATA 0x00021010 +#define DDRSS0_PHY_605_DATA 0x00100010 +#define DDRSS0_PHY_606_DATA 0x00100010 +#define DDRSS0_PHY_607_DATA 0x00100010 +#define DDRSS0_PHY_608_DATA 0x00100010 +#define DDRSS0_PHY_609_DATA 0x00050010 +#define DDRSS0_PHY_610_DATA 0x51517041 +#define DDRSS0_PHY_611_DATA 0x31C06001 +#define DDRSS0_PHY_612_DATA 0x07AB0340 +#define DDRSS0_PHY_613_DATA 0x00C0C001 +#define DDRSS0_PHY_614_DATA 0x0E0D0001 +#define DDRSS0_PHY_615_DATA 0x10001000 +#define DDRSS0_PHY_616_DATA 0x0C083E42 +#define DDRSS0_PHY_617_DATA 0x0F0C3701 +#define DDRSS0_PHY_618_DATA 0x01000140 +#define DDRSS0_PHY_619_DATA 0x0C000420 +#define DDRSS0_PHY_620_DATA 0x00000198 +#define DDRSS0_PHY_621_DATA 0x0A0000D0 +#define DDRSS0_PHY_622_DATA 0x00030200 +#define DDRSS0_PHY_623_DATA 0x02800000 +#define DDRSS0_PHY_624_DATA 0x80800000 +#define DDRSS0_PHY_625_DATA 0x000E2010 +#define DDRSS0_PHY_626_DATA 0x76543210 +#define DDRSS0_PHY_627_DATA 0x00000008 +#define DDRSS0_PHY_628_DATA 0x02800280 +#define DDRSS0_PHY_629_DATA 0x02800280 +#define DDRSS0_PHY_630_DATA 0x02800280 +#define DDRSS0_PHY_631_DATA 0x02800280 +#define DDRSS0_PHY_632_DATA 0x00000280 +#define DDRSS0_PHY_633_DATA 0x0000A000 +#define DDRSS0_PHY_634_DATA 0x00A000A0 +#define DDRSS0_PHY_635_DATA 0x00A000A0 +#define DDRSS0_PHY_636_DATA 0x00A000A0 +#define DDRSS0_PHY_637_DATA 0x00A000A0 +#define DDRSS0_PHY_638_DATA 0x00A000A0 +#define DDRSS0_PHY_639_DATA 0x00A000A0 +#define DDRSS0_PHY_640_DATA 0x00A000A0 +#define DDRSS0_PHY_641_DATA 0x00A000A0 +#define DDRSS0_PHY_642_DATA 0x01C200A0 +#define DDRSS0_PHY_643_DATA 0x01A00005 +#define DDRSS0_PHY_644_DATA 0x00000000 +#define DDRSS0_PHY_645_DATA 0x00000000 +#define DDRSS0_PHY_646_DATA 0x00080200 +#define DDRSS0_PHY_647_DATA 0x00000000 +#define DDRSS0_PHY_648_DATA 0x20202000 +#define DDRSS0_PHY_649_DATA 0x20202020 +#define DDRSS0_PHY_650_DATA 0xF0F02020 +#define DDRSS0_PHY_651_DATA 0x00000000 +#define DDRSS0_PHY_652_DATA 0x00000000 +#define DDRSS0_PHY_653_DATA 0x00000000 +#define DDRSS0_PHY_654_DATA 0x00000000 +#define DDRSS0_PHY_655_DATA 0x00000000 +#define DDRSS0_PHY_656_DATA 0x00000000 +#define DDRSS0_PHY_657_DATA 0x00000000 +#define DDRSS0_PHY_658_DATA 0x00000000 +#define DDRSS0_PHY_659_DATA 0x00000000 +#define DDRSS0_PHY_660_DATA 0x00000000 +#define DDRSS0_PHY_661_DATA 0x00000000 +#define DDRSS0_PHY_662_DATA 0x00000000 +#define DDRSS0_PHY_663_DATA 0x00000000 +#define DDRSS0_PHY_664_DATA 0x00000000 +#define DDRSS0_PHY_665_DATA 0x00000000 +#define DDRSS0_PHY_666_DATA 0x00000000 +#define DDRSS0_PHY_667_DATA 0x00000000 +#define DDRSS0_PHY_668_DATA 0x00000000 +#define DDRSS0_PHY_669_DATA 0x00000000 +#define DDRSS0_PHY_670_DATA 0x00000000 +#define DDRSS0_PHY_671_DATA 0x00000000 +#define DDRSS0_PHY_672_DATA 0x00000000 +#define DDRSS0_PHY_673_DATA 0x00000000 +#define DDRSS0_PHY_674_DATA 0x00000000 +#define DDRSS0_PHY_675_DATA 0x00000000 +#define DDRSS0_PHY_676_DATA 0x00000000 +#define DDRSS0_PHY_677_DATA 0x00000000 +#define DDRSS0_PHY_678_DATA 0x00000000 +#define DDRSS0_PHY_679_DATA 0x00000000 +#define DDRSS0_PHY_680_DATA 0x00000000 +#define DDRSS0_PHY_681_DATA 0x00000000 +#define DDRSS0_PHY_682_DATA 0x00000000 +#define DDRSS0_PHY_683_DATA 0x00000000 +#define DDRSS0_PHY_684_DATA 0x00000000 +#define DDRSS0_PHY_685_DATA 0x00000000 +#define DDRSS0_PHY_686_DATA 0x00000000 +#define DDRSS0_PHY_687_DATA 0x00000000 +#define DDRSS0_PHY_688_DATA 0x00000000 +#define DDRSS0_PHY_689_DATA 0x00000000 +#define DDRSS0_PHY_690_DATA 0x00000000 +#define DDRSS0_PHY_691_DATA 0x00000000 +#define DDRSS0_PHY_692_DATA 0x00000000 +#define DDRSS0_PHY_693_DATA 0x00000000 +#define DDRSS0_PHY_694_DATA 0x00000000 +#define DDRSS0_PHY_695_DATA 0x00000000 +#define DDRSS0_PHY_696_DATA 0x00000000 +#define DDRSS0_PHY_697_DATA 0x00000000 +#define DDRSS0_PHY_698_DATA 0x00000000 +#define DDRSS0_PHY_699_DATA 0x00000000 +#define DDRSS0_PHY_700_DATA 0x00000000 +#define DDRSS0_PHY_701_DATA 0x00000000 +#define DDRSS0_PHY_702_DATA 0x00000000 +#define DDRSS0_PHY_703_DATA 0x00000000 +#define DDRSS0_PHY_704_DATA 0x00000000 +#define DDRSS0_PHY_705_DATA 0x00000000 +#define DDRSS0_PHY_706_DATA 0x00000000 +#define DDRSS0_PHY_707_DATA 0x00000000 +#define DDRSS0_PHY_708_DATA 0x00000000 +#define DDRSS0_PHY_709_DATA 0x00000000 +#define DDRSS0_PHY_710_DATA 0x00000000 +#define DDRSS0_PHY_711_DATA 0x00000000 +#define DDRSS0_PHY_712_DATA 0x00000000 +#define DDRSS0_PHY_713_DATA 0x00000000 +#define DDRSS0_PHY_714_DATA 0x00000000 +#define DDRSS0_PHY_715_DATA 0x00000000 +#define DDRSS0_PHY_716_DATA 0x00000000 +#define DDRSS0_PHY_717_DATA 0x00000000 +#define DDRSS0_PHY_718_DATA 0x00000000 +#define DDRSS0_PHY_719_DATA 0x00000000 +#define DDRSS0_PHY_720_DATA 0x00000000 +#define DDRSS0_PHY_721_DATA 0x00000000 +#define DDRSS0_PHY_722_DATA 0x00000000 +#define DDRSS0_PHY_723_DATA 0x00000000 +#define DDRSS0_PHY_724_DATA 0x00000000 +#define DDRSS0_PHY_725_DATA 0x00000000 +#define DDRSS0_PHY_726_DATA 0x00000000 +#define DDRSS0_PHY_727_DATA 0x00000000 +#define DDRSS0_PHY_728_DATA 0x00000000 +#define DDRSS0_PHY_729_DATA 0x00000000 +#define DDRSS0_PHY_730_DATA 0x00000000 +#define DDRSS0_PHY_731_DATA 0x00000000 +#define DDRSS0_PHY_732_DATA 0x00000000 +#define DDRSS0_PHY_733_DATA 0x00000000 +#define DDRSS0_PHY_734_DATA 0x00000000 +#define DDRSS0_PHY_735_DATA 0x00000000 +#define DDRSS0_PHY_736_DATA 0x00000000 +#define DDRSS0_PHY_737_DATA 0x00000000 +#define DDRSS0_PHY_738_DATA 0x00000000 +#define DDRSS0_PHY_739_DATA 0x00000000 +#define DDRSS0_PHY_740_DATA 0x00000000 +#define DDRSS0_PHY_741_DATA 0x00000000 +#define DDRSS0_PHY_742_DATA 0x00000000 +#define DDRSS0_PHY_743_DATA 0x00000000 +#define DDRSS0_PHY_744_DATA 0x00000000 +#define DDRSS0_PHY_745_DATA 0x00000000 +#define DDRSS0_PHY_746_DATA 0x00000000 +#define DDRSS0_PHY_747_DATA 0x00000000 +#define DDRSS0_PHY_748_DATA 0x00000000 +#define DDRSS0_PHY_749_DATA 0x00000000 +#define DDRSS0_PHY_750_DATA 0x00000000 +#define DDRSS0_PHY_751_DATA 0x00000000 +#define DDRSS0_PHY_752_DATA 0x00000000 +#define DDRSS0_PHY_753_DATA 0x00000000 +#define DDRSS0_PHY_754_DATA 0x00000000 +#define DDRSS0_PHY_755_DATA 0x00000000 +#define DDRSS0_PHY_756_DATA 0x00000000 +#define DDRSS0_PHY_757_DATA 0x00000000 +#define DDRSS0_PHY_758_DATA 0x00000000 +#define DDRSS0_PHY_759_DATA 0x00000000 +#define DDRSS0_PHY_760_DATA 0x00000000 +#define DDRSS0_PHY_761_DATA 0x00000000 +#define DDRSS0_PHY_762_DATA 0x00000000 +#define DDRSS0_PHY_763_DATA 0x00000000 +#define DDRSS0_PHY_764_DATA 0x00000000 +#define DDRSS0_PHY_765_DATA 0x00000000 +#define DDRSS0_PHY_766_DATA 0x00000000 +#define DDRSS0_PHY_767_DATA 0x00000000 +#define DDRSS0_PHY_768_DATA 0x000004F0 +#define DDRSS0_PHY_769_DATA 0x00000000 +#define DDRSS0_PHY_770_DATA 0x00030200 +#define DDRSS0_PHY_771_DATA 0x00000000 +#define DDRSS0_PHY_772_DATA 0x00000000 +#define DDRSS0_PHY_773_DATA 0x01030000 +#define DDRSS0_PHY_774_DATA 0x00010000 +#define DDRSS0_PHY_775_DATA 0x01030004 +#define DDRSS0_PHY_776_DATA 0x01000000 +#define DDRSS0_PHY_777_DATA 0x00000000 +#define DDRSS0_PHY_778_DATA 0x00000000 +#define DDRSS0_PHY_779_DATA 0x01000001 +#define DDRSS0_PHY_780_DATA 0x00000100 +#define DDRSS0_PHY_781_DATA 0x000800C0 +#define DDRSS0_PHY_782_DATA 0x060100CC +#define DDRSS0_PHY_783_DATA 0x00030066 +#define DDRSS0_PHY_784_DATA 0x00000000 +#define DDRSS0_PHY_785_DATA 0x00000301 +#define DDRSS0_PHY_786_DATA 0x0000AAAA +#define DDRSS0_PHY_787_DATA 0x00005555 +#define DDRSS0_PHY_788_DATA 0x0000B5B5 +#define DDRSS0_PHY_789_DATA 0x00004A4A +#define DDRSS0_PHY_790_DATA 0x00005656 +#define DDRSS0_PHY_791_DATA 0x0000A9A9 +#define DDRSS0_PHY_792_DATA 0x0000A9A9 +#define DDRSS0_PHY_793_DATA 0x0000B5B5 +#define DDRSS0_PHY_794_DATA 0x00000000 +#define DDRSS0_PHY_795_DATA 0x00000000 +#define DDRSS0_PHY_796_DATA 0x2A000000 +#define DDRSS0_PHY_797_DATA 0x00000808 +#define DDRSS0_PHY_798_DATA 0x0F000000 +#define DDRSS0_PHY_799_DATA 0x00000F0F +#define DDRSS0_PHY_800_DATA 0x10400000 +#define DDRSS0_PHY_801_DATA 0x0C002006 +#define DDRSS0_PHY_802_DATA 0x00000000 +#define DDRSS0_PHY_803_DATA 0x00000000 +#define DDRSS0_PHY_804_DATA 0x55555555 +#define DDRSS0_PHY_805_DATA 0xAAAAAAAA +#define DDRSS0_PHY_806_DATA 0x55555555 +#define DDRSS0_PHY_807_DATA 0xAAAAAAAA +#define DDRSS0_PHY_808_DATA 0x00005555 +#define DDRSS0_PHY_809_DATA 0x01000100 +#define DDRSS0_PHY_810_DATA 0x00800180 +#define DDRSS0_PHY_811_DATA 0x00000000 +#define DDRSS0_PHY_812_DATA 0x00000000 +#define DDRSS0_PHY_813_DATA 0x00000000 +#define DDRSS0_PHY_814_DATA 0x00000000 +#define DDRSS0_PHY_815_DATA 0x00000000 +#define DDRSS0_PHY_816_DATA 0x00000000 +#define DDRSS0_PHY_817_DATA 0x00000000 +#define DDRSS0_PHY_818_DATA 0x00000000 +#define DDRSS0_PHY_819_DATA 0x00000000 +#define DDRSS0_PHY_820_DATA 0x00000000 +#define DDRSS0_PHY_821_DATA 0x00000000 +#define DDRSS0_PHY_822_DATA 0x00000000 +#define DDRSS0_PHY_823_DATA 0x00000000 +#define DDRSS0_PHY_824_DATA 0x00000000 +#define DDRSS0_PHY_825_DATA 0x00000000 +#define DDRSS0_PHY_826_DATA 0x00000000 +#define DDRSS0_PHY_827_DATA 0x00000000 +#define DDRSS0_PHY_828_DATA 0x00000000 +#define DDRSS0_PHY_829_DATA 0x00000000 +#define DDRSS0_PHY_830_DATA 0x00000000 +#define DDRSS0_PHY_831_DATA 0x00000000 +#define DDRSS0_PHY_832_DATA 0x00000000 +#define DDRSS0_PHY_833_DATA 0x00000000 +#define DDRSS0_PHY_834_DATA 0x00000104 +#define DDRSS0_PHY_835_DATA 0x00000120 +#define DDRSS0_PHY_836_DATA 0x00000000 +#define DDRSS0_PHY_837_DATA 0x00000000 +#define DDRSS0_PHY_838_DATA 0x00000000 +#define DDRSS0_PHY_839_DATA 0x00000000 +#define DDRSS0_PHY_840_DATA 0x00000000 +#define DDRSS0_PHY_841_DATA 0x00000000 +#define DDRSS0_PHY_842_DATA 0x00000000 +#define DDRSS0_PHY_843_DATA 0x00000001 +#define DDRSS0_PHY_844_DATA 0x07FF0000 +#define DDRSS0_PHY_845_DATA 0x0080081F +#define DDRSS0_PHY_846_DATA 0x00081020 +#define DDRSS0_PHY_847_DATA 0x04010000 +#define DDRSS0_PHY_848_DATA 0x00000000 +#define DDRSS0_PHY_849_DATA 0x00000000 +#define DDRSS0_PHY_850_DATA 0x00000000 +#define DDRSS0_PHY_851_DATA 0x00000100 +#define DDRSS0_PHY_852_DATA 0x01CC0C01 +#define DDRSS0_PHY_853_DATA 0x1003CC0C +#define DDRSS0_PHY_854_DATA 0x20000140 +#define DDRSS0_PHY_855_DATA 0x07FF0200 +#define DDRSS0_PHY_856_DATA 0x0000DD01 +#define DDRSS0_PHY_857_DATA 0x10100303 +#define DDRSS0_PHY_858_DATA 0x10101010 +#define DDRSS0_PHY_859_DATA 0x10101010 +#define DDRSS0_PHY_860_DATA 0x00021010 +#define DDRSS0_PHY_861_DATA 0x00100010 +#define DDRSS0_PHY_862_DATA 0x00100010 +#define DDRSS0_PHY_863_DATA 0x00100010 +#define DDRSS0_PHY_864_DATA 0x00100010 +#define DDRSS0_PHY_865_DATA 0x00050010 +#define DDRSS0_PHY_866_DATA 0x51517041 +#define DDRSS0_PHY_867_DATA 0x31C06001 +#define DDRSS0_PHY_868_DATA 0x07AB0340 +#define DDRSS0_PHY_869_DATA 0x00C0C001 +#define DDRSS0_PHY_870_DATA 0x0E0D0001 +#define DDRSS0_PHY_871_DATA 0x10001000 +#define DDRSS0_PHY_872_DATA 0x0C083E42 +#define DDRSS0_PHY_873_DATA 0x0F0C3701 +#define DDRSS0_PHY_874_DATA 0x01000140 +#define DDRSS0_PHY_875_DATA 0x0C000420 +#define DDRSS0_PHY_876_DATA 0x00000198 +#define DDRSS0_PHY_877_DATA 0x0A0000D0 +#define DDRSS0_PHY_878_DATA 0x00030200 +#define DDRSS0_PHY_879_DATA 0x02800000 +#define DDRSS0_PHY_880_DATA 0x80800000 +#define DDRSS0_PHY_881_DATA 0x000E2010 +#define DDRSS0_PHY_882_DATA 0x76543210 +#define DDRSS0_PHY_883_DATA 0x00000008 +#define DDRSS0_PHY_884_DATA 0x02800280 +#define DDRSS0_PHY_885_DATA 0x02800280 +#define DDRSS0_PHY_886_DATA 0x02800280 +#define DDRSS0_PHY_887_DATA 0x02800280 +#define DDRSS0_PHY_888_DATA 0x00000280 +#define DDRSS0_PHY_889_DATA 0x0000A000 +#define DDRSS0_PHY_890_DATA 0x00A000A0 +#define DDRSS0_PHY_891_DATA 0x00A000A0 +#define DDRSS0_PHY_892_DATA 0x00A000A0 +#define DDRSS0_PHY_893_DATA 0x00A000A0 +#define DDRSS0_PHY_894_DATA 0x00A000A0 +#define DDRSS0_PHY_895_DATA 0x00A000A0 +#define DDRSS0_PHY_896_DATA 0x00A000A0 +#define DDRSS0_PHY_897_DATA 0x00A000A0 +#define DDRSS0_PHY_898_DATA 0x01C200A0 +#define DDRSS0_PHY_899_DATA 0x01A00005 +#define DDRSS0_PHY_900_DATA 0x00000000 +#define DDRSS0_PHY_901_DATA 0x00000000 +#define DDRSS0_PHY_902_DATA 0x00080200 +#define DDRSS0_PHY_903_DATA 0x00000000 +#define DDRSS0_PHY_904_DATA 0x20202000 +#define DDRSS0_PHY_905_DATA 0x20202020 +#define DDRSS0_PHY_906_DATA 0xF0F02020 +#define DDRSS0_PHY_907_DATA 0x00000000 +#define DDRSS0_PHY_908_DATA 0x00000000 +#define DDRSS0_PHY_909_DATA 0x00000000 +#define DDRSS0_PHY_910_DATA 0x00000000 +#define DDRSS0_PHY_911_DATA 0x00000000 +#define DDRSS0_PHY_912_DATA 0x00000000 +#define DDRSS0_PHY_913_DATA 0x00000000 +#define DDRSS0_PHY_914_DATA 0x00000000 +#define DDRSS0_PHY_915_DATA 0x00000000 +#define DDRSS0_PHY_916_DATA 0x00000000 +#define DDRSS0_PHY_917_DATA 0x00000000 +#define DDRSS0_PHY_918_DATA 0x00000000 +#define DDRSS0_PHY_919_DATA 0x00000000 +#define DDRSS0_PHY_920_DATA 0x00000000 +#define DDRSS0_PHY_921_DATA 0x00000000 +#define DDRSS0_PHY_922_DATA 0x00000000 +#define DDRSS0_PHY_923_DATA 0x00000000 +#define DDRSS0_PHY_924_DATA 0x00000000 +#define DDRSS0_PHY_925_DATA 0x00000000 +#define DDRSS0_PHY_926_DATA 0x00000000 +#define DDRSS0_PHY_927_DATA 0x00000000 +#define DDRSS0_PHY_928_DATA 0x00000000 +#define DDRSS0_PHY_929_DATA 0x00000000 +#define DDRSS0_PHY_930_DATA 0x00000000 +#define DDRSS0_PHY_931_DATA 0x00000000 +#define DDRSS0_PHY_932_DATA 0x00000000 +#define DDRSS0_PHY_933_DATA 0x00000000 +#define DDRSS0_PHY_934_DATA 0x00000000 +#define DDRSS0_PHY_935_DATA 0x00000000 +#define DDRSS0_PHY_936_DATA 0x00000000 +#define DDRSS0_PHY_937_DATA 0x00000000 +#define DDRSS0_PHY_938_DATA 0x00000000 +#define DDRSS0_PHY_939_DATA 0x00000000 +#define DDRSS0_PHY_940_DATA 0x00000000 +#define DDRSS0_PHY_941_DATA 0x00000000 +#define DDRSS0_PHY_942_DATA 0x00000000 +#define DDRSS0_PHY_943_DATA 0x00000000 +#define DDRSS0_PHY_944_DATA 0x00000000 +#define DDRSS0_PHY_945_DATA 0x00000000 +#define DDRSS0_PHY_946_DATA 0x00000000 +#define DDRSS0_PHY_947_DATA 0x00000000 +#define DDRSS0_PHY_948_DATA 0x00000000 +#define DDRSS0_PHY_949_DATA 0x00000000 +#define DDRSS0_PHY_950_DATA 0x00000000 +#define DDRSS0_PHY_951_DATA 0x00000000 +#define DDRSS0_PHY_952_DATA 0x00000000 +#define DDRSS0_PHY_953_DATA 0x00000000 +#define DDRSS0_PHY_954_DATA 0x00000000 +#define DDRSS0_PHY_955_DATA 0x00000000 +#define DDRSS0_PHY_956_DATA 0x00000000 +#define DDRSS0_PHY_957_DATA 0x00000000 +#define DDRSS0_PHY_958_DATA 0x00000000 +#define DDRSS0_PHY_959_DATA 0x00000000 +#define DDRSS0_PHY_960_DATA 0x00000000 +#define DDRSS0_PHY_961_DATA 0x00000000 +#define DDRSS0_PHY_962_DATA 0x00000000 +#define DDRSS0_PHY_963_DATA 0x00000000 +#define DDRSS0_PHY_964_DATA 0x00000000 +#define DDRSS0_PHY_965_DATA 0x00000000 +#define DDRSS0_PHY_966_DATA 0x00000000 +#define DDRSS0_PHY_967_DATA 0x00000000 +#define DDRSS0_PHY_968_DATA 0x00000000 +#define DDRSS0_PHY_969_DATA 0x00000000 +#define DDRSS0_PHY_970_DATA 0x00000000 +#define DDRSS0_PHY_971_DATA 0x00000000 +#define DDRSS0_PHY_972_DATA 0x00000000 +#define DDRSS0_PHY_973_DATA 0x00000000 +#define DDRSS0_PHY_974_DATA 0x00000000 +#define DDRSS0_PHY_975_DATA 0x00000000 +#define DDRSS0_PHY_976_DATA 0x00000000 +#define DDRSS0_PHY_977_DATA 0x00000000 +#define DDRSS0_PHY_978_DATA 0x00000000 +#define DDRSS0_PHY_979_DATA 0x00000000 +#define DDRSS0_PHY_980_DATA 0x00000000 +#define DDRSS0_PHY_981_DATA 0x00000000 +#define DDRSS0_PHY_982_DATA 0x00000000 +#define DDRSS0_PHY_983_DATA 0x00000000 +#define DDRSS0_PHY_984_DATA 0x00000000 +#define DDRSS0_PHY_985_DATA 0x00000000 +#define DDRSS0_PHY_986_DATA 0x00000000 +#define DDRSS0_PHY_987_DATA 0x00000000 +#define DDRSS0_PHY_988_DATA 0x00000000 +#define DDRSS0_PHY_989_DATA 0x00000000 +#define DDRSS0_PHY_990_DATA 0x00000000 +#define DDRSS0_PHY_991_DATA 0x00000000 +#define DDRSS0_PHY_992_DATA 0x00000000 +#define DDRSS0_PHY_993_DATA 0x00000000 +#define DDRSS0_PHY_994_DATA 0x00000000 +#define DDRSS0_PHY_995_DATA 0x00000000 +#define DDRSS0_PHY_996_DATA 0x00000000 +#define DDRSS0_PHY_997_DATA 0x00000000 +#define DDRSS0_PHY_998_DATA 0x00000000 +#define DDRSS0_PHY_999_DATA 0x00000000 +#define DDRSS0_PHY_1000_DATA 0x00000000 +#define DDRSS0_PHY_1001_DATA 0x00000000 +#define DDRSS0_PHY_1002_DATA 0x00000000 +#define DDRSS0_PHY_1003_DATA 0x00000000 +#define DDRSS0_PHY_1004_DATA 0x00000000 +#define DDRSS0_PHY_1005_DATA 0x00000000 +#define DDRSS0_PHY_1006_DATA 0x00000000 +#define DDRSS0_PHY_1007_DATA 0x00000000 +#define DDRSS0_PHY_1008_DATA 0x00000000 +#define DDRSS0_PHY_1009_DATA 0x00000000 +#define DDRSS0_PHY_1010_DATA 0x00000000 +#define DDRSS0_PHY_1011_DATA 0x00000000 +#define DDRSS0_PHY_1012_DATA 0x00000000 +#define DDRSS0_PHY_1013_DATA 0x00000000 +#define DDRSS0_PHY_1014_DATA 0x00000000 +#define DDRSS0_PHY_1015_DATA 0x00000000 +#define DDRSS0_PHY_1016_DATA 0x00000000 +#define DDRSS0_PHY_1017_DATA 0x00000000 +#define DDRSS0_PHY_1018_DATA 0x00000000 +#define DDRSS0_PHY_1019_DATA 0x00000000 +#define DDRSS0_PHY_1020_DATA 0x00000000 +#define DDRSS0_PHY_1021_DATA 0x00000000 +#define DDRSS0_PHY_1022_DATA 0x00000000 +#define DDRSS0_PHY_1023_DATA 0x00000000 +#define DDRSS0_PHY_1024_DATA 0x00000000 +#define DDRSS0_PHY_1025_DATA 0x00000000 +#define DDRSS0_PHY_1026_DATA 0x00000000 +#define DDRSS0_PHY_1027_DATA 0x00000000 +#define DDRSS0_PHY_1028_DATA 0x00000000 +#define DDRSS0_PHY_1029_DATA 0x00000100 +#define DDRSS0_PHY_1030_DATA 0x00000200 +#define DDRSS0_PHY_1031_DATA 0x00000000 +#define DDRSS0_PHY_1032_DATA 0x00000000 +#define DDRSS0_PHY_1033_DATA 0x00000000 +#define DDRSS0_PHY_1034_DATA 0x00000000 +#define DDRSS0_PHY_1035_DATA 0x00400000 +#define DDRSS0_PHY_1036_DATA 0x00000080 +#define DDRSS0_PHY_1037_DATA 0x00DCBA98 +#define DDRSS0_PHY_1038_DATA 0x03000000 +#define DDRSS0_PHY_1039_DATA 0x00200000 +#define DDRSS0_PHY_1040_DATA 0x00000000 +#define DDRSS0_PHY_1041_DATA 0x00000000 +#define DDRSS0_PHY_1042_DATA 0x00000000 +#define DDRSS0_PHY_1043_DATA 0x00000000 +#define DDRSS0_PHY_1044_DATA 0x00000000 +#define DDRSS0_PHY_1045_DATA 0x0000002A +#define DDRSS0_PHY_1046_DATA 0x00000015 +#define DDRSS0_PHY_1047_DATA 0x00000015 +#define DDRSS0_PHY_1048_DATA 0x0000002A +#define DDRSS0_PHY_1049_DATA 0x00000033 +#define DDRSS0_PHY_1050_DATA 0x0000000C +#define DDRSS0_PHY_1051_DATA 0x0000000C +#define DDRSS0_PHY_1052_DATA 0x00000033 +#define DDRSS0_PHY_1053_DATA 0x00543210 +#define DDRSS0_PHY_1054_DATA 0x003F0000 +#define DDRSS0_PHY_1055_DATA 0x000F013F +#define DDRSS0_PHY_1056_DATA 0x20202003 +#define DDRSS0_PHY_1057_DATA 0x00202020 +#define DDRSS0_PHY_1058_DATA 0x20008008 +#define DDRSS0_PHY_1059_DATA 0x00000810 +#define DDRSS0_PHY_1060_DATA 0x00000F00 +#define DDRSS0_PHY_1061_DATA 0x00000000 +#define DDRSS0_PHY_1062_DATA 0x00000000 +#define DDRSS0_PHY_1063_DATA 0x00000000 +#define DDRSS0_PHY_1064_DATA 0x000305CC +#define DDRSS0_PHY_1065_DATA 0x00030000 +#define DDRSS0_PHY_1066_DATA 0x00000300 +#define DDRSS0_PHY_1067_DATA 0x00000300 +#define DDRSS0_PHY_1068_DATA 0x00000300 +#define DDRSS0_PHY_1069_DATA 0x00000300 +#define DDRSS0_PHY_1070_DATA 0x00000300 +#define DDRSS0_PHY_1071_DATA 0x42080010 +#define DDRSS0_PHY_1072_DATA 0x0000803E +#define DDRSS0_PHY_1073_DATA 0x00000001 +#define DDRSS0_PHY_1074_DATA 0x01000102 +#define DDRSS0_PHY_1075_DATA 0x00008000 +#define DDRSS0_PHY_1076_DATA 0x00000000 +#define DDRSS0_PHY_1077_DATA 0x00000000 +#define DDRSS0_PHY_1078_DATA 0x00000000 +#define DDRSS0_PHY_1079_DATA 0x00000000 +#define DDRSS0_PHY_1080_DATA 0x00000000 +#define DDRSS0_PHY_1081_DATA 0x00000000 +#define DDRSS0_PHY_1082_DATA 0x00000000 +#define DDRSS0_PHY_1083_DATA 0x00000000 +#define DDRSS0_PHY_1084_DATA 0x00000000 +#define DDRSS0_PHY_1085_DATA 0x00000000 +#define DDRSS0_PHY_1086_DATA 0x00000000 +#define DDRSS0_PHY_1087_DATA 0x00000000 +#define DDRSS0_PHY_1088_DATA 0x00000000 +#define DDRSS0_PHY_1089_DATA 0x00000000 +#define DDRSS0_PHY_1090_DATA 0x00000000 +#define DDRSS0_PHY_1091_DATA 0x00000000 +#define DDRSS0_PHY_1092_DATA 0x00000000 +#define DDRSS0_PHY_1093_DATA 0x00000000 +#define DDRSS0_PHY_1094_DATA 0x00000000 +#define DDRSS0_PHY_1095_DATA 0x00000000 +#define DDRSS0_PHY_1096_DATA 0x00000000 +#define DDRSS0_PHY_1097_DATA 0x00000000 +#define DDRSS0_PHY_1098_DATA 0x00000000 +#define DDRSS0_PHY_1099_DATA 0x00000000 +#define DDRSS0_PHY_1100_DATA 0x00000000 +#define DDRSS0_PHY_1101_DATA 0x00000000 +#define DDRSS0_PHY_1102_DATA 0x00000000 +#define DDRSS0_PHY_1103_DATA 0x00000000 +#define DDRSS0_PHY_1104_DATA 0x00000000 +#define DDRSS0_PHY_1105_DATA 0x00000000 +#define DDRSS0_PHY_1106_DATA 0x00000000 +#define DDRSS0_PHY_1107_DATA 0x00000000 +#define DDRSS0_PHY_1108_DATA 0x00000000 +#define DDRSS0_PHY_1109_DATA 0x00000000 +#define DDRSS0_PHY_1110_DATA 0x00000000 +#define DDRSS0_PHY_1111_DATA 0x00000000 +#define DDRSS0_PHY_1112_DATA 0x00000000 +#define DDRSS0_PHY_1113_DATA 0x00000000 +#define DDRSS0_PHY_1114_DATA 0x00000000 +#define DDRSS0_PHY_1115_DATA 0x00000000 +#define DDRSS0_PHY_1116_DATA 0x00000000 +#define DDRSS0_PHY_1117_DATA 0x00000000 +#define DDRSS0_PHY_1118_DATA 0x00000000 +#define DDRSS0_PHY_1119_DATA 0x00000000 +#define DDRSS0_PHY_1120_DATA 0x00000000 +#define DDRSS0_PHY_1121_DATA 0x00000000 +#define DDRSS0_PHY_1122_DATA 0x00000000 +#define DDRSS0_PHY_1123_DATA 0x00000000 +#define DDRSS0_PHY_1124_DATA 0x00000000 +#define DDRSS0_PHY_1125_DATA 0x00000000 +#define DDRSS0_PHY_1126_DATA 0x00000000 +#define DDRSS0_PHY_1127_DATA 0x00000000 +#define DDRSS0_PHY_1128_DATA 0x00000000 +#define DDRSS0_PHY_1129_DATA 0x00000000 +#define DDRSS0_PHY_1130_DATA 0x00000000 +#define DDRSS0_PHY_1131_DATA 0x00000000 +#define DDRSS0_PHY_1132_DATA 0x00000000 +#define DDRSS0_PHY_1133_DATA 0x00000000 +#define DDRSS0_PHY_1134_DATA 0x00000000 +#define DDRSS0_PHY_1135_DATA 0x00000000 +#define DDRSS0_PHY_1136_DATA 0x00000000 +#define DDRSS0_PHY_1137_DATA 0x00000000 +#define DDRSS0_PHY_1138_DATA 0x00000000 +#define DDRSS0_PHY_1139_DATA 0x00000000 +#define DDRSS0_PHY_1140_DATA 0x00000000 +#define DDRSS0_PHY_1141_DATA 0x00000000 +#define DDRSS0_PHY_1142_DATA 0x00000000 +#define DDRSS0_PHY_1143_DATA 0x00000000 +#define DDRSS0_PHY_1144_DATA 0x00000000 +#define DDRSS0_PHY_1145_DATA 0x00000000 +#define DDRSS0_PHY_1146_DATA 0x00000000 +#define DDRSS0_PHY_1147_DATA 0x00000000 +#define DDRSS0_PHY_1148_DATA 0x00000000 +#define DDRSS0_PHY_1149_DATA 0x00000000 +#define DDRSS0_PHY_1150_DATA 0x00000000 +#define DDRSS0_PHY_1151_DATA 0x00000000 +#define DDRSS0_PHY_1152_DATA 0x00000000 +#define DDRSS0_PHY_1153_DATA 0x00000000 +#define DDRSS0_PHY_1154_DATA 0x00000000 +#define DDRSS0_PHY_1155_DATA 0x00000000 +#define DDRSS0_PHY_1156_DATA 0x00000000 +#define DDRSS0_PHY_1157_DATA 0x00000000 +#define DDRSS0_PHY_1158_DATA 0x00000000 +#define DDRSS0_PHY_1159_DATA 0x00000000 +#define DDRSS0_PHY_1160_DATA 0x00000000 +#define DDRSS0_PHY_1161_DATA 0x00000000 +#define DDRSS0_PHY_1162_DATA 0x00000000 +#define DDRSS0_PHY_1163_DATA 0x00000000 +#define DDRSS0_PHY_1164_DATA 0x00000000 +#define DDRSS0_PHY_1165_DATA 0x00000000 +#define DDRSS0_PHY_1166_DATA 0x00000000 +#define DDRSS0_PHY_1167_DATA 0x00000000 +#define DDRSS0_PHY_1168_DATA 0x00000000 +#define DDRSS0_PHY_1169_DATA 0x00000000 +#define DDRSS0_PHY_1170_DATA 0x00000000 +#define DDRSS0_PHY_1171_DATA 0x00000000 +#define DDRSS0_PHY_1172_DATA 0x00000000 +#define DDRSS0_PHY_1173_DATA 0x00000000 +#define DDRSS0_PHY_1174_DATA 0x00000000 +#define DDRSS0_PHY_1175_DATA 0x00000000 +#define DDRSS0_PHY_1176_DATA 0x00000000 +#define DDRSS0_PHY_1177_DATA 0x00000000 +#define DDRSS0_PHY_1178_DATA 0x00000000 +#define DDRSS0_PHY_1179_DATA 0x00000000 +#define DDRSS0_PHY_1180_DATA 0x00000000 +#define DDRSS0_PHY_1181_DATA 0x00000000 +#define DDRSS0_PHY_1182_DATA 0x00000000 +#define DDRSS0_PHY_1183_DATA 0x00000000 +#define DDRSS0_PHY_1184_DATA 0x00000000 +#define DDRSS0_PHY_1185_DATA 0x00000000 +#define DDRSS0_PHY_1186_DATA 0x00000000 +#define DDRSS0_PHY_1187_DATA 0x00000000 +#define DDRSS0_PHY_1188_DATA 0x00000000 +#define DDRSS0_PHY_1189_DATA 0x00000000 +#define DDRSS0_PHY_1190_DATA 0x00000000 +#define DDRSS0_PHY_1191_DATA 0x00000000 +#define DDRSS0_PHY_1192_DATA 0x00000000 +#define DDRSS0_PHY_1193_DATA 0x00000000 +#define DDRSS0_PHY_1194_DATA 0x00000000 +#define DDRSS0_PHY_1195_DATA 0x00000000 +#define DDRSS0_PHY_1196_DATA 0x00000000 +#define DDRSS0_PHY_1197_DATA 0x00000000 +#define DDRSS0_PHY_1198_DATA 0x00000000 +#define DDRSS0_PHY_1199_DATA 0x00000000 +#define DDRSS0_PHY_1200_DATA 0x00000000 +#define DDRSS0_PHY_1201_DATA 0x00000000 +#define DDRSS0_PHY_1202_DATA 0x00000000 +#define DDRSS0_PHY_1203_DATA 0x00000000 +#define DDRSS0_PHY_1204_DATA 0x00000000 +#define DDRSS0_PHY_1205_DATA 0x00000000 +#define DDRSS0_PHY_1206_DATA 0x00000000 +#define DDRSS0_PHY_1207_DATA 0x00000000 +#define DDRSS0_PHY_1208_DATA 0x00000000 +#define DDRSS0_PHY_1209_DATA 0x00000000 +#define DDRSS0_PHY_1210_DATA 0x00000000 +#define DDRSS0_PHY_1211_DATA 0x00000000 +#define DDRSS0_PHY_1212_DATA 0x00000000 +#define DDRSS0_PHY_1213_DATA 0x00000000 +#define DDRSS0_PHY_1214_DATA 0x00000000 +#define DDRSS0_PHY_1215_DATA 0x00000000 +#define DDRSS0_PHY_1216_DATA 0x00000000 +#define DDRSS0_PHY_1217_DATA 0x00000000 +#define DDRSS0_PHY_1218_DATA 0x00000000 +#define DDRSS0_PHY_1219_DATA 0x00000000 +#define DDRSS0_PHY_1220_DATA 0x00000000 +#define DDRSS0_PHY_1221_DATA 0x00000000 +#define DDRSS0_PHY_1222_DATA 0x00000000 +#define DDRSS0_PHY_1223_DATA 0x00000000 +#define DDRSS0_PHY_1224_DATA 0x00000000 +#define DDRSS0_PHY_1225_DATA 0x00000000 +#define DDRSS0_PHY_1226_DATA 0x00000000 +#define DDRSS0_PHY_1227_DATA 0x00000000 +#define DDRSS0_PHY_1228_DATA 0x00000000 +#define DDRSS0_PHY_1229_DATA 0x00000000 +#define DDRSS0_PHY_1230_DATA 0x00000000 +#define DDRSS0_PHY_1231_DATA 0x00000000 +#define DDRSS0_PHY_1232_DATA 0x00000000 +#define DDRSS0_PHY_1233_DATA 0x00000000 +#define DDRSS0_PHY_1234_DATA 0x00000000 +#define DDRSS0_PHY_1235_DATA 0x00000000 +#define DDRSS0_PHY_1236_DATA 0x00000000 +#define DDRSS0_PHY_1237_DATA 0x00000000 +#define DDRSS0_PHY_1238_DATA 0x00000000 +#define DDRSS0_PHY_1239_DATA 0x00000000 +#define DDRSS0_PHY_1240_DATA 0x00000000 +#define DDRSS0_PHY_1241_DATA 0x00000000 +#define DDRSS0_PHY_1242_DATA 0x00000000 +#define DDRSS0_PHY_1243_DATA 0x00000000 +#define DDRSS0_PHY_1244_DATA 0x00000000 +#define DDRSS0_PHY_1245_DATA 0x00000000 +#define DDRSS0_PHY_1246_DATA 0x00000000 +#define DDRSS0_PHY_1247_DATA 0x00000000 +#define DDRSS0_PHY_1248_DATA 0x00000000 +#define DDRSS0_PHY_1249_DATA 0x00000000 +#define DDRSS0_PHY_1250_DATA 0x00000000 +#define DDRSS0_PHY_1251_DATA 0x00000000 +#define DDRSS0_PHY_1252_DATA 0x00000000 +#define DDRSS0_PHY_1253_DATA 0x00000000 +#define DDRSS0_PHY_1254_DATA 0x00000000 +#define DDRSS0_PHY_1255_DATA 0x00000000 +#define DDRSS0_PHY_1256_DATA 0x00000000 +#define DDRSS0_PHY_1257_DATA 0x00000000 +#define DDRSS0_PHY_1258_DATA 0x00000000 +#define DDRSS0_PHY_1259_DATA 0x00000000 +#define DDRSS0_PHY_1260_DATA 0x00000000 +#define DDRSS0_PHY_1261_DATA 0x00000000 +#define DDRSS0_PHY_1262_DATA 0x00000000 +#define DDRSS0_PHY_1263_DATA 0x00000000 +#define DDRSS0_PHY_1264_DATA 0x00000000 +#define DDRSS0_PHY_1265_DATA 0x00000000 +#define DDRSS0_PHY_1266_DATA 0x00000000 +#define DDRSS0_PHY_1267_DATA 0x00000000 +#define DDRSS0_PHY_1268_DATA 0x00000000 +#define DDRSS0_PHY_1269_DATA 0x00000000 +#define DDRSS0_PHY_1270_DATA 0x00000000 +#define DDRSS0_PHY_1271_DATA 0x00000000 +#define DDRSS0_PHY_1272_DATA 0x00000000 +#define DDRSS0_PHY_1273_DATA 0x00000000 +#define DDRSS0_PHY_1274_DATA 0x00000000 +#define DDRSS0_PHY_1275_DATA 0x00000000 +#define DDRSS0_PHY_1276_DATA 0x00000000 +#define DDRSS0_PHY_1277_DATA 0x00000000 +#define DDRSS0_PHY_1278_DATA 0x00000000 +#define DDRSS0_PHY_1279_DATA 0x00000000 +#define DDRSS0_PHY_1280_DATA 0x00000000 +#define DDRSS0_PHY_1281_DATA 0x00010100 +#define DDRSS0_PHY_1282_DATA 0x00000000 +#define DDRSS0_PHY_1283_DATA 0x00000000 +#define DDRSS0_PHY_1284_DATA 0x00050000 +#define DDRSS0_PHY_1285_DATA 0x04000000 +#define DDRSS0_PHY_1286_DATA 0x00000055 +#define DDRSS0_PHY_1287_DATA 0x00000000 +#define DDRSS0_PHY_1288_DATA 0x00000000 +#define DDRSS0_PHY_1289_DATA 0x00000000 +#define DDRSS0_PHY_1290_DATA 0x00000000 +#define DDRSS0_PHY_1291_DATA 0x00002001 +#define DDRSS0_PHY_1292_DATA 0x0000400F +#define DDRSS0_PHY_1293_DATA 0x50020028 +#define DDRSS0_PHY_1294_DATA 0x01010000 +#define DDRSS0_PHY_1295_DATA 0x80080001 +#define DDRSS0_PHY_1296_DATA 0x10200000 +#define DDRSS0_PHY_1297_DATA 0x00000008 +#define DDRSS0_PHY_1298_DATA 0x00000000 +#define DDRSS0_PHY_1299_DATA 0x01090E00 +#define DDRSS0_PHY_1300_DATA 0x00040101 +#define DDRSS0_PHY_1301_DATA 0x0000010F +#define DDRSS0_PHY_1302_DATA 0x00000000 +#define DDRSS0_PHY_1303_DATA 0x0000FFFF +#define DDRSS0_PHY_1304_DATA 0x00000000 +#define DDRSS0_PHY_1305_DATA 0x01010000 +#define DDRSS0_PHY_1306_DATA 0x01080402 +#define DDRSS0_PHY_1307_DATA 0x01200F02 +#define DDRSS0_PHY_1308_DATA 0x00194280 +#define DDRSS0_PHY_1309_DATA 0x00000004 +#define DDRSS0_PHY_1310_DATA 0x00042000 +#define DDRSS0_PHY_1311_DATA 0x00000000 +#define DDRSS0_PHY_1312_DATA 0x00000000 +#define DDRSS0_PHY_1313_DATA 0x00000000 +#define DDRSS0_PHY_1314_DATA 0x00000000 +#define DDRSS0_PHY_1315_DATA 0x00000000 +#define DDRSS0_PHY_1316_DATA 0x00000000 +#define DDRSS0_PHY_1317_DATA 0x01000000 +#define DDRSS0_PHY_1318_DATA 0x00000705 +#define DDRSS0_PHY_1319_DATA 0x00000054 +#define DDRSS0_PHY_1320_DATA 0x00030820 +#define DDRSS0_PHY_1321_DATA 0x00010820 +#define DDRSS0_PHY_1322_DATA 0x00010820 +#define DDRSS0_PHY_1323_DATA 0x00010820 +#define DDRSS0_PHY_1324_DATA 0x00010820 +#define DDRSS0_PHY_1325_DATA 0x00010820 +#define DDRSS0_PHY_1326_DATA 0x00010820 +#define DDRSS0_PHY_1327_DATA 0x00010820 +#define DDRSS0_PHY_1328_DATA 0x00010820 +#define DDRSS0_PHY_1329_DATA 0x00000000 +#define DDRSS0_PHY_1330_DATA 0x00000074 +#define DDRSS0_PHY_1331_DATA 0x00000400 +#define DDRSS0_PHY_1332_DATA 0x00000108 +#define DDRSS0_PHY_1333_DATA 0x00000000 +#define DDRSS0_PHY_1334_DATA 0x00000000 +#define DDRSS0_PHY_1335_DATA 0x00000000 +#define DDRSS0_PHY_1336_DATA 0x00000000 +#define DDRSS0_PHY_1337_DATA 0x00000000 +#define DDRSS0_PHY_1338_DATA 0x03000000 +#define DDRSS0_PHY_1339_DATA 0x00000000 +#define DDRSS0_PHY_1340_DATA 0x00000000 +#define DDRSS0_PHY_1341_DATA 0x00000000 +#define DDRSS0_PHY_1342_DATA 0x04102006 +#define DDRSS0_PHY_1343_DATA 0x00041020 +#define DDRSS0_PHY_1344_DATA 0x01C98C98 +#define DDRSS0_PHY_1345_DATA 0x3F400000 +#define DDRSS0_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS0_PHY_1347_DATA 0x0000001F +#define DDRSS0_PHY_1348_DATA 0x00000000 +#define DDRSS0_PHY_1349_DATA 0x00000000 +#define DDRSS0_PHY_1350_DATA 0x00000000 +#define DDRSS0_PHY_1351_DATA 0x00010000 +#define DDRSS0_PHY_1352_DATA 0x00000000 +#define DDRSS0_PHY_1353_DATA 0x00000000 +#define DDRSS0_PHY_1354_DATA 0x00000000 +#define DDRSS0_PHY_1355_DATA 0x00000000 +#define DDRSS0_PHY_1356_DATA 0x76543210 +#define DDRSS0_PHY_1357_DATA 0x00010198 +#define DDRSS0_PHY_1358_DATA 0x00000000 +#define DDRSS0_PHY_1359_DATA 0x00000000 +#define DDRSS0_PHY_1360_DATA 0x00000000 +#define DDRSS0_PHY_1361_DATA 0x00040700 +#define DDRSS0_PHY_1362_DATA 0x00000000 +#define DDRSS0_PHY_1363_DATA 0x00000000 +#define DDRSS0_PHY_1364_DATA 0x00000000 +#define DDRSS0_PHY_1365_DATA 0x00000000 +#define DDRSS0_PHY_1366_DATA 0x00000000 +#define DDRSS0_PHY_1367_DATA 0x00000002 +#define DDRSS0_PHY_1368_DATA 0x00000000 +#define DDRSS0_PHY_1369_DATA 0x00000000 +#define DDRSS0_PHY_1370_DATA 0x00000000 +#define DDRSS0_PHY_1371_DATA 0x00000000 +#define DDRSS0_PHY_1372_DATA 0x00000000 +#define DDRSS0_PHY_1373_DATA 0x00000000 +#define DDRSS0_PHY_1374_DATA 0x00080000 +#define DDRSS0_PHY_1375_DATA 0x000007FF +#define DDRSS0_PHY_1376_DATA 0x00000000 +#define DDRSS0_PHY_1377_DATA 0x00000000 +#define DDRSS0_PHY_1378_DATA 0x00000000 +#define DDRSS0_PHY_1379_DATA 0x00000000 +#define DDRSS0_PHY_1380_DATA 0x00000000 +#define DDRSS0_PHY_1381_DATA 0x00000000 +#define DDRSS0_PHY_1382_DATA 0x000FFFFF +#define DDRSS0_PHY_1383_DATA 0x000FFFFF +#define DDRSS0_PHY_1384_DATA 0x0000FFFF +#define DDRSS0_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS0_PHY_1386_DATA 0x030FFFFF +#define DDRSS0_PHY_1387_DATA 0x01FFFFFF +#define DDRSS0_PHY_1388_DATA 0x0000FFFF +#define DDRSS0_PHY_1389_DATA 0x00000000 +#define DDRSS0_PHY_1390_DATA 0x00000000 +#define DDRSS0_PHY_1391_DATA 0x00000000 +#define DDRSS0_PHY_1392_DATA 0x00000000 +#define DDRSS0_PHY_1393_DATA 0x0001F7C0 +#define DDRSS0_PHY_1394_DATA 0x00000003 +#define DDRSS0_PHY_1395_DATA 0x00000000 +#define DDRSS0_PHY_1396_DATA 0x00001142 +#define DDRSS0_PHY_1397_DATA 0x010207AB +#define DDRSS0_PHY_1398_DATA 0x01000080 +#define DDRSS0_PHY_1399_DATA 0x03900390 +#define DDRSS0_PHY_1400_DATA 0x03900390 +#define DDRSS0_PHY_1401_DATA 0x00000390 +#define DDRSS0_PHY_1402_DATA 0x00000390 +#define DDRSS0_PHY_1403_DATA 0x00000390 +#define DDRSS0_PHY_1404_DATA 0x00000390 +#define DDRSS0_PHY_1405_DATA 0x00000005 +#define DDRSS0_PHY_1406_DATA 0x01813FCC +#define DDRSS0_PHY_1407_DATA 0x000000CC +#define DDRSS0_PHY_1408_DATA 0x0C000DFF +#define DDRSS0_PHY_1409_DATA 0x30000DFF +#define DDRSS0_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1411_DATA 0x000100F0 +#define DDRSS0_PHY_1412_DATA 0x780DFFCC +#define DDRSS0_PHY_1413_DATA 0x00007E31 +#define DDRSS0_PHY_1414_DATA 0x000CBF11 +#define DDRSS0_PHY_1415_DATA 0x01990010 +#define DDRSS0_PHY_1416_DATA 0x000CBF11 +#define DDRSS0_PHY_1417_DATA 0x01990010 +#define DDRSS0_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1419_DATA 0x00EF00F0 +#define DDRSS0_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1421_DATA 0x01FF00F0 +#define DDRSS0_PHY_1422_DATA 0x20040006 + +#define DDRSS1_CTL_00_DATA 0x00000B00 +#define DDRSS1_CTL_01_DATA 0x00000000 +#define DDRSS1_CTL_02_DATA 0x00000000 +#define DDRSS1_CTL_03_DATA 0x00000000 +#define DDRSS1_CTL_04_DATA 0x00000000 +#define DDRSS1_CTL_05_DATA 0x00000000 +#define DDRSS1_CTL_06_DATA 0x00000000 +#define DDRSS1_CTL_07_DATA 0x00002AF8 +#define DDRSS1_CTL_08_DATA 0x0001ADAF +#define DDRSS1_CTL_09_DATA 0x00000005 +#define DDRSS1_CTL_10_DATA 0x0000006E +#define DDRSS1_CTL_11_DATA 0x000681C8 +#define DDRSS1_CTL_12_DATA 0x004111C9 +#define DDRSS1_CTL_13_DATA 0x00000005 +#define DDRSS1_CTL_14_DATA 0x000010A9 +#define DDRSS1_CTL_15_DATA 0x000681C8 +#define DDRSS1_CTL_16_DATA 0x004111C9 +#define DDRSS1_CTL_17_DATA 0x00000005 +#define DDRSS1_CTL_18_DATA 0x000010A9 +#define DDRSS1_CTL_19_DATA 0x01010000 +#define DDRSS1_CTL_20_DATA 0x02011001 +#define DDRSS1_CTL_21_DATA 0x02010000 +#define DDRSS1_CTL_22_DATA 0x00020100 +#define DDRSS1_CTL_23_DATA 0x0000000B +#define DDRSS1_CTL_24_DATA 0x0000001C +#define DDRSS1_CTL_25_DATA 0x00000000 +#define DDRSS1_CTL_26_DATA 0x00000000 +#define DDRSS1_CTL_27_DATA 0x03020200 +#define DDRSS1_CTL_28_DATA 0x00005656 +#define DDRSS1_CTL_29_DATA 0x00100000 +#define DDRSS1_CTL_30_DATA 0x00000000 +#define DDRSS1_CTL_31_DATA 0x00000000 +#define DDRSS1_CTL_32_DATA 0x00000000 +#define DDRSS1_CTL_33_DATA 0x00000000 +#define DDRSS1_CTL_34_DATA 0x040C0000 +#define DDRSS1_CTL_35_DATA 0x12481248 +#define DDRSS1_CTL_36_DATA 0x00050804 +#define DDRSS1_CTL_37_DATA 0x09040008 +#define DDRSS1_CTL_38_DATA 0x15000204 +#define DDRSS1_CTL_39_DATA 0x1760008B +#define DDRSS1_CTL_40_DATA 0x1500422B +#define DDRSS1_CTL_41_DATA 0x1760008B +#define DDRSS1_CTL_42_DATA 0x2000422B +#define DDRSS1_CTL_43_DATA 0x000A0A09 +#define DDRSS1_CTL_44_DATA 0x040003C5 +#define DDRSS1_CTL_45_DATA 0x1E161104 +#define DDRSS1_CTL_46_DATA 0x1000922C +#define DDRSS1_CTL_47_DATA 0x1E161110 +#define DDRSS1_CTL_48_DATA 0x1000922C +#define DDRSS1_CTL_49_DATA 0x02030410 +#define DDRSS1_CTL_50_DATA 0x2C040500 +#define DDRSS1_CTL_51_DATA 0x08292C29 +#define DDRSS1_CTL_52_DATA 0x14000E0A +#define DDRSS1_CTL_53_DATA 0x04010A0A +#define DDRSS1_CTL_54_DATA 0x01010004 +#define DDRSS1_CTL_55_DATA 0x04545408 +#define DDRSS1_CTL_56_DATA 0x04313104 +#define DDRSS1_CTL_57_DATA 0x00003131 +#define DDRSS1_CTL_58_DATA 0x00010100 +#define DDRSS1_CTL_59_DATA 0x03010000 +#define DDRSS1_CTL_60_DATA 0x00001508 +#define DDRSS1_CTL_61_DATA 0x00000063 +#define DDRSS1_CTL_62_DATA 0x0000032B +#define DDRSS1_CTL_63_DATA 0x00001035 +#define DDRSS1_CTL_64_DATA 0x0000032B +#define DDRSS1_CTL_65_DATA 0x00001035 +#define DDRSS1_CTL_66_DATA 0x00000005 +#define DDRSS1_CTL_67_DATA 0x00050000 +#define DDRSS1_CTL_68_DATA 0x00CB0012 +#define DDRSS1_CTL_69_DATA 0x00CB0408 +#define DDRSS1_CTL_70_DATA 0x00400408 +#define DDRSS1_CTL_71_DATA 0x00120103 +#define DDRSS1_CTL_72_DATA 0x00100005 +#define DDRSS1_CTL_73_DATA 0x2F080010 +#define DDRSS1_CTL_74_DATA 0x0505012F +#define DDRSS1_CTL_75_DATA 0x0401030A +#define DDRSS1_CTL_76_DATA 0x041E100B +#define DDRSS1_CTL_77_DATA 0x100B0401 +#define DDRSS1_CTL_78_DATA 0x0001041E +#define DDRSS1_CTL_79_DATA 0x00160016 +#define DDRSS1_CTL_80_DATA 0x033B033B +#define DDRSS1_CTL_81_DATA 0x033B033B +#define DDRSS1_CTL_82_DATA 0x03050505 +#define DDRSS1_CTL_83_DATA 0x03010303 +#define DDRSS1_CTL_84_DATA 0x200B100B +#define DDRSS1_CTL_85_DATA 0x04041004 +#define DDRSS1_CTL_86_DATA 0x200B100B +#define DDRSS1_CTL_87_DATA 0x04041004 +#define DDRSS1_CTL_88_DATA 0x03010000 +#define DDRSS1_CTL_89_DATA 0x00010000 +#define DDRSS1_CTL_90_DATA 0x00000000 +#define DDRSS1_CTL_91_DATA 0x00000000 +#define DDRSS1_CTL_92_DATA 0x01000000 +#define DDRSS1_CTL_93_DATA 0x80104002 +#define DDRSS1_CTL_94_DATA 0x00000000 +#define DDRSS1_CTL_95_DATA 0x00040005 +#define DDRSS1_CTL_96_DATA 0x00000000 +#define DDRSS1_CTL_97_DATA 0x00050000 +#define DDRSS1_CTL_98_DATA 0x00000004 +#define DDRSS1_CTL_99_DATA 0x00000000 +#define DDRSS1_CTL_100_DATA 0x00040005 +#define DDRSS1_CTL_101_DATA 0x00000000 +#define DDRSS1_CTL_102_DATA 0x000018C0 +#define DDRSS1_CTL_103_DATA 0x000018C0 +#define DDRSS1_CTL_104_DATA 0x000018C0 +#define DDRSS1_CTL_105_DATA 0x000018C0 +#define DDRSS1_CTL_106_DATA 0x000018C0 +#define DDRSS1_CTL_107_DATA 0x00000000 +#define DDRSS1_CTL_108_DATA 0x000002B5 +#define DDRSS1_CTL_109_DATA 0x00040D40 +#define DDRSS1_CTL_110_DATA 0x00040D40 +#define DDRSS1_CTL_111_DATA 0x00040D40 +#define DDRSS1_CTL_112_DATA 0x00040D40 +#define DDRSS1_CTL_113_DATA 0x00040D40 +#define DDRSS1_CTL_114_DATA 0x00000000 +#define DDRSS1_CTL_115_DATA 0x00007173 +#define DDRSS1_CTL_116_DATA 0x00040D40 +#define DDRSS1_CTL_117_DATA 0x00040D40 +#define DDRSS1_CTL_118_DATA 0x00040D40 +#define DDRSS1_CTL_119_DATA 0x00040D40 +#define DDRSS1_CTL_120_DATA 0x00040D40 +#define DDRSS1_CTL_121_DATA 0x00000000 +#define DDRSS1_CTL_122_DATA 0x00007173 +#define DDRSS1_CTL_123_DATA 0x00000000 +#define DDRSS1_CTL_124_DATA 0x00000000 +#define DDRSS1_CTL_125_DATA 0x00000000 +#define DDRSS1_CTL_126_DATA 0x00000000 +#define DDRSS1_CTL_127_DATA 0x00000000 +#define DDRSS1_CTL_128_DATA 0x00000000 +#define DDRSS1_CTL_129_DATA 0x00000000 +#define DDRSS1_CTL_130_DATA 0x00000000 +#define DDRSS1_CTL_131_DATA 0x0B030500 +#define DDRSS1_CTL_132_DATA 0x00040B04 +#define DDRSS1_CTL_133_DATA 0x0A090000 +#define DDRSS1_CTL_134_DATA 0x0A090701 +#define DDRSS1_CTL_135_DATA 0x0900000E +#define DDRSS1_CTL_136_DATA 0x0907010A +#define DDRSS1_CTL_137_DATA 0x00000E0A +#define DDRSS1_CTL_138_DATA 0x07010A09 +#define DDRSS1_CTL_139_DATA 0x000E0A09 +#define DDRSS1_CTL_140_DATA 0x07000401 +#define DDRSS1_CTL_141_DATA 0x00000000 +#define DDRSS1_CTL_142_DATA 0x00000000 +#define DDRSS1_CTL_143_DATA 0x00000000 +#define DDRSS1_CTL_144_DATA 0x00000000 +#define DDRSS1_CTL_145_DATA 0x00000000 +#define DDRSS1_CTL_146_DATA 0x00000000 +#define DDRSS1_CTL_147_DATA 0x00000000 +#define DDRSS1_CTL_148_DATA 0x08080000 +#define DDRSS1_CTL_149_DATA 0x01000000 +#define DDRSS1_CTL_150_DATA 0x800000C0 +#define DDRSS1_CTL_151_DATA 0x800000C0 +#define DDRSS1_CTL_152_DATA 0x800000C0 +#define DDRSS1_CTL_153_DATA 0x00000000 +#define DDRSS1_CTL_154_DATA 0x00001500 +#define DDRSS1_CTL_155_DATA 0x00000000 +#define DDRSS1_CTL_156_DATA 0x00000001 +#define DDRSS1_CTL_157_DATA 0x00000002 +#define DDRSS1_CTL_158_DATA 0x0000100E +#define DDRSS1_CTL_159_DATA 0x00000000 +#define DDRSS1_CTL_160_DATA 0x00000000 +#define DDRSS1_CTL_161_DATA 0x00000000 +#define DDRSS1_CTL_162_DATA 0x00000000 +#define DDRSS1_CTL_163_DATA 0x00000000 +#define DDRSS1_CTL_164_DATA 0x000B0000 +#define DDRSS1_CTL_165_DATA 0x000E0006 +#define DDRSS1_CTL_166_DATA 0x000E0404 +#define DDRSS1_CTL_167_DATA 0x00D601AB +#define DDRSS1_CTL_168_DATA 0x10100216 +#define DDRSS1_CTL_169_DATA 0x01AB0216 +#define DDRSS1_CTL_170_DATA 0x021600D6 +#define DDRSS1_CTL_171_DATA 0x02161010 +#define DDRSS1_CTL_172_DATA 0x00000000 +#define DDRSS1_CTL_173_DATA 0x00000000 +#define DDRSS1_CTL_174_DATA 0x00000000 +#define DDRSS1_CTL_175_DATA 0x3FF40084 +#define DDRSS1_CTL_176_DATA 0x33003FF4 +#define DDRSS1_CTL_177_DATA 0x00003333 +#define DDRSS1_CTL_178_DATA 0x35000000 +#define DDRSS1_CTL_179_DATA 0x27270035 +#define DDRSS1_CTL_180_DATA 0x0F0F0000 +#define DDRSS1_CTL_181_DATA 0x16000000 +#define DDRSS1_CTL_182_DATA 0x00841616 +#define DDRSS1_CTL_183_DATA 0x3FF43FF4 +#define DDRSS1_CTL_184_DATA 0x33333300 +#define DDRSS1_CTL_185_DATA 0x00000000 +#define DDRSS1_CTL_186_DATA 0x00353500 +#define DDRSS1_CTL_187_DATA 0x00002727 +#define DDRSS1_CTL_188_DATA 0x00000F0F +#define DDRSS1_CTL_189_DATA 0x16161600 +#define DDRSS1_CTL_190_DATA 0x00000020 +#define DDRSS1_CTL_191_DATA 0x00000000 +#define DDRSS1_CTL_192_DATA 0x00000001 +#define DDRSS1_CTL_193_DATA 0x00000000 +#define DDRSS1_CTL_194_DATA 0x01000000 +#define DDRSS1_CTL_195_DATA 0x00000001 +#define DDRSS1_CTL_196_DATA 0x00000000 +#define DDRSS1_CTL_197_DATA 0x00000000 +#define DDRSS1_CTL_198_DATA 0x00000000 +#define DDRSS1_CTL_199_DATA 0x00000000 +#define DDRSS1_CTL_200_DATA 0x00000000 +#define DDRSS1_CTL_201_DATA 0x00000000 +#define DDRSS1_CTL_202_DATA 0x00000000 +#define DDRSS1_CTL_203_DATA 0x00000000 +#define DDRSS1_CTL_204_DATA 0x00000000 +#define DDRSS1_CTL_205_DATA 0x00000000 +#define DDRSS1_CTL_206_DATA 0x02000000 +#define DDRSS1_CTL_207_DATA 0x01080101 +#define DDRSS1_CTL_208_DATA 0x00000000 +#define DDRSS1_CTL_209_DATA 0x00000000 +#define DDRSS1_CTL_210_DATA 0x00000000 +#define DDRSS1_CTL_211_DATA 0x00000000 +#define DDRSS1_CTL_212_DATA 0x00000000 +#define DDRSS1_CTL_213_DATA 0x00000000 +#define DDRSS1_CTL_214_DATA 0x00000000 +#define DDRSS1_CTL_215_DATA 0x00000000 +#define DDRSS1_CTL_216_DATA 0x00000000 +#define DDRSS1_CTL_217_DATA 0x00000000 +#define DDRSS1_CTL_218_DATA 0x00000000 +#define DDRSS1_CTL_219_DATA 0x00000000 +#define DDRSS1_CTL_220_DATA 0x00000000 +#define DDRSS1_CTL_221_DATA 0x00000000 +#define DDRSS1_CTL_222_DATA 0x00001000 +#define DDRSS1_CTL_223_DATA 0x006403E8 +#define DDRSS1_CTL_224_DATA 0x00000000 +#define DDRSS1_CTL_225_DATA 0x00000000 +#define DDRSS1_CTL_226_DATA 0x00000000 +#define DDRSS1_CTL_227_DATA 0x15110000 +#define DDRSS1_CTL_228_DATA 0x00040C18 +#define DDRSS1_CTL_229_DATA 0xF000C000 +#define DDRSS1_CTL_230_DATA 0x0000F000 +#define DDRSS1_CTL_231_DATA 0x00000000 +#define DDRSS1_CTL_232_DATA 0x00000000 +#define DDRSS1_CTL_233_DATA 0xC0000000 +#define DDRSS1_CTL_234_DATA 0xF000F000 +#define DDRSS1_CTL_235_DATA 0x00000000 +#define DDRSS1_CTL_236_DATA 0x00000000 +#define DDRSS1_CTL_237_DATA 0x00000000 +#define DDRSS1_CTL_238_DATA 0xF000C000 +#define DDRSS1_CTL_239_DATA 0x0000F000 +#define DDRSS1_CTL_240_DATA 0x00000000 +#define DDRSS1_CTL_241_DATA 0x00000000 +#define DDRSS1_CTL_242_DATA 0x00030000 +#define DDRSS1_CTL_243_DATA 0x00000000 +#define DDRSS1_CTL_244_DATA 0x00000000 +#define DDRSS1_CTL_245_DATA 0x00000000 +#define DDRSS1_CTL_246_DATA 0x00000000 +#define DDRSS1_CTL_247_DATA 0x00000000 +#define DDRSS1_CTL_248_DATA 0x00000000 +#define DDRSS1_CTL_249_DATA 0x00000000 +#define DDRSS1_CTL_250_DATA 0x00000000 +#define DDRSS1_CTL_251_DATA 0x00000000 +#define DDRSS1_CTL_252_DATA 0x00000000 +#define DDRSS1_CTL_253_DATA 0x00000000 +#define DDRSS1_CTL_254_DATA 0x00000000 +#define DDRSS1_CTL_255_DATA 0x00000000 +#define DDRSS1_CTL_256_DATA 0x00000000 +#define DDRSS1_CTL_257_DATA 0x01000200 +#define DDRSS1_CTL_258_DATA 0x00370040 +#define DDRSS1_CTL_259_DATA 0x00020008 +#define DDRSS1_CTL_260_DATA 0x00400100 +#define DDRSS1_CTL_261_DATA 0x00400855 +#define DDRSS1_CTL_262_DATA 0x01000200 +#define DDRSS1_CTL_263_DATA 0x08550040 +#define DDRSS1_CTL_264_DATA 0x00000040 +#define DDRSS1_CTL_265_DATA 0x006B0003 +#define DDRSS1_CTL_266_DATA 0x0100006B +#define DDRSS1_CTL_267_DATA 0x03030303 +#define DDRSS1_CTL_268_DATA 0x00000000 +#define DDRSS1_CTL_269_DATA 0x00000202 +#define DDRSS1_CTL_270_DATA 0x00001FFF +#define DDRSS1_CTL_271_DATA 0x3FFF2000 +#define DDRSS1_CTL_272_DATA 0x03FF0000 +#define DDRSS1_CTL_273_DATA 0x000103FF +#define DDRSS1_CTL_274_DATA 0x0FFF0B00 +#define DDRSS1_CTL_275_DATA 0x01010001 +#define DDRSS1_CTL_276_DATA 0x01010101 +#define DDRSS1_CTL_277_DATA 0x01180101 +#define DDRSS1_CTL_278_DATA 0x00030000 +#define DDRSS1_CTL_279_DATA 0x00000000 +#define DDRSS1_CTL_280_DATA 0x00000000 +#define DDRSS1_CTL_281_DATA 0x00000000 +#define DDRSS1_CTL_282_DATA 0x00000000 +#define DDRSS1_CTL_283_DATA 0x00000000 +#define DDRSS1_CTL_284_DATA 0x00000000 +#define DDRSS1_CTL_285_DATA 0x00000000 +#define DDRSS1_CTL_286_DATA 0x00040101 +#define DDRSS1_CTL_287_DATA 0x04010100 +#define DDRSS1_CTL_288_DATA 0x00000000 +#define DDRSS1_CTL_289_DATA 0x00000000 +#define DDRSS1_CTL_290_DATA 0x03030300 +#define DDRSS1_CTL_291_DATA 0x00000001 +#define DDRSS1_CTL_292_DATA 0x00000000 +#define DDRSS1_CTL_293_DATA 0x00000000 +#define DDRSS1_CTL_294_DATA 0x00000000 +#define DDRSS1_CTL_295_DATA 0x00000000 +#define DDRSS1_CTL_296_DATA 0x00000000 +#define DDRSS1_CTL_297_DATA 0x00000000 +#define DDRSS1_CTL_298_DATA 0x00000000 +#define DDRSS1_CTL_299_DATA 0x00000000 +#define DDRSS1_CTL_300_DATA 0x00000000 +#define DDRSS1_CTL_301_DATA 0x00000000 +#define DDRSS1_CTL_302_DATA 0x00000000 +#define DDRSS1_CTL_303_DATA 0x00000000 +#define DDRSS1_CTL_304_DATA 0x00000000 +#define DDRSS1_CTL_305_DATA 0x00000000 +#define DDRSS1_CTL_306_DATA 0x00000000 +#define DDRSS1_CTL_307_DATA 0x00000000 +#define DDRSS1_CTL_308_DATA 0x00000000 +#define DDRSS1_CTL_309_DATA 0x00000000 +#define DDRSS1_CTL_310_DATA 0x00000000 +#define DDRSS1_CTL_311_DATA 0x00000000 +#define DDRSS1_CTL_312_DATA 0x00000000 +#define DDRSS1_CTL_313_DATA 0x01000000 +#define DDRSS1_CTL_314_DATA 0x00020201 +#define DDRSS1_CTL_315_DATA 0x01000101 +#define DDRSS1_CTL_316_DATA 0x01010001 +#define DDRSS1_CTL_317_DATA 0x00010101 +#define DDRSS1_CTL_318_DATA 0x050A0A03 +#define DDRSS1_CTL_319_DATA 0x10081F1F +#define DDRSS1_CTL_320_DATA 0x00090310 +#define DDRSS1_CTL_321_DATA 0x0B0C030F +#define DDRSS1_CTL_322_DATA 0x0B0C0306 +#define DDRSS1_CTL_323_DATA 0x0C090006 +#define DDRSS1_CTL_324_DATA 0x0100000C +#define DDRSS1_CTL_325_DATA 0x08040801 +#define DDRSS1_CTL_326_DATA 0x00000004 +#define DDRSS1_CTL_327_DATA 0x00000000 +#define DDRSS1_CTL_328_DATA 0x00010000 +#define DDRSS1_CTL_329_DATA 0x00280D00 +#define DDRSS1_CTL_330_DATA 0x00000001 +#define DDRSS1_CTL_331_DATA 0x00030001 +#define DDRSS1_CTL_332_DATA 0x00000000 +#define DDRSS1_CTL_333_DATA 0x00000000 +#define DDRSS1_CTL_334_DATA 0x00000000 +#define DDRSS1_CTL_335_DATA 0x00000000 +#define DDRSS1_CTL_336_DATA 0x00000000 +#define DDRSS1_CTL_337_DATA 0x00000000 +#define DDRSS1_CTL_338_DATA 0x00000000 +#define DDRSS1_CTL_339_DATA 0x00000000 +#define DDRSS1_CTL_340_DATA 0x01000000 +#define DDRSS1_CTL_341_DATA 0x00000001 +#define DDRSS1_CTL_342_DATA 0x00010100 +#define DDRSS1_CTL_343_DATA 0x03030000 +#define DDRSS1_CTL_344_DATA 0x00000000 +#define DDRSS1_CTL_345_DATA 0x00000000 +#define DDRSS1_CTL_346_DATA 0x00000000 +#define DDRSS1_CTL_347_DATA 0x00000000 +#define DDRSS1_CTL_348_DATA 0x00000000 +#define DDRSS1_CTL_349_DATA 0x00000000 +#define DDRSS1_CTL_350_DATA 0x00000000 +#define DDRSS1_CTL_351_DATA 0x00000000 +#define DDRSS1_CTL_352_DATA 0x00000000 +#define DDRSS1_CTL_353_DATA 0x00000000 +#define DDRSS1_CTL_354_DATA 0x00000000 +#define DDRSS1_CTL_355_DATA 0x00000000 +#define DDRSS1_CTL_356_DATA 0x00000000 +#define DDRSS1_CTL_357_DATA 0x00000000 +#define DDRSS1_CTL_358_DATA 0x00000000 +#define DDRSS1_CTL_359_DATA 0x00000000 +#define DDRSS1_CTL_360_DATA 0x000556AA +#define DDRSS1_CTL_361_DATA 0x000AAAAA +#define DDRSS1_CTL_362_DATA 0x000AA955 +#define DDRSS1_CTL_363_DATA 0x00055555 +#define DDRSS1_CTL_364_DATA 0x000B3133 +#define DDRSS1_CTL_365_DATA 0x0004CD33 +#define DDRSS1_CTL_366_DATA 0x0004CECC +#define DDRSS1_CTL_367_DATA 0x000B32CC +#define DDRSS1_CTL_368_DATA 0x00010300 +#define DDRSS1_CTL_369_DATA 0x03000100 +#define DDRSS1_CTL_370_DATA 0x00000000 +#define DDRSS1_CTL_371_DATA 0x00000000 +#define DDRSS1_CTL_372_DATA 0x00000000 +#define DDRSS1_CTL_373_DATA 0x00000000 +#define DDRSS1_CTL_374_DATA 0x00000000 +#define DDRSS1_CTL_375_DATA 0x00000000 +#define DDRSS1_CTL_376_DATA 0x00000000 +#define DDRSS1_CTL_377_DATA 0x00010000 +#define DDRSS1_CTL_378_DATA 0x00000404 +#define DDRSS1_CTL_379_DATA 0x00000000 +#define DDRSS1_CTL_380_DATA 0x00000000 +#define DDRSS1_CTL_381_DATA 0x00000000 +#define DDRSS1_CTL_382_DATA 0x00000000 +#define DDRSS1_CTL_383_DATA 0x00000000 +#define DDRSS1_CTL_384_DATA 0x00000000 +#define DDRSS1_CTL_385_DATA 0x00000000 +#define DDRSS1_CTL_386_DATA 0x00000000 +#define DDRSS1_CTL_387_DATA 0x3A3A1B00 +#define DDRSS1_CTL_388_DATA 0x000A0000 +#define DDRSS1_CTL_389_DATA 0x000000C6 +#define DDRSS1_CTL_390_DATA 0x00000200 +#define DDRSS1_CTL_391_DATA 0x00000200 +#define DDRSS1_CTL_392_DATA 0x00000200 +#define DDRSS1_CTL_393_DATA 0x00000200 +#define DDRSS1_CTL_394_DATA 0x00000252 +#define DDRSS1_CTL_395_DATA 0x000007BC +#define DDRSS1_CTL_396_DATA 0x00000204 +#define DDRSS1_CTL_397_DATA 0x0000206A +#define DDRSS1_CTL_398_DATA 0x00000200 +#define DDRSS1_CTL_399_DATA 0x00000200 +#define DDRSS1_CTL_400_DATA 0x00000200 +#define DDRSS1_CTL_401_DATA 0x00000200 +#define DDRSS1_CTL_402_DATA 0x0000613E +#define DDRSS1_CTL_403_DATA 0x00014424 +#define DDRSS1_CTL_404_DATA 0x00000E15 +#define DDRSS1_CTL_405_DATA 0x0000206A +#define DDRSS1_CTL_406_DATA 0x00000200 +#define DDRSS1_CTL_407_DATA 0x00000200 +#define DDRSS1_CTL_408_DATA 0x00000200 +#define DDRSS1_CTL_409_DATA 0x00000200 +#define DDRSS1_CTL_410_DATA 0x0000613E +#define DDRSS1_CTL_411_DATA 0x00014424 +#define DDRSS1_CTL_412_DATA 0x02020E15 +#define DDRSS1_CTL_413_DATA 0x03030202 +#define DDRSS1_CTL_414_DATA 0x00000022 +#define DDRSS1_CTL_415_DATA 0x00000000 +#define DDRSS1_CTL_416_DATA 0x00000000 +#define DDRSS1_CTL_417_DATA 0x00001403 +#define DDRSS1_CTL_418_DATA 0x000007D0 +#define DDRSS1_CTL_419_DATA 0x00000000 +#define DDRSS1_CTL_420_DATA 0x00000000 +#define DDRSS1_CTL_421_DATA 0x00030000 +#define DDRSS1_CTL_422_DATA 0x0007001F +#define DDRSS1_CTL_423_DATA 0x001B0033 +#define DDRSS1_CTL_424_DATA 0x001B0033 +#define DDRSS1_CTL_425_DATA 0x00000000 +#define DDRSS1_CTL_426_DATA 0x00000000 +#define DDRSS1_CTL_427_DATA 0x02000000 +#define DDRSS1_CTL_428_DATA 0x01000404 +#define DDRSS1_CTL_429_DATA 0x0B1E0B1E +#define DDRSS1_CTL_430_DATA 0x00000105 +#define DDRSS1_CTL_431_DATA 0x00010101 +#define DDRSS1_CTL_432_DATA 0x00010101 +#define DDRSS1_CTL_433_DATA 0x00010001 +#define DDRSS1_CTL_434_DATA 0x00000101 +#define DDRSS1_CTL_435_DATA 0x02000201 +#define DDRSS1_CTL_436_DATA 0x02010000 +#define DDRSS1_CTL_437_DATA 0x00000200 +#define DDRSS1_CTL_438_DATA 0x28060000 +#define DDRSS1_CTL_439_DATA 0x00000128 +#define DDRSS1_CTL_440_DATA 0xFFFFFFFF +#define DDRSS1_CTL_441_DATA 0xFFFFFFFF +#define DDRSS1_CTL_442_DATA 0x00000000 +#define DDRSS1_CTL_443_DATA 0x00000000 +#define DDRSS1_CTL_444_DATA 0x00000000 +#define DDRSS1_CTL_445_DATA 0x00000000 +#define DDRSS1_CTL_446_DATA 0x00000000 +#define DDRSS1_CTL_447_DATA 0x00000000 +#define DDRSS1_CTL_448_DATA 0x00000000 +#define DDRSS1_CTL_449_DATA 0x00000000 +#define DDRSS1_CTL_450_DATA 0x00000000 +#define DDRSS1_CTL_451_DATA 0x00000000 +#define DDRSS1_CTL_452_DATA 0x00000000 +#define DDRSS1_CTL_453_DATA 0x00000000 +#define DDRSS1_CTL_454_DATA 0x00000000 +#define DDRSS1_CTL_455_DATA 0x00000000 +#define DDRSS1_CTL_456_DATA 0x00000000 +#define DDRSS1_CTL_457_DATA 0x00000000 +#define DDRSS1_CTL_458_DATA 0x00000000 + +#define DDRSS1_PI_00_DATA 0x00000B00 +#define DDRSS1_PI_01_DATA 0x00000000 +#define DDRSS1_PI_02_DATA 0x00000000 +#define DDRSS1_PI_03_DATA 0x00000000 +#define DDRSS1_PI_04_DATA 0x00000000 +#define DDRSS1_PI_05_DATA 0x00000101 +#define DDRSS1_PI_06_DATA 0x00640000 +#define DDRSS1_PI_07_DATA 0x00000001 +#define DDRSS1_PI_08_DATA 0x00000000 +#define DDRSS1_PI_09_DATA 0x00000000 +#define DDRSS1_PI_10_DATA 0x00000000 +#define DDRSS1_PI_11_DATA 0x00000000 +#define DDRSS1_PI_12_DATA 0x00000007 +#define DDRSS1_PI_13_DATA 0x00010002 +#define DDRSS1_PI_14_DATA 0x0800000F +#define DDRSS1_PI_15_DATA 0x00000103 +#define DDRSS1_PI_16_DATA 0x00000005 +#define DDRSS1_PI_17_DATA 0x00000000 +#define DDRSS1_PI_18_DATA 0x00000000 +#define DDRSS1_PI_19_DATA 0x00000000 +#define DDRSS1_PI_20_DATA 0x00000000 +#define DDRSS1_PI_21_DATA 0x00000000 +#define DDRSS1_PI_22_DATA 0x00000000 +#define DDRSS1_PI_23_DATA 0x00000000 +#define DDRSS1_PI_24_DATA 0x00000000 +#define DDRSS1_PI_25_DATA 0x00000000 +#define DDRSS1_PI_26_DATA 0x00010100 +#define DDRSS1_PI_27_DATA 0x00280A00 +#define DDRSS1_PI_28_DATA 0x00000000 +#define DDRSS1_PI_29_DATA 0x0F000000 +#define DDRSS1_PI_30_DATA 0x00003200 +#define DDRSS1_PI_31_DATA 0x00000000 +#define DDRSS1_PI_32_DATA 0x00000000 +#define DDRSS1_PI_33_DATA 0x01010102 +#define DDRSS1_PI_34_DATA 0x00000000 +#define DDRSS1_PI_35_DATA 0x000000AA +#define DDRSS1_PI_36_DATA 0x00000055 +#define DDRSS1_PI_37_DATA 0x000000B5 +#define DDRSS1_PI_38_DATA 0x0000004A +#define DDRSS1_PI_39_DATA 0x00000056 +#define DDRSS1_PI_40_DATA 0x000000A9 +#define DDRSS1_PI_41_DATA 0x000000A9 +#define DDRSS1_PI_42_DATA 0x000000B5 +#define DDRSS1_PI_43_DATA 0x00000000 +#define DDRSS1_PI_44_DATA 0x00000000 +#define DDRSS1_PI_45_DATA 0x000F0F00 +#define DDRSS1_PI_46_DATA 0x0000001B +#define DDRSS1_PI_47_DATA 0x000007D0 +#define DDRSS1_PI_48_DATA 0x00000300 +#define DDRSS1_PI_49_DATA 0x00000000 +#define DDRSS1_PI_50_DATA 0x00000000 +#define DDRSS1_PI_51_DATA 0x01000000 +#define DDRSS1_PI_52_DATA 0x00010101 +#define DDRSS1_PI_53_DATA 0x00000000 +#define DDRSS1_PI_54_DATA 0x00030000 +#define DDRSS1_PI_55_DATA 0x0F000000 +#define DDRSS1_PI_56_DATA 0x00000017 +#define DDRSS1_PI_57_DATA 0x00000000 +#define DDRSS1_PI_58_DATA 0x00000000 +#define DDRSS1_PI_59_DATA 0x00000000 +#define DDRSS1_PI_60_DATA 0x0A0A140A +#define DDRSS1_PI_61_DATA 0x10020101 +#define DDRSS1_PI_62_DATA 0x00020805 +#define DDRSS1_PI_63_DATA 0x01000404 +#define DDRSS1_PI_64_DATA 0x00000000 +#define DDRSS1_PI_65_DATA 0x00000000 +#define DDRSS1_PI_66_DATA 0x00000100 +#define DDRSS1_PI_67_DATA 0x0001010F +#define DDRSS1_PI_68_DATA 0x00340000 +#define DDRSS1_PI_69_DATA 0x00000000 +#define DDRSS1_PI_70_DATA 0x00000000 +#define DDRSS1_PI_71_DATA 0x0000FFFF +#define DDRSS1_PI_72_DATA 0x00000000 +#define DDRSS1_PI_73_DATA 0x00080000 +#define DDRSS1_PI_74_DATA 0x02000200 +#define DDRSS1_PI_75_DATA 0x01000100 +#define DDRSS1_PI_76_DATA 0x01000000 +#define DDRSS1_PI_77_DATA 0x02000200 +#define DDRSS1_PI_78_DATA 0x00000200 +#define DDRSS1_PI_79_DATA 0x00000000 +#define DDRSS1_PI_80_DATA 0x00000000 +#define DDRSS1_PI_81_DATA 0x00000000 +#define DDRSS1_PI_82_DATA 0x00000000 +#define DDRSS1_PI_83_DATA 0x00000000 +#define DDRSS1_PI_84_DATA 0x00000000 +#define DDRSS1_PI_85_DATA 0x00000000 +#define DDRSS1_PI_86_DATA 0x00000000 +#define DDRSS1_PI_87_DATA 0x00000000 +#define DDRSS1_PI_88_DATA 0x00000000 +#define DDRSS1_PI_89_DATA 0x00000000 +#define DDRSS1_PI_90_DATA 0x00000000 +#define DDRSS1_PI_91_DATA 0x00000400 +#define DDRSS1_PI_92_DATA 0x02010000 +#define DDRSS1_PI_93_DATA 0x00080003 +#define DDRSS1_PI_94_DATA 0x00080000 +#define DDRSS1_PI_95_DATA 0x00000001 +#define DDRSS1_PI_96_DATA 0x00000000 +#define DDRSS1_PI_97_DATA 0x0000AA00 +#define DDRSS1_PI_98_DATA 0x00000000 +#define DDRSS1_PI_99_DATA 0x00000000 +#define DDRSS1_PI_100_DATA 0x00010000 +#define DDRSS1_PI_101_DATA 0x00000000 +#define DDRSS1_PI_102_DATA 0x00000000 +#define DDRSS1_PI_103_DATA 0x00000000 +#define DDRSS1_PI_104_DATA 0x00000000 +#define DDRSS1_PI_105_DATA 0x00000000 +#define DDRSS1_PI_106_DATA 0x00000000 +#define DDRSS1_PI_107_DATA 0x00000000 +#define DDRSS1_PI_108_DATA 0x00000000 +#define DDRSS1_PI_109_DATA 0x00000000 +#define DDRSS1_PI_110_DATA 0x00000000 +#define DDRSS1_PI_111_DATA 0x00000000 +#define DDRSS1_PI_112_DATA 0x00000000 +#define DDRSS1_PI_113_DATA 0x00000000 +#define DDRSS1_PI_114_DATA 0x00000000 +#define DDRSS1_PI_115_DATA 0x00000000 +#define DDRSS1_PI_116_DATA 0x00000000 +#define DDRSS1_PI_117_DATA 0x00000000 +#define DDRSS1_PI_118_DATA 0x00000000 +#define DDRSS1_PI_119_DATA 0x00000000 +#define DDRSS1_PI_120_DATA 0x00000000 +#define DDRSS1_PI_121_DATA 0x00000000 +#define DDRSS1_PI_122_DATA 0x00000000 +#define DDRSS1_PI_123_DATA 0x00000000 +#define DDRSS1_PI_124_DATA 0x00000000 +#define DDRSS1_PI_125_DATA 0x00000008 +#define DDRSS1_PI_126_DATA 0x00000000 +#define DDRSS1_PI_127_DATA 0x00000000 +#define DDRSS1_PI_128_DATA 0x00000000 +#define DDRSS1_PI_129_DATA 0x00000000 +#define DDRSS1_PI_130_DATA 0x00000000 +#define DDRSS1_PI_131_DATA 0x00000000 +#define DDRSS1_PI_132_DATA 0x00000000 +#define DDRSS1_PI_133_DATA 0x00000000 +#define DDRSS1_PI_134_DATA 0x00000002 +#define DDRSS1_PI_135_DATA 0x00000000 +#define DDRSS1_PI_136_DATA 0x00000000 +#define DDRSS1_PI_137_DATA 0x0000000A +#define DDRSS1_PI_138_DATA 0x00000019 +#define DDRSS1_PI_139_DATA 0x00000100 +#define DDRSS1_PI_140_DATA 0x00000000 +#define DDRSS1_PI_141_DATA 0x00000000 +#define DDRSS1_PI_142_DATA 0x00000000 +#define DDRSS1_PI_143_DATA 0x00000000 +#define DDRSS1_PI_144_DATA 0x01000000 +#define DDRSS1_PI_145_DATA 0x00010003 +#define DDRSS1_PI_146_DATA 0x02000101 +#define DDRSS1_PI_147_DATA 0x01030001 +#define DDRSS1_PI_148_DATA 0x00010400 +#define DDRSS1_PI_149_DATA 0x06000105 +#define DDRSS1_PI_150_DATA 0x01070001 +#define DDRSS1_PI_151_DATA 0x00000000 +#define DDRSS1_PI_152_DATA 0x00000000 +#define DDRSS1_PI_153_DATA 0x00000000 +#define DDRSS1_PI_154_DATA 0x00010001 +#define DDRSS1_PI_155_DATA 0x00000000 +#define DDRSS1_PI_156_DATA 0x00000000 +#define DDRSS1_PI_157_DATA 0x00000000 +#define DDRSS1_PI_158_DATA 0x00000000 +#define DDRSS1_PI_159_DATA 0x00000401 +#define DDRSS1_PI_160_DATA 0x00000000 +#define DDRSS1_PI_161_DATA 0x00010000 +#define DDRSS1_PI_162_DATA 0x00000000 +#define DDRSS1_PI_163_DATA 0x2B2B0200 +#define DDRSS1_PI_164_DATA 0x00000034 +#define DDRSS1_PI_165_DATA 0x00000064 +#define DDRSS1_PI_166_DATA 0x00020064 +#define DDRSS1_PI_167_DATA 0x02000200 +#define DDRSS1_PI_168_DATA 0x48120C04 +#define DDRSS1_PI_169_DATA 0x00154812 +#define DDRSS1_PI_170_DATA 0x00000063 +#define DDRSS1_PI_171_DATA 0x0000032B +#define DDRSS1_PI_172_DATA 0x00001035 +#define DDRSS1_PI_173_DATA 0x0000032B +#define DDRSS1_PI_174_DATA 0x04001035 +#define DDRSS1_PI_175_DATA 0x01010404 +#define DDRSS1_PI_176_DATA 0x00001501 +#define DDRSS1_PI_177_DATA 0x00150015 +#define DDRSS1_PI_178_DATA 0x01000100 +#define DDRSS1_PI_179_DATA 0x00000100 +#define DDRSS1_PI_180_DATA 0x00000000 +#define DDRSS1_PI_181_DATA 0x01010101 +#define DDRSS1_PI_182_DATA 0x00000101 +#define DDRSS1_PI_183_DATA 0x00000000 +#define DDRSS1_PI_184_DATA 0x00000000 +#define DDRSS1_PI_185_DATA 0x15040000 +#define DDRSS1_PI_186_DATA 0x0E0E0215 +#define DDRSS1_PI_187_DATA 0x00040402 +#define DDRSS1_PI_188_DATA 0x000D0035 +#define DDRSS1_PI_189_DATA 0x00218049 +#define DDRSS1_PI_190_DATA 0x00218049 +#define DDRSS1_PI_191_DATA 0x01010101 +#define DDRSS1_PI_192_DATA 0x0004000E +#define DDRSS1_PI_193_DATA 0x00040216 +#define DDRSS1_PI_194_DATA 0x01000216 +#define DDRSS1_PI_195_DATA 0x000F000F +#define DDRSS1_PI_196_DATA 0x02170100 +#define DDRSS1_PI_197_DATA 0x01000217 +#define DDRSS1_PI_198_DATA 0x02170217 +#define DDRSS1_PI_199_DATA 0x32103200 +#define DDRSS1_PI_200_DATA 0x01013210 +#define DDRSS1_PI_201_DATA 0x0A070601 +#define DDRSS1_PI_202_DATA 0x1F130A0D +#define DDRSS1_PI_203_DATA 0x1F130A14 +#define DDRSS1_PI_204_DATA 0x0000C014 +#define DDRSS1_PI_205_DATA 0x00C01000 +#define DDRSS1_PI_206_DATA 0x00C01000 +#define DDRSS1_PI_207_DATA 0x00021000 +#define DDRSS1_PI_208_DATA 0x0024000E +#define DDRSS1_PI_209_DATA 0x00240216 +#define DDRSS1_PI_210_DATA 0x00110216 +#define DDRSS1_PI_211_DATA 0x32000056 +#define DDRSS1_PI_212_DATA 0x00000301 +#define DDRSS1_PI_213_DATA 0x005B0036 +#define DDRSS1_PI_214_DATA 0x03013212 +#define DDRSS1_PI_215_DATA 0x00003600 +#define DDRSS1_PI_216_DATA 0x3212005B +#define DDRSS1_PI_217_DATA 0x09000301 +#define DDRSS1_PI_218_DATA 0x04010504 +#define DDRSS1_PI_219_DATA 0x04000364 +#define DDRSS1_PI_220_DATA 0x0A032001 +#define DDRSS1_PI_221_DATA 0x2C31110A +#define DDRSS1_PI_222_DATA 0x00002918 +#define DDRSS1_PI_223_DATA 0x6000838E +#define DDRSS1_PI_224_DATA 0x1E202008 +#define DDRSS1_PI_225_DATA 0x2C311116 +#define DDRSS1_PI_226_DATA 0x00002918 +#define DDRSS1_PI_227_DATA 0x6000838E +#define DDRSS1_PI_228_DATA 0x1E202008 +#define DDRSS1_PI_229_DATA 0x0000C616 +#define DDRSS1_PI_230_DATA 0x000007BC +#define DDRSS1_PI_231_DATA 0x0000206A +#define DDRSS1_PI_232_DATA 0x00014424 +#define DDRSS1_PI_233_DATA 0x0000206A +#define DDRSS1_PI_234_DATA 0x00014424 +#define DDRSS1_PI_235_DATA 0x033B0016 +#define DDRSS1_PI_236_DATA 0x0303033B +#define DDRSS1_PI_237_DATA 0x002AF803 +#define DDRSS1_PI_238_DATA 0x0001ADAF +#define DDRSS1_PI_239_DATA 0x00000005 +#define DDRSS1_PI_240_DATA 0x0000006E +#define DDRSS1_PI_241_DATA 0x00000016 +#define DDRSS1_PI_242_DATA 0x000681C8 +#define DDRSS1_PI_243_DATA 0x0001ADAF +#define DDRSS1_PI_244_DATA 0x00000005 +#define DDRSS1_PI_245_DATA 0x000010A9 +#define DDRSS1_PI_246_DATA 0x0000033B +#define DDRSS1_PI_247_DATA 0x000681C8 +#define DDRSS1_PI_248_DATA 0x0001ADAF +#define DDRSS1_PI_249_DATA 0x00000005 +#define DDRSS1_PI_250_DATA 0x000010A9 +#define DDRSS1_PI_251_DATA 0x0100033B +#define DDRSS1_PI_252_DATA 0x00370040 +#define DDRSS1_PI_253_DATA 0x00010008 +#define DDRSS1_PI_254_DATA 0x08550040 +#define DDRSS1_PI_255_DATA 0x00010040 +#define DDRSS1_PI_256_DATA 0x08550040 +#define DDRSS1_PI_257_DATA 0x00000340 +#define DDRSS1_PI_258_DATA 0x006B006B +#define DDRSS1_PI_259_DATA 0x08040404 +#define DDRSS1_PI_260_DATA 0x00000055 +#define DDRSS1_PI_261_DATA 0x55083C5A +#define DDRSS1_PI_262_DATA 0x5A000000 +#define DDRSS1_PI_263_DATA 0x0055083C +#define DDRSS1_PI_264_DATA 0x3C5A0000 +#define DDRSS1_PI_265_DATA 0x00005508 +#define DDRSS1_PI_266_DATA 0x0C3C5A00 +#define DDRSS1_PI_267_DATA 0x080F0E0D +#define DDRSS1_PI_268_DATA 0x000B0A09 +#define DDRSS1_PI_269_DATA 0x00030201 +#define DDRSS1_PI_270_DATA 0x01000000 +#define DDRSS1_PI_271_DATA 0x04020201 +#define DDRSS1_PI_272_DATA 0x00080804 +#define DDRSS1_PI_273_DATA 0x00000000 +#define DDRSS1_PI_274_DATA 0x00000000 +#define DDRSS1_PI_275_DATA 0x00330084 +#define DDRSS1_PI_276_DATA 0x00160000 +#define DDRSS1_PI_277_DATA 0x35333FF4 +#define DDRSS1_PI_278_DATA 0x00160F27 +#define DDRSS1_PI_279_DATA 0x35333FF4 +#define DDRSS1_PI_280_DATA 0x00160F27 +#define DDRSS1_PI_281_DATA 0x00330084 +#define DDRSS1_PI_282_DATA 0x00160000 +#define DDRSS1_PI_283_DATA 0x35333FF4 +#define DDRSS1_PI_284_DATA 0x00160F27 +#define DDRSS1_PI_285_DATA 0x35333FF4 +#define DDRSS1_PI_286_DATA 0x00160F27 +#define DDRSS1_PI_287_DATA 0x00330084 +#define DDRSS1_PI_288_DATA 0x00160000 +#define DDRSS1_PI_289_DATA 0x35333FF4 +#define DDRSS1_PI_290_DATA 0x00160F27 +#define DDRSS1_PI_291_DATA 0x35333FF4 +#define DDRSS1_PI_292_DATA 0x00160F27 +#define DDRSS1_PI_293_DATA 0x00330084 +#define DDRSS1_PI_294_DATA 0x00160000 +#define DDRSS1_PI_295_DATA 0x35333FF4 +#define DDRSS1_PI_296_DATA 0x00160F27 +#define DDRSS1_PI_297_DATA 0x35333FF4 +#define DDRSS1_PI_298_DATA 0x00160F27 +#define DDRSS1_PI_299_DATA 0x00000000 + +#define DDRSS1_PHY_00_DATA 0x000004F0 +#define DDRSS1_PHY_01_DATA 0x00000000 +#define DDRSS1_PHY_02_DATA 0x00030200 +#define DDRSS1_PHY_03_DATA 0x00000000 +#define DDRSS1_PHY_04_DATA 0x00000000 +#define DDRSS1_PHY_05_DATA 0x01030000 +#define DDRSS1_PHY_06_DATA 0x00010000 +#define DDRSS1_PHY_07_DATA 0x01030004 +#define DDRSS1_PHY_08_DATA 0x01000000 +#define DDRSS1_PHY_09_DATA 0x00000000 +#define DDRSS1_PHY_10_DATA 0x00000000 +#define DDRSS1_PHY_11_DATA 0x01000001 +#define DDRSS1_PHY_12_DATA 0x00000100 +#define DDRSS1_PHY_13_DATA 0x000800C0 +#define DDRSS1_PHY_14_DATA 0x060100CC +#define DDRSS1_PHY_15_DATA 0x00030066 +#define DDRSS1_PHY_16_DATA 0x00000000 +#define DDRSS1_PHY_17_DATA 0x00000301 +#define DDRSS1_PHY_18_DATA 0x0000AAAA +#define DDRSS1_PHY_19_DATA 0x00005555 +#define DDRSS1_PHY_20_DATA 0x0000B5B5 +#define DDRSS1_PHY_21_DATA 0x00004A4A +#define DDRSS1_PHY_22_DATA 0x00005656 +#define DDRSS1_PHY_23_DATA 0x0000A9A9 +#define DDRSS1_PHY_24_DATA 0x0000A9A9 +#define DDRSS1_PHY_25_DATA 0x0000B5B5 +#define DDRSS1_PHY_26_DATA 0x00000000 +#define DDRSS1_PHY_27_DATA 0x00000000 +#define DDRSS1_PHY_28_DATA 0x2A000000 +#define DDRSS1_PHY_29_DATA 0x00000808 +#define DDRSS1_PHY_30_DATA 0x0F000000 +#define DDRSS1_PHY_31_DATA 0x00000F0F +#define DDRSS1_PHY_32_DATA 0x10400000 +#define DDRSS1_PHY_33_DATA 0x0C002006 +#define DDRSS1_PHY_34_DATA 0x00000000 +#define DDRSS1_PHY_35_DATA 0x00000000 +#define DDRSS1_PHY_36_DATA 0x55555555 +#define DDRSS1_PHY_37_DATA 0xAAAAAAAA +#define DDRSS1_PHY_38_DATA 0x55555555 +#define DDRSS1_PHY_39_DATA 0xAAAAAAAA +#define DDRSS1_PHY_40_DATA 0x00005555 +#define DDRSS1_PHY_41_DATA 0x01000100 +#define DDRSS1_PHY_42_DATA 0x00800180 +#define DDRSS1_PHY_43_DATA 0x00000001 +#define DDRSS1_PHY_44_DATA 0x00000000 +#define DDRSS1_PHY_45_DATA 0x00000000 +#define DDRSS1_PHY_46_DATA 0x00000000 +#define DDRSS1_PHY_47_DATA 0x00000000 +#define DDRSS1_PHY_48_DATA 0x00000000 +#define DDRSS1_PHY_49_DATA 0x00000000 +#define DDRSS1_PHY_50_DATA 0x00000000 +#define DDRSS1_PHY_51_DATA 0x00000000 +#define DDRSS1_PHY_52_DATA 0x00000000 +#define DDRSS1_PHY_53_DATA 0x00000000 +#define DDRSS1_PHY_54_DATA 0x00000000 +#define DDRSS1_PHY_55_DATA 0x00000000 +#define DDRSS1_PHY_56_DATA 0x00000000 +#define DDRSS1_PHY_57_DATA 0x00000000 +#define DDRSS1_PHY_58_DATA 0x00000000 +#define DDRSS1_PHY_59_DATA 0x00000000 +#define DDRSS1_PHY_60_DATA 0x00000000 +#define DDRSS1_PHY_61_DATA 0x00000000 +#define DDRSS1_PHY_62_DATA 0x00000000 +#define DDRSS1_PHY_63_DATA 0x00000000 +#define DDRSS1_PHY_64_DATA 0x00000000 +#define DDRSS1_PHY_65_DATA 0x00000000 +#define DDRSS1_PHY_66_DATA 0x00000104 +#define DDRSS1_PHY_67_DATA 0x00000120 +#define DDRSS1_PHY_68_DATA 0x00000000 +#define DDRSS1_PHY_69_DATA 0x00000000 +#define DDRSS1_PHY_70_DATA 0x00000000 +#define DDRSS1_PHY_71_DATA 0x00000000 +#define DDRSS1_PHY_72_DATA 0x00000000 +#define DDRSS1_PHY_73_DATA 0x00000000 +#define DDRSS1_PHY_74_DATA 0x00000000 +#define DDRSS1_PHY_75_DATA 0x00000001 +#define DDRSS1_PHY_76_DATA 0x07FF0000 +#define DDRSS1_PHY_77_DATA 0x0080081F +#define DDRSS1_PHY_78_DATA 0x00081020 +#define DDRSS1_PHY_79_DATA 0x04010000 +#define DDRSS1_PHY_80_DATA 0x00000000 +#define DDRSS1_PHY_81_DATA 0x00000000 +#define DDRSS1_PHY_82_DATA 0x00000000 +#define DDRSS1_PHY_83_DATA 0x00000100 +#define DDRSS1_PHY_84_DATA 0x01CC0C01 +#define DDRSS1_PHY_85_DATA 0x1003CC0C +#define DDRSS1_PHY_86_DATA 0x20000140 +#define DDRSS1_PHY_87_DATA 0x07FF0200 +#define DDRSS1_PHY_88_DATA 0x0000DD01 +#define DDRSS1_PHY_89_DATA 0x10100303 +#define DDRSS1_PHY_90_DATA 0x10101010 +#define DDRSS1_PHY_91_DATA 0x10101010 +#define DDRSS1_PHY_92_DATA 0x00021010 +#define DDRSS1_PHY_93_DATA 0x00100010 +#define DDRSS1_PHY_94_DATA 0x00100010 +#define DDRSS1_PHY_95_DATA 0x00100010 +#define DDRSS1_PHY_96_DATA 0x00100010 +#define DDRSS1_PHY_97_DATA 0x00050010 +#define DDRSS1_PHY_98_DATA 0x51517041 +#define DDRSS1_PHY_99_DATA 0x31C06001 +#define DDRSS1_PHY_100_DATA 0x07AB0340 +#define DDRSS1_PHY_101_DATA 0x00C0C001 +#define DDRSS1_PHY_102_DATA 0x0E0D0001 +#define DDRSS1_PHY_103_DATA 0x10001000 +#define DDRSS1_PHY_104_DATA 0x0C083E42 +#define DDRSS1_PHY_105_DATA 0x0F0C3701 +#define DDRSS1_PHY_106_DATA 0x01000140 +#define DDRSS1_PHY_107_DATA 0x0C000420 +#define DDRSS1_PHY_108_DATA 0x00000198 +#define DDRSS1_PHY_109_DATA 0x0A0000D0 +#define DDRSS1_PHY_110_DATA 0x00030200 +#define DDRSS1_PHY_111_DATA 0x02800000 +#define DDRSS1_PHY_112_DATA 0x80800000 +#define DDRSS1_PHY_113_DATA 0x000E2010 +#define DDRSS1_PHY_114_DATA 0x76543210 +#define DDRSS1_PHY_115_DATA 0x00000008 +#define DDRSS1_PHY_116_DATA 0x02800280 +#define DDRSS1_PHY_117_DATA 0x02800280 +#define DDRSS1_PHY_118_DATA 0x02800280 +#define DDRSS1_PHY_119_DATA 0x02800280 +#define DDRSS1_PHY_120_DATA 0x00000280 +#define DDRSS1_PHY_121_DATA 0x0000A000 +#define DDRSS1_PHY_122_DATA 0x00A000A0 +#define DDRSS1_PHY_123_DATA 0x00A000A0 +#define DDRSS1_PHY_124_DATA 0x00A000A0 +#define DDRSS1_PHY_125_DATA 0x00A000A0 +#define DDRSS1_PHY_126_DATA 0x00A000A0 +#define DDRSS1_PHY_127_DATA 0x00A000A0 +#define DDRSS1_PHY_128_DATA 0x00A000A0 +#define DDRSS1_PHY_129_DATA 0x00A000A0 +#define DDRSS1_PHY_130_DATA 0x01C200A0 +#define DDRSS1_PHY_131_DATA 0x01A00005 +#define DDRSS1_PHY_132_DATA 0x00000000 +#define DDRSS1_PHY_133_DATA 0x00000000 +#define DDRSS1_PHY_134_DATA 0x00080200 +#define DDRSS1_PHY_135_DATA 0x00000000 +#define DDRSS1_PHY_136_DATA 0x20202000 +#define DDRSS1_PHY_137_DATA 0x20202020 +#define DDRSS1_PHY_138_DATA 0xF0F02020 +#define DDRSS1_PHY_139_DATA 0x00000000 +#define DDRSS1_PHY_140_DATA 0x00000000 +#define DDRSS1_PHY_141_DATA 0x00000000 +#define DDRSS1_PHY_142_DATA 0x00000000 +#define DDRSS1_PHY_143_DATA 0x00000000 +#define DDRSS1_PHY_144_DATA 0x00000000 +#define DDRSS1_PHY_145_DATA 0x00000000 +#define DDRSS1_PHY_146_DATA 0x00000000 +#define DDRSS1_PHY_147_DATA 0x00000000 +#define DDRSS1_PHY_148_DATA 0x00000000 +#define DDRSS1_PHY_149_DATA 0x00000000 +#define DDRSS1_PHY_150_DATA 0x00000000 +#define DDRSS1_PHY_151_DATA 0x00000000 +#define DDRSS1_PHY_152_DATA 0x00000000 +#define DDRSS1_PHY_153_DATA 0x00000000 +#define DDRSS1_PHY_154_DATA 0x00000000 +#define DDRSS1_PHY_155_DATA 0x00000000 +#define DDRSS1_PHY_156_DATA 0x00000000 +#define DDRSS1_PHY_157_DATA 0x00000000 +#define DDRSS1_PHY_158_DATA 0x00000000 +#define DDRSS1_PHY_159_DATA 0x00000000 +#define DDRSS1_PHY_160_DATA 0x00000000 +#define DDRSS1_PHY_161_DATA 0x00000000 +#define DDRSS1_PHY_162_DATA 0x00000000 +#define DDRSS1_PHY_163_DATA 0x00000000 +#define DDRSS1_PHY_164_DATA 0x00000000 +#define DDRSS1_PHY_165_DATA 0x00000000 +#define DDRSS1_PHY_166_DATA 0x00000000 +#define DDRSS1_PHY_167_DATA 0x00000000 +#define DDRSS1_PHY_168_DATA 0x00000000 +#define DDRSS1_PHY_169_DATA 0x00000000 +#define DDRSS1_PHY_170_DATA 0x00000000 +#define DDRSS1_PHY_171_DATA 0x00000000 +#define DDRSS1_PHY_172_DATA 0x00000000 +#define DDRSS1_PHY_173_DATA 0x00000000 +#define DDRSS1_PHY_174_DATA 0x00000000 +#define DDRSS1_PHY_175_DATA 0x00000000 +#define DDRSS1_PHY_176_DATA 0x00000000 +#define DDRSS1_PHY_177_DATA 0x00000000 +#define DDRSS1_PHY_178_DATA 0x00000000 +#define DDRSS1_PHY_179_DATA 0x00000000 +#define DDRSS1_PHY_180_DATA 0x00000000 +#define DDRSS1_PHY_181_DATA 0x00000000 +#define DDRSS1_PHY_182_DATA 0x00000000 +#define DDRSS1_PHY_183_DATA 0x00000000 +#define DDRSS1_PHY_184_DATA 0x00000000 +#define DDRSS1_PHY_185_DATA 0x00000000 +#define DDRSS1_PHY_186_DATA 0x00000000 +#define DDRSS1_PHY_187_DATA 0x00000000 +#define DDRSS1_PHY_188_DATA 0x00000000 +#define DDRSS1_PHY_189_DATA 0x00000000 +#define DDRSS1_PHY_190_DATA 0x00000000 +#define DDRSS1_PHY_191_DATA 0x00000000 +#define DDRSS1_PHY_192_DATA 0x00000000 +#define DDRSS1_PHY_193_DATA 0x00000000 +#define DDRSS1_PHY_194_DATA 0x00000000 +#define DDRSS1_PHY_195_DATA 0x00000000 +#define DDRSS1_PHY_196_DATA 0x00000000 +#define DDRSS1_PHY_197_DATA 0x00000000 +#define DDRSS1_PHY_198_DATA 0x00000000 +#define DDRSS1_PHY_199_DATA 0x00000000 +#define DDRSS1_PHY_200_DATA 0x00000000 +#define DDRSS1_PHY_201_DATA 0x00000000 +#define DDRSS1_PHY_202_DATA 0x00000000 +#define DDRSS1_PHY_203_DATA 0x00000000 +#define DDRSS1_PHY_204_DATA 0x00000000 +#define DDRSS1_PHY_205_DATA 0x00000000 +#define DDRSS1_PHY_206_DATA 0x00000000 +#define DDRSS1_PHY_207_DATA 0x00000000 +#define DDRSS1_PHY_208_DATA 0x00000000 +#define DDRSS1_PHY_209_DATA 0x00000000 +#define DDRSS1_PHY_210_DATA 0x00000000 +#define DDRSS1_PHY_211_DATA 0x00000000 +#define DDRSS1_PHY_212_DATA 0x00000000 +#define DDRSS1_PHY_213_DATA 0x00000000 +#define DDRSS1_PHY_214_DATA 0x00000000 +#define DDRSS1_PHY_215_DATA 0x00000000 +#define DDRSS1_PHY_216_DATA 0x00000000 +#define DDRSS1_PHY_217_DATA 0x00000000 +#define DDRSS1_PHY_218_DATA 0x00000000 +#define DDRSS1_PHY_219_DATA 0x00000000 +#define DDRSS1_PHY_220_DATA 0x00000000 +#define DDRSS1_PHY_221_DATA 0x00000000 +#define DDRSS1_PHY_222_DATA 0x00000000 +#define DDRSS1_PHY_223_DATA 0x00000000 +#define DDRSS1_PHY_224_DATA 0x00000000 +#define DDRSS1_PHY_225_DATA 0x00000000 +#define DDRSS1_PHY_226_DATA 0x00000000 +#define DDRSS1_PHY_227_DATA 0x00000000 +#define DDRSS1_PHY_228_DATA 0x00000000 +#define DDRSS1_PHY_229_DATA 0x00000000 +#define DDRSS1_PHY_230_DATA 0x00000000 +#define DDRSS1_PHY_231_DATA 0x00000000 +#define DDRSS1_PHY_232_DATA 0x00000000 +#define DDRSS1_PHY_233_DATA 0x00000000 +#define DDRSS1_PHY_234_DATA 0x00000000 +#define DDRSS1_PHY_235_DATA 0x00000000 +#define DDRSS1_PHY_236_DATA 0x00000000 +#define DDRSS1_PHY_237_DATA 0x00000000 +#define DDRSS1_PHY_238_DATA 0x00000000 +#define DDRSS1_PHY_239_DATA 0x00000000 +#define DDRSS1_PHY_240_DATA 0x00000000 +#define DDRSS1_PHY_241_DATA 0x00000000 +#define DDRSS1_PHY_242_DATA 0x00000000 +#define DDRSS1_PHY_243_DATA 0x00000000 +#define DDRSS1_PHY_244_DATA 0x00000000 +#define DDRSS1_PHY_245_DATA 0x00000000 +#define DDRSS1_PHY_246_DATA 0x00000000 +#define DDRSS1_PHY_247_DATA 0x00000000 +#define DDRSS1_PHY_248_DATA 0x00000000 +#define DDRSS1_PHY_249_DATA 0x00000000 +#define DDRSS1_PHY_250_DATA 0x00000000 +#define DDRSS1_PHY_251_DATA 0x00000000 +#define DDRSS1_PHY_252_DATA 0x00000000 +#define DDRSS1_PHY_253_DATA 0x00000000 +#define DDRSS1_PHY_254_DATA 0x00000000 +#define DDRSS1_PHY_255_DATA 0x00000000 +#define DDRSS1_PHY_256_DATA 0x000004F0 +#define DDRSS1_PHY_257_DATA 0x00000000 +#define DDRSS1_PHY_258_DATA 0x00030200 +#define DDRSS1_PHY_259_DATA 0x00000000 +#define DDRSS1_PHY_260_DATA 0x00000000 +#define DDRSS1_PHY_261_DATA 0x01030000 +#define DDRSS1_PHY_262_DATA 0x00010000 +#define DDRSS1_PHY_263_DATA 0x01030004 +#define DDRSS1_PHY_264_DATA 0x01000000 +#define DDRSS1_PHY_265_DATA 0x00000000 +#define DDRSS1_PHY_266_DATA 0x00000000 +#define DDRSS1_PHY_267_DATA 0x01000001 +#define DDRSS1_PHY_268_DATA 0x00000100 +#define DDRSS1_PHY_269_DATA 0x000800C0 +#define DDRSS1_PHY_270_DATA 0x060100CC +#define DDRSS1_PHY_271_DATA 0x00030066 +#define DDRSS1_PHY_272_DATA 0x00000000 +#define DDRSS1_PHY_273_DATA 0x00000301 +#define DDRSS1_PHY_274_DATA 0x0000AAAA +#define DDRSS1_PHY_275_DATA 0x00005555 +#define DDRSS1_PHY_276_DATA 0x0000B5B5 +#define DDRSS1_PHY_277_DATA 0x00004A4A +#define DDRSS1_PHY_278_DATA 0x00005656 +#define DDRSS1_PHY_279_DATA 0x0000A9A9 +#define DDRSS1_PHY_280_DATA 0x0000A9A9 +#define DDRSS1_PHY_281_DATA 0x0000B5B5 +#define DDRSS1_PHY_282_DATA 0x00000000 +#define DDRSS1_PHY_283_DATA 0x00000000 +#define DDRSS1_PHY_284_DATA 0x2A000000 +#define DDRSS1_PHY_285_DATA 0x00000808 +#define DDRSS1_PHY_286_DATA 0x0F000000 +#define DDRSS1_PHY_287_DATA 0x00000F0F +#define DDRSS1_PHY_288_DATA 0x10400000 +#define DDRSS1_PHY_289_DATA 0x0C002006 +#define DDRSS1_PHY_290_DATA 0x00000000 +#define DDRSS1_PHY_291_DATA 0x00000000 +#define DDRSS1_PHY_292_DATA 0x55555555 +#define DDRSS1_PHY_293_DATA 0xAAAAAAAA +#define DDRSS1_PHY_294_DATA 0x55555555 +#define DDRSS1_PHY_295_DATA 0xAAAAAAAA +#define DDRSS1_PHY_296_DATA 0x00005555 +#define DDRSS1_PHY_297_DATA 0x01000100 +#define DDRSS1_PHY_298_DATA 0x00800180 +#define DDRSS1_PHY_299_DATA 0x00000000 +#define DDRSS1_PHY_300_DATA 0x00000000 +#define DDRSS1_PHY_301_DATA 0x00000000 +#define DDRSS1_PHY_302_DATA 0x00000000 +#define DDRSS1_PHY_303_DATA 0x00000000 +#define DDRSS1_PHY_304_DATA 0x00000000 +#define DDRSS1_PHY_305_DATA 0x00000000 +#define DDRSS1_PHY_306_DATA 0x00000000 +#define DDRSS1_PHY_307_DATA 0x00000000 +#define DDRSS1_PHY_308_DATA 0x00000000 +#define DDRSS1_PHY_309_DATA 0x00000000 +#define DDRSS1_PHY_310_DATA 0x00000000 +#define DDRSS1_PHY_311_DATA 0x00000000 +#define DDRSS1_PHY_312_DATA 0x00000000 +#define DDRSS1_PHY_313_DATA 0x00000000 +#define DDRSS1_PHY_314_DATA 0x00000000 +#define DDRSS1_PHY_315_DATA 0x00000000 +#define DDRSS1_PHY_316_DATA 0x00000000 +#define DDRSS1_PHY_317_DATA 0x00000000 +#define DDRSS1_PHY_318_DATA 0x00000000 +#define DDRSS1_PHY_319_DATA 0x00000000 +#define DDRSS1_PHY_320_DATA 0x00000000 +#define DDRSS1_PHY_321_DATA 0x00000000 +#define DDRSS1_PHY_322_DATA 0x00000104 +#define DDRSS1_PHY_323_DATA 0x00000120 +#define DDRSS1_PHY_324_DATA 0x00000000 +#define DDRSS1_PHY_325_DATA 0x00000000 +#define DDRSS1_PHY_326_DATA 0x00000000 +#define DDRSS1_PHY_327_DATA 0x00000000 +#define DDRSS1_PHY_328_DATA 0x00000000 +#define DDRSS1_PHY_329_DATA 0x00000000 +#define DDRSS1_PHY_330_DATA 0x00000000 +#define DDRSS1_PHY_331_DATA 0x00000001 +#define DDRSS1_PHY_332_DATA 0x07FF0000 +#define DDRSS1_PHY_333_DATA 0x0080081F +#define DDRSS1_PHY_334_DATA 0x00081020 +#define DDRSS1_PHY_335_DATA 0x04010000 +#define DDRSS1_PHY_336_DATA 0x00000000 +#define DDRSS1_PHY_337_DATA 0x00000000 +#define DDRSS1_PHY_338_DATA 0x00000000 +#define DDRSS1_PHY_339_DATA 0x00000100 +#define DDRSS1_PHY_340_DATA 0x01CC0C01 +#define DDRSS1_PHY_341_DATA 0x1003CC0C +#define DDRSS1_PHY_342_DATA 0x20000140 +#define DDRSS1_PHY_343_DATA 0x07FF0200 +#define DDRSS1_PHY_344_DATA 0x0000DD01 +#define DDRSS1_PHY_345_DATA 0x10100303 +#define DDRSS1_PHY_346_DATA 0x10101010 +#define DDRSS1_PHY_347_DATA 0x10101010 +#define DDRSS1_PHY_348_DATA 0x00021010 +#define DDRSS1_PHY_349_DATA 0x00100010 +#define DDRSS1_PHY_350_DATA 0x00100010 +#define DDRSS1_PHY_351_DATA 0x00100010 +#define DDRSS1_PHY_352_DATA 0x00100010 +#define DDRSS1_PHY_353_DATA 0x00050010 +#define DDRSS1_PHY_354_DATA 0x51517041 +#define DDRSS1_PHY_355_DATA 0x31C06001 +#define DDRSS1_PHY_356_DATA 0x07AB0340 +#define DDRSS1_PHY_357_DATA 0x00C0C001 +#define DDRSS1_PHY_358_DATA 0x0E0D0001 +#define DDRSS1_PHY_359_DATA 0x10001000 +#define DDRSS1_PHY_360_DATA 0x0C083E42 +#define DDRSS1_PHY_361_DATA 0x0F0C3701 +#define DDRSS1_PHY_362_DATA 0x01000140 +#define DDRSS1_PHY_363_DATA 0x0C000420 +#define DDRSS1_PHY_364_DATA 0x00000198 +#define DDRSS1_PHY_365_DATA 0x0A0000D0 +#define DDRSS1_PHY_366_DATA 0x00030200 +#define DDRSS1_PHY_367_DATA 0x02800000 +#define DDRSS1_PHY_368_DATA 0x80800000 +#define DDRSS1_PHY_369_DATA 0x000E2010 +#define DDRSS1_PHY_370_DATA 0x76543210 +#define DDRSS1_PHY_371_DATA 0x00000008 +#define DDRSS1_PHY_372_DATA 0x02800280 +#define DDRSS1_PHY_373_DATA 0x02800280 +#define DDRSS1_PHY_374_DATA 0x02800280 +#define DDRSS1_PHY_375_DATA 0x02800280 +#define DDRSS1_PHY_376_DATA 0x00000280 +#define DDRSS1_PHY_377_DATA 0x0000A000 +#define DDRSS1_PHY_378_DATA 0x00A000A0 +#define DDRSS1_PHY_379_DATA 0x00A000A0 +#define DDRSS1_PHY_380_DATA 0x00A000A0 +#define DDRSS1_PHY_381_DATA 0x00A000A0 +#define DDRSS1_PHY_382_DATA 0x00A000A0 +#define DDRSS1_PHY_383_DATA 0x00A000A0 +#define DDRSS1_PHY_384_DATA 0x00A000A0 +#define DDRSS1_PHY_385_DATA 0x00A000A0 +#define DDRSS1_PHY_386_DATA 0x01C200A0 +#define DDRSS1_PHY_387_DATA 0x01A00005 +#define DDRSS1_PHY_388_DATA 0x00000000 +#define DDRSS1_PHY_389_DATA 0x00000000 +#define DDRSS1_PHY_390_DATA 0x00080200 +#define DDRSS1_PHY_391_DATA 0x00000000 +#define DDRSS1_PHY_392_DATA 0x20202000 +#define DDRSS1_PHY_393_DATA 0x20202020 +#define DDRSS1_PHY_394_DATA 0xF0F02020 +#define DDRSS1_PHY_395_DATA 0x00000000 +#define DDRSS1_PHY_396_DATA 0x00000000 +#define DDRSS1_PHY_397_DATA 0x00000000 +#define DDRSS1_PHY_398_DATA 0x00000000 +#define DDRSS1_PHY_399_DATA 0x00000000 +#define DDRSS1_PHY_400_DATA 0x00000000 +#define DDRSS1_PHY_401_DATA 0x00000000 +#define DDRSS1_PHY_402_DATA 0x00000000 +#define DDRSS1_PHY_403_DATA 0x00000000 +#define DDRSS1_PHY_404_DATA 0x00000000 +#define DDRSS1_PHY_405_DATA 0x00000000 +#define DDRSS1_PHY_406_DATA 0x00000000 +#define DDRSS1_PHY_407_DATA 0x00000000 +#define DDRSS1_PHY_408_DATA 0x00000000 +#define DDRSS1_PHY_409_DATA 0x00000000 +#define DDRSS1_PHY_410_DATA 0x00000000 +#define DDRSS1_PHY_411_DATA 0x00000000 +#define DDRSS1_PHY_412_DATA 0x00000000 +#define DDRSS1_PHY_413_DATA 0x00000000 +#define DDRSS1_PHY_414_DATA 0x00000000 +#define DDRSS1_PHY_415_DATA 0x00000000 +#define DDRSS1_PHY_416_DATA 0x00000000 +#define DDRSS1_PHY_417_DATA 0x00000000 +#define DDRSS1_PHY_418_DATA 0x00000000 +#define DDRSS1_PHY_419_DATA 0x00000000 +#define DDRSS1_PHY_420_DATA 0x00000000 +#define DDRSS1_PHY_421_DATA 0x00000000 +#define DDRSS1_PHY_422_DATA 0x00000000 +#define DDRSS1_PHY_423_DATA 0x00000000 +#define DDRSS1_PHY_424_DATA 0x00000000 +#define DDRSS1_PHY_425_DATA 0x00000000 +#define DDRSS1_PHY_426_DATA 0x00000000 +#define DDRSS1_PHY_427_DATA 0x00000000 +#define DDRSS1_PHY_428_DATA 0x00000000 +#define DDRSS1_PHY_429_DATA 0x00000000 +#define DDRSS1_PHY_430_DATA 0x00000000 +#define DDRSS1_PHY_431_DATA 0x00000000 +#define DDRSS1_PHY_432_DATA 0x00000000 +#define DDRSS1_PHY_433_DATA 0x00000000 +#define DDRSS1_PHY_434_DATA 0x00000000 +#define DDRSS1_PHY_435_DATA 0x00000000 +#define DDRSS1_PHY_436_DATA 0x00000000 +#define DDRSS1_PHY_437_DATA 0x00000000 +#define DDRSS1_PHY_438_DATA 0x00000000 +#define DDRSS1_PHY_439_DATA 0x00000000 +#define DDRSS1_PHY_440_DATA 0x00000000 +#define DDRSS1_PHY_441_DATA 0x00000000 +#define DDRSS1_PHY_442_DATA 0x00000000 +#define DDRSS1_PHY_443_DATA 0x00000000 +#define DDRSS1_PHY_444_DATA 0x00000000 +#define DDRSS1_PHY_445_DATA 0x00000000 +#define DDRSS1_PHY_446_DATA 0x00000000 +#define DDRSS1_PHY_447_DATA 0x00000000 +#define DDRSS1_PHY_448_DATA 0x00000000 +#define DDRSS1_PHY_449_DATA 0x00000000 +#define DDRSS1_PHY_450_DATA 0x00000000 +#define DDRSS1_PHY_451_DATA 0x00000000 +#define DDRSS1_PHY_452_DATA 0x00000000 +#define DDRSS1_PHY_453_DATA 0x00000000 +#define DDRSS1_PHY_454_DATA 0x00000000 +#define DDRSS1_PHY_455_DATA 0x00000000 +#define DDRSS1_PHY_456_DATA 0x00000000 +#define DDRSS1_PHY_457_DATA 0x00000000 +#define DDRSS1_PHY_458_DATA 0x00000000 +#define DDRSS1_PHY_459_DATA 0x00000000 +#define DDRSS1_PHY_460_DATA 0x00000000 +#define DDRSS1_PHY_461_DATA 0x00000000 +#define DDRSS1_PHY_462_DATA 0x00000000 +#define DDRSS1_PHY_463_DATA 0x00000000 +#define DDRSS1_PHY_464_DATA 0x00000000 +#define DDRSS1_PHY_465_DATA 0x00000000 +#define DDRSS1_PHY_466_DATA 0x00000000 +#define DDRSS1_PHY_467_DATA 0x00000000 +#define DDRSS1_PHY_468_DATA 0x00000000 +#define DDRSS1_PHY_469_DATA 0x00000000 +#define DDRSS1_PHY_470_DATA 0x00000000 +#define DDRSS1_PHY_471_DATA 0x00000000 +#define DDRSS1_PHY_472_DATA 0x00000000 +#define DDRSS1_PHY_473_DATA 0x00000000 +#define DDRSS1_PHY_474_DATA 0x00000000 +#define DDRSS1_PHY_475_DATA 0x00000000 +#define DDRSS1_PHY_476_DATA 0x00000000 +#define DDRSS1_PHY_477_DATA 0x00000000 +#define DDRSS1_PHY_478_DATA 0x00000000 +#define DDRSS1_PHY_479_DATA 0x00000000 +#define DDRSS1_PHY_480_DATA 0x00000000 +#define DDRSS1_PHY_481_DATA 0x00000000 +#define DDRSS1_PHY_482_DATA 0x00000000 +#define DDRSS1_PHY_483_DATA 0x00000000 +#define DDRSS1_PHY_484_DATA 0x00000000 +#define DDRSS1_PHY_485_DATA 0x00000000 +#define DDRSS1_PHY_486_DATA 0x00000000 +#define DDRSS1_PHY_487_DATA 0x00000000 +#define DDRSS1_PHY_488_DATA 0x00000000 +#define DDRSS1_PHY_489_DATA 0x00000000 +#define DDRSS1_PHY_490_DATA 0x00000000 +#define DDRSS1_PHY_491_DATA 0x00000000 +#define DDRSS1_PHY_492_DATA 0x00000000 +#define DDRSS1_PHY_493_DATA 0x00000000 +#define DDRSS1_PHY_494_DATA 0x00000000 +#define DDRSS1_PHY_495_DATA 0x00000000 +#define DDRSS1_PHY_496_DATA 0x00000000 +#define DDRSS1_PHY_497_DATA 0x00000000 +#define DDRSS1_PHY_498_DATA 0x00000000 +#define DDRSS1_PHY_499_DATA 0x00000000 +#define DDRSS1_PHY_500_DATA 0x00000000 +#define DDRSS1_PHY_501_DATA 0x00000000 +#define DDRSS1_PHY_502_DATA 0x00000000 +#define DDRSS1_PHY_503_DATA 0x00000000 +#define DDRSS1_PHY_504_DATA 0x00000000 +#define DDRSS1_PHY_505_DATA 0x00000000 +#define DDRSS1_PHY_506_DATA 0x00000000 +#define DDRSS1_PHY_507_DATA 0x00000000 +#define DDRSS1_PHY_508_DATA 0x00000000 +#define DDRSS1_PHY_509_DATA 0x00000000 +#define DDRSS1_PHY_510_DATA 0x00000000 +#define DDRSS1_PHY_511_DATA 0x00000000 +#define DDRSS1_PHY_512_DATA 0x000004F0 +#define DDRSS1_PHY_513_DATA 0x00000000 +#define DDRSS1_PHY_514_DATA 0x00030200 +#define DDRSS1_PHY_515_DATA 0x00000000 +#define DDRSS1_PHY_516_DATA 0x00000000 +#define DDRSS1_PHY_517_DATA 0x01030000 +#define DDRSS1_PHY_518_DATA 0x00010000 +#define DDRSS1_PHY_519_DATA 0x01030004 +#define DDRSS1_PHY_520_DATA 0x01000000 +#define DDRSS1_PHY_521_DATA 0x00000000 +#define DDRSS1_PHY_522_DATA 0x00000000 +#define DDRSS1_PHY_523_DATA 0x01000001 +#define DDRSS1_PHY_524_DATA 0x00000100 +#define DDRSS1_PHY_525_DATA 0x000800C0 +#define DDRSS1_PHY_526_DATA 0x060100CC +#define DDRSS1_PHY_527_DATA 0x00030066 +#define DDRSS1_PHY_528_DATA 0x00000000 +#define DDRSS1_PHY_529_DATA 0x00000301 +#define DDRSS1_PHY_530_DATA 0x0000AAAA +#define DDRSS1_PHY_531_DATA 0x00005555 +#define DDRSS1_PHY_532_DATA 0x0000B5B5 +#define DDRSS1_PHY_533_DATA 0x00004A4A +#define DDRSS1_PHY_534_DATA 0x00005656 +#define DDRSS1_PHY_535_DATA 0x0000A9A9 +#define DDRSS1_PHY_536_DATA 0x0000A9A9 +#define DDRSS1_PHY_537_DATA 0x0000B5B5 +#define DDRSS1_PHY_538_DATA 0x00000000 +#define DDRSS1_PHY_539_DATA 0x00000000 +#define DDRSS1_PHY_540_DATA 0x2A000000 +#define DDRSS1_PHY_541_DATA 0x00000808 +#define DDRSS1_PHY_542_DATA 0x0F000000 +#define DDRSS1_PHY_543_DATA 0x00000F0F +#define DDRSS1_PHY_544_DATA 0x10400000 +#define DDRSS1_PHY_545_DATA 0x0C002006 +#define DDRSS1_PHY_546_DATA 0x00000000 +#define DDRSS1_PHY_547_DATA 0x00000000 +#define DDRSS1_PHY_548_DATA 0x55555555 +#define DDRSS1_PHY_549_DATA 0xAAAAAAAA +#define DDRSS1_PHY_550_DATA 0x55555555 +#define DDRSS1_PHY_551_DATA 0xAAAAAAAA +#define DDRSS1_PHY_552_DATA 0x00005555 +#define DDRSS1_PHY_553_DATA 0x01000100 +#define DDRSS1_PHY_554_DATA 0x00800180 +#define DDRSS1_PHY_555_DATA 0x00000001 +#define DDRSS1_PHY_556_DATA 0x00000000 +#define DDRSS1_PHY_557_DATA 0x00000000 +#define DDRSS1_PHY_558_DATA 0x00000000 +#define DDRSS1_PHY_559_DATA 0x00000000 +#define DDRSS1_PHY_560_DATA 0x00000000 +#define DDRSS1_PHY_561_DATA 0x00000000 +#define DDRSS1_PHY_562_DATA 0x00000000 +#define DDRSS1_PHY_563_DATA 0x00000000 +#define DDRSS1_PHY_564_DATA 0x00000000 +#define DDRSS1_PHY_565_DATA 0x00000000 +#define DDRSS1_PHY_566_DATA 0x00000000 +#define DDRSS1_PHY_567_DATA 0x00000000 +#define DDRSS1_PHY_568_DATA 0x00000000 +#define DDRSS1_PHY_569_DATA 0x00000000 +#define DDRSS1_PHY_570_DATA 0x00000000 +#define DDRSS1_PHY_571_DATA 0x00000000 +#define DDRSS1_PHY_572_DATA 0x00000000 +#define DDRSS1_PHY_573_DATA 0x00000000 +#define DDRSS1_PHY_574_DATA 0x00000000 +#define DDRSS1_PHY_575_DATA 0x00000000 +#define DDRSS1_PHY_576_DATA 0x00000000 +#define DDRSS1_PHY_577_DATA 0x00000000 +#define DDRSS1_PHY_578_DATA 0x00000104 +#define DDRSS1_PHY_579_DATA 0x00000120 +#define DDRSS1_PHY_580_DATA 0x00000000 +#define DDRSS1_PHY_581_DATA 0x00000000 +#define DDRSS1_PHY_582_DATA 0x00000000 +#define DDRSS1_PHY_583_DATA 0x00000000 +#define DDRSS1_PHY_584_DATA 0x00000000 +#define DDRSS1_PHY_585_DATA 0x00000000 +#define DDRSS1_PHY_586_DATA 0x00000000 +#define DDRSS1_PHY_587_DATA 0x00000001 +#define DDRSS1_PHY_588_DATA 0x07FF0000 +#define DDRSS1_PHY_589_DATA 0x0080081F +#define DDRSS1_PHY_590_DATA 0x00081020 +#define DDRSS1_PHY_591_DATA 0x04010000 +#define DDRSS1_PHY_592_DATA 0x00000000 +#define DDRSS1_PHY_593_DATA 0x00000000 +#define DDRSS1_PHY_594_DATA 0x00000000 +#define DDRSS1_PHY_595_DATA 0x00000100 +#define DDRSS1_PHY_596_DATA 0x01CC0C01 +#define DDRSS1_PHY_597_DATA 0x1003CC0C +#define DDRSS1_PHY_598_DATA 0x20000140 +#define DDRSS1_PHY_599_DATA 0x07FF0200 +#define DDRSS1_PHY_600_DATA 0x0000DD01 +#define DDRSS1_PHY_601_DATA 0x10100303 +#define DDRSS1_PHY_602_DATA 0x10101010 +#define DDRSS1_PHY_603_DATA 0x10101010 +#define DDRSS1_PHY_604_DATA 0x00021010 +#define DDRSS1_PHY_605_DATA 0x00100010 +#define DDRSS1_PHY_606_DATA 0x00100010 +#define DDRSS1_PHY_607_DATA 0x00100010 +#define DDRSS1_PHY_608_DATA 0x00100010 +#define DDRSS1_PHY_609_DATA 0x00050010 +#define DDRSS1_PHY_610_DATA 0x51517041 +#define DDRSS1_PHY_611_DATA 0x31C06001 +#define DDRSS1_PHY_612_DATA 0x07AB0340 +#define DDRSS1_PHY_613_DATA 0x00C0C001 +#define DDRSS1_PHY_614_DATA 0x0E0D0001 +#define DDRSS1_PHY_615_DATA 0x10001000 +#define DDRSS1_PHY_616_DATA 0x0C083E42 +#define DDRSS1_PHY_617_DATA 0x0F0C3701 +#define DDRSS1_PHY_618_DATA 0x01000140 +#define DDRSS1_PHY_619_DATA 0x0C000420 +#define DDRSS1_PHY_620_DATA 0x00000198 +#define DDRSS1_PHY_621_DATA 0x0A0000D0 +#define DDRSS1_PHY_622_DATA 0x00030200 +#define DDRSS1_PHY_623_DATA 0x02800000 +#define DDRSS1_PHY_624_DATA 0x80800000 +#define DDRSS1_PHY_625_DATA 0x000E2010 +#define DDRSS1_PHY_626_DATA 0x76543210 +#define DDRSS1_PHY_627_DATA 0x00000008 +#define DDRSS1_PHY_628_DATA 0x02800280 +#define DDRSS1_PHY_629_DATA 0x02800280 +#define DDRSS1_PHY_630_DATA 0x02800280 +#define DDRSS1_PHY_631_DATA 0x02800280 +#define DDRSS1_PHY_632_DATA 0x00000280 +#define DDRSS1_PHY_633_DATA 0x0000A000 +#define DDRSS1_PHY_634_DATA 0x00A000A0 +#define DDRSS1_PHY_635_DATA 0x00A000A0 +#define DDRSS1_PHY_636_DATA 0x00A000A0 +#define DDRSS1_PHY_637_DATA 0x00A000A0 +#define DDRSS1_PHY_638_DATA 0x00A000A0 +#define DDRSS1_PHY_639_DATA 0x00A000A0 +#define DDRSS1_PHY_640_DATA 0x00A000A0 +#define DDRSS1_PHY_641_DATA 0x00A000A0 +#define DDRSS1_PHY_642_DATA 0x01C200A0 +#define DDRSS1_PHY_643_DATA 0x01A00005 +#define DDRSS1_PHY_644_DATA 0x00000000 +#define DDRSS1_PHY_645_DATA 0x00000000 +#define DDRSS1_PHY_646_DATA 0x00080200 +#define DDRSS1_PHY_647_DATA 0x00000000 +#define DDRSS1_PHY_648_DATA 0x20202000 +#define DDRSS1_PHY_649_DATA 0x20202020 +#define DDRSS1_PHY_650_DATA 0xF0F02020 +#define DDRSS1_PHY_651_DATA 0x00000000 +#define DDRSS1_PHY_652_DATA 0x00000000 +#define DDRSS1_PHY_653_DATA 0x00000000 +#define DDRSS1_PHY_654_DATA 0x00000000 +#define DDRSS1_PHY_655_DATA 0x00000000 +#define DDRSS1_PHY_656_DATA 0x00000000 +#define DDRSS1_PHY_657_DATA 0x00000000 +#define DDRSS1_PHY_658_DATA 0x00000000 +#define DDRSS1_PHY_659_DATA 0x00000000 +#define DDRSS1_PHY_660_DATA 0x00000000 +#define DDRSS1_PHY_661_DATA 0x00000000 +#define DDRSS1_PHY_662_DATA 0x00000000 +#define DDRSS1_PHY_663_DATA 0x00000000 +#define DDRSS1_PHY_664_DATA 0x00000000 +#define DDRSS1_PHY_665_DATA 0x00000000 +#define DDRSS1_PHY_666_DATA 0x00000000 +#define DDRSS1_PHY_667_DATA 0x00000000 +#define DDRSS1_PHY_668_DATA 0x00000000 +#define DDRSS1_PHY_669_DATA 0x00000000 +#define DDRSS1_PHY_670_DATA 0x00000000 +#define DDRSS1_PHY_671_DATA 0x00000000 +#define DDRSS1_PHY_672_DATA 0x00000000 +#define DDRSS1_PHY_673_DATA 0x00000000 +#define DDRSS1_PHY_674_DATA 0x00000000 +#define DDRSS1_PHY_675_DATA 0x00000000 +#define DDRSS1_PHY_676_DATA 0x00000000 +#define DDRSS1_PHY_677_DATA 0x00000000 +#define DDRSS1_PHY_678_DATA 0x00000000 +#define DDRSS1_PHY_679_DATA 0x00000000 +#define DDRSS1_PHY_680_DATA 0x00000000 +#define DDRSS1_PHY_681_DATA 0x00000000 +#define DDRSS1_PHY_682_DATA 0x00000000 +#define DDRSS1_PHY_683_DATA 0x00000000 +#define DDRSS1_PHY_684_DATA 0x00000000 +#define DDRSS1_PHY_685_DATA 0x00000000 +#define DDRSS1_PHY_686_DATA 0x00000000 +#define DDRSS1_PHY_687_DATA 0x00000000 +#define DDRSS1_PHY_688_DATA 0x00000000 +#define DDRSS1_PHY_689_DATA 0x00000000 +#define DDRSS1_PHY_690_DATA 0x00000000 +#define DDRSS1_PHY_691_DATA 0x00000000 +#define DDRSS1_PHY_692_DATA 0x00000000 +#define DDRSS1_PHY_693_DATA 0x00000000 +#define DDRSS1_PHY_694_DATA 0x00000000 +#define DDRSS1_PHY_695_DATA 0x00000000 +#define DDRSS1_PHY_696_DATA 0x00000000 +#define DDRSS1_PHY_697_DATA 0x00000000 +#define DDRSS1_PHY_698_DATA 0x00000000 +#define DDRSS1_PHY_699_DATA 0x00000000 +#define DDRSS1_PHY_700_DATA 0x00000000 +#define DDRSS1_PHY_701_DATA 0x00000000 +#define DDRSS1_PHY_702_DATA 0x00000000 +#define DDRSS1_PHY_703_DATA 0x00000000 +#define DDRSS1_PHY_704_DATA 0x00000000 +#define DDRSS1_PHY_705_DATA 0x00000000 +#define DDRSS1_PHY_706_DATA 0x00000000 +#define DDRSS1_PHY_707_DATA 0x00000000 +#define DDRSS1_PHY_708_DATA 0x00000000 +#define DDRSS1_PHY_709_DATA 0x00000000 +#define DDRSS1_PHY_710_DATA 0x00000000 +#define DDRSS1_PHY_711_DATA 0x00000000 +#define DDRSS1_PHY_712_DATA 0x00000000 +#define DDRSS1_PHY_713_DATA 0x00000000 +#define DDRSS1_PHY_714_DATA 0x00000000 +#define DDRSS1_PHY_715_DATA 0x00000000 +#define DDRSS1_PHY_716_DATA 0x00000000 +#define DDRSS1_PHY_717_DATA 0x00000000 +#define DDRSS1_PHY_718_DATA 0x00000000 +#define DDRSS1_PHY_719_DATA 0x00000000 +#define DDRSS1_PHY_720_DATA 0x00000000 +#define DDRSS1_PHY_721_DATA 0x00000000 +#define DDRSS1_PHY_722_DATA 0x00000000 +#define DDRSS1_PHY_723_DATA 0x00000000 +#define DDRSS1_PHY_724_DATA 0x00000000 +#define DDRSS1_PHY_725_DATA 0x00000000 +#define DDRSS1_PHY_726_DATA 0x00000000 +#define DDRSS1_PHY_727_DATA 0x00000000 +#define DDRSS1_PHY_728_DATA 0x00000000 +#define DDRSS1_PHY_729_DATA 0x00000000 +#define DDRSS1_PHY_730_DATA 0x00000000 +#define DDRSS1_PHY_731_DATA 0x00000000 +#define DDRSS1_PHY_732_DATA 0x00000000 +#define DDRSS1_PHY_733_DATA 0x00000000 +#define DDRSS1_PHY_734_DATA 0x00000000 +#define DDRSS1_PHY_735_DATA 0x00000000 +#define DDRSS1_PHY_736_DATA 0x00000000 +#define DDRSS1_PHY_737_DATA 0x00000000 +#define DDRSS1_PHY_738_DATA 0x00000000 +#define DDRSS1_PHY_739_DATA 0x00000000 +#define DDRSS1_PHY_740_DATA 0x00000000 +#define DDRSS1_PHY_741_DATA 0x00000000 +#define DDRSS1_PHY_742_DATA 0x00000000 +#define DDRSS1_PHY_743_DATA 0x00000000 +#define DDRSS1_PHY_744_DATA 0x00000000 +#define DDRSS1_PHY_745_DATA 0x00000000 +#define DDRSS1_PHY_746_DATA 0x00000000 +#define DDRSS1_PHY_747_DATA 0x00000000 +#define DDRSS1_PHY_748_DATA 0x00000000 +#define DDRSS1_PHY_749_DATA 0x00000000 +#define DDRSS1_PHY_750_DATA 0x00000000 +#define DDRSS1_PHY_751_DATA 0x00000000 +#define DDRSS1_PHY_752_DATA 0x00000000 +#define DDRSS1_PHY_753_DATA 0x00000000 +#define DDRSS1_PHY_754_DATA 0x00000000 +#define DDRSS1_PHY_755_DATA 0x00000000 +#define DDRSS1_PHY_756_DATA 0x00000000 +#define DDRSS1_PHY_757_DATA 0x00000000 +#define DDRSS1_PHY_758_DATA 0x00000000 +#define DDRSS1_PHY_759_DATA 0x00000000 +#define DDRSS1_PHY_760_DATA 0x00000000 +#define DDRSS1_PHY_761_DATA 0x00000000 +#define DDRSS1_PHY_762_DATA 0x00000000 +#define DDRSS1_PHY_763_DATA 0x00000000 +#define DDRSS1_PHY_764_DATA 0x00000000 +#define DDRSS1_PHY_765_DATA 0x00000000 +#define DDRSS1_PHY_766_DATA 0x00000000 +#define DDRSS1_PHY_767_DATA 0x00000000 +#define DDRSS1_PHY_768_DATA 0x000004F0 +#define DDRSS1_PHY_769_DATA 0x00000000 +#define DDRSS1_PHY_770_DATA 0x00030200 +#define DDRSS1_PHY_771_DATA 0x00000000 +#define DDRSS1_PHY_772_DATA 0x00000000 +#define DDRSS1_PHY_773_DATA 0x01030000 +#define DDRSS1_PHY_774_DATA 0x00010000 +#define DDRSS1_PHY_775_DATA 0x01030004 +#define DDRSS1_PHY_776_DATA 0x01000000 +#define DDRSS1_PHY_777_DATA 0x00000000 +#define DDRSS1_PHY_778_DATA 0x00000000 +#define DDRSS1_PHY_779_DATA 0x01000001 +#define DDRSS1_PHY_780_DATA 0x00000100 +#define DDRSS1_PHY_781_DATA 0x000800C0 +#define DDRSS1_PHY_782_DATA 0x060100CC +#define DDRSS1_PHY_783_DATA 0x00030066 +#define DDRSS1_PHY_784_DATA 0x00000000 +#define DDRSS1_PHY_785_DATA 0x00000301 +#define DDRSS1_PHY_786_DATA 0x0000AAAA +#define DDRSS1_PHY_787_DATA 0x00005555 +#define DDRSS1_PHY_788_DATA 0x0000B5B5 +#define DDRSS1_PHY_789_DATA 0x00004A4A +#define DDRSS1_PHY_790_DATA 0x00005656 +#define DDRSS1_PHY_791_DATA 0x0000A9A9 +#define DDRSS1_PHY_792_DATA 0x0000A9A9 +#define DDRSS1_PHY_793_DATA 0x0000B5B5 +#define DDRSS1_PHY_794_DATA 0x00000000 +#define DDRSS1_PHY_795_DATA 0x00000000 +#define DDRSS1_PHY_796_DATA 0x2A000000 +#define DDRSS1_PHY_797_DATA 0x00000808 +#define DDRSS1_PHY_798_DATA 0x0F000000 +#define DDRSS1_PHY_799_DATA 0x00000F0F +#define DDRSS1_PHY_800_DATA 0x10400000 +#define DDRSS1_PHY_801_DATA 0x0C002006 +#define DDRSS1_PHY_802_DATA 0x00000000 +#define DDRSS1_PHY_803_DATA 0x00000000 +#define DDRSS1_PHY_804_DATA 0x55555555 +#define DDRSS1_PHY_805_DATA 0xAAAAAAAA +#define DDRSS1_PHY_806_DATA 0x55555555 +#define DDRSS1_PHY_807_DATA 0xAAAAAAAA +#define DDRSS1_PHY_808_DATA 0x00005555 +#define DDRSS1_PHY_809_DATA 0x01000100 +#define DDRSS1_PHY_810_DATA 0x00800180 +#define DDRSS1_PHY_811_DATA 0x00000000 +#define DDRSS1_PHY_812_DATA 0x00000000 +#define DDRSS1_PHY_813_DATA 0x00000000 +#define DDRSS1_PHY_814_DATA 0x00000000 +#define DDRSS1_PHY_815_DATA 0x00000000 +#define DDRSS1_PHY_816_DATA 0x00000000 +#define DDRSS1_PHY_817_DATA 0x00000000 +#define DDRSS1_PHY_818_DATA 0x00000000 +#define DDRSS1_PHY_819_DATA 0x00000000 +#define DDRSS1_PHY_820_DATA 0x00000000 +#define DDRSS1_PHY_821_DATA 0x00000000 +#define DDRSS1_PHY_822_DATA 0x00000000 +#define DDRSS1_PHY_823_DATA 0x00000000 +#define DDRSS1_PHY_824_DATA 0x00000000 +#define DDRSS1_PHY_825_DATA 0x00000000 +#define DDRSS1_PHY_826_DATA 0x00000000 +#define DDRSS1_PHY_827_DATA 0x00000000 +#define DDRSS1_PHY_828_DATA 0x00000000 +#define DDRSS1_PHY_829_DATA 0x00000000 +#define DDRSS1_PHY_830_DATA 0x00000000 +#define DDRSS1_PHY_831_DATA 0x00000000 +#define DDRSS1_PHY_832_DATA 0x00000000 +#define DDRSS1_PHY_833_DATA 0x00000000 +#define DDRSS1_PHY_834_DATA 0x00000104 +#define DDRSS1_PHY_835_DATA 0x00000120 +#define DDRSS1_PHY_836_DATA 0x00000000 +#define DDRSS1_PHY_837_DATA 0x00000000 +#define DDRSS1_PHY_838_DATA 0x00000000 +#define DDRSS1_PHY_839_DATA 0x00000000 +#define DDRSS1_PHY_840_DATA 0x00000000 +#define DDRSS1_PHY_841_DATA 0x00000000 +#define DDRSS1_PHY_842_DATA 0x00000000 +#define DDRSS1_PHY_843_DATA 0x00000001 +#define DDRSS1_PHY_844_DATA 0x07FF0000 +#define DDRSS1_PHY_845_DATA 0x0080081F +#define DDRSS1_PHY_846_DATA 0x00081020 +#define DDRSS1_PHY_847_DATA 0x04010000 +#define DDRSS1_PHY_848_DATA 0x00000000 +#define DDRSS1_PHY_849_DATA 0x00000000 +#define DDRSS1_PHY_850_DATA 0x00000000 +#define DDRSS1_PHY_851_DATA 0x00000100 +#define DDRSS1_PHY_852_DATA 0x01CC0C01 +#define DDRSS1_PHY_853_DATA 0x1003CC0C +#define DDRSS1_PHY_854_DATA 0x20000140 +#define DDRSS1_PHY_855_DATA 0x07FF0200 +#define DDRSS1_PHY_856_DATA 0x0000DD01 +#define DDRSS1_PHY_857_DATA 0x10100303 +#define DDRSS1_PHY_858_DATA 0x10101010 +#define DDRSS1_PHY_859_DATA 0x10101010 +#define DDRSS1_PHY_860_DATA 0x00021010 +#define DDRSS1_PHY_861_DATA 0x00100010 +#define DDRSS1_PHY_862_DATA 0x00100010 +#define DDRSS1_PHY_863_DATA 0x00100010 +#define DDRSS1_PHY_864_DATA 0x00100010 +#define DDRSS1_PHY_865_DATA 0x00050010 +#define DDRSS1_PHY_866_DATA 0x51517041 +#define DDRSS1_PHY_867_DATA 0x31C06001 +#define DDRSS1_PHY_868_DATA 0x07AB0340 +#define DDRSS1_PHY_869_DATA 0x00C0C001 +#define DDRSS1_PHY_870_DATA 0x0E0D0001 +#define DDRSS1_PHY_871_DATA 0x10001000 +#define DDRSS1_PHY_872_DATA 0x0C083E42 +#define DDRSS1_PHY_873_DATA 0x0F0C3701 +#define DDRSS1_PHY_874_DATA 0x01000140 +#define DDRSS1_PHY_875_DATA 0x0C000420 +#define DDRSS1_PHY_876_DATA 0x00000198 +#define DDRSS1_PHY_877_DATA 0x0A0000D0 +#define DDRSS1_PHY_878_DATA 0x00030200 +#define DDRSS1_PHY_879_DATA 0x02800000 +#define DDRSS1_PHY_880_DATA 0x80800000 +#define DDRSS1_PHY_881_DATA 0x000E2010 +#define DDRSS1_PHY_882_DATA 0x76543210 +#define DDRSS1_PHY_883_DATA 0x00000008 +#define DDRSS1_PHY_884_DATA 0x02800280 +#define DDRSS1_PHY_885_DATA 0x02800280 +#define DDRSS1_PHY_886_DATA 0x02800280 +#define DDRSS1_PHY_887_DATA 0x02800280 +#define DDRSS1_PHY_888_DATA 0x00000280 +#define DDRSS1_PHY_889_DATA 0x0000A000 +#define DDRSS1_PHY_890_DATA 0x00A000A0 +#define DDRSS1_PHY_891_DATA 0x00A000A0 +#define DDRSS1_PHY_892_DATA 0x00A000A0 +#define DDRSS1_PHY_893_DATA 0x00A000A0 +#define DDRSS1_PHY_894_DATA 0x00A000A0 +#define DDRSS1_PHY_895_DATA 0x00A000A0 +#define DDRSS1_PHY_896_DATA 0x00A000A0 +#define DDRSS1_PHY_897_DATA 0x00A000A0 +#define DDRSS1_PHY_898_DATA 0x01C200A0 +#define DDRSS1_PHY_899_DATA 0x01A00005 +#define DDRSS1_PHY_900_DATA 0x00000000 +#define DDRSS1_PHY_901_DATA 0x00000000 +#define DDRSS1_PHY_902_DATA 0x00080200 +#define DDRSS1_PHY_903_DATA 0x00000000 +#define DDRSS1_PHY_904_DATA 0x20202000 +#define DDRSS1_PHY_905_DATA 0x20202020 +#define DDRSS1_PHY_906_DATA 0xF0F02020 +#define DDRSS1_PHY_907_DATA 0x00000000 +#define DDRSS1_PHY_908_DATA 0x00000000 +#define DDRSS1_PHY_909_DATA 0x00000000 +#define DDRSS1_PHY_910_DATA 0x00000000 +#define DDRSS1_PHY_911_DATA 0x00000000 +#define DDRSS1_PHY_912_DATA 0x00000000 +#define DDRSS1_PHY_913_DATA 0x00000000 +#define DDRSS1_PHY_914_DATA 0x00000000 +#define DDRSS1_PHY_915_DATA 0x00000000 +#define DDRSS1_PHY_916_DATA 0x00000000 +#define DDRSS1_PHY_917_DATA 0x00000000 +#define DDRSS1_PHY_918_DATA 0x00000000 +#define DDRSS1_PHY_919_DATA 0x00000000 +#define DDRSS1_PHY_920_DATA 0x00000000 +#define DDRSS1_PHY_921_DATA 0x00000000 +#define DDRSS1_PHY_922_DATA 0x00000000 +#define DDRSS1_PHY_923_DATA 0x00000000 +#define DDRSS1_PHY_924_DATA 0x00000000 +#define DDRSS1_PHY_925_DATA 0x00000000 +#define DDRSS1_PHY_926_DATA 0x00000000 +#define DDRSS1_PHY_927_DATA 0x00000000 +#define DDRSS1_PHY_928_DATA 0x00000000 +#define DDRSS1_PHY_929_DATA 0x00000000 +#define DDRSS1_PHY_930_DATA 0x00000000 +#define DDRSS1_PHY_931_DATA 0x00000000 +#define DDRSS1_PHY_932_DATA 0x00000000 +#define DDRSS1_PHY_933_DATA 0x00000000 +#define DDRSS1_PHY_934_DATA 0x00000000 +#define DDRSS1_PHY_935_DATA 0x00000000 +#define DDRSS1_PHY_936_DATA 0x00000000 +#define DDRSS1_PHY_937_DATA 0x00000000 +#define DDRSS1_PHY_938_DATA 0x00000000 +#define DDRSS1_PHY_939_DATA 0x00000000 +#define DDRSS1_PHY_940_DATA 0x00000000 +#define DDRSS1_PHY_941_DATA 0x00000000 +#define DDRSS1_PHY_942_DATA 0x00000000 +#define DDRSS1_PHY_943_DATA 0x00000000 +#define DDRSS1_PHY_944_DATA 0x00000000 +#define DDRSS1_PHY_945_DATA 0x00000000 +#define DDRSS1_PHY_946_DATA 0x00000000 +#define DDRSS1_PHY_947_DATA 0x00000000 +#define DDRSS1_PHY_948_DATA 0x00000000 +#define DDRSS1_PHY_949_DATA 0x00000000 +#define DDRSS1_PHY_950_DATA 0x00000000 +#define DDRSS1_PHY_951_DATA 0x00000000 +#define DDRSS1_PHY_952_DATA 0x00000000 +#define DDRSS1_PHY_953_DATA 0x00000000 +#define DDRSS1_PHY_954_DATA 0x00000000 +#define DDRSS1_PHY_955_DATA 0x00000000 +#define DDRSS1_PHY_956_DATA 0x00000000 +#define DDRSS1_PHY_957_DATA 0x00000000 +#define DDRSS1_PHY_958_DATA 0x00000000 +#define DDRSS1_PHY_959_DATA 0x00000000 +#define DDRSS1_PHY_960_DATA 0x00000000 +#define DDRSS1_PHY_961_DATA 0x00000000 +#define DDRSS1_PHY_962_DATA 0x00000000 +#define DDRSS1_PHY_963_DATA 0x00000000 +#define DDRSS1_PHY_964_DATA 0x00000000 +#define DDRSS1_PHY_965_DATA 0x00000000 +#define DDRSS1_PHY_966_DATA 0x00000000 +#define DDRSS1_PHY_967_DATA 0x00000000 +#define DDRSS1_PHY_968_DATA 0x00000000 +#define DDRSS1_PHY_969_DATA 0x00000000 +#define DDRSS1_PHY_970_DATA 0x00000000 +#define DDRSS1_PHY_971_DATA 0x00000000 +#define DDRSS1_PHY_972_DATA 0x00000000 +#define DDRSS1_PHY_973_DATA 0x00000000 +#define DDRSS1_PHY_974_DATA 0x00000000 +#define DDRSS1_PHY_975_DATA 0x00000000 +#define DDRSS1_PHY_976_DATA 0x00000000 +#define DDRSS1_PHY_977_DATA 0x00000000 +#define DDRSS1_PHY_978_DATA 0x00000000 +#define DDRSS1_PHY_979_DATA 0x00000000 +#define DDRSS1_PHY_980_DATA 0x00000000 +#define DDRSS1_PHY_981_DATA 0x00000000 +#define DDRSS1_PHY_982_DATA 0x00000000 +#define DDRSS1_PHY_983_DATA 0x00000000 +#define DDRSS1_PHY_984_DATA 0x00000000 +#define DDRSS1_PHY_985_DATA 0x00000000 +#define DDRSS1_PHY_986_DATA 0x00000000 +#define DDRSS1_PHY_987_DATA 0x00000000 +#define DDRSS1_PHY_988_DATA 0x00000000 +#define DDRSS1_PHY_989_DATA 0x00000000 +#define DDRSS1_PHY_990_DATA 0x00000000 +#define DDRSS1_PHY_991_DATA 0x00000000 +#define DDRSS1_PHY_992_DATA 0x00000000 +#define DDRSS1_PHY_993_DATA 0x00000000 +#define DDRSS1_PHY_994_DATA 0x00000000 +#define DDRSS1_PHY_995_DATA 0x00000000 +#define DDRSS1_PHY_996_DATA 0x00000000 +#define DDRSS1_PHY_997_DATA 0x00000000 +#define DDRSS1_PHY_998_DATA 0x00000000 +#define DDRSS1_PHY_999_DATA 0x00000000 +#define DDRSS1_PHY_1000_DATA 0x00000000 +#define DDRSS1_PHY_1001_DATA 0x00000000 +#define DDRSS1_PHY_1002_DATA 0x00000000 +#define DDRSS1_PHY_1003_DATA 0x00000000 +#define DDRSS1_PHY_1004_DATA 0x00000000 +#define DDRSS1_PHY_1005_DATA 0x00000000 +#define DDRSS1_PHY_1006_DATA 0x00000000 +#define DDRSS1_PHY_1007_DATA 0x00000000 +#define DDRSS1_PHY_1008_DATA 0x00000000 +#define DDRSS1_PHY_1009_DATA 0x00000000 +#define DDRSS1_PHY_1010_DATA 0x00000000 +#define DDRSS1_PHY_1011_DATA 0x00000000 +#define DDRSS1_PHY_1012_DATA 0x00000000 +#define DDRSS1_PHY_1013_DATA 0x00000000 +#define DDRSS1_PHY_1014_DATA 0x00000000 +#define DDRSS1_PHY_1015_DATA 0x00000000 +#define DDRSS1_PHY_1016_DATA 0x00000000 +#define DDRSS1_PHY_1017_DATA 0x00000000 +#define DDRSS1_PHY_1018_DATA 0x00000000 +#define DDRSS1_PHY_1019_DATA 0x00000000 +#define DDRSS1_PHY_1020_DATA 0x00000000 +#define DDRSS1_PHY_1021_DATA 0x00000000 +#define DDRSS1_PHY_1022_DATA 0x00000000 +#define DDRSS1_PHY_1023_DATA 0x00000000 +#define DDRSS1_PHY_1024_DATA 0x00000000 +#define DDRSS1_PHY_1025_DATA 0x00000000 +#define DDRSS1_PHY_1026_DATA 0x00000000 +#define DDRSS1_PHY_1027_DATA 0x00000000 +#define DDRSS1_PHY_1028_DATA 0x00000000 +#define DDRSS1_PHY_1029_DATA 0x00000100 +#define DDRSS1_PHY_1030_DATA 0x00000200 +#define DDRSS1_PHY_1031_DATA 0x00000000 +#define DDRSS1_PHY_1032_DATA 0x00000000 +#define DDRSS1_PHY_1033_DATA 0x00000000 +#define DDRSS1_PHY_1034_DATA 0x00000000 +#define DDRSS1_PHY_1035_DATA 0x00400000 +#define DDRSS1_PHY_1036_DATA 0x00000080 +#define DDRSS1_PHY_1037_DATA 0x00DCBA98 +#define DDRSS1_PHY_1038_DATA 0x03000000 +#define DDRSS1_PHY_1039_DATA 0x00200000 +#define DDRSS1_PHY_1040_DATA 0x00000000 +#define DDRSS1_PHY_1041_DATA 0x00000000 +#define DDRSS1_PHY_1042_DATA 0x00000000 +#define DDRSS1_PHY_1043_DATA 0x00000000 +#define DDRSS1_PHY_1044_DATA 0x00000000 +#define DDRSS1_PHY_1045_DATA 0x0000002A +#define DDRSS1_PHY_1046_DATA 0x00000015 +#define DDRSS1_PHY_1047_DATA 0x00000015 +#define DDRSS1_PHY_1048_DATA 0x0000002A +#define DDRSS1_PHY_1049_DATA 0x00000033 +#define DDRSS1_PHY_1050_DATA 0x0000000C +#define DDRSS1_PHY_1051_DATA 0x0000000C +#define DDRSS1_PHY_1052_DATA 0x00000033 +#define DDRSS1_PHY_1053_DATA 0x00543210 +#define DDRSS1_PHY_1054_DATA 0x003F0000 +#define DDRSS1_PHY_1055_DATA 0x000F013F +#define DDRSS1_PHY_1056_DATA 0x20202003 +#define DDRSS1_PHY_1057_DATA 0x00202020 +#define DDRSS1_PHY_1058_DATA 0x20008008 +#define DDRSS1_PHY_1059_DATA 0x00000810 +#define DDRSS1_PHY_1060_DATA 0x00000F00 +#define DDRSS1_PHY_1061_DATA 0x00000000 +#define DDRSS1_PHY_1062_DATA 0x00000000 +#define DDRSS1_PHY_1063_DATA 0x00000000 +#define DDRSS1_PHY_1064_DATA 0x000305CC +#define DDRSS1_PHY_1065_DATA 0x00030000 +#define DDRSS1_PHY_1066_DATA 0x00000300 +#define DDRSS1_PHY_1067_DATA 0x00000300 +#define DDRSS1_PHY_1068_DATA 0x00000300 +#define DDRSS1_PHY_1069_DATA 0x00000300 +#define DDRSS1_PHY_1070_DATA 0x00000300 +#define DDRSS1_PHY_1071_DATA 0x42080010 +#define DDRSS1_PHY_1072_DATA 0x0000803E +#define DDRSS1_PHY_1073_DATA 0x00000001 +#define DDRSS1_PHY_1074_DATA 0x01000102 +#define DDRSS1_PHY_1075_DATA 0x00008000 +#define DDRSS1_PHY_1076_DATA 0x00000000 +#define DDRSS1_PHY_1077_DATA 0x00000000 +#define DDRSS1_PHY_1078_DATA 0x00000000 +#define DDRSS1_PHY_1079_DATA 0x00000000 +#define DDRSS1_PHY_1080_DATA 0x00000000 +#define DDRSS1_PHY_1081_DATA 0x00000000 +#define DDRSS1_PHY_1082_DATA 0x00000000 +#define DDRSS1_PHY_1083_DATA 0x00000000 +#define DDRSS1_PHY_1084_DATA 0x00000000 +#define DDRSS1_PHY_1085_DATA 0x00000000 +#define DDRSS1_PHY_1086_DATA 0x00000000 +#define DDRSS1_PHY_1087_DATA 0x00000000 +#define DDRSS1_PHY_1088_DATA 0x00000000 +#define DDRSS1_PHY_1089_DATA 0x00000000 +#define DDRSS1_PHY_1090_DATA 0x00000000 +#define DDRSS1_PHY_1091_DATA 0x00000000 +#define DDRSS1_PHY_1092_DATA 0x00000000 +#define DDRSS1_PHY_1093_DATA 0x00000000 +#define DDRSS1_PHY_1094_DATA 0x00000000 +#define DDRSS1_PHY_1095_DATA 0x00000000 +#define DDRSS1_PHY_1096_DATA 0x00000000 +#define DDRSS1_PHY_1097_DATA 0x00000000 +#define DDRSS1_PHY_1098_DATA 0x00000000 +#define DDRSS1_PHY_1099_DATA 0x00000000 +#define DDRSS1_PHY_1100_DATA 0x00000000 +#define DDRSS1_PHY_1101_DATA 0x00000000 +#define DDRSS1_PHY_1102_DATA 0x00000000 +#define DDRSS1_PHY_1103_DATA 0x00000000 +#define DDRSS1_PHY_1104_DATA 0x00000000 +#define DDRSS1_PHY_1105_DATA 0x00000000 +#define DDRSS1_PHY_1106_DATA 0x00000000 +#define DDRSS1_PHY_1107_DATA 0x00000000 +#define DDRSS1_PHY_1108_DATA 0x00000000 +#define DDRSS1_PHY_1109_DATA 0x00000000 +#define DDRSS1_PHY_1110_DATA 0x00000000 +#define DDRSS1_PHY_1111_DATA 0x00000000 +#define DDRSS1_PHY_1112_DATA 0x00000000 +#define DDRSS1_PHY_1113_DATA 0x00000000 +#define DDRSS1_PHY_1114_DATA 0x00000000 +#define DDRSS1_PHY_1115_DATA 0x00000000 +#define DDRSS1_PHY_1116_DATA 0x00000000 +#define DDRSS1_PHY_1117_DATA 0x00000000 +#define DDRSS1_PHY_1118_DATA 0x00000000 +#define DDRSS1_PHY_1119_DATA 0x00000000 +#define DDRSS1_PHY_1120_DATA 0x00000000 +#define DDRSS1_PHY_1121_DATA 0x00000000 +#define DDRSS1_PHY_1122_DATA 0x00000000 +#define DDRSS1_PHY_1123_DATA 0x00000000 +#define DDRSS1_PHY_1124_DATA 0x00000000 +#define DDRSS1_PHY_1125_DATA 0x00000000 +#define DDRSS1_PHY_1126_DATA 0x00000000 +#define DDRSS1_PHY_1127_DATA 0x00000000 +#define DDRSS1_PHY_1128_DATA 0x00000000 +#define DDRSS1_PHY_1129_DATA 0x00000000 +#define DDRSS1_PHY_1130_DATA 0x00000000 +#define DDRSS1_PHY_1131_DATA 0x00000000 +#define DDRSS1_PHY_1132_DATA 0x00000000 +#define DDRSS1_PHY_1133_DATA 0x00000000 +#define DDRSS1_PHY_1134_DATA 0x00000000 +#define DDRSS1_PHY_1135_DATA 0x00000000 +#define DDRSS1_PHY_1136_DATA 0x00000000 +#define DDRSS1_PHY_1137_DATA 0x00000000 +#define DDRSS1_PHY_1138_DATA 0x00000000 +#define DDRSS1_PHY_1139_DATA 0x00000000 +#define DDRSS1_PHY_1140_DATA 0x00000000 +#define DDRSS1_PHY_1141_DATA 0x00000000 +#define DDRSS1_PHY_1142_DATA 0x00000000 +#define DDRSS1_PHY_1143_DATA 0x00000000 +#define DDRSS1_PHY_1144_DATA 0x00000000 +#define DDRSS1_PHY_1145_DATA 0x00000000 +#define DDRSS1_PHY_1146_DATA 0x00000000 +#define DDRSS1_PHY_1147_DATA 0x00000000 +#define DDRSS1_PHY_1148_DATA 0x00000000 +#define DDRSS1_PHY_1149_DATA 0x00000000 +#define DDRSS1_PHY_1150_DATA 0x00000000 +#define DDRSS1_PHY_1151_DATA 0x00000000 +#define DDRSS1_PHY_1152_DATA 0x00000000 +#define DDRSS1_PHY_1153_DATA 0x00000000 +#define DDRSS1_PHY_1154_DATA 0x00000000 +#define DDRSS1_PHY_1155_DATA 0x00000000 +#define DDRSS1_PHY_1156_DATA 0x00000000 +#define DDRSS1_PHY_1157_DATA 0x00000000 +#define DDRSS1_PHY_1158_DATA 0x00000000 +#define DDRSS1_PHY_1159_DATA 0x00000000 +#define DDRSS1_PHY_1160_DATA 0x00000000 +#define DDRSS1_PHY_1161_DATA 0x00000000 +#define DDRSS1_PHY_1162_DATA 0x00000000 +#define DDRSS1_PHY_1163_DATA 0x00000000 +#define DDRSS1_PHY_1164_DATA 0x00000000 +#define DDRSS1_PHY_1165_DATA 0x00000000 +#define DDRSS1_PHY_1166_DATA 0x00000000 +#define DDRSS1_PHY_1167_DATA 0x00000000 +#define DDRSS1_PHY_1168_DATA 0x00000000 +#define DDRSS1_PHY_1169_DATA 0x00000000 +#define DDRSS1_PHY_1170_DATA 0x00000000 +#define DDRSS1_PHY_1171_DATA 0x00000000 +#define DDRSS1_PHY_1172_DATA 0x00000000 +#define DDRSS1_PHY_1173_DATA 0x00000000 +#define DDRSS1_PHY_1174_DATA 0x00000000 +#define DDRSS1_PHY_1175_DATA 0x00000000 +#define DDRSS1_PHY_1176_DATA 0x00000000 +#define DDRSS1_PHY_1177_DATA 0x00000000 +#define DDRSS1_PHY_1178_DATA 0x00000000 +#define DDRSS1_PHY_1179_DATA 0x00000000 +#define DDRSS1_PHY_1180_DATA 0x00000000 +#define DDRSS1_PHY_1181_DATA 0x00000000 +#define DDRSS1_PHY_1182_DATA 0x00000000 +#define DDRSS1_PHY_1183_DATA 0x00000000 +#define DDRSS1_PHY_1184_DATA 0x00000000 +#define DDRSS1_PHY_1185_DATA 0x00000000 +#define DDRSS1_PHY_1186_DATA 0x00000000 +#define DDRSS1_PHY_1187_DATA 0x00000000 +#define DDRSS1_PHY_1188_DATA 0x00000000 +#define DDRSS1_PHY_1189_DATA 0x00000000 +#define DDRSS1_PHY_1190_DATA 0x00000000 +#define DDRSS1_PHY_1191_DATA 0x00000000 +#define DDRSS1_PHY_1192_DATA 0x00000000 +#define DDRSS1_PHY_1193_DATA 0x00000000 +#define DDRSS1_PHY_1194_DATA 0x00000000 +#define DDRSS1_PHY_1195_DATA 0x00000000 +#define DDRSS1_PHY_1196_DATA 0x00000000 +#define DDRSS1_PHY_1197_DATA 0x00000000 +#define DDRSS1_PHY_1198_DATA 0x00000000 +#define DDRSS1_PHY_1199_DATA 0x00000000 +#define DDRSS1_PHY_1200_DATA 0x00000000 +#define DDRSS1_PHY_1201_DATA 0x00000000 +#define DDRSS1_PHY_1202_DATA 0x00000000 +#define DDRSS1_PHY_1203_DATA 0x00000000 +#define DDRSS1_PHY_1204_DATA 0x00000000 +#define DDRSS1_PHY_1205_DATA 0x00000000 +#define DDRSS1_PHY_1206_DATA 0x00000000 +#define DDRSS1_PHY_1207_DATA 0x00000000 +#define DDRSS1_PHY_1208_DATA 0x00000000 +#define DDRSS1_PHY_1209_DATA 0x00000000 +#define DDRSS1_PHY_1210_DATA 0x00000000 +#define DDRSS1_PHY_1211_DATA 0x00000000 +#define DDRSS1_PHY_1212_DATA 0x00000000 +#define DDRSS1_PHY_1213_DATA 0x00000000 +#define DDRSS1_PHY_1214_DATA 0x00000000 +#define DDRSS1_PHY_1215_DATA 0x00000000 +#define DDRSS1_PHY_1216_DATA 0x00000000 +#define DDRSS1_PHY_1217_DATA 0x00000000 +#define DDRSS1_PHY_1218_DATA 0x00000000 +#define DDRSS1_PHY_1219_DATA 0x00000000 +#define DDRSS1_PHY_1220_DATA 0x00000000 +#define DDRSS1_PHY_1221_DATA 0x00000000 +#define DDRSS1_PHY_1222_DATA 0x00000000 +#define DDRSS1_PHY_1223_DATA 0x00000000 +#define DDRSS1_PHY_1224_DATA 0x00000000 +#define DDRSS1_PHY_1225_DATA 0x00000000 +#define DDRSS1_PHY_1226_DATA 0x00000000 +#define DDRSS1_PHY_1227_DATA 0x00000000 +#define DDRSS1_PHY_1228_DATA 0x00000000 +#define DDRSS1_PHY_1229_DATA 0x00000000 +#define DDRSS1_PHY_1230_DATA 0x00000000 +#define DDRSS1_PHY_1231_DATA 0x00000000 +#define DDRSS1_PHY_1232_DATA 0x00000000 +#define DDRSS1_PHY_1233_DATA 0x00000000 +#define DDRSS1_PHY_1234_DATA 0x00000000 +#define DDRSS1_PHY_1235_DATA 0x00000000 +#define DDRSS1_PHY_1236_DATA 0x00000000 +#define DDRSS1_PHY_1237_DATA 0x00000000 +#define DDRSS1_PHY_1238_DATA 0x00000000 +#define DDRSS1_PHY_1239_DATA 0x00000000 +#define DDRSS1_PHY_1240_DATA 0x00000000 +#define DDRSS1_PHY_1241_DATA 0x00000000 +#define DDRSS1_PHY_1242_DATA 0x00000000 +#define DDRSS1_PHY_1243_DATA 0x00000000 +#define DDRSS1_PHY_1244_DATA 0x00000000 +#define DDRSS1_PHY_1245_DATA 0x00000000 +#define DDRSS1_PHY_1246_DATA 0x00000000 +#define DDRSS1_PHY_1247_DATA 0x00000000 +#define DDRSS1_PHY_1248_DATA 0x00000000 +#define DDRSS1_PHY_1249_DATA 0x00000000 +#define DDRSS1_PHY_1250_DATA 0x00000000 +#define DDRSS1_PHY_1251_DATA 0x00000000 +#define DDRSS1_PHY_1252_DATA 0x00000000 +#define DDRSS1_PHY_1253_DATA 0x00000000 +#define DDRSS1_PHY_1254_DATA 0x00000000 +#define DDRSS1_PHY_1255_DATA 0x00000000 +#define DDRSS1_PHY_1256_DATA 0x00000000 +#define DDRSS1_PHY_1257_DATA 0x00000000 +#define DDRSS1_PHY_1258_DATA 0x00000000 +#define DDRSS1_PHY_1259_DATA 0x00000000 +#define DDRSS1_PHY_1260_DATA 0x00000000 +#define DDRSS1_PHY_1261_DATA 0x00000000 +#define DDRSS1_PHY_1262_DATA 0x00000000 +#define DDRSS1_PHY_1263_DATA 0x00000000 +#define DDRSS1_PHY_1264_DATA 0x00000000 +#define DDRSS1_PHY_1265_DATA 0x00000000 +#define DDRSS1_PHY_1266_DATA 0x00000000 +#define DDRSS1_PHY_1267_DATA 0x00000000 +#define DDRSS1_PHY_1268_DATA 0x00000000 +#define DDRSS1_PHY_1269_DATA 0x00000000 +#define DDRSS1_PHY_1270_DATA 0x00000000 +#define DDRSS1_PHY_1271_DATA 0x00000000 +#define DDRSS1_PHY_1272_DATA 0x00000000 +#define DDRSS1_PHY_1273_DATA 0x00000000 +#define DDRSS1_PHY_1274_DATA 0x00000000 +#define DDRSS1_PHY_1275_DATA 0x00000000 +#define DDRSS1_PHY_1276_DATA 0x00000000 +#define DDRSS1_PHY_1277_DATA 0x00000000 +#define DDRSS1_PHY_1278_DATA 0x00000000 +#define DDRSS1_PHY_1279_DATA 0x00000000 +#define DDRSS1_PHY_1280_DATA 0x00000000 +#define DDRSS1_PHY_1281_DATA 0x00010100 +#define DDRSS1_PHY_1282_DATA 0x00000000 +#define DDRSS1_PHY_1283_DATA 0x00000000 +#define DDRSS1_PHY_1284_DATA 0x00050000 +#define DDRSS1_PHY_1285_DATA 0x04000000 +#define DDRSS1_PHY_1286_DATA 0x00000055 +#define DDRSS1_PHY_1287_DATA 0x00000000 +#define DDRSS1_PHY_1288_DATA 0x00000000 +#define DDRSS1_PHY_1289_DATA 0x00000000 +#define DDRSS1_PHY_1290_DATA 0x00000000 +#define DDRSS1_PHY_1291_DATA 0x00002001 +#define DDRSS1_PHY_1292_DATA 0x0000400F +#define DDRSS1_PHY_1293_DATA 0x50020028 +#define DDRSS1_PHY_1294_DATA 0x01010000 +#define DDRSS1_PHY_1295_DATA 0x80080001 +#define DDRSS1_PHY_1296_DATA 0x10200000 +#define DDRSS1_PHY_1297_DATA 0x00000008 +#define DDRSS1_PHY_1298_DATA 0x00000000 +#define DDRSS1_PHY_1299_DATA 0x01090E00 +#define DDRSS1_PHY_1300_DATA 0x00040101 +#define DDRSS1_PHY_1301_DATA 0x0000010F +#define DDRSS1_PHY_1302_DATA 0x00000000 +#define DDRSS1_PHY_1303_DATA 0x0000FFFF +#define DDRSS1_PHY_1304_DATA 0x00000000 +#define DDRSS1_PHY_1305_DATA 0x01010000 +#define DDRSS1_PHY_1306_DATA 0x01080402 +#define DDRSS1_PHY_1307_DATA 0x01200F02 +#define DDRSS1_PHY_1308_DATA 0x00194280 +#define DDRSS1_PHY_1309_DATA 0x00000004 +#define DDRSS1_PHY_1310_DATA 0x00042000 +#define DDRSS1_PHY_1311_DATA 0x00000000 +#define DDRSS1_PHY_1312_DATA 0x00000000 +#define DDRSS1_PHY_1313_DATA 0x00000000 +#define DDRSS1_PHY_1314_DATA 0x00000000 +#define DDRSS1_PHY_1315_DATA 0x00000000 +#define DDRSS1_PHY_1316_DATA 0x00000000 +#define DDRSS1_PHY_1317_DATA 0x01000000 +#define DDRSS1_PHY_1318_DATA 0x00000705 +#define DDRSS1_PHY_1319_DATA 0x00000054 +#define DDRSS1_PHY_1320_DATA 0x00030820 +#define DDRSS1_PHY_1321_DATA 0x00010820 +#define DDRSS1_PHY_1322_DATA 0x00010820 +#define DDRSS1_PHY_1323_DATA 0x00010820 +#define DDRSS1_PHY_1324_DATA 0x00010820 +#define DDRSS1_PHY_1325_DATA 0x00010820 +#define DDRSS1_PHY_1326_DATA 0x00010820 +#define DDRSS1_PHY_1327_DATA 0x00010820 +#define DDRSS1_PHY_1328_DATA 0x00010820 +#define DDRSS1_PHY_1329_DATA 0x00000000 +#define DDRSS1_PHY_1330_DATA 0x00000074 +#define DDRSS1_PHY_1331_DATA 0x00000400 +#define DDRSS1_PHY_1332_DATA 0x00000108 +#define DDRSS1_PHY_1333_DATA 0x00000000 +#define DDRSS1_PHY_1334_DATA 0x00000000 +#define DDRSS1_PHY_1335_DATA 0x00000000 +#define DDRSS1_PHY_1336_DATA 0x00000000 +#define DDRSS1_PHY_1337_DATA 0x00000000 +#define DDRSS1_PHY_1338_DATA 0x03000000 +#define DDRSS1_PHY_1339_DATA 0x00000000 +#define DDRSS1_PHY_1340_DATA 0x00000000 +#define DDRSS1_PHY_1341_DATA 0x00000000 +#define DDRSS1_PHY_1342_DATA 0x04102006 +#define DDRSS1_PHY_1343_DATA 0x00041020 +#define DDRSS1_PHY_1344_DATA 0x01C98C98 +#define DDRSS1_PHY_1345_DATA 0x3F400000 +#define DDRSS1_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS1_PHY_1347_DATA 0x0000001F +#define DDRSS1_PHY_1348_DATA 0x00000000 +#define DDRSS1_PHY_1349_DATA 0x00000000 +#define DDRSS1_PHY_1350_DATA 0x00000000 +#define DDRSS1_PHY_1351_DATA 0x00010000 +#define DDRSS1_PHY_1352_DATA 0x00000000 +#define DDRSS1_PHY_1353_DATA 0x00000000 +#define DDRSS1_PHY_1354_DATA 0x00000000 +#define DDRSS1_PHY_1355_DATA 0x00000000 +#define DDRSS1_PHY_1356_DATA 0x76543210 +#define DDRSS1_PHY_1357_DATA 0x00010198 +#define DDRSS1_PHY_1358_DATA 0x00000000 +#define DDRSS1_PHY_1359_DATA 0x00000000 +#define DDRSS1_PHY_1360_DATA 0x00000000 +#define DDRSS1_PHY_1361_DATA 0x00040700 +#define DDRSS1_PHY_1362_DATA 0x00000000 +#define DDRSS1_PHY_1363_DATA 0x00000000 +#define DDRSS1_PHY_1364_DATA 0x00000000 +#define DDRSS1_PHY_1365_DATA 0x00000000 +#define DDRSS1_PHY_1366_DATA 0x00000000 +#define DDRSS1_PHY_1367_DATA 0x00000002 +#define DDRSS1_PHY_1368_DATA 0x00000000 +#define DDRSS1_PHY_1369_DATA 0x00000000 +#define DDRSS1_PHY_1370_DATA 0x00000000 +#define DDRSS1_PHY_1371_DATA 0x00000000 +#define DDRSS1_PHY_1372_DATA 0x00000000 +#define DDRSS1_PHY_1373_DATA 0x00000000 +#define DDRSS1_PHY_1374_DATA 0x00080000 +#define DDRSS1_PHY_1375_DATA 0x000007FF +#define DDRSS1_PHY_1376_DATA 0x00000000 +#define DDRSS1_PHY_1377_DATA 0x00000000 +#define DDRSS1_PHY_1378_DATA 0x00000000 +#define DDRSS1_PHY_1379_DATA 0x00000000 +#define DDRSS1_PHY_1380_DATA 0x00000000 +#define DDRSS1_PHY_1381_DATA 0x00000000 +#define DDRSS1_PHY_1382_DATA 0x000FFFFF +#define DDRSS1_PHY_1383_DATA 0x000FFFFF +#define DDRSS1_PHY_1384_DATA 0x0000FFFF +#define DDRSS1_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS1_PHY_1386_DATA 0x030FFFFF +#define DDRSS1_PHY_1387_DATA 0x01FFFFFF +#define DDRSS1_PHY_1388_DATA 0x0000FFFF +#define DDRSS1_PHY_1389_DATA 0x00000000 +#define DDRSS1_PHY_1390_DATA 0x00000000 +#define DDRSS1_PHY_1391_DATA 0x00000000 +#define DDRSS1_PHY_1392_DATA 0x00000000 +#define DDRSS1_PHY_1393_DATA 0x0001F7C0 +#define DDRSS1_PHY_1394_DATA 0x00000003 +#define DDRSS1_PHY_1395_DATA 0x00000000 +#define DDRSS1_PHY_1396_DATA 0x00001142 +#define DDRSS1_PHY_1397_DATA 0x010207AB +#define DDRSS1_PHY_1398_DATA 0x01000080 +#define DDRSS1_PHY_1399_DATA 0x03900390 +#define DDRSS1_PHY_1400_DATA 0x03900390 +#define DDRSS1_PHY_1401_DATA 0x00000390 +#define DDRSS1_PHY_1402_DATA 0x00000390 +#define DDRSS1_PHY_1403_DATA 0x00000390 +#define DDRSS1_PHY_1404_DATA 0x00000390 +#define DDRSS1_PHY_1405_DATA 0x00000005 +#define DDRSS1_PHY_1406_DATA 0x01813FCC +#define DDRSS1_PHY_1407_DATA 0x000000CC +#define DDRSS1_PHY_1408_DATA 0x0C000DFF +#define DDRSS1_PHY_1409_DATA 0x30000DFF +#define DDRSS1_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1411_DATA 0x000100F0 +#define DDRSS1_PHY_1412_DATA 0x780DFFCC +#define DDRSS1_PHY_1413_DATA 0x00007E31 +#define DDRSS1_PHY_1414_DATA 0x000CBF11 +#define DDRSS1_PHY_1415_DATA 0x01990010 +#define DDRSS1_PHY_1416_DATA 0x000CBF11 +#define DDRSS1_PHY_1417_DATA 0x01990010 +#define DDRSS1_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1419_DATA 0x00EF00F0 +#define DDRSS1_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1421_DATA 0x01FF00F0 +#define DDRSS1_PHY_1422_DATA 0x20040006 + +#define DDRSS2_CTL_00_DATA 0x00000B00 +#define DDRSS2_CTL_01_DATA 0x00000000 +#define DDRSS2_CTL_02_DATA 0x00000000 +#define DDRSS2_CTL_03_DATA 0x00000000 +#define DDRSS2_CTL_04_DATA 0x00000000 +#define DDRSS2_CTL_05_DATA 0x00000000 +#define DDRSS2_CTL_06_DATA 0x00000000 +#define DDRSS2_CTL_07_DATA 0x00002AF8 +#define DDRSS2_CTL_08_DATA 0x0001ADAF +#define DDRSS2_CTL_09_DATA 0x00000005 +#define DDRSS2_CTL_10_DATA 0x0000006E +#define DDRSS2_CTL_11_DATA 0x000681C8 +#define DDRSS2_CTL_12_DATA 0x004111C9 +#define DDRSS2_CTL_13_DATA 0x00000005 +#define DDRSS2_CTL_14_DATA 0x000010A9 +#define DDRSS2_CTL_15_DATA 0x000681C8 +#define DDRSS2_CTL_16_DATA 0x004111C9 +#define DDRSS2_CTL_17_DATA 0x00000005 +#define DDRSS2_CTL_18_DATA 0x000010A9 +#define DDRSS2_CTL_19_DATA 0x01010000 +#define DDRSS2_CTL_20_DATA 0x02011001 +#define DDRSS2_CTL_21_DATA 0x02010000 +#define DDRSS2_CTL_22_DATA 0x00020100 +#define DDRSS2_CTL_23_DATA 0x0000000B +#define DDRSS2_CTL_24_DATA 0x0000001C +#define DDRSS2_CTL_25_DATA 0x00000000 +#define DDRSS2_CTL_26_DATA 0x00000000 +#define DDRSS2_CTL_27_DATA 0x03020200 +#define DDRSS2_CTL_28_DATA 0x00005656 +#define DDRSS2_CTL_29_DATA 0x00100000 +#define DDRSS2_CTL_30_DATA 0x00000000 +#define DDRSS2_CTL_31_DATA 0x00000000 +#define DDRSS2_CTL_32_DATA 0x00000000 +#define DDRSS2_CTL_33_DATA 0x00000000 +#define DDRSS2_CTL_34_DATA 0x040C0000 +#define DDRSS2_CTL_35_DATA 0x12481248 +#define DDRSS2_CTL_36_DATA 0x00050804 +#define DDRSS2_CTL_37_DATA 0x09040008 +#define DDRSS2_CTL_38_DATA 0x15000204 +#define DDRSS2_CTL_39_DATA 0x1760008B +#define DDRSS2_CTL_40_DATA 0x1500422B +#define DDRSS2_CTL_41_DATA 0x1760008B +#define DDRSS2_CTL_42_DATA 0x2000422B +#define DDRSS2_CTL_43_DATA 0x000A0A09 +#define DDRSS2_CTL_44_DATA 0x040003C5 +#define DDRSS2_CTL_45_DATA 0x1E161104 +#define DDRSS2_CTL_46_DATA 0x1000922C +#define DDRSS2_CTL_47_DATA 0x1E161110 +#define DDRSS2_CTL_48_DATA 0x1000922C +#define DDRSS2_CTL_49_DATA 0x02030410 +#define DDRSS2_CTL_50_DATA 0x2C040500 +#define DDRSS2_CTL_51_DATA 0x08292C29 +#define DDRSS2_CTL_52_DATA 0x14000E0A +#define DDRSS2_CTL_53_DATA 0x04010A0A +#define DDRSS2_CTL_54_DATA 0x01010004 +#define DDRSS2_CTL_55_DATA 0x04545408 +#define DDRSS2_CTL_56_DATA 0x04313104 +#define DDRSS2_CTL_57_DATA 0x00003131 +#define DDRSS2_CTL_58_DATA 0x00010100 +#define DDRSS2_CTL_59_DATA 0x03010000 +#define DDRSS2_CTL_60_DATA 0x00001508 +#define DDRSS2_CTL_61_DATA 0x00000063 +#define DDRSS2_CTL_62_DATA 0x0000032B +#define DDRSS2_CTL_63_DATA 0x00001035 +#define DDRSS2_CTL_64_DATA 0x0000032B +#define DDRSS2_CTL_65_DATA 0x00001035 +#define DDRSS2_CTL_66_DATA 0x00000005 +#define DDRSS2_CTL_67_DATA 0x00050000 +#define DDRSS2_CTL_68_DATA 0x00CB0012 +#define DDRSS2_CTL_69_DATA 0x00CB0408 +#define DDRSS2_CTL_70_DATA 0x00400408 +#define DDRSS2_CTL_71_DATA 0x00120103 +#define DDRSS2_CTL_72_DATA 0x00100005 +#define DDRSS2_CTL_73_DATA 0x2F080010 +#define DDRSS2_CTL_74_DATA 0x0505012F +#define DDRSS2_CTL_75_DATA 0x0401030A +#define DDRSS2_CTL_76_DATA 0x041E100B +#define DDRSS2_CTL_77_DATA 0x100B0401 +#define DDRSS2_CTL_78_DATA 0x0001041E +#define DDRSS2_CTL_79_DATA 0x00160016 +#define DDRSS2_CTL_80_DATA 0x033B033B +#define DDRSS2_CTL_81_DATA 0x033B033B +#define DDRSS2_CTL_82_DATA 0x03050505 +#define DDRSS2_CTL_83_DATA 0x03010303 +#define DDRSS2_CTL_84_DATA 0x200B100B +#define DDRSS2_CTL_85_DATA 0x04041004 +#define DDRSS2_CTL_86_DATA 0x200B100B +#define DDRSS2_CTL_87_DATA 0x04041004 +#define DDRSS2_CTL_88_DATA 0x03010000 +#define DDRSS2_CTL_89_DATA 0x00010000 +#define DDRSS2_CTL_90_DATA 0x00000000 +#define DDRSS2_CTL_91_DATA 0x00000000 +#define DDRSS2_CTL_92_DATA 0x01000000 +#define DDRSS2_CTL_93_DATA 0x80104002 +#define DDRSS2_CTL_94_DATA 0x00000000 +#define DDRSS2_CTL_95_DATA 0x00040005 +#define DDRSS2_CTL_96_DATA 0x00000000 +#define DDRSS2_CTL_97_DATA 0x00050000 +#define DDRSS2_CTL_98_DATA 0x00000004 +#define DDRSS2_CTL_99_DATA 0x00000000 +#define DDRSS2_CTL_100_DATA 0x00040005 +#define DDRSS2_CTL_101_DATA 0x00000000 +#define DDRSS2_CTL_102_DATA 0x000018C0 +#define DDRSS2_CTL_103_DATA 0x000018C0 +#define DDRSS2_CTL_104_DATA 0x000018C0 +#define DDRSS2_CTL_105_DATA 0x000018C0 +#define DDRSS2_CTL_106_DATA 0x000018C0 +#define DDRSS2_CTL_107_DATA 0x00000000 +#define DDRSS2_CTL_108_DATA 0x000002B5 +#define DDRSS2_CTL_109_DATA 0x00040D40 +#define DDRSS2_CTL_110_DATA 0x00040D40 +#define DDRSS2_CTL_111_DATA 0x00040D40 +#define DDRSS2_CTL_112_DATA 0x00040D40 +#define DDRSS2_CTL_113_DATA 0x00040D40 +#define DDRSS2_CTL_114_DATA 0x00000000 +#define DDRSS2_CTL_115_DATA 0x00007173 +#define DDRSS2_CTL_116_DATA 0x00040D40 +#define DDRSS2_CTL_117_DATA 0x00040D40 +#define DDRSS2_CTL_118_DATA 0x00040D40 +#define DDRSS2_CTL_119_DATA 0x00040D40 +#define DDRSS2_CTL_120_DATA 0x00040D40 +#define DDRSS2_CTL_121_DATA 0x00000000 +#define DDRSS2_CTL_122_DATA 0x00007173 +#define DDRSS2_CTL_123_DATA 0x00000000 +#define DDRSS2_CTL_124_DATA 0x00000000 +#define DDRSS2_CTL_125_DATA 0x00000000 +#define DDRSS2_CTL_126_DATA 0x00000000 +#define DDRSS2_CTL_127_DATA 0x00000000 +#define DDRSS2_CTL_128_DATA 0x00000000 +#define DDRSS2_CTL_129_DATA 0x00000000 +#define DDRSS2_CTL_130_DATA 0x00000000 +#define DDRSS2_CTL_131_DATA 0x0B030500 +#define DDRSS2_CTL_132_DATA 0x00040B04 +#define DDRSS2_CTL_133_DATA 0x0A090000 +#define DDRSS2_CTL_134_DATA 0x0A090701 +#define DDRSS2_CTL_135_DATA 0x0900000E +#define DDRSS2_CTL_136_DATA 0x0907010A +#define DDRSS2_CTL_137_DATA 0x00000E0A +#define DDRSS2_CTL_138_DATA 0x07010A09 +#define DDRSS2_CTL_139_DATA 0x000E0A09 +#define DDRSS2_CTL_140_DATA 0x07000401 +#define DDRSS2_CTL_141_DATA 0x00000000 +#define DDRSS2_CTL_142_DATA 0x00000000 +#define DDRSS2_CTL_143_DATA 0x00000000 +#define DDRSS2_CTL_144_DATA 0x00000000 +#define DDRSS2_CTL_145_DATA 0x00000000 +#define DDRSS2_CTL_146_DATA 0x00000000 +#define DDRSS2_CTL_147_DATA 0x00000000 +#define DDRSS2_CTL_148_DATA 0x08080000 +#define DDRSS2_CTL_149_DATA 0x01000000 +#define DDRSS2_CTL_150_DATA 0x800000C0 +#define DDRSS2_CTL_151_DATA 0x800000C0 +#define DDRSS2_CTL_152_DATA 0x800000C0 +#define DDRSS2_CTL_153_DATA 0x00000000 +#define DDRSS2_CTL_154_DATA 0x00001500 +#define DDRSS2_CTL_155_DATA 0x00000000 +#define DDRSS2_CTL_156_DATA 0x00000001 +#define DDRSS2_CTL_157_DATA 0x00000002 +#define DDRSS2_CTL_158_DATA 0x0000100E +#define DDRSS2_CTL_159_DATA 0x00000000 +#define DDRSS2_CTL_160_DATA 0x00000000 +#define DDRSS2_CTL_161_DATA 0x00000000 +#define DDRSS2_CTL_162_DATA 0x00000000 +#define DDRSS2_CTL_163_DATA 0x00000000 +#define DDRSS2_CTL_164_DATA 0x000B0000 +#define DDRSS2_CTL_165_DATA 0x000E0006 +#define DDRSS2_CTL_166_DATA 0x000E0404 +#define DDRSS2_CTL_167_DATA 0x00D601AB +#define DDRSS2_CTL_168_DATA 0x10100216 +#define DDRSS2_CTL_169_DATA 0x01AB0216 +#define DDRSS2_CTL_170_DATA 0x021600D6 +#define DDRSS2_CTL_171_DATA 0x02161010 +#define DDRSS2_CTL_172_DATA 0x00000000 +#define DDRSS2_CTL_173_DATA 0x00000000 +#define DDRSS2_CTL_174_DATA 0x00000000 +#define DDRSS2_CTL_175_DATA 0x3FF40084 +#define DDRSS2_CTL_176_DATA 0x33003FF4 +#define DDRSS2_CTL_177_DATA 0x00003333 +#define DDRSS2_CTL_178_DATA 0x35000000 +#define DDRSS2_CTL_179_DATA 0x27270035 +#define DDRSS2_CTL_180_DATA 0x0F0F0000 +#define DDRSS2_CTL_181_DATA 0x16000000 +#define DDRSS2_CTL_182_DATA 0x00841616 +#define DDRSS2_CTL_183_DATA 0x3FF43FF4 +#define DDRSS2_CTL_184_DATA 0x33333300 +#define DDRSS2_CTL_185_DATA 0x00000000 +#define DDRSS2_CTL_186_DATA 0x00353500 +#define DDRSS2_CTL_187_DATA 0x00002727 +#define DDRSS2_CTL_188_DATA 0x00000F0F +#define DDRSS2_CTL_189_DATA 0x16161600 +#define DDRSS2_CTL_190_DATA 0x00000020 +#define DDRSS2_CTL_191_DATA 0x00000000 +#define DDRSS2_CTL_192_DATA 0x00000001 +#define DDRSS2_CTL_193_DATA 0x00000000 +#define DDRSS2_CTL_194_DATA 0x01000000 +#define DDRSS2_CTL_195_DATA 0x00000001 +#define DDRSS2_CTL_196_DATA 0x00000000 +#define DDRSS2_CTL_197_DATA 0x00000000 +#define DDRSS2_CTL_198_DATA 0x00000000 +#define DDRSS2_CTL_199_DATA 0x00000000 +#define DDRSS2_CTL_200_DATA 0x00000000 +#define DDRSS2_CTL_201_DATA 0x00000000 +#define DDRSS2_CTL_202_DATA 0x00000000 +#define DDRSS2_CTL_203_DATA 0x00000000 +#define DDRSS2_CTL_204_DATA 0x00000000 +#define DDRSS2_CTL_205_DATA 0x00000000 +#define DDRSS2_CTL_206_DATA 0x02000000 +#define DDRSS2_CTL_207_DATA 0x01080101 +#define DDRSS2_CTL_208_DATA 0x00000000 +#define DDRSS2_CTL_209_DATA 0x00000000 +#define DDRSS2_CTL_210_DATA 0x00000000 +#define DDRSS2_CTL_211_DATA 0x00000000 +#define DDRSS2_CTL_212_DATA 0x00000000 +#define DDRSS2_CTL_213_DATA 0x00000000 +#define DDRSS2_CTL_214_DATA 0x00000000 +#define DDRSS2_CTL_215_DATA 0x00000000 +#define DDRSS2_CTL_216_DATA 0x00000000 +#define DDRSS2_CTL_217_DATA 0x00000000 +#define DDRSS2_CTL_218_DATA 0x00000000 +#define DDRSS2_CTL_219_DATA 0x00000000 +#define DDRSS2_CTL_220_DATA 0x00000000 +#define DDRSS2_CTL_221_DATA 0x00000000 +#define DDRSS2_CTL_222_DATA 0x00001000 +#define DDRSS2_CTL_223_DATA 0x006403E8 +#define DDRSS2_CTL_224_DATA 0x00000000 +#define DDRSS2_CTL_225_DATA 0x00000000 +#define DDRSS2_CTL_226_DATA 0x00000000 +#define DDRSS2_CTL_227_DATA 0x15110000 +#define DDRSS2_CTL_228_DATA 0x00040C18 +#define DDRSS2_CTL_229_DATA 0xF000C000 +#define DDRSS2_CTL_230_DATA 0x0000F000 +#define DDRSS2_CTL_231_DATA 0x00000000 +#define DDRSS2_CTL_232_DATA 0x00000000 +#define DDRSS2_CTL_233_DATA 0xC0000000 +#define DDRSS2_CTL_234_DATA 0xF000F000 +#define DDRSS2_CTL_235_DATA 0x00000000 +#define DDRSS2_CTL_236_DATA 0x00000000 +#define DDRSS2_CTL_237_DATA 0x00000000 +#define DDRSS2_CTL_238_DATA 0xF000C000 +#define DDRSS2_CTL_239_DATA 0x0000F000 +#define DDRSS2_CTL_240_DATA 0x00000000 +#define DDRSS2_CTL_241_DATA 0x00000000 +#define DDRSS2_CTL_242_DATA 0x00030000 +#define DDRSS2_CTL_243_DATA 0x00000000 +#define DDRSS2_CTL_244_DATA 0x00000000 +#define DDRSS2_CTL_245_DATA 0x00000000 +#define DDRSS2_CTL_246_DATA 0x00000000 +#define DDRSS2_CTL_247_DATA 0x00000000 +#define DDRSS2_CTL_248_DATA 0x00000000 +#define DDRSS2_CTL_249_DATA 0x00000000 +#define DDRSS2_CTL_250_DATA 0x00000000 +#define DDRSS2_CTL_251_DATA 0x00000000 +#define DDRSS2_CTL_252_DATA 0x00000000 +#define DDRSS2_CTL_253_DATA 0x00000000 +#define DDRSS2_CTL_254_DATA 0x00000000 +#define DDRSS2_CTL_255_DATA 0x00000000 +#define DDRSS2_CTL_256_DATA 0x00000000 +#define DDRSS2_CTL_257_DATA 0x01000200 +#define DDRSS2_CTL_258_DATA 0x00370040 +#define DDRSS2_CTL_259_DATA 0x00020008 +#define DDRSS2_CTL_260_DATA 0x00400100 +#define DDRSS2_CTL_261_DATA 0x00400855 +#define DDRSS2_CTL_262_DATA 0x01000200 +#define DDRSS2_CTL_263_DATA 0x08550040 +#define DDRSS2_CTL_264_DATA 0x00000040 +#define DDRSS2_CTL_265_DATA 0x006B0003 +#define DDRSS2_CTL_266_DATA 0x0100006B +#define DDRSS2_CTL_267_DATA 0x03030303 +#define DDRSS2_CTL_268_DATA 0x00000000 +#define DDRSS2_CTL_269_DATA 0x00000202 +#define DDRSS2_CTL_270_DATA 0x00001FFF +#define DDRSS2_CTL_271_DATA 0x3FFF2000 +#define DDRSS2_CTL_272_DATA 0x03FF0000 +#define DDRSS2_CTL_273_DATA 0x000103FF +#define DDRSS2_CTL_274_DATA 0x0FFF0B00 +#define DDRSS2_CTL_275_DATA 0x01010001 +#define DDRSS2_CTL_276_DATA 0x01010101 +#define DDRSS2_CTL_277_DATA 0x01180101 +#define DDRSS2_CTL_278_DATA 0x00030000 +#define DDRSS2_CTL_279_DATA 0x00000000 +#define DDRSS2_CTL_280_DATA 0x00000000 +#define DDRSS2_CTL_281_DATA 0x00000000 +#define DDRSS2_CTL_282_DATA 0x00000000 +#define DDRSS2_CTL_283_DATA 0x00000000 +#define DDRSS2_CTL_284_DATA 0x00000000 +#define DDRSS2_CTL_285_DATA 0x00000000 +#define DDRSS2_CTL_286_DATA 0x00040101 +#define DDRSS2_CTL_287_DATA 0x04010100 +#define DDRSS2_CTL_288_DATA 0x00000000 +#define DDRSS2_CTL_289_DATA 0x00000000 +#define DDRSS2_CTL_290_DATA 0x03030300 +#define DDRSS2_CTL_291_DATA 0x00000001 +#define DDRSS2_CTL_292_DATA 0x00000000 +#define DDRSS2_CTL_293_DATA 0x00000000 +#define DDRSS2_CTL_294_DATA 0x00000000 +#define DDRSS2_CTL_295_DATA 0x00000000 +#define DDRSS2_CTL_296_DATA 0x00000000 +#define DDRSS2_CTL_297_DATA 0x00000000 +#define DDRSS2_CTL_298_DATA 0x00000000 +#define DDRSS2_CTL_299_DATA 0x00000000 +#define DDRSS2_CTL_300_DATA 0x00000000 +#define DDRSS2_CTL_301_DATA 0x00000000 +#define DDRSS2_CTL_302_DATA 0x00000000 +#define DDRSS2_CTL_303_DATA 0x00000000 +#define DDRSS2_CTL_304_DATA 0x00000000 +#define DDRSS2_CTL_305_DATA 0x00000000 +#define DDRSS2_CTL_306_DATA 0x00000000 +#define DDRSS2_CTL_307_DATA 0x00000000 +#define DDRSS2_CTL_308_DATA 0x00000000 +#define DDRSS2_CTL_309_DATA 0x00000000 +#define DDRSS2_CTL_310_DATA 0x00000000 +#define DDRSS2_CTL_311_DATA 0x00000000 +#define DDRSS2_CTL_312_DATA 0x00000000 +#define DDRSS2_CTL_313_DATA 0x01000000 +#define DDRSS2_CTL_314_DATA 0x00020201 +#define DDRSS2_CTL_315_DATA 0x01000101 +#define DDRSS2_CTL_316_DATA 0x01010001 +#define DDRSS2_CTL_317_DATA 0x00010101 +#define DDRSS2_CTL_318_DATA 0x050A0A03 +#define DDRSS2_CTL_319_DATA 0x10081F1F +#define DDRSS2_CTL_320_DATA 0x00090310 +#define DDRSS2_CTL_321_DATA 0x0B0C030F +#define DDRSS2_CTL_322_DATA 0x0B0C0306 +#define DDRSS2_CTL_323_DATA 0x0C090006 +#define DDRSS2_CTL_324_DATA 0x0100000C +#define DDRSS2_CTL_325_DATA 0x08040801 +#define DDRSS2_CTL_326_DATA 0x00000004 +#define DDRSS2_CTL_327_DATA 0x00000000 +#define DDRSS2_CTL_328_DATA 0x00010000 +#define DDRSS2_CTL_329_DATA 0x00280D00 +#define DDRSS2_CTL_330_DATA 0x00000001 +#define DDRSS2_CTL_331_DATA 0x00030001 +#define DDRSS2_CTL_332_DATA 0x00000000 +#define DDRSS2_CTL_333_DATA 0x00000000 +#define DDRSS2_CTL_334_DATA 0x00000000 +#define DDRSS2_CTL_335_DATA 0x00000000 +#define DDRSS2_CTL_336_DATA 0x00000000 +#define DDRSS2_CTL_337_DATA 0x00000000 +#define DDRSS2_CTL_338_DATA 0x00000000 +#define DDRSS2_CTL_339_DATA 0x00000000 +#define DDRSS2_CTL_340_DATA 0x01000000 +#define DDRSS2_CTL_341_DATA 0x00000001 +#define DDRSS2_CTL_342_DATA 0x00010100 +#define DDRSS2_CTL_343_DATA 0x03030000 +#define DDRSS2_CTL_344_DATA 0x00000000 +#define DDRSS2_CTL_345_DATA 0x00000000 +#define DDRSS2_CTL_346_DATA 0x00000000 +#define DDRSS2_CTL_347_DATA 0x00000000 +#define DDRSS2_CTL_348_DATA 0x00000000 +#define DDRSS2_CTL_349_DATA 0x00000000 +#define DDRSS2_CTL_350_DATA 0x00000000 +#define DDRSS2_CTL_351_DATA 0x00000000 +#define DDRSS2_CTL_352_DATA 0x00000000 +#define DDRSS2_CTL_353_DATA 0x00000000 +#define DDRSS2_CTL_354_DATA 0x00000000 +#define DDRSS2_CTL_355_DATA 0x00000000 +#define DDRSS2_CTL_356_DATA 0x00000000 +#define DDRSS2_CTL_357_DATA 0x00000000 +#define DDRSS2_CTL_358_DATA 0x00000000 +#define DDRSS2_CTL_359_DATA 0x00000000 +#define DDRSS2_CTL_360_DATA 0x000556AA +#define DDRSS2_CTL_361_DATA 0x000AAAAA +#define DDRSS2_CTL_362_DATA 0x000AA955 +#define DDRSS2_CTL_363_DATA 0x00055555 +#define DDRSS2_CTL_364_DATA 0x000B3133 +#define DDRSS2_CTL_365_DATA 0x0004CD33 +#define DDRSS2_CTL_366_DATA 0x0004CECC +#define DDRSS2_CTL_367_DATA 0x000B32CC +#define DDRSS2_CTL_368_DATA 0x00010300 +#define DDRSS2_CTL_369_DATA 0x03000100 +#define DDRSS2_CTL_370_DATA 0x00000000 +#define DDRSS2_CTL_371_DATA 0x00000000 +#define DDRSS2_CTL_372_DATA 0x00000000 +#define DDRSS2_CTL_373_DATA 0x00000000 +#define DDRSS2_CTL_374_DATA 0x00000000 +#define DDRSS2_CTL_375_DATA 0x00000000 +#define DDRSS2_CTL_376_DATA 0x00000000 +#define DDRSS2_CTL_377_DATA 0x00010000 +#define DDRSS2_CTL_378_DATA 0x00000404 +#define DDRSS2_CTL_379_DATA 0x00000000 +#define DDRSS2_CTL_380_DATA 0x00000000 +#define DDRSS2_CTL_381_DATA 0x00000000 +#define DDRSS2_CTL_382_DATA 0x00000000 +#define DDRSS2_CTL_383_DATA 0x00000000 +#define DDRSS2_CTL_384_DATA 0x00000000 +#define DDRSS2_CTL_385_DATA 0x00000000 +#define DDRSS2_CTL_386_DATA 0x00000000 +#define DDRSS2_CTL_387_DATA 0x3A3A1B00 +#define DDRSS2_CTL_388_DATA 0x000A0000 +#define DDRSS2_CTL_389_DATA 0x000000C6 +#define DDRSS2_CTL_390_DATA 0x00000200 +#define DDRSS2_CTL_391_DATA 0x00000200 +#define DDRSS2_CTL_392_DATA 0x00000200 +#define DDRSS2_CTL_393_DATA 0x00000200 +#define DDRSS2_CTL_394_DATA 0x00000252 +#define DDRSS2_CTL_395_DATA 0x000007BC +#define DDRSS2_CTL_396_DATA 0x00000204 +#define DDRSS2_CTL_397_DATA 0x0000206A +#define DDRSS2_CTL_398_DATA 0x00000200 +#define DDRSS2_CTL_399_DATA 0x00000200 +#define DDRSS2_CTL_400_DATA 0x00000200 +#define DDRSS2_CTL_401_DATA 0x00000200 +#define DDRSS2_CTL_402_DATA 0x0000613E +#define DDRSS2_CTL_403_DATA 0x00014424 +#define DDRSS2_CTL_404_DATA 0x00000E15 +#define DDRSS2_CTL_405_DATA 0x0000206A +#define DDRSS2_CTL_406_DATA 0x00000200 +#define DDRSS2_CTL_407_DATA 0x00000200 +#define DDRSS2_CTL_408_DATA 0x00000200 +#define DDRSS2_CTL_409_DATA 0x00000200 +#define DDRSS2_CTL_410_DATA 0x0000613E +#define DDRSS2_CTL_411_DATA 0x00014424 +#define DDRSS2_CTL_412_DATA 0x02020E15 +#define DDRSS2_CTL_413_DATA 0x03030202 +#define DDRSS2_CTL_414_DATA 0x00000022 +#define DDRSS2_CTL_415_DATA 0x00000000 +#define DDRSS2_CTL_416_DATA 0x00000000 +#define DDRSS2_CTL_417_DATA 0x00001403 +#define DDRSS2_CTL_418_DATA 0x000007D0 +#define DDRSS2_CTL_419_DATA 0x00000000 +#define DDRSS2_CTL_420_DATA 0x00000000 +#define DDRSS2_CTL_421_DATA 0x00030000 +#define DDRSS2_CTL_422_DATA 0x0007001F +#define DDRSS2_CTL_423_DATA 0x001B0033 +#define DDRSS2_CTL_424_DATA 0x001B0033 +#define DDRSS2_CTL_425_DATA 0x00000000 +#define DDRSS2_CTL_426_DATA 0x00000000 +#define DDRSS2_CTL_427_DATA 0x02000000 +#define DDRSS2_CTL_428_DATA 0x01000404 +#define DDRSS2_CTL_429_DATA 0x0B1E0B1E +#define DDRSS2_CTL_430_DATA 0x00000105 +#define DDRSS2_CTL_431_DATA 0x00010101 +#define DDRSS2_CTL_432_DATA 0x00010101 +#define DDRSS2_CTL_433_DATA 0x00010001 +#define DDRSS2_CTL_434_DATA 0x00000101 +#define DDRSS2_CTL_435_DATA 0x02000201 +#define DDRSS2_CTL_436_DATA 0x02010000 +#define DDRSS2_CTL_437_DATA 0x00000200 +#define DDRSS2_CTL_438_DATA 0x28060000 +#define DDRSS2_CTL_439_DATA 0x00000128 +#define DDRSS2_CTL_440_DATA 0xFFFFFFFF +#define DDRSS2_CTL_441_DATA 0xFFFFFFFF +#define DDRSS2_CTL_442_DATA 0x00000000 +#define DDRSS2_CTL_443_DATA 0x00000000 +#define DDRSS2_CTL_444_DATA 0x00000000 +#define DDRSS2_CTL_445_DATA 0x00000000 +#define DDRSS2_CTL_446_DATA 0x00000000 +#define DDRSS2_CTL_447_DATA 0x00000000 +#define DDRSS2_CTL_448_DATA 0x00000000 +#define DDRSS2_CTL_449_DATA 0x00000000 +#define DDRSS2_CTL_450_DATA 0x00000000 +#define DDRSS2_CTL_451_DATA 0x00000000 +#define DDRSS2_CTL_452_DATA 0x00000000 +#define DDRSS2_CTL_453_DATA 0x00000000 +#define DDRSS2_CTL_454_DATA 0x00000000 +#define DDRSS2_CTL_455_DATA 0x00000000 +#define DDRSS2_CTL_456_DATA 0x00000000 +#define DDRSS2_CTL_457_DATA 0x00000000 +#define DDRSS2_CTL_458_DATA 0x00000000 + +#define DDRSS2_PI_00_DATA 0x00000B00 +#define DDRSS2_PI_01_DATA 0x00000000 +#define DDRSS2_PI_02_DATA 0x00000000 +#define DDRSS2_PI_03_DATA 0x00000000 +#define DDRSS2_PI_04_DATA 0x00000000 +#define DDRSS2_PI_05_DATA 0x00000101 +#define DDRSS2_PI_06_DATA 0x00640000 +#define DDRSS2_PI_07_DATA 0x00000001 +#define DDRSS2_PI_08_DATA 0x00000000 +#define DDRSS2_PI_09_DATA 0x00000000 +#define DDRSS2_PI_10_DATA 0x00000000 +#define DDRSS2_PI_11_DATA 0x00000000 +#define DDRSS2_PI_12_DATA 0x00000007 +#define DDRSS2_PI_13_DATA 0x00010002 +#define DDRSS2_PI_14_DATA 0x0800000F +#define DDRSS2_PI_15_DATA 0x00000103 +#define DDRSS2_PI_16_DATA 0x00000005 +#define DDRSS2_PI_17_DATA 0x00000000 +#define DDRSS2_PI_18_DATA 0x00000000 +#define DDRSS2_PI_19_DATA 0x00000000 +#define DDRSS2_PI_20_DATA 0x00000000 +#define DDRSS2_PI_21_DATA 0x00000000 +#define DDRSS2_PI_22_DATA 0x00000000 +#define DDRSS2_PI_23_DATA 0x00000000 +#define DDRSS2_PI_24_DATA 0x00000000 +#define DDRSS2_PI_25_DATA 0x00000000 +#define DDRSS2_PI_26_DATA 0x00010100 +#define DDRSS2_PI_27_DATA 0x00280A00 +#define DDRSS2_PI_28_DATA 0x00000000 +#define DDRSS2_PI_29_DATA 0x0F000000 +#define DDRSS2_PI_30_DATA 0x00003200 +#define DDRSS2_PI_31_DATA 0x00000000 +#define DDRSS2_PI_32_DATA 0x00000000 +#define DDRSS2_PI_33_DATA 0x01010102 +#define DDRSS2_PI_34_DATA 0x00000000 +#define DDRSS2_PI_35_DATA 0x000000AA +#define DDRSS2_PI_36_DATA 0x00000055 +#define DDRSS2_PI_37_DATA 0x000000B5 +#define DDRSS2_PI_38_DATA 0x0000004A +#define DDRSS2_PI_39_DATA 0x00000056 +#define DDRSS2_PI_40_DATA 0x000000A9 +#define DDRSS2_PI_41_DATA 0x000000A9 +#define DDRSS2_PI_42_DATA 0x000000B5 +#define DDRSS2_PI_43_DATA 0x00000000 +#define DDRSS2_PI_44_DATA 0x00000000 +#define DDRSS2_PI_45_DATA 0x000F0F00 +#define DDRSS2_PI_46_DATA 0x0000001B +#define DDRSS2_PI_47_DATA 0x000007D0 +#define DDRSS2_PI_48_DATA 0x00000300 +#define DDRSS2_PI_49_DATA 0x00000000 +#define DDRSS2_PI_50_DATA 0x00000000 +#define DDRSS2_PI_51_DATA 0x01000000 +#define DDRSS2_PI_52_DATA 0x00010101 +#define DDRSS2_PI_53_DATA 0x00000000 +#define DDRSS2_PI_54_DATA 0x00030000 +#define DDRSS2_PI_55_DATA 0x0F000000 +#define DDRSS2_PI_56_DATA 0x00000017 +#define DDRSS2_PI_57_DATA 0x00000000 +#define DDRSS2_PI_58_DATA 0x00000000 +#define DDRSS2_PI_59_DATA 0x00000000 +#define DDRSS2_PI_60_DATA 0x0A0A140A +#define DDRSS2_PI_61_DATA 0x10020101 +#define DDRSS2_PI_62_DATA 0x00020805 +#define DDRSS2_PI_63_DATA 0x01000404 +#define DDRSS2_PI_64_DATA 0x00000000 +#define DDRSS2_PI_65_DATA 0x00000000 +#define DDRSS2_PI_66_DATA 0x00000100 +#define DDRSS2_PI_67_DATA 0x0001010F +#define DDRSS2_PI_68_DATA 0x00340000 +#define DDRSS2_PI_69_DATA 0x00000000 +#define DDRSS2_PI_70_DATA 0x00000000 +#define DDRSS2_PI_71_DATA 0x0000FFFF +#define DDRSS2_PI_72_DATA 0x00000000 +#define DDRSS2_PI_73_DATA 0x00080000 +#define DDRSS2_PI_74_DATA 0x02000200 +#define DDRSS2_PI_75_DATA 0x01000100 +#define DDRSS2_PI_76_DATA 0x01000000 +#define DDRSS2_PI_77_DATA 0x02000200 +#define DDRSS2_PI_78_DATA 0x00000200 +#define DDRSS2_PI_79_DATA 0x00000000 +#define DDRSS2_PI_80_DATA 0x00000000 +#define DDRSS2_PI_81_DATA 0x00000000 +#define DDRSS2_PI_82_DATA 0x00000000 +#define DDRSS2_PI_83_DATA 0x00000000 +#define DDRSS2_PI_84_DATA 0x00000000 +#define DDRSS2_PI_85_DATA 0x00000000 +#define DDRSS2_PI_86_DATA 0x00000000 +#define DDRSS2_PI_87_DATA 0x00000000 +#define DDRSS2_PI_88_DATA 0x00000000 +#define DDRSS2_PI_89_DATA 0x00000000 +#define DDRSS2_PI_90_DATA 0x00000000 +#define DDRSS2_PI_91_DATA 0x00000400 +#define DDRSS2_PI_92_DATA 0x02010000 +#define DDRSS2_PI_93_DATA 0x00080003 +#define DDRSS2_PI_94_DATA 0x00080000 +#define DDRSS2_PI_95_DATA 0x00000001 +#define DDRSS2_PI_96_DATA 0x00000000 +#define DDRSS2_PI_97_DATA 0x0000AA00 +#define DDRSS2_PI_98_DATA 0x00000000 +#define DDRSS2_PI_99_DATA 0x00000000 +#define DDRSS2_PI_100_DATA 0x00010000 +#define DDRSS2_PI_101_DATA 0x00000000 +#define DDRSS2_PI_102_DATA 0x00000000 +#define DDRSS2_PI_103_DATA 0x00000000 +#define DDRSS2_PI_104_DATA 0x00000000 +#define DDRSS2_PI_105_DATA 0x00000000 +#define DDRSS2_PI_106_DATA 0x00000000 +#define DDRSS2_PI_107_DATA 0x00000000 +#define DDRSS2_PI_108_DATA 0x00000000 +#define DDRSS2_PI_109_DATA 0x00000000 +#define DDRSS2_PI_110_DATA 0x00000000 +#define DDRSS2_PI_111_DATA 0x00000000 +#define DDRSS2_PI_112_DATA 0x00000000 +#define DDRSS2_PI_113_DATA 0x00000000 +#define DDRSS2_PI_114_DATA 0x00000000 +#define DDRSS2_PI_115_DATA 0x00000000 +#define DDRSS2_PI_116_DATA 0x00000000 +#define DDRSS2_PI_117_DATA 0x00000000 +#define DDRSS2_PI_118_DATA 0x00000000 +#define DDRSS2_PI_119_DATA 0x00000000 +#define DDRSS2_PI_120_DATA 0x00000000 +#define DDRSS2_PI_121_DATA 0x00000000 +#define DDRSS2_PI_122_DATA 0x00000000 +#define DDRSS2_PI_123_DATA 0x00000000 +#define DDRSS2_PI_124_DATA 0x00000000 +#define DDRSS2_PI_125_DATA 0x00000008 +#define DDRSS2_PI_126_DATA 0x00000000 +#define DDRSS2_PI_127_DATA 0x00000000 +#define DDRSS2_PI_128_DATA 0x00000000 +#define DDRSS2_PI_129_DATA 0x00000000 +#define DDRSS2_PI_130_DATA 0x00000000 +#define DDRSS2_PI_131_DATA 0x00000000 +#define DDRSS2_PI_132_DATA 0x00000000 +#define DDRSS2_PI_133_DATA 0x00000000 +#define DDRSS2_PI_134_DATA 0x00000002 +#define DDRSS2_PI_135_DATA 0x00000000 +#define DDRSS2_PI_136_DATA 0x00000000 +#define DDRSS2_PI_137_DATA 0x0000000A +#define DDRSS2_PI_138_DATA 0x00000019 +#define DDRSS2_PI_139_DATA 0x00000100 +#define DDRSS2_PI_140_DATA 0x00000000 +#define DDRSS2_PI_141_DATA 0x00000000 +#define DDRSS2_PI_142_DATA 0x00000000 +#define DDRSS2_PI_143_DATA 0x00000000 +#define DDRSS2_PI_144_DATA 0x01000000 +#define DDRSS2_PI_145_DATA 0x00010003 +#define DDRSS2_PI_146_DATA 0x02000101 +#define DDRSS2_PI_147_DATA 0x01030001 +#define DDRSS2_PI_148_DATA 0x00010400 +#define DDRSS2_PI_149_DATA 0x06000105 +#define DDRSS2_PI_150_DATA 0x01070001 +#define DDRSS2_PI_151_DATA 0x00000000 +#define DDRSS2_PI_152_DATA 0x00000000 +#define DDRSS2_PI_153_DATA 0x00000000 +#define DDRSS2_PI_154_DATA 0x00010001 +#define DDRSS2_PI_155_DATA 0x00000000 +#define DDRSS2_PI_156_DATA 0x00000000 +#define DDRSS2_PI_157_DATA 0x00000000 +#define DDRSS2_PI_158_DATA 0x00000000 +#define DDRSS2_PI_159_DATA 0x00000401 +#define DDRSS2_PI_160_DATA 0x00000000 +#define DDRSS2_PI_161_DATA 0x00010000 +#define DDRSS2_PI_162_DATA 0x00000000 +#define DDRSS2_PI_163_DATA 0x2B2B0200 +#define DDRSS2_PI_164_DATA 0x00000034 +#define DDRSS2_PI_165_DATA 0x00000064 +#define DDRSS2_PI_166_DATA 0x00020064 +#define DDRSS2_PI_167_DATA 0x02000200 +#define DDRSS2_PI_168_DATA 0x48120C04 +#define DDRSS2_PI_169_DATA 0x00154812 +#define DDRSS2_PI_170_DATA 0x00000063 +#define DDRSS2_PI_171_DATA 0x0000032B +#define DDRSS2_PI_172_DATA 0x00001035 +#define DDRSS2_PI_173_DATA 0x0000032B +#define DDRSS2_PI_174_DATA 0x04001035 +#define DDRSS2_PI_175_DATA 0x01010404 +#define DDRSS2_PI_176_DATA 0x00001501 +#define DDRSS2_PI_177_DATA 0x00150015 +#define DDRSS2_PI_178_DATA 0x01000100 +#define DDRSS2_PI_179_DATA 0x00000100 +#define DDRSS2_PI_180_DATA 0x00000000 +#define DDRSS2_PI_181_DATA 0x01010101 +#define DDRSS2_PI_182_DATA 0x00000101 +#define DDRSS2_PI_183_DATA 0x00000000 +#define DDRSS2_PI_184_DATA 0x00000000 +#define DDRSS2_PI_185_DATA 0x15040000 +#define DDRSS2_PI_186_DATA 0x0E0E0215 +#define DDRSS2_PI_187_DATA 0x00040402 +#define DDRSS2_PI_188_DATA 0x000D0035 +#define DDRSS2_PI_189_DATA 0x00218049 +#define DDRSS2_PI_190_DATA 0x00218049 +#define DDRSS2_PI_191_DATA 0x01010101 +#define DDRSS2_PI_192_DATA 0x0004000E +#define DDRSS2_PI_193_DATA 0x00040216 +#define DDRSS2_PI_194_DATA 0x01000216 +#define DDRSS2_PI_195_DATA 0x000F000F +#define DDRSS2_PI_196_DATA 0x02170100 +#define DDRSS2_PI_197_DATA 0x01000217 +#define DDRSS2_PI_198_DATA 0x02170217 +#define DDRSS2_PI_199_DATA 0x32103200 +#define DDRSS2_PI_200_DATA 0x01013210 +#define DDRSS2_PI_201_DATA 0x0A070601 +#define DDRSS2_PI_202_DATA 0x1F130A0D +#define DDRSS2_PI_203_DATA 0x1F130A14 +#define DDRSS2_PI_204_DATA 0x0000C014 +#define DDRSS2_PI_205_DATA 0x00C01000 +#define DDRSS2_PI_206_DATA 0x00C01000 +#define DDRSS2_PI_207_DATA 0x00021000 +#define DDRSS2_PI_208_DATA 0x0024000E +#define DDRSS2_PI_209_DATA 0x00240216 +#define DDRSS2_PI_210_DATA 0x00110216 +#define DDRSS2_PI_211_DATA 0x32000056 +#define DDRSS2_PI_212_DATA 0x00000301 +#define DDRSS2_PI_213_DATA 0x005B0036 +#define DDRSS2_PI_214_DATA 0x03013212 +#define DDRSS2_PI_215_DATA 0x00003600 +#define DDRSS2_PI_216_DATA 0x3212005B +#define DDRSS2_PI_217_DATA 0x09000301 +#define DDRSS2_PI_218_DATA 0x04010504 +#define DDRSS2_PI_219_DATA 0x04000364 +#define DDRSS2_PI_220_DATA 0x0A032001 +#define DDRSS2_PI_221_DATA 0x2C31110A +#define DDRSS2_PI_222_DATA 0x00002918 +#define DDRSS2_PI_223_DATA 0x6000838E +#define DDRSS2_PI_224_DATA 0x1E202008 +#define DDRSS2_PI_225_DATA 0x2C311116 +#define DDRSS2_PI_226_DATA 0x00002918 +#define DDRSS2_PI_227_DATA 0x6000838E +#define DDRSS2_PI_228_DATA 0x1E202008 +#define DDRSS2_PI_229_DATA 0x0000C616 +#define DDRSS2_PI_230_DATA 0x000007BC +#define DDRSS2_PI_231_DATA 0x0000206A +#define DDRSS2_PI_232_DATA 0x00014424 +#define DDRSS2_PI_233_DATA 0x0000206A +#define DDRSS2_PI_234_DATA 0x00014424 +#define DDRSS2_PI_235_DATA 0x033B0016 +#define DDRSS2_PI_236_DATA 0x0303033B +#define DDRSS2_PI_237_DATA 0x002AF803 +#define DDRSS2_PI_238_DATA 0x0001ADAF +#define DDRSS2_PI_239_DATA 0x00000005 +#define DDRSS2_PI_240_DATA 0x0000006E +#define DDRSS2_PI_241_DATA 0x00000016 +#define DDRSS2_PI_242_DATA 0x000681C8 +#define DDRSS2_PI_243_DATA 0x0001ADAF +#define DDRSS2_PI_244_DATA 0x00000005 +#define DDRSS2_PI_245_DATA 0x000010A9 +#define DDRSS2_PI_246_DATA 0x0000033B +#define DDRSS2_PI_247_DATA 0x000681C8 +#define DDRSS2_PI_248_DATA 0x0001ADAF +#define DDRSS2_PI_249_DATA 0x00000005 +#define DDRSS2_PI_250_DATA 0x000010A9 +#define DDRSS2_PI_251_DATA 0x0100033B +#define DDRSS2_PI_252_DATA 0x00370040 +#define DDRSS2_PI_253_DATA 0x00010008 +#define DDRSS2_PI_254_DATA 0x08550040 +#define DDRSS2_PI_255_DATA 0x00010040 +#define DDRSS2_PI_256_DATA 0x08550040 +#define DDRSS2_PI_257_DATA 0x00000340 +#define DDRSS2_PI_258_DATA 0x006B006B +#define DDRSS2_PI_259_DATA 0x08040404 +#define DDRSS2_PI_260_DATA 0x00000055 +#define DDRSS2_PI_261_DATA 0x55083C5A +#define DDRSS2_PI_262_DATA 0x5A000000 +#define DDRSS2_PI_263_DATA 0x0055083C +#define DDRSS2_PI_264_DATA 0x3C5A0000 +#define DDRSS2_PI_265_DATA 0x00005508 +#define DDRSS2_PI_266_DATA 0x0C3C5A00 +#define DDRSS2_PI_267_DATA 0x080F0E0D +#define DDRSS2_PI_268_DATA 0x000B0A09 +#define DDRSS2_PI_269_DATA 0x00030201 +#define DDRSS2_PI_270_DATA 0x01000000 +#define DDRSS2_PI_271_DATA 0x04020201 +#define DDRSS2_PI_272_DATA 0x00080804 +#define DDRSS2_PI_273_DATA 0x00000000 +#define DDRSS2_PI_274_DATA 0x00000000 +#define DDRSS2_PI_275_DATA 0x00330084 +#define DDRSS2_PI_276_DATA 0x00160000 +#define DDRSS2_PI_277_DATA 0x35333FF4 +#define DDRSS2_PI_278_DATA 0x00160F27 +#define DDRSS2_PI_279_DATA 0x35333FF4 +#define DDRSS2_PI_280_DATA 0x00160F27 +#define DDRSS2_PI_281_DATA 0x00330084 +#define DDRSS2_PI_282_DATA 0x00160000 +#define DDRSS2_PI_283_DATA 0x35333FF4 +#define DDRSS2_PI_284_DATA 0x00160F27 +#define DDRSS2_PI_285_DATA 0x35333FF4 +#define DDRSS2_PI_286_DATA 0x00160F27 +#define DDRSS2_PI_287_DATA 0x00330084 +#define DDRSS2_PI_288_DATA 0x00160000 +#define DDRSS2_PI_289_DATA 0x35333FF4 +#define DDRSS2_PI_290_DATA 0x00160F27 +#define DDRSS2_PI_291_DATA 0x35333FF4 +#define DDRSS2_PI_292_DATA 0x00160F27 +#define DDRSS2_PI_293_DATA 0x00330084 +#define DDRSS2_PI_294_DATA 0x00160000 +#define DDRSS2_PI_295_DATA 0x35333FF4 +#define DDRSS2_PI_296_DATA 0x00160F27 +#define DDRSS2_PI_297_DATA 0x35333FF4 +#define DDRSS2_PI_298_DATA 0x00160F27 +#define DDRSS2_PI_299_DATA 0x00000000 + +#define DDRSS2_PHY_00_DATA 0x000004F0 +#define DDRSS2_PHY_01_DATA 0x00000000 +#define DDRSS2_PHY_02_DATA 0x00030200 +#define DDRSS2_PHY_03_DATA 0x00000000 +#define DDRSS2_PHY_04_DATA 0x00000000 +#define DDRSS2_PHY_05_DATA 0x01030000 +#define DDRSS2_PHY_06_DATA 0x00010000 +#define DDRSS2_PHY_07_DATA 0x01030004 +#define DDRSS2_PHY_08_DATA 0x01000000 +#define DDRSS2_PHY_09_DATA 0x00000000 +#define DDRSS2_PHY_10_DATA 0x00000000 +#define DDRSS2_PHY_11_DATA 0x01000001 +#define DDRSS2_PHY_12_DATA 0x00000100 +#define DDRSS2_PHY_13_DATA 0x000800C0 +#define DDRSS2_PHY_14_DATA 0x060100CC +#define DDRSS2_PHY_15_DATA 0x00030066 +#define DDRSS2_PHY_16_DATA 0x00000000 +#define DDRSS2_PHY_17_DATA 0x00000301 +#define DDRSS2_PHY_18_DATA 0x0000AAAA +#define DDRSS2_PHY_19_DATA 0x00005555 +#define DDRSS2_PHY_20_DATA 0x0000B5B5 +#define DDRSS2_PHY_21_DATA 0x00004A4A +#define DDRSS2_PHY_22_DATA 0x00005656 +#define DDRSS2_PHY_23_DATA 0x0000A9A9 +#define DDRSS2_PHY_24_DATA 0x0000A9A9 +#define DDRSS2_PHY_25_DATA 0x0000B5B5 +#define DDRSS2_PHY_26_DATA 0x00000000 +#define DDRSS2_PHY_27_DATA 0x00000000 +#define DDRSS2_PHY_28_DATA 0x2A000000 +#define DDRSS2_PHY_29_DATA 0x00000808 +#define DDRSS2_PHY_30_DATA 0x0F000000 +#define DDRSS2_PHY_31_DATA 0x00000F0F +#define DDRSS2_PHY_32_DATA 0x10400000 +#define DDRSS2_PHY_33_DATA 0x0C002006 +#define DDRSS2_PHY_34_DATA 0x00000000 +#define DDRSS2_PHY_35_DATA 0x00000000 +#define DDRSS2_PHY_36_DATA 0x55555555 +#define DDRSS2_PHY_37_DATA 0xAAAAAAAA +#define DDRSS2_PHY_38_DATA 0x55555555 +#define DDRSS2_PHY_39_DATA 0xAAAAAAAA +#define DDRSS2_PHY_40_DATA 0x00005555 +#define DDRSS2_PHY_41_DATA 0x01000100 +#define DDRSS2_PHY_42_DATA 0x00800180 +#define DDRSS2_PHY_43_DATA 0x00000001 +#define DDRSS2_PHY_44_DATA 0x00000000 +#define DDRSS2_PHY_45_DATA 0x00000000 +#define DDRSS2_PHY_46_DATA 0x00000000 +#define DDRSS2_PHY_47_DATA 0x00000000 +#define DDRSS2_PHY_48_DATA 0x00000000 +#define DDRSS2_PHY_49_DATA 0x00000000 +#define DDRSS2_PHY_50_DATA 0x00000000 +#define DDRSS2_PHY_51_DATA 0x00000000 +#define DDRSS2_PHY_52_DATA 0x00000000 +#define DDRSS2_PHY_53_DATA 0x00000000 +#define DDRSS2_PHY_54_DATA 0x00000000 +#define DDRSS2_PHY_55_DATA 0x00000000 +#define DDRSS2_PHY_56_DATA 0x00000000 +#define DDRSS2_PHY_57_DATA 0x00000000 +#define DDRSS2_PHY_58_DATA 0x00000000 +#define DDRSS2_PHY_59_DATA 0x00000000 +#define DDRSS2_PHY_60_DATA 0x00000000 +#define DDRSS2_PHY_61_DATA 0x00000000 +#define DDRSS2_PHY_62_DATA 0x00000000 +#define DDRSS2_PHY_63_DATA 0x00000000 +#define DDRSS2_PHY_64_DATA 0x00000000 +#define DDRSS2_PHY_65_DATA 0x00000000 +#define DDRSS2_PHY_66_DATA 0x00000104 +#define DDRSS2_PHY_67_DATA 0x00000120 +#define DDRSS2_PHY_68_DATA 0x00000000 +#define DDRSS2_PHY_69_DATA 0x00000000 +#define DDRSS2_PHY_70_DATA 0x00000000 +#define DDRSS2_PHY_71_DATA 0x00000000 +#define DDRSS2_PHY_72_DATA 0x00000000 +#define DDRSS2_PHY_73_DATA 0x00000000 +#define DDRSS2_PHY_74_DATA 0x00000000 +#define DDRSS2_PHY_75_DATA 0x00000001 +#define DDRSS2_PHY_76_DATA 0x07FF0000 +#define DDRSS2_PHY_77_DATA 0x0080081F +#define DDRSS2_PHY_78_DATA 0x00081020 +#define DDRSS2_PHY_79_DATA 0x04010000 +#define DDRSS2_PHY_80_DATA 0x00000000 +#define DDRSS2_PHY_81_DATA 0x00000000 +#define DDRSS2_PHY_82_DATA 0x00000000 +#define DDRSS2_PHY_83_DATA 0x00000100 +#define DDRSS2_PHY_84_DATA 0x01CC0C01 +#define DDRSS2_PHY_85_DATA 0x1003CC0C +#define DDRSS2_PHY_86_DATA 0x20000140 +#define DDRSS2_PHY_87_DATA 0x07FF0200 +#define DDRSS2_PHY_88_DATA 0x0000DD01 +#define DDRSS2_PHY_89_DATA 0x10100303 +#define DDRSS2_PHY_90_DATA 0x10101010 +#define DDRSS2_PHY_91_DATA 0x10101010 +#define DDRSS2_PHY_92_DATA 0x00021010 +#define DDRSS2_PHY_93_DATA 0x00100010 +#define DDRSS2_PHY_94_DATA 0x00100010 +#define DDRSS2_PHY_95_DATA 0x00100010 +#define DDRSS2_PHY_96_DATA 0x00100010 +#define DDRSS2_PHY_97_DATA 0x00050010 +#define DDRSS2_PHY_98_DATA 0x51517041 +#define DDRSS2_PHY_99_DATA 0x31C06001 +#define DDRSS2_PHY_100_DATA 0x07AB0340 +#define DDRSS2_PHY_101_DATA 0x00C0C001 +#define DDRSS2_PHY_102_DATA 0x0E0D0001 +#define DDRSS2_PHY_103_DATA 0x10001000 +#define DDRSS2_PHY_104_DATA 0x0C083E42 +#define DDRSS2_PHY_105_DATA 0x0F0C3701 +#define DDRSS2_PHY_106_DATA 0x01000140 +#define DDRSS2_PHY_107_DATA 0x0C000420 +#define DDRSS2_PHY_108_DATA 0x00000198 +#define DDRSS2_PHY_109_DATA 0x0A0000D0 +#define DDRSS2_PHY_110_DATA 0x00030200 +#define DDRSS2_PHY_111_DATA 0x02800000 +#define DDRSS2_PHY_112_DATA 0x80800000 +#define DDRSS2_PHY_113_DATA 0x000E2010 +#define DDRSS2_PHY_114_DATA 0x76543210 +#define DDRSS2_PHY_115_DATA 0x00000008 +#define DDRSS2_PHY_116_DATA 0x02800280 +#define DDRSS2_PHY_117_DATA 0x02800280 +#define DDRSS2_PHY_118_DATA 0x02800280 +#define DDRSS2_PHY_119_DATA 0x02800280 +#define DDRSS2_PHY_120_DATA 0x00000280 +#define DDRSS2_PHY_121_DATA 0x0000A000 +#define DDRSS2_PHY_122_DATA 0x00A000A0 +#define DDRSS2_PHY_123_DATA 0x00A000A0 +#define DDRSS2_PHY_124_DATA 0x00A000A0 +#define DDRSS2_PHY_125_DATA 0x00A000A0 +#define DDRSS2_PHY_126_DATA 0x00A000A0 +#define DDRSS2_PHY_127_DATA 0x00A000A0 +#define DDRSS2_PHY_128_DATA 0x00A000A0 +#define DDRSS2_PHY_129_DATA 0x00A000A0 +#define DDRSS2_PHY_130_DATA 0x01C200A0 +#define DDRSS2_PHY_131_DATA 0x01A00005 +#define DDRSS2_PHY_132_DATA 0x00000000 +#define DDRSS2_PHY_133_DATA 0x00000000 +#define DDRSS2_PHY_134_DATA 0x00080200 +#define DDRSS2_PHY_135_DATA 0x00000000 +#define DDRSS2_PHY_136_DATA 0x20202000 +#define DDRSS2_PHY_137_DATA 0x20202020 +#define DDRSS2_PHY_138_DATA 0xF0F02020 +#define DDRSS2_PHY_139_DATA 0x00000000 +#define DDRSS2_PHY_140_DATA 0x00000000 +#define DDRSS2_PHY_141_DATA 0x00000000 +#define DDRSS2_PHY_142_DATA 0x00000000 +#define DDRSS2_PHY_143_DATA 0x00000000 +#define DDRSS2_PHY_144_DATA 0x00000000 +#define DDRSS2_PHY_145_DATA 0x00000000 +#define DDRSS2_PHY_146_DATA 0x00000000 +#define DDRSS2_PHY_147_DATA 0x00000000 +#define DDRSS2_PHY_148_DATA 0x00000000 +#define DDRSS2_PHY_149_DATA 0x00000000 +#define DDRSS2_PHY_150_DATA 0x00000000 +#define DDRSS2_PHY_151_DATA 0x00000000 +#define DDRSS2_PHY_152_DATA 0x00000000 +#define DDRSS2_PHY_153_DATA 0x00000000 +#define DDRSS2_PHY_154_DATA 0x00000000 +#define DDRSS2_PHY_155_DATA 0x00000000 +#define DDRSS2_PHY_156_DATA 0x00000000 +#define DDRSS2_PHY_157_DATA 0x00000000 +#define DDRSS2_PHY_158_DATA 0x00000000 +#define DDRSS2_PHY_159_DATA 0x00000000 +#define DDRSS2_PHY_160_DATA 0x00000000 +#define DDRSS2_PHY_161_DATA 0x00000000 +#define DDRSS2_PHY_162_DATA 0x00000000 +#define DDRSS2_PHY_163_DATA 0x00000000 +#define DDRSS2_PHY_164_DATA 0x00000000 +#define DDRSS2_PHY_165_DATA 0x00000000 +#define DDRSS2_PHY_166_DATA 0x00000000 +#define DDRSS2_PHY_167_DATA 0x00000000 +#define DDRSS2_PHY_168_DATA 0x00000000 +#define DDRSS2_PHY_169_DATA 0x00000000 +#define DDRSS2_PHY_170_DATA 0x00000000 +#define DDRSS2_PHY_171_DATA 0x00000000 +#define DDRSS2_PHY_172_DATA 0x00000000 +#define DDRSS2_PHY_173_DATA 0x00000000 +#define DDRSS2_PHY_174_DATA 0x00000000 +#define DDRSS2_PHY_175_DATA 0x00000000 +#define DDRSS2_PHY_176_DATA 0x00000000 +#define DDRSS2_PHY_177_DATA 0x00000000 +#define DDRSS2_PHY_178_DATA 0x00000000 +#define DDRSS2_PHY_179_DATA 0x00000000 +#define DDRSS2_PHY_180_DATA 0x00000000 +#define DDRSS2_PHY_181_DATA 0x00000000 +#define DDRSS2_PHY_182_DATA 0x00000000 +#define DDRSS2_PHY_183_DATA 0x00000000 +#define DDRSS2_PHY_184_DATA 0x00000000 +#define DDRSS2_PHY_185_DATA 0x00000000 +#define DDRSS2_PHY_186_DATA 0x00000000 +#define DDRSS2_PHY_187_DATA 0x00000000 +#define DDRSS2_PHY_188_DATA 0x00000000 +#define DDRSS2_PHY_189_DATA 0x00000000 +#define DDRSS2_PHY_190_DATA 0x00000000 +#define DDRSS2_PHY_191_DATA 0x00000000 +#define DDRSS2_PHY_192_DATA 0x00000000 +#define DDRSS2_PHY_193_DATA 0x00000000 +#define DDRSS2_PHY_194_DATA 0x00000000 +#define DDRSS2_PHY_195_DATA 0x00000000 +#define DDRSS2_PHY_196_DATA 0x00000000 +#define DDRSS2_PHY_197_DATA 0x00000000 +#define DDRSS2_PHY_198_DATA 0x00000000 +#define DDRSS2_PHY_199_DATA 0x00000000 +#define DDRSS2_PHY_200_DATA 0x00000000 +#define DDRSS2_PHY_201_DATA 0x00000000 +#define DDRSS2_PHY_202_DATA 0x00000000 +#define DDRSS2_PHY_203_DATA 0x00000000 +#define DDRSS2_PHY_204_DATA 0x00000000 +#define DDRSS2_PHY_205_DATA 0x00000000 +#define DDRSS2_PHY_206_DATA 0x00000000 +#define DDRSS2_PHY_207_DATA 0x00000000 +#define DDRSS2_PHY_208_DATA 0x00000000 +#define DDRSS2_PHY_209_DATA 0x00000000 +#define DDRSS2_PHY_210_DATA 0x00000000 +#define DDRSS2_PHY_211_DATA 0x00000000 +#define DDRSS2_PHY_212_DATA 0x00000000 +#define DDRSS2_PHY_213_DATA 0x00000000 +#define DDRSS2_PHY_214_DATA 0x00000000 +#define DDRSS2_PHY_215_DATA 0x00000000 +#define DDRSS2_PHY_216_DATA 0x00000000 +#define DDRSS2_PHY_217_DATA 0x00000000 +#define DDRSS2_PHY_218_DATA 0x00000000 +#define DDRSS2_PHY_219_DATA 0x00000000 +#define DDRSS2_PHY_220_DATA 0x00000000 +#define DDRSS2_PHY_221_DATA 0x00000000 +#define DDRSS2_PHY_222_DATA 0x00000000 +#define DDRSS2_PHY_223_DATA 0x00000000 +#define DDRSS2_PHY_224_DATA 0x00000000 +#define DDRSS2_PHY_225_DATA 0x00000000 +#define DDRSS2_PHY_226_DATA 0x00000000 +#define DDRSS2_PHY_227_DATA 0x00000000 +#define DDRSS2_PHY_228_DATA 0x00000000 +#define DDRSS2_PHY_229_DATA 0x00000000 +#define DDRSS2_PHY_230_DATA 0x00000000 +#define DDRSS2_PHY_231_DATA 0x00000000 +#define DDRSS2_PHY_232_DATA 0x00000000 +#define DDRSS2_PHY_233_DATA 0x00000000 +#define DDRSS2_PHY_234_DATA 0x00000000 +#define DDRSS2_PHY_235_DATA 0x00000000 +#define DDRSS2_PHY_236_DATA 0x00000000 +#define DDRSS2_PHY_237_DATA 0x00000000 +#define DDRSS2_PHY_238_DATA 0x00000000 +#define DDRSS2_PHY_239_DATA 0x00000000 +#define DDRSS2_PHY_240_DATA 0x00000000 +#define DDRSS2_PHY_241_DATA 0x00000000 +#define DDRSS2_PHY_242_DATA 0x00000000 +#define DDRSS2_PHY_243_DATA 0x00000000 +#define DDRSS2_PHY_244_DATA 0x00000000 +#define DDRSS2_PHY_245_DATA 0x00000000 +#define DDRSS2_PHY_246_DATA 0x00000000 +#define DDRSS2_PHY_247_DATA 0x00000000 +#define DDRSS2_PHY_248_DATA 0x00000000 +#define DDRSS2_PHY_249_DATA 0x00000000 +#define DDRSS2_PHY_250_DATA 0x00000000 +#define DDRSS2_PHY_251_DATA 0x00000000 +#define DDRSS2_PHY_252_DATA 0x00000000 +#define DDRSS2_PHY_253_DATA 0x00000000 +#define DDRSS2_PHY_254_DATA 0x00000000 +#define DDRSS2_PHY_255_DATA 0x00000000 +#define DDRSS2_PHY_256_DATA 0x000004F0 +#define DDRSS2_PHY_257_DATA 0x00000000 +#define DDRSS2_PHY_258_DATA 0x00030200 +#define DDRSS2_PHY_259_DATA 0x00000000 +#define DDRSS2_PHY_260_DATA 0x00000000 +#define DDRSS2_PHY_261_DATA 0x01030000 +#define DDRSS2_PHY_262_DATA 0x00010000 +#define DDRSS2_PHY_263_DATA 0x01030004 +#define DDRSS2_PHY_264_DATA 0x01000000 +#define DDRSS2_PHY_265_DATA 0x00000000 +#define DDRSS2_PHY_266_DATA 0x00000000 +#define DDRSS2_PHY_267_DATA 0x01000001 +#define DDRSS2_PHY_268_DATA 0x00000100 +#define DDRSS2_PHY_269_DATA 0x000800C0 +#define DDRSS2_PHY_270_DATA 0x060100CC +#define DDRSS2_PHY_271_DATA 0x00030066 +#define DDRSS2_PHY_272_DATA 0x00000000 +#define DDRSS2_PHY_273_DATA 0x00000301 +#define DDRSS2_PHY_274_DATA 0x0000AAAA +#define DDRSS2_PHY_275_DATA 0x00005555 +#define DDRSS2_PHY_276_DATA 0x0000B5B5 +#define DDRSS2_PHY_277_DATA 0x00004A4A +#define DDRSS2_PHY_278_DATA 0x00005656 +#define DDRSS2_PHY_279_DATA 0x0000A9A9 +#define DDRSS2_PHY_280_DATA 0x0000A9A9 +#define DDRSS2_PHY_281_DATA 0x0000B5B5 +#define DDRSS2_PHY_282_DATA 0x00000000 +#define DDRSS2_PHY_283_DATA 0x00000000 +#define DDRSS2_PHY_284_DATA 0x2A000000 +#define DDRSS2_PHY_285_DATA 0x00000808 +#define DDRSS2_PHY_286_DATA 0x0F000000 +#define DDRSS2_PHY_287_DATA 0x00000F0F +#define DDRSS2_PHY_288_DATA 0x10400000 +#define DDRSS2_PHY_289_DATA 0x0C002006 +#define DDRSS2_PHY_290_DATA 0x00000000 +#define DDRSS2_PHY_291_DATA 0x00000000 +#define DDRSS2_PHY_292_DATA 0x55555555 +#define DDRSS2_PHY_293_DATA 0xAAAAAAAA +#define DDRSS2_PHY_294_DATA 0x55555555 +#define DDRSS2_PHY_295_DATA 0xAAAAAAAA +#define DDRSS2_PHY_296_DATA 0x00005555 +#define DDRSS2_PHY_297_DATA 0x01000100 +#define DDRSS2_PHY_298_DATA 0x00800180 +#define DDRSS2_PHY_299_DATA 0x00000000 +#define DDRSS2_PHY_300_DATA 0x00000000 +#define DDRSS2_PHY_301_DATA 0x00000000 +#define DDRSS2_PHY_302_DATA 0x00000000 +#define DDRSS2_PHY_303_DATA 0x00000000 +#define DDRSS2_PHY_304_DATA 0x00000000 +#define DDRSS2_PHY_305_DATA 0x00000000 +#define DDRSS2_PHY_306_DATA 0x00000000 +#define DDRSS2_PHY_307_DATA 0x00000000 +#define DDRSS2_PHY_308_DATA 0x00000000 +#define DDRSS2_PHY_309_DATA 0x00000000 +#define DDRSS2_PHY_310_DATA 0x00000000 +#define DDRSS2_PHY_311_DATA 0x00000000 +#define DDRSS2_PHY_312_DATA 0x00000000 +#define DDRSS2_PHY_313_DATA 0x00000000 +#define DDRSS2_PHY_314_DATA 0x00000000 +#define DDRSS2_PHY_315_DATA 0x00000000 +#define DDRSS2_PHY_316_DATA 0x00000000 +#define DDRSS2_PHY_317_DATA 0x00000000 +#define DDRSS2_PHY_318_DATA 0x00000000 +#define DDRSS2_PHY_319_DATA 0x00000000 +#define DDRSS2_PHY_320_DATA 0x00000000 +#define DDRSS2_PHY_321_DATA 0x00000000 +#define DDRSS2_PHY_322_DATA 0x00000104 +#define DDRSS2_PHY_323_DATA 0x00000120 +#define DDRSS2_PHY_324_DATA 0x00000000 +#define DDRSS2_PHY_325_DATA 0x00000000 +#define DDRSS2_PHY_326_DATA 0x00000000 +#define DDRSS2_PHY_327_DATA 0x00000000 +#define DDRSS2_PHY_328_DATA 0x00000000 +#define DDRSS2_PHY_329_DATA 0x00000000 +#define DDRSS2_PHY_330_DATA 0x00000000 +#define DDRSS2_PHY_331_DATA 0x00000001 +#define DDRSS2_PHY_332_DATA 0x07FF0000 +#define DDRSS2_PHY_333_DATA 0x0080081F +#define DDRSS2_PHY_334_DATA 0x00081020 +#define DDRSS2_PHY_335_DATA 0x04010000 +#define DDRSS2_PHY_336_DATA 0x00000000 +#define DDRSS2_PHY_337_DATA 0x00000000 +#define DDRSS2_PHY_338_DATA 0x00000000 +#define DDRSS2_PHY_339_DATA 0x00000100 +#define DDRSS2_PHY_340_DATA 0x01CC0C01 +#define DDRSS2_PHY_341_DATA 0x1003CC0C +#define DDRSS2_PHY_342_DATA 0x20000140 +#define DDRSS2_PHY_343_DATA 0x07FF0200 +#define DDRSS2_PHY_344_DATA 0x0000DD01 +#define DDRSS2_PHY_345_DATA 0x10100303 +#define DDRSS2_PHY_346_DATA 0x10101010 +#define DDRSS2_PHY_347_DATA 0x10101010 +#define DDRSS2_PHY_348_DATA 0x00021010 +#define DDRSS2_PHY_349_DATA 0x00100010 +#define DDRSS2_PHY_350_DATA 0x00100010 +#define DDRSS2_PHY_351_DATA 0x00100010 +#define DDRSS2_PHY_352_DATA 0x00100010 +#define DDRSS2_PHY_353_DATA 0x00050010 +#define DDRSS2_PHY_354_DATA 0x51517041 +#define DDRSS2_PHY_355_DATA 0x31C06001 +#define DDRSS2_PHY_356_DATA 0x07AB0340 +#define DDRSS2_PHY_357_DATA 0x00C0C001 +#define DDRSS2_PHY_358_DATA 0x0E0D0001 +#define DDRSS2_PHY_359_DATA 0x10001000 +#define DDRSS2_PHY_360_DATA 0x0C083E42 +#define DDRSS2_PHY_361_DATA 0x0F0C3701 +#define DDRSS2_PHY_362_DATA 0x01000140 +#define DDRSS2_PHY_363_DATA 0x0C000420 +#define DDRSS2_PHY_364_DATA 0x00000198 +#define DDRSS2_PHY_365_DATA 0x0A0000D0 +#define DDRSS2_PHY_366_DATA 0x00030200 +#define DDRSS2_PHY_367_DATA 0x02800000 +#define DDRSS2_PHY_368_DATA 0x80800000 +#define DDRSS2_PHY_369_DATA 0x000E2010 +#define DDRSS2_PHY_370_DATA 0x76543210 +#define DDRSS2_PHY_371_DATA 0x00000008 +#define DDRSS2_PHY_372_DATA 0x02800280 +#define DDRSS2_PHY_373_DATA 0x02800280 +#define DDRSS2_PHY_374_DATA 0x02800280 +#define DDRSS2_PHY_375_DATA 0x02800280 +#define DDRSS2_PHY_376_DATA 0x00000280 +#define DDRSS2_PHY_377_DATA 0x0000A000 +#define DDRSS2_PHY_378_DATA 0x00A000A0 +#define DDRSS2_PHY_379_DATA 0x00A000A0 +#define DDRSS2_PHY_380_DATA 0x00A000A0 +#define DDRSS2_PHY_381_DATA 0x00A000A0 +#define DDRSS2_PHY_382_DATA 0x00A000A0 +#define DDRSS2_PHY_383_DATA 0x00A000A0 +#define DDRSS2_PHY_384_DATA 0x00A000A0 +#define DDRSS2_PHY_385_DATA 0x00A000A0 +#define DDRSS2_PHY_386_DATA 0x01C200A0 +#define DDRSS2_PHY_387_DATA 0x01A00005 +#define DDRSS2_PHY_388_DATA 0x00000000 +#define DDRSS2_PHY_389_DATA 0x00000000 +#define DDRSS2_PHY_390_DATA 0x00080200 +#define DDRSS2_PHY_391_DATA 0x00000000 +#define DDRSS2_PHY_392_DATA 0x20202000 +#define DDRSS2_PHY_393_DATA 0x20202020 +#define DDRSS2_PHY_394_DATA 0xF0F02020 +#define DDRSS2_PHY_395_DATA 0x00000000 +#define DDRSS2_PHY_396_DATA 0x00000000 +#define DDRSS2_PHY_397_DATA 0x00000000 +#define DDRSS2_PHY_398_DATA 0x00000000 +#define DDRSS2_PHY_399_DATA 0x00000000 +#define DDRSS2_PHY_400_DATA 0x00000000 +#define DDRSS2_PHY_401_DATA 0x00000000 +#define DDRSS2_PHY_402_DATA 0x00000000 +#define DDRSS2_PHY_403_DATA 0x00000000 +#define DDRSS2_PHY_404_DATA 0x00000000 +#define DDRSS2_PHY_405_DATA 0x00000000 +#define DDRSS2_PHY_406_DATA 0x00000000 +#define DDRSS2_PHY_407_DATA 0x00000000 +#define DDRSS2_PHY_408_DATA 0x00000000 +#define DDRSS2_PHY_409_DATA 0x00000000 +#define DDRSS2_PHY_410_DATA 0x00000000 +#define DDRSS2_PHY_411_DATA 0x00000000 +#define DDRSS2_PHY_412_DATA 0x00000000 +#define DDRSS2_PHY_413_DATA 0x00000000 +#define DDRSS2_PHY_414_DATA 0x00000000 +#define DDRSS2_PHY_415_DATA 0x00000000 +#define DDRSS2_PHY_416_DATA 0x00000000 +#define DDRSS2_PHY_417_DATA 0x00000000 +#define DDRSS2_PHY_418_DATA 0x00000000 +#define DDRSS2_PHY_419_DATA 0x00000000 +#define DDRSS2_PHY_420_DATA 0x00000000 +#define DDRSS2_PHY_421_DATA 0x00000000 +#define DDRSS2_PHY_422_DATA 0x00000000 +#define DDRSS2_PHY_423_DATA 0x00000000 +#define DDRSS2_PHY_424_DATA 0x00000000 +#define DDRSS2_PHY_425_DATA 0x00000000 +#define DDRSS2_PHY_426_DATA 0x00000000 +#define DDRSS2_PHY_427_DATA 0x00000000 +#define DDRSS2_PHY_428_DATA 0x00000000 +#define DDRSS2_PHY_429_DATA 0x00000000 +#define DDRSS2_PHY_430_DATA 0x00000000 +#define DDRSS2_PHY_431_DATA 0x00000000 +#define DDRSS2_PHY_432_DATA 0x00000000 +#define DDRSS2_PHY_433_DATA 0x00000000 +#define DDRSS2_PHY_434_DATA 0x00000000 +#define DDRSS2_PHY_435_DATA 0x00000000 +#define DDRSS2_PHY_436_DATA 0x00000000 +#define DDRSS2_PHY_437_DATA 0x00000000 +#define DDRSS2_PHY_438_DATA 0x00000000 +#define DDRSS2_PHY_439_DATA 0x00000000 +#define DDRSS2_PHY_440_DATA 0x00000000 +#define DDRSS2_PHY_441_DATA 0x00000000 +#define DDRSS2_PHY_442_DATA 0x00000000 +#define DDRSS2_PHY_443_DATA 0x00000000 +#define DDRSS2_PHY_444_DATA 0x00000000 +#define DDRSS2_PHY_445_DATA 0x00000000 +#define DDRSS2_PHY_446_DATA 0x00000000 +#define DDRSS2_PHY_447_DATA 0x00000000 +#define DDRSS2_PHY_448_DATA 0x00000000 +#define DDRSS2_PHY_449_DATA 0x00000000 +#define DDRSS2_PHY_450_DATA 0x00000000 +#define DDRSS2_PHY_451_DATA 0x00000000 +#define DDRSS2_PHY_452_DATA 0x00000000 +#define DDRSS2_PHY_453_DATA 0x00000000 +#define DDRSS2_PHY_454_DATA 0x00000000 +#define DDRSS2_PHY_455_DATA 0x00000000 +#define DDRSS2_PHY_456_DATA 0x00000000 +#define DDRSS2_PHY_457_DATA 0x00000000 +#define DDRSS2_PHY_458_DATA 0x00000000 +#define DDRSS2_PHY_459_DATA 0x00000000 +#define DDRSS2_PHY_460_DATA 0x00000000 +#define DDRSS2_PHY_461_DATA 0x00000000 +#define DDRSS2_PHY_462_DATA 0x00000000 +#define DDRSS2_PHY_463_DATA 0x00000000 +#define DDRSS2_PHY_464_DATA 0x00000000 +#define DDRSS2_PHY_465_DATA 0x00000000 +#define DDRSS2_PHY_466_DATA 0x00000000 +#define DDRSS2_PHY_467_DATA 0x00000000 +#define DDRSS2_PHY_468_DATA 0x00000000 +#define DDRSS2_PHY_469_DATA 0x00000000 +#define DDRSS2_PHY_470_DATA 0x00000000 +#define DDRSS2_PHY_471_DATA 0x00000000 +#define DDRSS2_PHY_472_DATA 0x00000000 +#define DDRSS2_PHY_473_DATA 0x00000000 +#define DDRSS2_PHY_474_DATA 0x00000000 +#define DDRSS2_PHY_475_DATA 0x00000000 +#define DDRSS2_PHY_476_DATA 0x00000000 +#define DDRSS2_PHY_477_DATA 0x00000000 +#define DDRSS2_PHY_478_DATA 0x00000000 +#define DDRSS2_PHY_479_DATA 0x00000000 +#define DDRSS2_PHY_480_DATA 0x00000000 +#define DDRSS2_PHY_481_DATA 0x00000000 +#define DDRSS2_PHY_482_DATA 0x00000000 +#define DDRSS2_PHY_483_DATA 0x00000000 +#define DDRSS2_PHY_484_DATA 0x00000000 +#define DDRSS2_PHY_485_DATA 0x00000000 +#define DDRSS2_PHY_486_DATA 0x00000000 +#define DDRSS2_PHY_487_DATA 0x00000000 +#define DDRSS2_PHY_488_DATA 0x00000000 +#define DDRSS2_PHY_489_DATA 0x00000000 +#define DDRSS2_PHY_490_DATA 0x00000000 +#define DDRSS2_PHY_491_DATA 0x00000000 +#define DDRSS2_PHY_492_DATA 0x00000000 +#define DDRSS2_PHY_493_DATA 0x00000000 +#define DDRSS2_PHY_494_DATA 0x00000000 +#define DDRSS2_PHY_495_DATA 0x00000000 +#define DDRSS2_PHY_496_DATA 0x00000000 +#define DDRSS2_PHY_497_DATA 0x00000000 +#define DDRSS2_PHY_498_DATA 0x00000000 +#define DDRSS2_PHY_499_DATA 0x00000000 +#define DDRSS2_PHY_500_DATA 0x00000000 +#define DDRSS2_PHY_501_DATA 0x00000000 +#define DDRSS2_PHY_502_DATA 0x00000000 +#define DDRSS2_PHY_503_DATA 0x00000000 +#define DDRSS2_PHY_504_DATA 0x00000000 +#define DDRSS2_PHY_505_DATA 0x00000000 +#define DDRSS2_PHY_506_DATA 0x00000000 +#define DDRSS2_PHY_507_DATA 0x00000000 +#define DDRSS2_PHY_508_DATA 0x00000000 +#define DDRSS2_PHY_509_DATA 0x00000000 +#define DDRSS2_PHY_510_DATA 0x00000000 +#define DDRSS2_PHY_511_DATA 0x00000000 +#define DDRSS2_PHY_512_DATA 0x000004F0 +#define DDRSS2_PHY_513_DATA 0x00000000 +#define DDRSS2_PHY_514_DATA 0x00030200 +#define DDRSS2_PHY_515_DATA 0x00000000 +#define DDRSS2_PHY_516_DATA 0x00000000 +#define DDRSS2_PHY_517_DATA 0x01030000 +#define DDRSS2_PHY_518_DATA 0x00010000 +#define DDRSS2_PHY_519_DATA 0x01030004 +#define DDRSS2_PHY_520_DATA 0x01000000 +#define DDRSS2_PHY_521_DATA 0x00000000 +#define DDRSS2_PHY_522_DATA 0x00000000 +#define DDRSS2_PHY_523_DATA 0x01000001 +#define DDRSS2_PHY_524_DATA 0x00000100 +#define DDRSS2_PHY_525_DATA 0x000800C0 +#define DDRSS2_PHY_526_DATA 0x060100CC +#define DDRSS2_PHY_527_DATA 0x00030066 +#define DDRSS2_PHY_528_DATA 0x00000000 +#define DDRSS2_PHY_529_DATA 0x00000301 +#define DDRSS2_PHY_530_DATA 0x0000AAAA +#define DDRSS2_PHY_531_DATA 0x00005555 +#define DDRSS2_PHY_532_DATA 0x0000B5B5 +#define DDRSS2_PHY_533_DATA 0x00004A4A +#define DDRSS2_PHY_534_DATA 0x00005656 +#define DDRSS2_PHY_535_DATA 0x0000A9A9 +#define DDRSS2_PHY_536_DATA 0x0000A9A9 +#define DDRSS2_PHY_537_DATA 0x0000B5B5 +#define DDRSS2_PHY_538_DATA 0x00000000 +#define DDRSS2_PHY_539_DATA 0x00000000 +#define DDRSS2_PHY_540_DATA 0x2A000000 +#define DDRSS2_PHY_541_DATA 0x00000808 +#define DDRSS2_PHY_542_DATA 0x0F000000 +#define DDRSS2_PHY_543_DATA 0x00000F0F +#define DDRSS2_PHY_544_DATA 0x10400000 +#define DDRSS2_PHY_545_DATA 0x0C002006 +#define DDRSS2_PHY_546_DATA 0x00000000 +#define DDRSS2_PHY_547_DATA 0x00000000 +#define DDRSS2_PHY_548_DATA 0x55555555 +#define DDRSS2_PHY_549_DATA 0xAAAAAAAA +#define DDRSS2_PHY_550_DATA 0x55555555 +#define DDRSS2_PHY_551_DATA 0xAAAAAAAA +#define DDRSS2_PHY_552_DATA 0x00005555 +#define DDRSS2_PHY_553_DATA 0x01000100 +#define DDRSS2_PHY_554_DATA 0x00800180 +#define DDRSS2_PHY_555_DATA 0x00000001 +#define DDRSS2_PHY_556_DATA 0x00000000 +#define DDRSS2_PHY_557_DATA 0x00000000 +#define DDRSS2_PHY_558_DATA 0x00000000 +#define DDRSS2_PHY_559_DATA 0x00000000 +#define DDRSS2_PHY_560_DATA 0x00000000 +#define DDRSS2_PHY_561_DATA 0x00000000 +#define DDRSS2_PHY_562_DATA 0x00000000 +#define DDRSS2_PHY_563_DATA 0x00000000 +#define DDRSS2_PHY_564_DATA 0x00000000 +#define DDRSS2_PHY_565_DATA 0x00000000 +#define DDRSS2_PHY_566_DATA 0x00000000 +#define DDRSS2_PHY_567_DATA 0x00000000 +#define DDRSS2_PHY_568_DATA 0x00000000 +#define DDRSS2_PHY_569_DATA 0x00000000 +#define DDRSS2_PHY_570_DATA 0x00000000 +#define DDRSS2_PHY_571_DATA 0x00000000 +#define DDRSS2_PHY_572_DATA 0x00000000 +#define DDRSS2_PHY_573_DATA 0x00000000 +#define DDRSS2_PHY_574_DATA 0x00000000 +#define DDRSS2_PHY_575_DATA 0x00000000 +#define DDRSS2_PHY_576_DATA 0x00000000 +#define DDRSS2_PHY_577_DATA 0x00000000 +#define DDRSS2_PHY_578_DATA 0x00000104 +#define DDRSS2_PHY_579_DATA 0x00000120 +#define DDRSS2_PHY_580_DATA 0x00000000 +#define DDRSS2_PHY_581_DATA 0x00000000 +#define DDRSS2_PHY_582_DATA 0x00000000 +#define DDRSS2_PHY_583_DATA 0x00000000 +#define DDRSS2_PHY_584_DATA 0x00000000 +#define DDRSS2_PHY_585_DATA 0x00000000 +#define DDRSS2_PHY_586_DATA 0x00000000 +#define DDRSS2_PHY_587_DATA 0x00000001 +#define DDRSS2_PHY_588_DATA 0x07FF0000 +#define DDRSS2_PHY_589_DATA 0x0080081F +#define DDRSS2_PHY_590_DATA 0x00081020 +#define DDRSS2_PHY_591_DATA 0x04010000 +#define DDRSS2_PHY_592_DATA 0x00000000 +#define DDRSS2_PHY_593_DATA 0x00000000 +#define DDRSS2_PHY_594_DATA 0x00000000 +#define DDRSS2_PHY_595_DATA 0x00000100 +#define DDRSS2_PHY_596_DATA 0x01CC0C01 +#define DDRSS2_PHY_597_DATA 0x1003CC0C +#define DDRSS2_PHY_598_DATA 0x20000140 +#define DDRSS2_PHY_599_DATA 0x07FF0200 +#define DDRSS2_PHY_600_DATA 0x0000DD01 +#define DDRSS2_PHY_601_DATA 0x10100303 +#define DDRSS2_PHY_602_DATA 0x10101010 +#define DDRSS2_PHY_603_DATA 0x10101010 +#define DDRSS2_PHY_604_DATA 0x00021010 +#define DDRSS2_PHY_605_DATA 0x00100010 +#define DDRSS2_PHY_606_DATA 0x00100010 +#define DDRSS2_PHY_607_DATA 0x00100010 +#define DDRSS2_PHY_608_DATA 0x00100010 +#define DDRSS2_PHY_609_DATA 0x00050010 +#define DDRSS2_PHY_610_DATA 0x51517041 +#define DDRSS2_PHY_611_DATA 0x31C06001 +#define DDRSS2_PHY_612_DATA 0x07AB0340 +#define DDRSS2_PHY_613_DATA 0x00C0C001 +#define DDRSS2_PHY_614_DATA 0x0E0D0001 +#define DDRSS2_PHY_615_DATA 0x10001000 +#define DDRSS2_PHY_616_DATA 0x0C083E42 +#define DDRSS2_PHY_617_DATA 0x0F0C3701 +#define DDRSS2_PHY_618_DATA 0x01000140 +#define DDRSS2_PHY_619_DATA 0x0C000420 +#define DDRSS2_PHY_620_DATA 0x00000198 +#define DDRSS2_PHY_621_DATA 0x0A0000D0 +#define DDRSS2_PHY_622_DATA 0x00030200 +#define DDRSS2_PHY_623_DATA 0x02800000 +#define DDRSS2_PHY_624_DATA 0x80800000 +#define DDRSS2_PHY_625_DATA 0x000E2010 +#define DDRSS2_PHY_626_DATA 0x76543210 +#define DDRSS2_PHY_627_DATA 0x00000008 +#define DDRSS2_PHY_628_DATA 0x02800280 +#define DDRSS2_PHY_629_DATA 0x02800280 +#define DDRSS2_PHY_630_DATA 0x02800280 +#define DDRSS2_PHY_631_DATA 0x02800280 +#define DDRSS2_PHY_632_DATA 0x00000280 +#define DDRSS2_PHY_633_DATA 0x0000A000 +#define DDRSS2_PHY_634_DATA 0x00A000A0 +#define DDRSS2_PHY_635_DATA 0x00A000A0 +#define DDRSS2_PHY_636_DATA 0x00A000A0 +#define DDRSS2_PHY_637_DATA 0x00A000A0 +#define DDRSS2_PHY_638_DATA 0x00A000A0 +#define DDRSS2_PHY_639_DATA 0x00A000A0 +#define DDRSS2_PHY_640_DATA 0x00A000A0 +#define DDRSS2_PHY_641_DATA 0x00A000A0 +#define DDRSS2_PHY_642_DATA 0x01C200A0 +#define DDRSS2_PHY_643_DATA 0x01A00005 +#define DDRSS2_PHY_644_DATA 0x00000000 +#define DDRSS2_PHY_645_DATA 0x00000000 +#define DDRSS2_PHY_646_DATA 0x00080200 +#define DDRSS2_PHY_647_DATA 0x00000000 +#define DDRSS2_PHY_648_DATA 0x20202000 +#define DDRSS2_PHY_649_DATA 0x20202020 +#define DDRSS2_PHY_650_DATA 0xF0F02020 +#define DDRSS2_PHY_651_DATA 0x00000000 +#define DDRSS2_PHY_652_DATA 0x00000000 +#define DDRSS2_PHY_653_DATA 0x00000000 +#define DDRSS2_PHY_654_DATA 0x00000000 +#define DDRSS2_PHY_655_DATA 0x00000000 +#define DDRSS2_PHY_656_DATA 0x00000000 +#define DDRSS2_PHY_657_DATA 0x00000000 +#define DDRSS2_PHY_658_DATA 0x00000000 +#define DDRSS2_PHY_659_DATA 0x00000000 +#define DDRSS2_PHY_660_DATA 0x00000000 +#define DDRSS2_PHY_661_DATA 0x00000000 +#define DDRSS2_PHY_662_DATA 0x00000000 +#define DDRSS2_PHY_663_DATA 0x00000000 +#define DDRSS2_PHY_664_DATA 0x00000000 +#define DDRSS2_PHY_665_DATA 0x00000000 +#define DDRSS2_PHY_666_DATA 0x00000000 +#define DDRSS2_PHY_667_DATA 0x00000000 +#define DDRSS2_PHY_668_DATA 0x00000000 +#define DDRSS2_PHY_669_DATA 0x00000000 +#define DDRSS2_PHY_670_DATA 0x00000000 +#define DDRSS2_PHY_671_DATA 0x00000000 +#define DDRSS2_PHY_672_DATA 0x00000000 +#define DDRSS2_PHY_673_DATA 0x00000000 +#define DDRSS2_PHY_674_DATA 0x00000000 +#define DDRSS2_PHY_675_DATA 0x00000000 +#define DDRSS2_PHY_676_DATA 0x00000000 +#define DDRSS2_PHY_677_DATA 0x00000000 +#define DDRSS2_PHY_678_DATA 0x00000000 +#define DDRSS2_PHY_679_DATA 0x00000000 +#define DDRSS2_PHY_680_DATA 0x00000000 +#define DDRSS2_PHY_681_DATA 0x00000000 +#define DDRSS2_PHY_682_DATA 0x00000000 +#define DDRSS2_PHY_683_DATA 0x00000000 +#define DDRSS2_PHY_684_DATA 0x00000000 +#define DDRSS2_PHY_685_DATA 0x00000000 +#define DDRSS2_PHY_686_DATA 0x00000000 +#define DDRSS2_PHY_687_DATA 0x00000000 +#define DDRSS2_PHY_688_DATA 0x00000000 +#define DDRSS2_PHY_689_DATA 0x00000000 +#define DDRSS2_PHY_690_DATA 0x00000000 +#define DDRSS2_PHY_691_DATA 0x00000000 +#define DDRSS2_PHY_692_DATA 0x00000000 +#define DDRSS2_PHY_693_DATA 0x00000000 +#define DDRSS2_PHY_694_DATA 0x00000000 +#define DDRSS2_PHY_695_DATA 0x00000000 +#define DDRSS2_PHY_696_DATA 0x00000000 +#define DDRSS2_PHY_697_DATA 0x00000000 +#define DDRSS2_PHY_698_DATA 0x00000000 +#define DDRSS2_PHY_699_DATA 0x00000000 +#define DDRSS2_PHY_700_DATA 0x00000000 +#define DDRSS2_PHY_701_DATA 0x00000000 +#define DDRSS2_PHY_702_DATA 0x00000000 +#define DDRSS2_PHY_703_DATA 0x00000000 +#define DDRSS2_PHY_704_DATA 0x00000000 +#define DDRSS2_PHY_705_DATA 0x00000000 +#define DDRSS2_PHY_706_DATA 0x00000000 +#define DDRSS2_PHY_707_DATA 0x00000000 +#define DDRSS2_PHY_708_DATA 0x00000000 +#define DDRSS2_PHY_709_DATA 0x00000000 +#define DDRSS2_PHY_710_DATA 0x00000000 +#define DDRSS2_PHY_711_DATA 0x00000000 +#define DDRSS2_PHY_712_DATA 0x00000000 +#define DDRSS2_PHY_713_DATA 0x00000000 +#define DDRSS2_PHY_714_DATA 0x00000000 +#define DDRSS2_PHY_715_DATA 0x00000000 +#define DDRSS2_PHY_716_DATA 0x00000000 +#define DDRSS2_PHY_717_DATA 0x00000000 +#define DDRSS2_PHY_718_DATA 0x00000000 +#define DDRSS2_PHY_719_DATA 0x00000000 +#define DDRSS2_PHY_720_DATA 0x00000000 +#define DDRSS2_PHY_721_DATA 0x00000000 +#define DDRSS2_PHY_722_DATA 0x00000000 +#define DDRSS2_PHY_723_DATA 0x00000000 +#define DDRSS2_PHY_724_DATA 0x00000000 +#define DDRSS2_PHY_725_DATA 0x00000000 +#define DDRSS2_PHY_726_DATA 0x00000000 +#define DDRSS2_PHY_727_DATA 0x00000000 +#define DDRSS2_PHY_728_DATA 0x00000000 +#define DDRSS2_PHY_729_DATA 0x00000000 +#define DDRSS2_PHY_730_DATA 0x00000000 +#define DDRSS2_PHY_731_DATA 0x00000000 +#define DDRSS2_PHY_732_DATA 0x00000000 +#define DDRSS2_PHY_733_DATA 0x00000000 +#define DDRSS2_PHY_734_DATA 0x00000000 +#define DDRSS2_PHY_735_DATA 0x00000000 +#define DDRSS2_PHY_736_DATA 0x00000000 +#define DDRSS2_PHY_737_DATA 0x00000000 +#define DDRSS2_PHY_738_DATA 0x00000000 +#define DDRSS2_PHY_739_DATA 0x00000000 +#define DDRSS2_PHY_740_DATA 0x00000000 +#define DDRSS2_PHY_741_DATA 0x00000000 +#define DDRSS2_PHY_742_DATA 0x00000000 +#define DDRSS2_PHY_743_DATA 0x00000000 +#define DDRSS2_PHY_744_DATA 0x00000000 +#define DDRSS2_PHY_745_DATA 0x00000000 +#define DDRSS2_PHY_746_DATA 0x00000000 +#define DDRSS2_PHY_747_DATA 0x00000000 +#define DDRSS2_PHY_748_DATA 0x00000000 +#define DDRSS2_PHY_749_DATA 0x00000000 +#define DDRSS2_PHY_750_DATA 0x00000000 +#define DDRSS2_PHY_751_DATA 0x00000000 +#define DDRSS2_PHY_752_DATA 0x00000000 +#define DDRSS2_PHY_753_DATA 0x00000000 +#define DDRSS2_PHY_754_DATA 0x00000000 +#define DDRSS2_PHY_755_DATA 0x00000000 +#define DDRSS2_PHY_756_DATA 0x00000000 +#define DDRSS2_PHY_757_DATA 0x00000000 +#define DDRSS2_PHY_758_DATA 0x00000000 +#define DDRSS2_PHY_759_DATA 0x00000000 +#define DDRSS2_PHY_760_DATA 0x00000000 +#define DDRSS2_PHY_761_DATA 0x00000000 +#define DDRSS2_PHY_762_DATA 0x00000000 +#define DDRSS2_PHY_763_DATA 0x00000000 +#define DDRSS2_PHY_764_DATA 0x00000000 +#define DDRSS2_PHY_765_DATA 0x00000000 +#define DDRSS2_PHY_766_DATA 0x00000000 +#define DDRSS2_PHY_767_DATA 0x00000000 +#define DDRSS2_PHY_768_DATA 0x000004F0 +#define DDRSS2_PHY_769_DATA 0x00000000 +#define DDRSS2_PHY_770_DATA 0x00030200 +#define DDRSS2_PHY_771_DATA 0x00000000 +#define DDRSS2_PHY_772_DATA 0x00000000 +#define DDRSS2_PHY_773_DATA 0x01030000 +#define DDRSS2_PHY_774_DATA 0x00010000 +#define DDRSS2_PHY_775_DATA 0x01030004 +#define DDRSS2_PHY_776_DATA 0x01000000 +#define DDRSS2_PHY_777_DATA 0x00000000 +#define DDRSS2_PHY_778_DATA 0x00000000 +#define DDRSS2_PHY_779_DATA 0x01000001 +#define DDRSS2_PHY_780_DATA 0x00000100 +#define DDRSS2_PHY_781_DATA 0x000800C0 +#define DDRSS2_PHY_782_DATA 0x060100CC +#define DDRSS2_PHY_783_DATA 0x00030066 +#define DDRSS2_PHY_784_DATA 0x00000000 +#define DDRSS2_PHY_785_DATA 0x00000301 +#define DDRSS2_PHY_786_DATA 0x0000AAAA +#define DDRSS2_PHY_787_DATA 0x00005555 +#define DDRSS2_PHY_788_DATA 0x0000B5B5 +#define DDRSS2_PHY_789_DATA 0x00004A4A +#define DDRSS2_PHY_790_DATA 0x00005656 +#define DDRSS2_PHY_791_DATA 0x0000A9A9 +#define DDRSS2_PHY_792_DATA 0x0000A9A9 +#define DDRSS2_PHY_793_DATA 0x0000B5B5 +#define DDRSS2_PHY_794_DATA 0x00000000 +#define DDRSS2_PHY_795_DATA 0x00000000 +#define DDRSS2_PHY_796_DATA 0x2A000000 +#define DDRSS2_PHY_797_DATA 0x00000808 +#define DDRSS2_PHY_798_DATA 0x0F000000 +#define DDRSS2_PHY_799_DATA 0x00000F0F +#define DDRSS2_PHY_800_DATA 0x10400000 +#define DDRSS2_PHY_801_DATA 0x0C002006 +#define DDRSS2_PHY_802_DATA 0x00000000 +#define DDRSS2_PHY_803_DATA 0x00000000 +#define DDRSS2_PHY_804_DATA 0x55555555 +#define DDRSS2_PHY_805_DATA 0xAAAAAAAA +#define DDRSS2_PHY_806_DATA 0x55555555 +#define DDRSS2_PHY_807_DATA 0xAAAAAAAA +#define DDRSS2_PHY_808_DATA 0x00005555 +#define DDRSS2_PHY_809_DATA 0x01000100 +#define DDRSS2_PHY_810_DATA 0x00800180 +#define DDRSS2_PHY_811_DATA 0x00000000 +#define DDRSS2_PHY_812_DATA 0x00000000 +#define DDRSS2_PHY_813_DATA 0x00000000 +#define DDRSS2_PHY_814_DATA 0x00000000 +#define DDRSS2_PHY_815_DATA 0x00000000 +#define DDRSS2_PHY_816_DATA 0x00000000 +#define DDRSS2_PHY_817_DATA 0x00000000 +#define DDRSS2_PHY_818_DATA 0x00000000 +#define DDRSS2_PHY_819_DATA 0x00000000 +#define DDRSS2_PHY_820_DATA 0x00000000 +#define DDRSS2_PHY_821_DATA 0x00000000 +#define DDRSS2_PHY_822_DATA 0x00000000 +#define DDRSS2_PHY_823_DATA 0x00000000 +#define DDRSS2_PHY_824_DATA 0x00000000 +#define DDRSS2_PHY_825_DATA 0x00000000 +#define DDRSS2_PHY_826_DATA 0x00000000 +#define DDRSS2_PHY_827_DATA 0x00000000 +#define DDRSS2_PHY_828_DATA 0x00000000 +#define DDRSS2_PHY_829_DATA 0x00000000 +#define DDRSS2_PHY_830_DATA 0x00000000 +#define DDRSS2_PHY_831_DATA 0x00000000 +#define DDRSS2_PHY_832_DATA 0x00000000 +#define DDRSS2_PHY_833_DATA 0x00000000 +#define DDRSS2_PHY_834_DATA 0x00000104 +#define DDRSS2_PHY_835_DATA 0x00000120 +#define DDRSS2_PHY_836_DATA 0x00000000 +#define DDRSS2_PHY_837_DATA 0x00000000 +#define DDRSS2_PHY_838_DATA 0x00000000 +#define DDRSS2_PHY_839_DATA 0x00000000 +#define DDRSS2_PHY_840_DATA 0x00000000 +#define DDRSS2_PHY_841_DATA 0x00000000 +#define DDRSS2_PHY_842_DATA 0x00000000 +#define DDRSS2_PHY_843_DATA 0x00000001 +#define DDRSS2_PHY_844_DATA 0x07FF0000 +#define DDRSS2_PHY_845_DATA 0x0080081F +#define DDRSS2_PHY_846_DATA 0x00081020 +#define DDRSS2_PHY_847_DATA 0x04010000 +#define DDRSS2_PHY_848_DATA 0x00000000 +#define DDRSS2_PHY_849_DATA 0x00000000 +#define DDRSS2_PHY_850_DATA 0x00000000 +#define DDRSS2_PHY_851_DATA 0x00000100 +#define DDRSS2_PHY_852_DATA 0x01CC0C01 +#define DDRSS2_PHY_853_DATA 0x1003CC0C +#define DDRSS2_PHY_854_DATA 0x20000140 +#define DDRSS2_PHY_855_DATA 0x07FF0200 +#define DDRSS2_PHY_856_DATA 0x0000DD01 +#define DDRSS2_PHY_857_DATA 0x10100303 +#define DDRSS2_PHY_858_DATA 0x10101010 +#define DDRSS2_PHY_859_DATA 0x10101010 +#define DDRSS2_PHY_860_DATA 0x00021010 +#define DDRSS2_PHY_861_DATA 0x00100010 +#define DDRSS2_PHY_862_DATA 0x00100010 +#define DDRSS2_PHY_863_DATA 0x00100010 +#define DDRSS2_PHY_864_DATA 0x00100010 +#define DDRSS2_PHY_865_DATA 0x00050010 +#define DDRSS2_PHY_866_DATA 0x51517041 +#define DDRSS2_PHY_867_DATA 0x31C06001 +#define DDRSS2_PHY_868_DATA 0x07AB0340 +#define DDRSS2_PHY_869_DATA 0x00C0C001 +#define DDRSS2_PHY_870_DATA 0x0E0D0001 +#define DDRSS2_PHY_871_DATA 0x10001000 +#define DDRSS2_PHY_872_DATA 0x0C083E42 +#define DDRSS2_PHY_873_DATA 0x0F0C3701 +#define DDRSS2_PHY_874_DATA 0x01000140 +#define DDRSS2_PHY_875_DATA 0x0C000420 +#define DDRSS2_PHY_876_DATA 0x00000198 +#define DDRSS2_PHY_877_DATA 0x0A0000D0 +#define DDRSS2_PHY_878_DATA 0x00030200 +#define DDRSS2_PHY_879_DATA 0x02800000 +#define DDRSS2_PHY_880_DATA 0x80800000 +#define DDRSS2_PHY_881_DATA 0x000E2010 +#define DDRSS2_PHY_882_DATA 0x76543210 +#define DDRSS2_PHY_883_DATA 0x00000008 +#define DDRSS2_PHY_884_DATA 0x02800280 +#define DDRSS2_PHY_885_DATA 0x02800280 +#define DDRSS2_PHY_886_DATA 0x02800280 +#define DDRSS2_PHY_887_DATA 0x02800280 +#define DDRSS2_PHY_888_DATA 0x00000280 +#define DDRSS2_PHY_889_DATA 0x0000A000 +#define DDRSS2_PHY_890_DATA 0x00A000A0 +#define DDRSS2_PHY_891_DATA 0x00A000A0 +#define DDRSS2_PHY_892_DATA 0x00A000A0 +#define DDRSS2_PHY_893_DATA 0x00A000A0 +#define DDRSS2_PHY_894_DATA 0x00A000A0 +#define DDRSS2_PHY_895_DATA 0x00A000A0 +#define DDRSS2_PHY_896_DATA 0x00A000A0 +#define DDRSS2_PHY_897_DATA 0x00A000A0 +#define DDRSS2_PHY_898_DATA 0x01C200A0 +#define DDRSS2_PHY_899_DATA 0x01A00005 +#define DDRSS2_PHY_900_DATA 0x00000000 +#define DDRSS2_PHY_901_DATA 0x00000000 +#define DDRSS2_PHY_902_DATA 0x00080200 +#define DDRSS2_PHY_903_DATA 0x00000000 +#define DDRSS2_PHY_904_DATA 0x20202000 +#define DDRSS2_PHY_905_DATA 0x20202020 +#define DDRSS2_PHY_906_DATA 0xF0F02020 +#define DDRSS2_PHY_907_DATA 0x00000000 +#define DDRSS2_PHY_908_DATA 0x00000000 +#define DDRSS2_PHY_909_DATA 0x00000000 +#define DDRSS2_PHY_910_DATA 0x00000000 +#define DDRSS2_PHY_911_DATA 0x00000000 +#define DDRSS2_PHY_912_DATA 0x00000000 +#define DDRSS2_PHY_913_DATA 0x00000000 +#define DDRSS2_PHY_914_DATA 0x00000000 +#define DDRSS2_PHY_915_DATA 0x00000000 +#define DDRSS2_PHY_916_DATA 0x00000000 +#define DDRSS2_PHY_917_DATA 0x00000000 +#define DDRSS2_PHY_918_DATA 0x00000000 +#define DDRSS2_PHY_919_DATA 0x00000000 +#define DDRSS2_PHY_920_DATA 0x00000000 +#define DDRSS2_PHY_921_DATA 0x00000000 +#define DDRSS2_PHY_922_DATA 0x00000000 +#define DDRSS2_PHY_923_DATA 0x00000000 +#define DDRSS2_PHY_924_DATA 0x00000000 +#define DDRSS2_PHY_925_DATA 0x00000000 +#define DDRSS2_PHY_926_DATA 0x00000000 +#define DDRSS2_PHY_927_DATA 0x00000000 +#define DDRSS2_PHY_928_DATA 0x00000000 +#define DDRSS2_PHY_929_DATA 0x00000000 +#define DDRSS2_PHY_930_DATA 0x00000000 +#define DDRSS2_PHY_931_DATA 0x00000000 +#define DDRSS2_PHY_932_DATA 0x00000000 +#define DDRSS2_PHY_933_DATA 0x00000000 +#define DDRSS2_PHY_934_DATA 0x00000000 +#define DDRSS2_PHY_935_DATA 0x00000000 +#define DDRSS2_PHY_936_DATA 0x00000000 +#define DDRSS2_PHY_937_DATA 0x00000000 +#define DDRSS2_PHY_938_DATA 0x00000000 +#define DDRSS2_PHY_939_DATA 0x00000000 +#define DDRSS2_PHY_940_DATA 0x00000000 +#define DDRSS2_PHY_941_DATA 0x00000000 +#define DDRSS2_PHY_942_DATA 0x00000000 +#define DDRSS2_PHY_943_DATA 0x00000000 +#define DDRSS2_PHY_944_DATA 0x00000000 +#define DDRSS2_PHY_945_DATA 0x00000000 +#define DDRSS2_PHY_946_DATA 0x00000000 +#define DDRSS2_PHY_947_DATA 0x00000000 +#define DDRSS2_PHY_948_DATA 0x00000000 +#define DDRSS2_PHY_949_DATA 0x00000000 +#define DDRSS2_PHY_950_DATA 0x00000000 +#define DDRSS2_PHY_951_DATA 0x00000000 +#define DDRSS2_PHY_952_DATA 0x00000000 +#define DDRSS2_PHY_953_DATA 0x00000000 +#define DDRSS2_PHY_954_DATA 0x00000000 +#define DDRSS2_PHY_955_DATA 0x00000000 +#define DDRSS2_PHY_956_DATA 0x00000000 +#define DDRSS2_PHY_957_DATA 0x00000000 +#define DDRSS2_PHY_958_DATA 0x00000000 +#define DDRSS2_PHY_959_DATA 0x00000000 +#define DDRSS2_PHY_960_DATA 0x00000000 +#define DDRSS2_PHY_961_DATA 0x00000000 +#define DDRSS2_PHY_962_DATA 0x00000000 +#define DDRSS2_PHY_963_DATA 0x00000000 +#define DDRSS2_PHY_964_DATA 0x00000000 +#define DDRSS2_PHY_965_DATA 0x00000000 +#define DDRSS2_PHY_966_DATA 0x00000000 +#define DDRSS2_PHY_967_DATA 0x00000000 +#define DDRSS2_PHY_968_DATA 0x00000000 +#define DDRSS2_PHY_969_DATA 0x00000000 +#define DDRSS2_PHY_970_DATA 0x00000000 +#define DDRSS2_PHY_971_DATA 0x00000000 +#define DDRSS2_PHY_972_DATA 0x00000000 +#define DDRSS2_PHY_973_DATA 0x00000000 +#define DDRSS2_PHY_974_DATA 0x00000000 +#define DDRSS2_PHY_975_DATA 0x00000000 +#define DDRSS2_PHY_976_DATA 0x00000000 +#define DDRSS2_PHY_977_DATA 0x00000000 +#define DDRSS2_PHY_978_DATA 0x00000000 +#define DDRSS2_PHY_979_DATA 0x00000000 +#define DDRSS2_PHY_980_DATA 0x00000000 +#define DDRSS2_PHY_981_DATA 0x00000000 +#define DDRSS2_PHY_982_DATA 0x00000000 +#define DDRSS2_PHY_983_DATA 0x00000000 +#define DDRSS2_PHY_984_DATA 0x00000000 +#define DDRSS2_PHY_985_DATA 0x00000000 +#define DDRSS2_PHY_986_DATA 0x00000000 +#define DDRSS2_PHY_987_DATA 0x00000000 +#define DDRSS2_PHY_988_DATA 0x00000000 +#define DDRSS2_PHY_989_DATA 0x00000000 +#define DDRSS2_PHY_990_DATA 0x00000000 +#define DDRSS2_PHY_991_DATA 0x00000000 +#define DDRSS2_PHY_992_DATA 0x00000000 +#define DDRSS2_PHY_993_DATA 0x00000000 +#define DDRSS2_PHY_994_DATA 0x00000000 +#define DDRSS2_PHY_995_DATA 0x00000000 +#define DDRSS2_PHY_996_DATA 0x00000000 +#define DDRSS2_PHY_997_DATA 0x00000000 +#define DDRSS2_PHY_998_DATA 0x00000000 +#define DDRSS2_PHY_999_DATA 0x00000000 +#define DDRSS2_PHY_1000_DATA 0x00000000 +#define DDRSS2_PHY_1001_DATA 0x00000000 +#define DDRSS2_PHY_1002_DATA 0x00000000 +#define DDRSS2_PHY_1003_DATA 0x00000000 +#define DDRSS2_PHY_1004_DATA 0x00000000 +#define DDRSS2_PHY_1005_DATA 0x00000000 +#define DDRSS2_PHY_1006_DATA 0x00000000 +#define DDRSS2_PHY_1007_DATA 0x00000000 +#define DDRSS2_PHY_1008_DATA 0x00000000 +#define DDRSS2_PHY_1009_DATA 0x00000000 +#define DDRSS2_PHY_1010_DATA 0x00000000 +#define DDRSS2_PHY_1011_DATA 0x00000000 +#define DDRSS2_PHY_1012_DATA 0x00000000 +#define DDRSS2_PHY_1013_DATA 0x00000000 +#define DDRSS2_PHY_1014_DATA 0x00000000 +#define DDRSS2_PHY_1015_DATA 0x00000000 +#define DDRSS2_PHY_1016_DATA 0x00000000 +#define DDRSS2_PHY_1017_DATA 0x00000000 +#define DDRSS2_PHY_1018_DATA 0x00000000 +#define DDRSS2_PHY_1019_DATA 0x00000000 +#define DDRSS2_PHY_1020_DATA 0x00000000 +#define DDRSS2_PHY_1021_DATA 0x00000000 +#define DDRSS2_PHY_1022_DATA 0x00000000 +#define DDRSS2_PHY_1023_DATA 0x00000000 +#define DDRSS2_PHY_1024_DATA 0x00000000 +#define DDRSS2_PHY_1025_DATA 0x00000000 +#define DDRSS2_PHY_1026_DATA 0x00000000 +#define DDRSS2_PHY_1027_DATA 0x00000000 +#define DDRSS2_PHY_1028_DATA 0x00000000 +#define DDRSS2_PHY_1029_DATA 0x00000100 +#define DDRSS2_PHY_1030_DATA 0x00000200 +#define DDRSS2_PHY_1031_DATA 0x00000000 +#define DDRSS2_PHY_1032_DATA 0x00000000 +#define DDRSS2_PHY_1033_DATA 0x00000000 +#define DDRSS2_PHY_1034_DATA 0x00000000 +#define DDRSS2_PHY_1035_DATA 0x00400000 +#define DDRSS2_PHY_1036_DATA 0x00000080 +#define DDRSS2_PHY_1037_DATA 0x00DCBA98 +#define DDRSS2_PHY_1038_DATA 0x03000000 +#define DDRSS2_PHY_1039_DATA 0x00200000 +#define DDRSS2_PHY_1040_DATA 0x00000000 +#define DDRSS2_PHY_1041_DATA 0x00000000 +#define DDRSS2_PHY_1042_DATA 0x00000000 +#define DDRSS2_PHY_1043_DATA 0x00000000 +#define DDRSS2_PHY_1044_DATA 0x00000000 +#define DDRSS2_PHY_1045_DATA 0x0000002A +#define DDRSS2_PHY_1046_DATA 0x00000015 +#define DDRSS2_PHY_1047_DATA 0x00000015 +#define DDRSS2_PHY_1048_DATA 0x0000002A +#define DDRSS2_PHY_1049_DATA 0x00000033 +#define DDRSS2_PHY_1050_DATA 0x0000000C +#define DDRSS2_PHY_1051_DATA 0x0000000C +#define DDRSS2_PHY_1052_DATA 0x00000033 +#define DDRSS2_PHY_1053_DATA 0x00543210 +#define DDRSS2_PHY_1054_DATA 0x003F0000 +#define DDRSS2_PHY_1055_DATA 0x000F013F +#define DDRSS2_PHY_1056_DATA 0x20202003 +#define DDRSS2_PHY_1057_DATA 0x00202020 +#define DDRSS2_PHY_1058_DATA 0x20008008 +#define DDRSS2_PHY_1059_DATA 0x00000810 +#define DDRSS2_PHY_1060_DATA 0x00000F00 +#define DDRSS2_PHY_1061_DATA 0x00000000 +#define DDRSS2_PHY_1062_DATA 0x00000000 +#define DDRSS2_PHY_1063_DATA 0x00000000 +#define DDRSS2_PHY_1064_DATA 0x000305CC +#define DDRSS2_PHY_1065_DATA 0x00030000 +#define DDRSS2_PHY_1066_DATA 0x00000300 +#define DDRSS2_PHY_1067_DATA 0x00000300 +#define DDRSS2_PHY_1068_DATA 0x00000300 +#define DDRSS2_PHY_1069_DATA 0x00000300 +#define DDRSS2_PHY_1070_DATA 0x00000300 +#define DDRSS2_PHY_1071_DATA 0x42080010 +#define DDRSS2_PHY_1072_DATA 0x0000803E +#define DDRSS2_PHY_1073_DATA 0x00000001 +#define DDRSS2_PHY_1074_DATA 0x01000102 +#define DDRSS2_PHY_1075_DATA 0x00008000 +#define DDRSS2_PHY_1076_DATA 0x00000000 +#define DDRSS2_PHY_1077_DATA 0x00000000 +#define DDRSS2_PHY_1078_DATA 0x00000000 +#define DDRSS2_PHY_1079_DATA 0x00000000 +#define DDRSS2_PHY_1080_DATA 0x00000000 +#define DDRSS2_PHY_1081_DATA 0x00000000 +#define DDRSS2_PHY_1082_DATA 0x00000000 +#define DDRSS2_PHY_1083_DATA 0x00000000 +#define DDRSS2_PHY_1084_DATA 0x00000000 +#define DDRSS2_PHY_1085_DATA 0x00000000 +#define DDRSS2_PHY_1086_DATA 0x00000000 +#define DDRSS2_PHY_1087_DATA 0x00000000 +#define DDRSS2_PHY_1088_DATA 0x00000000 +#define DDRSS2_PHY_1089_DATA 0x00000000 +#define DDRSS2_PHY_1090_DATA 0x00000000 +#define DDRSS2_PHY_1091_DATA 0x00000000 +#define DDRSS2_PHY_1092_DATA 0x00000000 +#define DDRSS2_PHY_1093_DATA 0x00000000 +#define DDRSS2_PHY_1094_DATA 0x00000000 +#define DDRSS2_PHY_1095_DATA 0x00000000 +#define DDRSS2_PHY_1096_DATA 0x00000000 +#define DDRSS2_PHY_1097_DATA 0x00000000 +#define DDRSS2_PHY_1098_DATA 0x00000000 +#define DDRSS2_PHY_1099_DATA 0x00000000 +#define DDRSS2_PHY_1100_DATA 0x00000000 +#define DDRSS2_PHY_1101_DATA 0x00000000 +#define DDRSS2_PHY_1102_DATA 0x00000000 +#define DDRSS2_PHY_1103_DATA 0x00000000 +#define DDRSS2_PHY_1104_DATA 0x00000000 +#define DDRSS2_PHY_1105_DATA 0x00000000 +#define DDRSS2_PHY_1106_DATA 0x00000000 +#define DDRSS2_PHY_1107_DATA 0x00000000 +#define DDRSS2_PHY_1108_DATA 0x00000000 +#define DDRSS2_PHY_1109_DATA 0x00000000 +#define DDRSS2_PHY_1110_DATA 0x00000000 +#define DDRSS2_PHY_1111_DATA 0x00000000 +#define DDRSS2_PHY_1112_DATA 0x00000000 +#define DDRSS2_PHY_1113_DATA 0x00000000 +#define DDRSS2_PHY_1114_DATA 0x00000000 +#define DDRSS2_PHY_1115_DATA 0x00000000 +#define DDRSS2_PHY_1116_DATA 0x00000000 +#define DDRSS2_PHY_1117_DATA 0x00000000 +#define DDRSS2_PHY_1118_DATA 0x00000000 +#define DDRSS2_PHY_1119_DATA 0x00000000 +#define DDRSS2_PHY_1120_DATA 0x00000000 +#define DDRSS2_PHY_1121_DATA 0x00000000 +#define DDRSS2_PHY_1122_DATA 0x00000000 +#define DDRSS2_PHY_1123_DATA 0x00000000 +#define DDRSS2_PHY_1124_DATA 0x00000000 +#define DDRSS2_PHY_1125_DATA 0x00000000 +#define DDRSS2_PHY_1126_DATA 0x00000000 +#define DDRSS2_PHY_1127_DATA 0x00000000 +#define DDRSS2_PHY_1128_DATA 0x00000000 +#define DDRSS2_PHY_1129_DATA 0x00000000 +#define DDRSS2_PHY_1130_DATA 0x00000000 +#define DDRSS2_PHY_1131_DATA 0x00000000 +#define DDRSS2_PHY_1132_DATA 0x00000000 +#define DDRSS2_PHY_1133_DATA 0x00000000 +#define DDRSS2_PHY_1134_DATA 0x00000000 +#define DDRSS2_PHY_1135_DATA 0x00000000 +#define DDRSS2_PHY_1136_DATA 0x00000000 +#define DDRSS2_PHY_1137_DATA 0x00000000 +#define DDRSS2_PHY_1138_DATA 0x00000000 +#define DDRSS2_PHY_1139_DATA 0x00000000 +#define DDRSS2_PHY_1140_DATA 0x00000000 +#define DDRSS2_PHY_1141_DATA 0x00000000 +#define DDRSS2_PHY_1142_DATA 0x00000000 +#define DDRSS2_PHY_1143_DATA 0x00000000 +#define DDRSS2_PHY_1144_DATA 0x00000000 +#define DDRSS2_PHY_1145_DATA 0x00000000 +#define DDRSS2_PHY_1146_DATA 0x00000000 +#define DDRSS2_PHY_1147_DATA 0x00000000 +#define DDRSS2_PHY_1148_DATA 0x00000000 +#define DDRSS2_PHY_1149_DATA 0x00000000 +#define DDRSS2_PHY_1150_DATA 0x00000000 +#define DDRSS2_PHY_1151_DATA 0x00000000 +#define DDRSS2_PHY_1152_DATA 0x00000000 +#define DDRSS2_PHY_1153_DATA 0x00000000 +#define DDRSS2_PHY_1154_DATA 0x00000000 +#define DDRSS2_PHY_1155_DATA 0x00000000 +#define DDRSS2_PHY_1156_DATA 0x00000000 +#define DDRSS2_PHY_1157_DATA 0x00000000 +#define DDRSS2_PHY_1158_DATA 0x00000000 +#define DDRSS2_PHY_1159_DATA 0x00000000 +#define DDRSS2_PHY_1160_DATA 0x00000000 +#define DDRSS2_PHY_1161_DATA 0x00000000 +#define DDRSS2_PHY_1162_DATA 0x00000000 +#define DDRSS2_PHY_1163_DATA 0x00000000 +#define DDRSS2_PHY_1164_DATA 0x00000000 +#define DDRSS2_PHY_1165_DATA 0x00000000 +#define DDRSS2_PHY_1166_DATA 0x00000000 +#define DDRSS2_PHY_1167_DATA 0x00000000 +#define DDRSS2_PHY_1168_DATA 0x00000000 +#define DDRSS2_PHY_1169_DATA 0x00000000 +#define DDRSS2_PHY_1170_DATA 0x00000000 +#define DDRSS2_PHY_1171_DATA 0x00000000 +#define DDRSS2_PHY_1172_DATA 0x00000000 +#define DDRSS2_PHY_1173_DATA 0x00000000 +#define DDRSS2_PHY_1174_DATA 0x00000000 +#define DDRSS2_PHY_1175_DATA 0x00000000 +#define DDRSS2_PHY_1176_DATA 0x00000000 +#define DDRSS2_PHY_1177_DATA 0x00000000 +#define DDRSS2_PHY_1178_DATA 0x00000000 +#define DDRSS2_PHY_1179_DATA 0x00000000 +#define DDRSS2_PHY_1180_DATA 0x00000000 +#define DDRSS2_PHY_1181_DATA 0x00000000 +#define DDRSS2_PHY_1182_DATA 0x00000000 +#define DDRSS2_PHY_1183_DATA 0x00000000 +#define DDRSS2_PHY_1184_DATA 0x00000000 +#define DDRSS2_PHY_1185_DATA 0x00000000 +#define DDRSS2_PHY_1186_DATA 0x00000000 +#define DDRSS2_PHY_1187_DATA 0x00000000 +#define DDRSS2_PHY_1188_DATA 0x00000000 +#define DDRSS2_PHY_1189_DATA 0x00000000 +#define DDRSS2_PHY_1190_DATA 0x00000000 +#define DDRSS2_PHY_1191_DATA 0x00000000 +#define DDRSS2_PHY_1192_DATA 0x00000000 +#define DDRSS2_PHY_1193_DATA 0x00000000 +#define DDRSS2_PHY_1194_DATA 0x00000000 +#define DDRSS2_PHY_1195_DATA 0x00000000 +#define DDRSS2_PHY_1196_DATA 0x00000000 +#define DDRSS2_PHY_1197_DATA 0x00000000 +#define DDRSS2_PHY_1198_DATA 0x00000000 +#define DDRSS2_PHY_1199_DATA 0x00000000 +#define DDRSS2_PHY_1200_DATA 0x00000000 +#define DDRSS2_PHY_1201_DATA 0x00000000 +#define DDRSS2_PHY_1202_DATA 0x00000000 +#define DDRSS2_PHY_1203_DATA 0x00000000 +#define DDRSS2_PHY_1204_DATA 0x00000000 +#define DDRSS2_PHY_1205_DATA 0x00000000 +#define DDRSS2_PHY_1206_DATA 0x00000000 +#define DDRSS2_PHY_1207_DATA 0x00000000 +#define DDRSS2_PHY_1208_DATA 0x00000000 +#define DDRSS2_PHY_1209_DATA 0x00000000 +#define DDRSS2_PHY_1210_DATA 0x00000000 +#define DDRSS2_PHY_1211_DATA 0x00000000 +#define DDRSS2_PHY_1212_DATA 0x00000000 +#define DDRSS2_PHY_1213_DATA 0x00000000 +#define DDRSS2_PHY_1214_DATA 0x00000000 +#define DDRSS2_PHY_1215_DATA 0x00000000 +#define DDRSS2_PHY_1216_DATA 0x00000000 +#define DDRSS2_PHY_1217_DATA 0x00000000 +#define DDRSS2_PHY_1218_DATA 0x00000000 +#define DDRSS2_PHY_1219_DATA 0x00000000 +#define DDRSS2_PHY_1220_DATA 0x00000000 +#define DDRSS2_PHY_1221_DATA 0x00000000 +#define DDRSS2_PHY_1222_DATA 0x00000000 +#define DDRSS2_PHY_1223_DATA 0x00000000 +#define DDRSS2_PHY_1224_DATA 0x00000000 +#define DDRSS2_PHY_1225_DATA 0x00000000 +#define DDRSS2_PHY_1226_DATA 0x00000000 +#define DDRSS2_PHY_1227_DATA 0x00000000 +#define DDRSS2_PHY_1228_DATA 0x00000000 +#define DDRSS2_PHY_1229_DATA 0x00000000 +#define DDRSS2_PHY_1230_DATA 0x00000000 +#define DDRSS2_PHY_1231_DATA 0x00000000 +#define DDRSS2_PHY_1232_DATA 0x00000000 +#define DDRSS2_PHY_1233_DATA 0x00000000 +#define DDRSS2_PHY_1234_DATA 0x00000000 +#define DDRSS2_PHY_1235_DATA 0x00000000 +#define DDRSS2_PHY_1236_DATA 0x00000000 +#define DDRSS2_PHY_1237_DATA 0x00000000 +#define DDRSS2_PHY_1238_DATA 0x00000000 +#define DDRSS2_PHY_1239_DATA 0x00000000 +#define DDRSS2_PHY_1240_DATA 0x00000000 +#define DDRSS2_PHY_1241_DATA 0x00000000 +#define DDRSS2_PHY_1242_DATA 0x00000000 +#define DDRSS2_PHY_1243_DATA 0x00000000 +#define DDRSS2_PHY_1244_DATA 0x00000000 +#define DDRSS2_PHY_1245_DATA 0x00000000 +#define DDRSS2_PHY_1246_DATA 0x00000000 +#define DDRSS2_PHY_1247_DATA 0x00000000 +#define DDRSS2_PHY_1248_DATA 0x00000000 +#define DDRSS2_PHY_1249_DATA 0x00000000 +#define DDRSS2_PHY_1250_DATA 0x00000000 +#define DDRSS2_PHY_1251_DATA 0x00000000 +#define DDRSS2_PHY_1252_DATA 0x00000000 +#define DDRSS2_PHY_1253_DATA 0x00000000 +#define DDRSS2_PHY_1254_DATA 0x00000000 +#define DDRSS2_PHY_1255_DATA 0x00000000 +#define DDRSS2_PHY_1256_DATA 0x00000000 +#define DDRSS2_PHY_1257_DATA 0x00000000 +#define DDRSS2_PHY_1258_DATA 0x00000000 +#define DDRSS2_PHY_1259_DATA 0x00000000 +#define DDRSS2_PHY_1260_DATA 0x00000000 +#define DDRSS2_PHY_1261_DATA 0x00000000 +#define DDRSS2_PHY_1262_DATA 0x00000000 +#define DDRSS2_PHY_1263_DATA 0x00000000 +#define DDRSS2_PHY_1264_DATA 0x00000000 +#define DDRSS2_PHY_1265_DATA 0x00000000 +#define DDRSS2_PHY_1266_DATA 0x00000000 +#define DDRSS2_PHY_1267_DATA 0x00000000 +#define DDRSS2_PHY_1268_DATA 0x00000000 +#define DDRSS2_PHY_1269_DATA 0x00000000 +#define DDRSS2_PHY_1270_DATA 0x00000000 +#define DDRSS2_PHY_1271_DATA 0x00000000 +#define DDRSS2_PHY_1272_DATA 0x00000000 +#define DDRSS2_PHY_1273_DATA 0x00000000 +#define DDRSS2_PHY_1274_DATA 0x00000000 +#define DDRSS2_PHY_1275_DATA 0x00000000 +#define DDRSS2_PHY_1276_DATA 0x00000000 +#define DDRSS2_PHY_1277_DATA 0x00000000 +#define DDRSS2_PHY_1278_DATA 0x00000000 +#define DDRSS2_PHY_1279_DATA 0x00000000 +#define DDRSS2_PHY_1280_DATA 0x00000000 +#define DDRSS2_PHY_1281_DATA 0x00010100 +#define DDRSS2_PHY_1282_DATA 0x00000000 +#define DDRSS2_PHY_1283_DATA 0x00000000 +#define DDRSS2_PHY_1284_DATA 0x00050000 +#define DDRSS2_PHY_1285_DATA 0x04000000 +#define DDRSS2_PHY_1286_DATA 0x00000055 +#define DDRSS2_PHY_1287_DATA 0x00000000 +#define DDRSS2_PHY_1288_DATA 0x00000000 +#define DDRSS2_PHY_1289_DATA 0x00000000 +#define DDRSS2_PHY_1290_DATA 0x00000000 +#define DDRSS2_PHY_1291_DATA 0x00002001 +#define DDRSS2_PHY_1292_DATA 0x0000400F +#define DDRSS2_PHY_1293_DATA 0x50020028 +#define DDRSS2_PHY_1294_DATA 0x01010000 +#define DDRSS2_PHY_1295_DATA 0x80080001 +#define DDRSS2_PHY_1296_DATA 0x10200000 +#define DDRSS2_PHY_1297_DATA 0x00000008 +#define DDRSS2_PHY_1298_DATA 0x00000000 +#define DDRSS2_PHY_1299_DATA 0x01090E00 +#define DDRSS2_PHY_1300_DATA 0x00040101 +#define DDRSS2_PHY_1301_DATA 0x0000010F +#define DDRSS2_PHY_1302_DATA 0x00000000 +#define DDRSS2_PHY_1303_DATA 0x0000FFFF +#define DDRSS2_PHY_1304_DATA 0x00000000 +#define DDRSS2_PHY_1305_DATA 0x01010000 +#define DDRSS2_PHY_1306_DATA 0x01080402 +#define DDRSS2_PHY_1307_DATA 0x01200F02 +#define DDRSS2_PHY_1308_DATA 0x00194280 +#define DDRSS2_PHY_1309_DATA 0x00000004 +#define DDRSS2_PHY_1310_DATA 0x00042000 +#define DDRSS2_PHY_1311_DATA 0x00000000 +#define DDRSS2_PHY_1312_DATA 0x00000000 +#define DDRSS2_PHY_1313_DATA 0x00000000 +#define DDRSS2_PHY_1314_DATA 0x00000000 +#define DDRSS2_PHY_1315_DATA 0x00000000 +#define DDRSS2_PHY_1316_DATA 0x00000000 +#define DDRSS2_PHY_1317_DATA 0x01000000 +#define DDRSS2_PHY_1318_DATA 0x00000705 +#define DDRSS2_PHY_1319_DATA 0x00000054 +#define DDRSS2_PHY_1320_DATA 0x00030820 +#define DDRSS2_PHY_1321_DATA 0x00010820 +#define DDRSS2_PHY_1322_DATA 0x00010820 +#define DDRSS2_PHY_1323_DATA 0x00010820 +#define DDRSS2_PHY_1324_DATA 0x00010820 +#define DDRSS2_PHY_1325_DATA 0x00010820 +#define DDRSS2_PHY_1326_DATA 0x00010820 +#define DDRSS2_PHY_1327_DATA 0x00010820 +#define DDRSS2_PHY_1328_DATA 0x00010820 +#define DDRSS2_PHY_1329_DATA 0x00000000 +#define DDRSS2_PHY_1330_DATA 0x00000074 +#define DDRSS2_PHY_1331_DATA 0x00000400 +#define DDRSS2_PHY_1332_DATA 0x00000108 +#define DDRSS2_PHY_1333_DATA 0x00000000 +#define DDRSS2_PHY_1334_DATA 0x00000000 +#define DDRSS2_PHY_1335_DATA 0x00000000 +#define DDRSS2_PHY_1336_DATA 0x00000000 +#define DDRSS2_PHY_1337_DATA 0x00000000 +#define DDRSS2_PHY_1338_DATA 0x03000000 +#define DDRSS2_PHY_1339_DATA 0x00000000 +#define DDRSS2_PHY_1340_DATA 0x00000000 +#define DDRSS2_PHY_1341_DATA 0x00000000 +#define DDRSS2_PHY_1342_DATA 0x04102006 +#define DDRSS2_PHY_1343_DATA 0x00041020 +#define DDRSS2_PHY_1344_DATA 0x01C98C98 +#define DDRSS2_PHY_1345_DATA 0x3F400000 +#define DDRSS2_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS2_PHY_1347_DATA 0x0000001F +#define DDRSS2_PHY_1348_DATA 0x00000000 +#define DDRSS2_PHY_1349_DATA 0x00000000 +#define DDRSS2_PHY_1350_DATA 0x00000000 +#define DDRSS2_PHY_1351_DATA 0x00010000 +#define DDRSS2_PHY_1352_DATA 0x00000000 +#define DDRSS2_PHY_1353_DATA 0x00000000 +#define DDRSS2_PHY_1354_DATA 0x00000000 +#define DDRSS2_PHY_1355_DATA 0x00000000 +#define DDRSS2_PHY_1356_DATA 0x76543210 +#define DDRSS2_PHY_1357_DATA 0x00010198 +#define DDRSS2_PHY_1358_DATA 0x00000000 +#define DDRSS2_PHY_1359_DATA 0x00000000 +#define DDRSS2_PHY_1360_DATA 0x00000000 +#define DDRSS2_PHY_1361_DATA 0x00040700 +#define DDRSS2_PHY_1362_DATA 0x00000000 +#define DDRSS2_PHY_1363_DATA 0x00000000 +#define DDRSS2_PHY_1364_DATA 0x00000000 +#define DDRSS2_PHY_1365_DATA 0x00000000 +#define DDRSS2_PHY_1366_DATA 0x00000000 +#define DDRSS2_PHY_1367_DATA 0x00000002 +#define DDRSS2_PHY_1368_DATA 0x00000000 +#define DDRSS2_PHY_1369_DATA 0x00000000 +#define DDRSS2_PHY_1370_DATA 0x00000000 +#define DDRSS2_PHY_1371_DATA 0x00000000 +#define DDRSS2_PHY_1372_DATA 0x00000000 +#define DDRSS2_PHY_1373_DATA 0x00000000 +#define DDRSS2_PHY_1374_DATA 0x00080000 +#define DDRSS2_PHY_1375_DATA 0x000007FF +#define DDRSS2_PHY_1376_DATA 0x00000000 +#define DDRSS2_PHY_1377_DATA 0x00000000 +#define DDRSS2_PHY_1378_DATA 0x00000000 +#define DDRSS2_PHY_1379_DATA 0x00000000 +#define DDRSS2_PHY_1380_DATA 0x00000000 +#define DDRSS2_PHY_1381_DATA 0x00000000 +#define DDRSS2_PHY_1382_DATA 0x000FFFFF +#define DDRSS2_PHY_1383_DATA 0x000FFFFF +#define DDRSS2_PHY_1384_DATA 0x0000FFFF +#define DDRSS2_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS2_PHY_1386_DATA 0x030FFFFF +#define DDRSS2_PHY_1387_DATA 0x01FFFFFF +#define DDRSS2_PHY_1388_DATA 0x0000FFFF +#define DDRSS2_PHY_1389_DATA 0x00000000 +#define DDRSS2_PHY_1390_DATA 0x00000000 +#define DDRSS2_PHY_1391_DATA 0x00000000 +#define DDRSS2_PHY_1392_DATA 0x00000000 +#define DDRSS2_PHY_1393_DATA 0x0001F7C0 +#define DDRSS2_PHY_1394_DATA 0x00000003 +#define DDRSS2_PHY_1395_DATA 0x00000000 +#define DDRSS2_PHY_1396_DATA 0x00001142 +#define DDRSS2_PHY_1397_DATA 0x010207AB +#define DDRSS2_PHY_1398_DATA 0x01000080 +#define DDRSS2_PHY_1399_DATA 0x03900390 +#define DDRSS2_PHY_1400_DATA 0x03900390 +#define DDRSS2_PHY_1401_DATA 0x00000390 +#define DDRSS2_PHY_1402_DATA 0x00000390 +#define DDRSS2_PHY_1403_DATA 0x00000390 +#define DDRSS2_PHY_1404_DATA 0x00000390 +#define DDRSS2_PHY_1405_DATA 0x00000005 +#define DDRSS2_PHY_1406_DATA 0x01813FCC +#define DDRSS2_PHY_1407_DATA 0x000000CC +#define DDRSS2_PHY_1408_DATA 0x0C000DFF +#define DDRSS2_PHY_1409_DATA 0x30000DFF +#define DDRSS2_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS2_PHY_1411_DATA 0x000100F0 +#define DDRSS2_PHY_1412_DATA 0x780DFFCC +#define DDRSS2_PHY_1413_DATA 0x00007E31 +#define DDRSS2_PHY_1414_DATA 0x000CBF11 +#define DDRSS2_PHY_1415_DATA 0x01990010 +#define DDRSS2_PHY_1416_DATA 0x000CBF11 +#define DDRSS2_PHY_1417_DATA 0x01990010 +#define DDRSS2_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS2_PHY_1419_DATA 0x00EF00F0 +#define DDRSS2_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS2_PHY_1421_DATA 0x01FF00F0 +#define DDRSS2_PHY_1422_DATA 0x20040006 + +#define DDRSS3_CTL_00_DATA 0x00000B00 +#define DDRSS3_CTL_01_DATA 0x00000000 +#define DDRSS3_CTL_02_DATA 0x00000000 +#define DDRSS3_CTL_03_DATA 0x00000000 +#define DDRSS3_CTL_04_DATA 0x00000000 +#define DDRSS3_CTL_05_DATA 0x00000000 +#define DDRSS3_CTL_06_DATA 0x00000000 +#define DDRSS3_CTL_07_DATA 0x00002AF8 +#define DDRSS3_CTL_08_DATA 0x0001ADAF +#define DDRSS3_CTL_09_DATA 0x00000005 +#define DDRSS3_CTL_10_DATA 0x0000006E +#define DDRSS3_CTL_11_DATA 0x000681C8 +#define DDRSS3_CTL_12_DATA 0x004111C9 +#define DDRSS3_CTL_13_DATA 0x00000005 +#define DDRSS3_CTL_14_DATA 0x000010A9 +#define DDRSS3_CTL_15_DATA 0x000681C8 +#define DDRSS3_CTL_16_DATA 0x004111C9 +#define DDRSS3_CTL_17_DATA 0x00000005 +#define DDRSS3_CTL_18_DATA 0x000010A9 +#define DDRSS3_CTL_19_DATA 0x01010000 +#define DDRSS3_CTL_20_DATA 0x02011001 +#define DDRSS3_CTL_21_DATA 0x02010000 +#define DDRSS3_CTL_22_DATA 0x00020100 +#define DDRSS3_CTL_23_DATA 0x0000000B +#define DDRSS3_CTL_24_DATA 0x0000001C +#define DDRSS3_CTL_25_DATA 0x00000000 +#define DDRSS3_CTL_26_DATA 0x00000000 +#define DDRSS3_CTL_27_DATA 0x03020200 +#define DDRSS3_CTL_28_DATA 0x00005656 +#define DDRSS3_CTL_29_DATA 0x00100000 +#define DDRSS3_CTL_30_DATA 0x00000000 +#define DDRSS3_CTL_31_DATA 0x00000000 +#define DDRSS3_CTL_32_DATA 0x00000000 +#define DDRSS3_CTL_33_DATA 0x00000000 +#define DDRSS3_CTL_34_DATA 0x040C0000 +#define DDRSS3_CTL_35_DATA 0x12481248 +#define DDRSS3_CTL_36_DATA 0x00050804 +#define DDRSS3_CTL_37_DATA 0x09040008 +#define DDRSS3_CTL_38_DATA 0x15000204 +#define DDRSS3_CTL_39_DATA 0x1760008B +#define DDRSS3_CTL_40_DATA 0x1500422B +#define DDRSS3_CTL_41_DATA 0x1760008B +#define DDRSS3_CTL_42_DATA 0x2000422B +#define DDRSS3_CTL_43_DATA 0x000A0A09 +#define DDRSS3_CTL_44_DATA 0x040003C5 +#define DDRSS3_CTL_45_DATA 0x1E161104 +#define DDRSS3_CTL_46_DATA 0x1000922C +#define DDRSS3_CTL_47_DATA 0x1E161110 +#define DDRSS3_CTL_48_DATA 0x1000922C +#define DDRSS3_CTL_49_DATA 0x02030410 +#define DDRSS3_CTL_50_DATA 0x2C040500 +#define DDRSS3_CTL_51_DATA 0x08292C29 +#define DDRSS3_CTL_52_DATA 0x14000E0A +#define DDRSS3_CTL_53_DATA 0x04010A0A +#define DDRSS3_CTL_54_DATA 0x01010004 +#define DDRSS3_CTL_55_DATA 0x04545408 +#define DDRSS3_CTL_56_DATA 0x04313104 +#define DDRSS3_CTL_57_DATA 0x00003131 +#define DDRSS3_CTL_58_DATA 0x00010100 +#define DDRSS3_CTL_59_DATA 0x03010000 +#define DDRSS3_CTL_60_DATA 0x00001508 +#define DDRSS3_CTL_61_DATA 0x00000063 +#define DDRSS3_CTL_62_DATA 0x0000032B +#define DDRSS3_CTL_63_DATA 0x00001035 +#define DDRSS3_CTL_64_DATA 0x0000032B +#define DDRSS3_CTL_65_DATA 0x00001035 +#define DDRSS3_CTL_66_DATA 0x00000005 +#define DDRSS3_CTL_67_DATA 0x00050000 +#define DDRSS3_CTL_68_DATA 0x00CB0012 +#define DDRSS3_CTL_69_DATA 0x00CB0408 +#define DDRSS3_CTL_70_DATA 0x00400408 +#define DDRSS3_CTL_71_DATA 0x00120103 +#define DDRSS3_CTL_72_DATA 0x00100005 +#define DDRSS3_CTL_73_DATA 0x2F080010 +#define DDRSS3_CTL_74_DATA 0x0505012F +#define DDRSS3_CTL_75_DATA 0x0401030A +#define DDRSS3_CTL_76_DATA 0x041E100B +#define DDRSS3_CTL_77_DATA 0x100B0401 +#define DDRSS3_CTL_78_DATA 0x0001041E +#define DDRSS3_CTL_79_DATA 0x00160016 +#define DDRSS3_CTL_80_DATA 0x033B033B +#define DDRSS3_CTL_81_DATA 0x033B033B +#define DDRSS3_CTL_82_DATA 0x03050505 +#define DDRSS3_CTL_83_DATA 0x03010303 +#define DDRSS3_CTL_84_DATA 0x200B100B +#define DDRSS3_CTL_85_DATA 0x04041004 +#define DDRSS3_CTL_86_DATA 0x200B100B +#define DDRSS3_CTL_87_DATA 0x04041004 +#define DDRSS3_CTL_88_DATA 0x03010000 +#define DDRSS3_CTL_89_DATA 0x00010000 +#define DDRSS3_CTL_90_DATA 0x00000000 +#define DDRSS3_CTL_91_DATA 0x00000000 +#define DDRSS3_CTL_92_DATA 0x01000000 +#define DDRSS3_CTL_93_DATA 0x80104002 +#define DDRSS3_CTL_94_DATA 0x00000000 +#define DDRSS3_CTL_95_DATA 0x00040005 +#define DDRSS3_CTL_96_DATA 0x00000000 +#define DDRSS3_CTL_97_DATA 0x00050000 +#define DDRSS3_CTL_98_DATA 0x00000004 +#define DDRSS3_CTL_99_DATA 0x00000000 +#define DDRSS3_CTL_100_DATA 0x00040005 +#define DDRSS3_CTL_101_DATA 0x00000000 +#define DDRSS3_CTL_102_DATA 0x000018C0 +#define DDRSS3_CTL_103_DATA 0x000018C0 +#define DDRSS3_CTL_104_DATA 0x000018C0 +#define DDRSS3_CTL_105_DATA 0x000018C0 +#define DDRSS3_CTL_106_DATA 0x000018C0 +#define DDRSS3_CTL_107_DATA 0x00000000 +#define DDRSS3_CTL_108_DATA 0x000002B5 +#define DDRSS3_CTL_109_DATA 0x00040D40 +#define DDRSS3_CTL_110_DATA 0x00040D40 +#define DDRSS3_CTL_111_DATA 0x00040D40 +#define DDRSS3_CTL_112_DATA 0x00040D40 +#define DDRSS3_CTL_113_DATA 0x00040D40 +#define DDRSS3_CTL_114_DATA 0x00000000 +#define DDRSS3_CTL_115_DATA 0x00007173 +#define DDRSS3_CTL_116_DATA 0x00040D40 +#define DDRSS3_CTL_117_DATA 0x00040D40 +#define DDRSS3_CTL_118_DATA 0x00040D40 +#define DDRSS3_CTL_119_DATA 0x00040D40 +#define DDRSS3_CTL_120_DATA 0x00040D40 +#define DDRSS3_CTL_121_DATA 0x00000000 +#define DDRSS3_CTL_122_DATA 0x00007173 +#define DDRSS3_CTL_123_DATA 0x00000000 +#define DDRSS3_CTL_124_DATA 0x00000000 +#define DDRSS3_CTL_125_DATA 0x00000000 +#define DDRSS3_CTL_126_DATA 0x00000000 +#define DDRSS3_CTL_127_DATA 0x00000000 +#define DDRSS3_CTL_128_DATA 0x00000000 +#define DDRSS3_CTL_129_DATA 0x00000000 +#define DDRSS3_CTL_130_DATA 0x00000000 +#define DDRSS3_CTL_131_DATA 0x0B030500 +#define DDRSS3_CTL_132_DATA 0x00040B04 +#define DDRSS3_CTL_133_DATA 0x0A090000 +#define DDRSS3_CTL_134_DATA 0x0A090701 +#define DDRSS3_CTL_135_DATA 0x0900000E +#define DDRSS3_CTL_136_DATA 0x0907010A +#define DDRSS3_CTL_137_DATA 0x00000E0A +#define DDRSS3_CTL_138_DATA 0x07010A09 +#define DDRSS3_CTL_139_DATA 0x000E0A09 +#define DDRSS3_CTL_140_DATA 0x07000401 +#define DDRSS3_CTL_141_DATA 0x00000000 +#define DDRSS3_CTL_142_DATA 0x00000000 +#define DDRSS3_CTL_143_DATA 0x00000000 +#define DDRSS3_CTL_144_DATA 0x00000000 +#define DDRSS3_CTL_145_DATA 0x00000000 +#define DDRSS3_CTL_146_DATA 0x00000000 +#define DDRSS3_CTL_147_DATA 0x00000000 +#define DDRSS3_CTL_148_DATA 0x08080000 +#define DDRSS3_CTL_149_DATA 0x01000000 +#define DDRSS3_CTL_150_DATA 0x800000C0 +#define DDRSS3_CTL_151_DATA 0x800000C0 +#define DDRSS3_CTL_152_DATA 0x800000C0 +#define DDRSS3_CTL_153_DATA 0x00000000 +#define DDRSS3_CTL_154_DATA 0x00001500 +#define DDRSS3_CTL_155_DATA 0x00000000 +#define DDRSS3_CTL_156_DATA 0x00000001 +#define DDRSS3_CTL_157_DATA 0x00000002 +#define DDRSS3_CTL_158_DATA 0x0000100E +#define DDRSS3_CTL_159_DATA 0x00000000 +#define DDRSS3_CTL_160_DATA 0x00000000 +#define DDRSS3_CTL_161_DATA 0x00000000 +#define DDRSS3_CTL_162_DATA 0x00000000 +#define DDRSS3_CTL_163_DATA 0x00000000 +#define DDRSS3_CTL_164_DATA 0x000B0000 +#define DDRSS3_CTL_165_DATA 0x000E0006 +#define DDRSS3_CTL_166_DATA 0x000E0404 +#define DDRSS3_CTL_167_DATA 0x00D601AB +#define DDRSS3_CTL_168_DATA 0x10100216 +#define DDRSS3_CTL_169_DATA 0x01AB0216 +#define DDRSS3_CTL_170_DATA 0x021600D6 +#define DDRSS3_CTL_171_DATA 0x02161010 +#define DDRSS3_CTL_172_DATA 0x00000000 +#define DDRSS3_CTL_173_DATA 0x00000000 +#define DDRSS3_CTL_174_DATA 0x00000000 +#define DDRSS3_CTL_175_DATA 0x3FF40084 +#define DDRSS3_CTL_176_DATA 0x33003FF4 +#define DDRSS3_CTL_177_DATA 0x00003333 +#define DDRSS3_CTL_178_DATA 0x35000000 +#define DDRSS3_CTL_179_DATA 0x27270035 +#define DDRSS3_CTL_180_DATA 0x0F0F0000 +#define DDRSS3_CTL_181_DATA 0x16000000 +#define DDRSS3_CTL_182_DATA 0x00841616 +#define DDRSS3_CTL_183_DATA 0x3FF43FF4 +#define DDRSS3_CTL_184_DATA 0x33333300 +#define DDRSS3_CTL_185_DATA 0x00000000 +#define DDRSS3_CTL_186_DATA 0x00353500 +#define DDRSS3_CTL_187_DATA 0x00002727 +#define DDRSS3_CTL_188_DATA 0x00000F0F +#define DDRSS3_CTL_189_DATA 0x16161600 +#define DDRSS3_CTL_190_DATA 0x00000020 +#define DDRSS3_CTL_191_DATA 0x00000000 +#define DDRSS3_CTL_192_DATA 0x00000001 +#define DDRSS3_CTL_193_DATA 0x00000000 +#define DDRSS3_CTL_194_DATA 0x01000000 +#define DDRSS3_CTL_195_DATA 0x00000001 +#define DDRSS3_CTL_196_DATA 0x00000000 +#define DDRSS3_CTL_197_DATA 0x00000000 +#define DDRSS3_CTL_198_DATA 0x00000000 +#define DDRSS3_CTL_199_DATA 0x00000000 +#define DDRSS3_CTL_200_DATA 0x00000000 +#define DDRSS3_CTL_201_DATA 0x00000000 +#define DDRSS3_CTL_202_DATA 0x00000000 +#define DDRSS3_CTL_203_DATA 0x00000000 +#define DDRSS3_CTL_204_DATA 0x00000000 +#define DDRSS3_CTL_205_DATA 0x00000000 +#define DDRSS3_CTL_206_DATA 0x02000000 +#define DDRSS3_CTL_207_DATA 0x01080101 +#define DDRSS3_CTL_208_DATA 0x00000000 +#define DDRSS3_CTL_209_DATA 0x00000000 +#define DDRSS3_CTL_210_DATA 0x00000000 +#define DDRSS3_CTL_211_DATA 0x00000000 +#define DDRSS3_CTL_212_DATA 0x00000000 +#define DDRSS3_CTL_213_DATA 0x00000000 +#define DDRSS3_CTL_214_DATA 0x00000000 +#define DDRSS3_CTL_215_DATA 0x00000000 +#define DDRSS3_CTL_216_DATA 0x00000000 +#define DDRSS3_CTL_217_DATA 0x00000000 +#define DDRSS3_CTL_218_DATA 0x00000000 +#define DDRSS3_CTL_219_DATA 0x00000000 +#define DDRSS3_CTL_220_DATA 0x00000000 +#define DDRSS3_CTL_221_DATA 0x00000000 +#define DDRSS3_CTL_222_DATA 0x00001000 +#define DDRSS3_CTL_223_DATA 0x006403E8 +#define DDRSS3_CTL_224_DATA 0x00000000 +#define DDRSS3_CTL_225_DATA 0x00000000 +#define DDRSS3_CTL_226_DATA 0x00000000 +#define DDRSS3_CTL_227_DATA 0x15110000 +#define DDRSS3_CTL_228_DATA 0x00040C18 +#define DDRSS3_CTL_229_DATA 0xF000C000 +#define DDRSS3_CTL_230_DATA 0x0000F000 +#define DDRSS3_CTL_231_DATA 0x00000000 +#define DDRSS3_CTL_232_DATA 0x00000000 +#define DDRSS3_CTL_233_DATA 0xC0000000 +#define DDRSS3_CTL_234_DATA 0xF000F000 +#define DDRSS3_CTL_235_DATA 0x00000000 +#define DDRSS3_CTL_236_DATA 0x00000000 +#define DDRSS3_CTL_237_DATA 0x00000000 +#define DDRSS3_CTL_238_DATA 0xF000C000 +#define DDRSS3_CTL_239_DATA 0x0000F000 +#define DDRSS3_CTL_240_DATA 0x00000000 +#define DDRSS3_CTL_241_DATA 0x00000000 +#define DDRSS3_CTL_242_DATA 0x00030000 +#define DDRSS3_CTL_243_DATA 0x00000000 +#define DDRSS3_CTL_244_DATA 0x00000000 +#define DDRSS3_CTL_245_DATA 0x00000000 +#define DDRSS3_CTL_246_DATA 0x00000000 +#define DDRSS3_CTL_247_DATA 0x00000000 +#define DDRSS3_CTL_248_DATA 0x00000000 +#define DDRSS3_CTL_249_DATA 0x00000000 +#define DDRSS3_CTL_250_DATA 0x00000000 +#define DDRSS3_CTL_251_DATA 0x00000000 +#define DDRSS3_CTL_252_DATA 0x00000000 +#define DDRSS3_CTL_253_DATA 0x00000000 +#define DDRSS3_CTL_254_DATA 0x00000000 +#define DDRSS3_CTL_255_DATA 0x00000000 +#define DDRSS3_CTL_256_DATA 0x00000000 +#define DDRSS3_CTL_257_DATA 0x01000200 +#define DDRSS3_CTL_258_DATA 0x00370040 +#define DDRSS3_CTL_259_DATA 0x00020008 +#define DDRSS3_CTL_260_DATA 0x00400100 +#define DDRSS3_CTL_261_DATA 0x00400855 +#define DDRSS3_CTL_262_DATA 0x01000200 +#define DDRSS3_CTL_263_DATA 0x08550040 +#define DDRSS3_CTL_264_DATA 0x00000040 +#define DDRSS3_CTL_265_DATA 0x006B0003 +#define DDRSS3_CTL_266_DATA 0x0100006B +#define DDRSS3_CTL_267_DATA 0x03030303 +#define DDRSS3_CTL_268_DATA 0x00000000 +#define DDRSS3_CTL_269_DATA 0x00000202 +#define DDRSS3_CTL_270_DATA 0x00001FFF +#define DDRSS3_CTL_271_DATA 0x3FFF2000 +#define DDRSS3_CTL_272_DATA 0x03FF0000 +#define DDRSS3_CTL_273_DATA 0x000103FF +#define DDRSS3_CTL_274_DATA 0x0FFF0B00 +#define DDRSS3_CTL_275_DATA 0x01010001 +#define DDRSS3_CTL_276_DATA 0x01010101 +#define DDRSS3_CTL_277_DATA 0x01180101 +#define DDRSS3_CTL_278_DATA 0x00030000 +#define DDRSS3_CTL_279_DATA 0x00000000 +#define DDRSS3_CTL_280_DATA 0x00000000 +#define DDRSS3_CTL_281_DATA 0x00000000 +#define DDRSS3_CTL_282_DATA 0x00000000 +#define DDRSS3_CTL_283_DATA 0x00000000 +#define DDRSS3_CTL_284_DATA 0x00000000 +#define DDRSS3_CTL_285_DATA 0x00000000 +#define DDRSS3_CTL_286_DATA 0x00040101 +#define DDRSS3_CTL_287_DATA 0x04010100 +#define DDRSS3_CTL_288_DATA 0x00000000 +#define DDRSS3_CTL_289_DATA 0x00000000 +#define DDRSS3_CTL_290_DATA 0x03030300 +#define DDRSS3_CTL_291_DATA 0x00000001 +#define DDRSS3_CTL_292_DATA 0x00000000 +#define DDRSS3_CTL_293_DATA 0x00000000 +#define DDRSS3_CTL_294_DATA 0x00000000 +#define DDRSS3_CTL_295_DATA 0x00000000 +#define DDRSS3_CTL_296_DATA 0x00000000 +#define DDRSS3_CTL_297_DATA 0x00000000 +#define DDRSS3_CTL_298_DATA 0x00000000 +#define DDRSS3_CTL_299_DATA 0x00000000 +#define DDRSS3_CTL_300_DATA 0x00000000 +#define DDRSS3_CTL_301_DATA 0x00000000 +#define DDRSS3_CTL_302_DATA 0x00000000 +#define DDRSS3_CTL_303_DATA 0x00000000 +#define DDRSS3_CTL_304_DATA 0x00000000 +#define DDRSS3_CTL_305_DATA 0x00000000 +#define DDRSS3_CTL_306_DATA 0x00000000 +#define DDRSS3_CTL_307_DATA 0x00000000 +#define DDRSS3_CTL_308_DATA 0x00000000 +#define DDRSS3_CTL_309_DATA 0x00000000 +#define DDRSS3_CTL_310_DATA 0x00000000 +#define DDRSS3_CTL_311_DATA 0x00000000 +#define DDRSS3_CTL_312_DATA 0x00000000 +#define DDRSS3_CTL_313_DATA 0x01000000 +#define DDRSS3_CTL_314_DATA 0x00020201 +#define DDRSS3_CTL_315_DATA 0x01000101 +#define DDRSS3_CTL_316_DATA 0x01010001 +#define DDRSS3_CTL_317_DATA 0x00010101 +#define DDRSS3_CTL_318_DATA 0x050A0A03 +#define DDRSS3_CTL_319_DATA 0x10081F1F +#define DDRSS3_CTL_320_DATA 0x00090310 +#define DDRSS3_CTL_321_DATA 0x0B0C030F +#define DDRSS3_CTL_322_DATA 0x0B0C0306 +#define DDRSS3_CTL_323_DATA 0x0C090006 +#define DDRSS3_CTL_324_DATA 0x0100000C +#define DDRSS3_CTL_325_DATA 0x08040801 +#define DDRSS3_CTL_326_DATA 0x00000004 +#define DDRSS3_CTL_327_DATA 0x00000000 +#define DDRSS3_CTL_328_DATA 0x00010000 +#define DDRSS3_CTL_329_DATA 0x00280D00 +#define DDRSS3_CTL_330_DATA 0x00000001 +#define DDRSS3_CTL_331_DATA 0x00030001 +#define DDRSS3_CTL_332_DATA 0x00000000 +#define DDRSS3_CTL_333_DATA 0x00000000 +#define DDRSS3_CTL_334_DATA 0x00000000 +#define DDRSS3_CTL_335_DATA 0x00000000 +#define DDRSS3_CTL_336_DATA 0x00000000 +#define DDRSS3_CTL_337_DATA 0x00000000 +#define DDRSS3_CTL_338_DATA 0x00000000 +#define DDRSS3_CTL_339_DATA 0x00000000 +#define DDRSS3_CTL_340_DATA 0x01000000 +#define DDRSS3_CTL_341_DATA 0x00000001 +#define DDRSS3_CTL_342_DATA 0x00010100 +#define DDRSS3_CTL_343_DATA 0x03030000 +#define DDRSS3_CTL_344_DATA 0x00000000 +#define DDRSS3_CTL_345_DATA 0x00000000 +#define DDRSS3_CTL_346_DATA 0x00000000 +#define DDRSS3_CTL_347_DATA 0x00000000 +#define DDRSS3_CTL_348_DATA 0x00000000 +#define DDRSS3_CTL_349_DATA 0x00000000 +#define DDRSS3_CTL_350_DATA 0x00000000 +#define DDRSS3_CTL_351_DATA 0x00000000 +#define DDRSS3_CTL_352_DATA 0x00000000 +#define DDRSS3_CTL_353_DATA 0x00000000 +#define DDRSS3_CTL_354_DATA 0x00000000 +#define DDRSS3_CTL_355_DATA 0x00000000 +#define DDRSS3_CTL_356_DATA 0x00000000 +#define DDRSS3_CTL_357_DATA 0x00000000 +#define DDRSS3_CTL_358_DATA 0x00000000 +#define DDRSS3_CTL_359_DATA 0x00000000 +#define DDRSS3_CTL_360_DATA 0x000556AA +#define DDRSS3_CTL_361_DATA 0x000AAAAA +#define DDRSS3_CTL_362_DATA 0x000AA955 +#define DDRSS3_CTL_363_DATA 0x00055555 +#define DDRSS3_CTL_364_DATA 0x000B3133 +#define DDRSS3_CTL_365_DATA 0x0004CD33 +#define DDRSS3_CTL_366_DATA 0x0004CECC +#define DDRSS3_CTL_367_DATA 0x000B32CC +#define DDRSS3_CTL_368_DATA 0x00010300 +#define DDRSS3_CTL_369_DATA 0x03000100 +#define DDRSS3_CTL_370_DATA 0x00000000 +#define DDRSS3_CTL_371_DATA 0x00000000 +#define DDRSS3_CTL_372_DATA 0x00000000 +#define DDRSS3_CTL_373_DATA 0x00000000 +#define DDRSS3_CTL_374_DATA 0x00000000 +#define DDRSS3_CTL_375_DATA 0x00000000 +#define DDRSS3_CTL_376_DATA 0x00000000 +#define DDRSS3_CTL_377_DATA 0x00010000 +#define DDRSS3_CTL_378_DATA 0x00000404 +#define DDRSS3_CTL_379_DATA 0x00000000 +#define DDRSS3_CTL_380_DATA 0x00000000 +#define DDRSS3_CTL_381_DATA 0x00000000 +#define DDRSS3_CTL_382_DATA 0x00000000 +#define DDRSS3_CTL_383_DATA 0x00000000 +#define DDRSS3_CTL_384_DATA 0x00000000 +#define DDRSS3_CTL_385_DATA 0x00000000 +#define DDRSS3_CTL_386_DATA 0x00000000 +#define DDRSS3_CTL_387_DATA 0x3A3A1B00 +#define DDRSS3_CTL_388_DATA 0x000A0000 +#define DDRSS3_CTL_389_DATA 0x000000C6 +#define DDRSS3_CTL_390_DATA 0x00000200 +#define DDRSS3_CTL_391_DATA 0x00000200 +#define DDRSS3_CTL_392_DATA 0x00000200 +#define DDRSS3_CTL_393_DATA 0x00000200 +#define DDRSS3_CTL_394_DATA 0x00000252 +#define DDRSS3_CTL_395_DATA 0x000007BC +#define DDRSS3_CTL_396_DATA 0x00000204 +#define DDRSS3_CTL_397_DATA 0x0000206A +#define DDRSS3_CTL_398_DATA 0x00000200 +#define DDRSS3_CTL_399_DATA 0x00000200 +#define DDRSS3_CTL_400_DATA 0x00000200 +#define DDRSS3_CTL_401_DATA 0x00000200 +#define DDRSS3_CTL_402_DATA 0x0000613E +#define DDRSS3_CTL_403_DATA 0x00014424 +#define DDRSS3_CTL_404_DATA 0x00000E15 +#define DDRSS3_CTL_405_DATA 0x0000206A +#define DDRSS3_CTL_406_DATA 0x00000200 +#define DDRSS3_CTL_407_DATA 0x00000200 +#define DDRSS3_CTL_408_DATA 0x00000200 +#define DDRSS3_CTL_409_DATA 0x00000200 +#define DDRSS3_CTL_410_DATA 0x0000613E +#define DDRSS3_CTL_411_DATA 0x00014424 +#define DDRSS3_CTL_412_DATA 0x02020E15 +#define DDRSS3_CTL_413_DATA 0x03030202 +#define DDRSS3_CTL_414_DATA 0x00000022 +#define DDRSS3_CTL_415_DATA 0x00000000 +#define DDRSS3_CTL_416_DATA 0x00000000 +#define DDRSS3_CTL_417_DATA 0x00001403 +#define DDRSS3_CTL_418_DATA 0x000007D0 +#define DDRSS3_CTL_419_DATA 0x00000000 +#define DDRSS3_CTL_420_DATA 0x00000000 +#define DDRSS3_CTL_421_DATA 0x00030000 +#define DDRSS3_CTL_422_DATA 0x0007001F +#define DDRSS3_CTL_423_DATA 0x001B0033 +#define DDRSS3_CTL_424_DATA 0x001B0033 +#define DDRSS3_CTL_425_DATA 0x00000000 +#define DDRSS3_CTL_426_DATA 0x00000000 +#define DDRSS3_CTL_427_DATA 0x02000000 +#define DDRSS3_CTL_428_DATA 0x01000404 +#define DDRSS3_CTL_429_DATA 0x0B1E0B1E +#define DDRSS3_CTL_430_DATA 0x00000105 +#define DDRSS3_CTL_431_DATA 0x00010101 +#define DDRSS3_CTL_432_DATA 0x00010101 +#define DDRSS3_CTL_433_DATA 0x00010001 +#define DDRSS3_CTL_434_DATA 0x00000101 +#define DDRSS3_CTL_435_DATA 0x02000201 +#define DDRSS3_CTL_436_DATA 0x02010000 +#define DDRSS3_CTL_437_DATA 0x00000200 +#define DDRSS3_CTL_438_DATA 0x28060000 +#define DDRSS3_CTL_439_DATA 0x00000128 +#define DDRSS3_CTL_440_DATA 0xFFFFFFFF +#define DDRSS3_CTL_441_DATA 0xFFFFFFFF +#define DDRSS3_CTL_442_DATA 0x00000000 +#define DDRSS3_CTL_443_DATA 0x00000000 +#define DDRSS3_CTL_444_DATA 0x00000000 +#define DDRSS3_CTL_445_DATA 0x00000000 +#define DDRSS3_CTL_446_DATA 0x00000000 +#define DDRSS3_CTL_447_DATA 0x00000000 +#define DDRSS3_CTL_448_DATA 0x00000000 +#define DDRSS3_CTL_449_DATA 0x00000000 +#define DDRSS3_CTL_450_DATA 0x00000000 +#define DDRSS3_CTL_451_DATA 0x00000000 +#define DDRSS3_CTL_452_DATA 0x00000000 +#define DDRSS3_CTL_453_DATA 0x00000000 +#define DDRSS3_CTL_454_DATA 0x00000000 +#define DDRSS3_CTL_455_DATA 0x00000000 +#define DDRSS3_CTL_456_DATA 0x00000000 +#define DDRSS3_CTL_457_DATA 0x00000000 +#define DDRSS3_CTL_458_DATA 0x00000000 + +#define DDRSS3_PI_00_DATA 0x00000B00 +#define DDRSS3_PI_01_DATA 0x00000000 +#define DDRSS3_PI_02_DATA 0x00000000 +#define DDRSS3_PI_03_DATA 0x00000000 +#define DDRSS3_PI_04_DATA 0x00000000 +#define DDRSS3_PI_05_DATA 0x00000101 +#define DDRSS3_PI_06_DATA 0x00640000 +#define DDRSS3_PI_07_DATA 0x00000001 +#define DDRSS3_PI_08_DATA 0x00000000 +#define DDRSS3_PI_09_DATA 0x00000000 +#define DDRSS3_PI_10_DATA 0x00000000 +#define DDRSS3_PI_11_DATA 0x00000000 +#define DDRSS3_PI_12_DATA 0x00000007 +#define DDRSS3_PI_13_DATA 0x00010002 +#define DDRSS3_PI_14_DATA 0x0800000F +#define DDRSS3_PI_15_DATA 0x00000103 +#define DDRSS3_PI_16_DATA 0x00000005 +#define DDRSS3_PI_17_DATA 0x00000000 +#define DDRSS3_PI_18_DATA 0x00000000 +#define DDRSS3_PI_19_DATA 0x00000000 +#define DDRSS3_PI_20_DATA 0x00000000 +#define DDRSS3_PI_21_DATA 0x00000000 +#define DDRSS3_PI_22_DATA 0x00000000 +#define DDRSS3_PI_23_DATA 0x00000000 +#define DDRSS3_PI_24_DATA 0x00000000 +#define DDRSS3_PI_25_DATA 0x00000000 +#define DDRSS3_PI_26_DATA 0x00010100 +#define DDRSS3_PI_27_DATA 0x00280A00 +#define DDRSS3_PI_28_DATA 0x00000000 +#define DDRSS3_PI_29_DATA 0x0F000000 +#define DDRSS3_PI_30_DATA 0x00003200 +#define DDRSS3_PI_31_DATA 0x00000000 +#define DDRSS3_PI_32_DATA 0x00000000 +#define DDRSS3_PI_33_DATA 0x01010102 +#define DDRSS3_PI_34_DATA 0x00000000 +#define DDRSS3_PI_35_DATA 0x000000AA +#define DDRSS3_PI_36_DATA 0x00000055 +#define DDRSS3_PI_37_DATA 0x000000B5 +#define DDRSS3_PI_38_DATA 0x0000004A +#define DDRSS3_PI_39_DATA 0x00000056 +#define DDRSS3_PI_40_DATA 0x000000A9 +#define DDRSS3_PI_41_DATA 0x000000A9 +#define DDRSS3_PI_42_DATA 0x000000B5 +#define DDRSS3_PI_43_DATA 0x00000000 +#define DDRSS3_PI_44_DATA 0x00000000 +#define DDRSS3_PI_45_DATA 0x000F0F00 +#define DDRSS3_PI_46_DATA 0x0000001B +#define DDRSS3_PI_47_DATA 0x000007D0 +#define DDRSS3_PI_48_DATA 0x00000300 +#define DDRSS3_PI_49_DATA 0x00000000 +#define DDRSS3_PI_50_DATA 0x00000000 +#define DDRSS3_PI_51_DATA 0x01000000 +#define DDRSS3_PI_52_DATA 0x00010101 +#define DDRSS3_PI_53_DATA 0x00000000 +#define DDRSS3_PI_54_DATA 0x00030000 +#define DDRSS3_PI_55_DATA 0x0F000000 +#define DDRSS3_PI_56_DATA 0x00000017 +#define DDRSS3_PI_57_DATA 0x00000000 +#define DDRSS3_PI_58_DATA 0x00000000 +#define DDRSS3_PI_59_DATA 0x00000000 +#define DDRSS3_PI_60_DATA 0x0A0A140A +#define DDRSS3_PI_61_DATA 0x10020101 +#define DDRSS3_PI_62_DATA 0x00020805 +#define DDRSS3_PI_63_DATA 0x01000404 +#define DDRSS3_PI_64_DATA 0x00000000 +#define DDRSS3_PI_65_DATA 0x00000000 +#define DDRSS3_PI_66_DATA 0x00000100 +#define DDRSS3_PI_67_DATA 0x0001010F +#define DDRSS3_PI_68_DATA 0x00340000 +#define DDRSS3_PI_69_DATA 0x00000000 +#define DDRSS3_PI_70_DATA 0x00000000 +#define DDRSS3_PI_71_DATA 0x0000FFFF +#define DDRSS3_PI_72_DATA 0x00000000 +#define DDRSS3_PI_73_DATA 0x00080000 +#define DDRSS3_PI_74_DATA 0x02000200 +#define DDRSS3_PI_75_DATA 0x01000100 +#define DDRSS3_PI_76_DATA 0x01000000 +#define DDRSS3_PI_77_DATA 0x02000200 +#define DDRSS3_PI_78_DATA 0x00000200 +#define DDRSS3_PI_79_DATA 0x00000000 +#define DDRSS3_PI_80_DATA 0x00000000 +#define DDRSS3_PI_81_DATA 0x00000000 +#define DDRSS3_PI_82_DATA 0x00000000 +#define DDRSS3_PI_83_DATA 0x00000000 +#define DDRSS3_PI_84_DATA 0x00000000 +#define DDRSS3_PI_85_DATA 0x00000000 +#define DDRSS3_PI_86_DATA 0x00000000 +#define DDRSS3_PI_87_DATA 0x00000000 +#define DDRSS3_PI_88_DATA 0x00000000 +#define DDRSS3_PI_89_DATA 0x00000000 +#define DDRSS3_PI_90_DATA 0x00000000 +#define DDRSS3_PI_91_DATA 0x00000400 +#define DDRSS3_PI_92_DATA 0x02010000 +#define DDRSS3_PI_93_DATA 0x00080003 +#define DDRSS3_PI_94_DATA 0x00080000 +#define DDRSS3_PI_95_DATA 0x00000001 +#define DDRSS3_PI_96_DATA 0x00000000 +#define DDRSS3_PI_97_DATA 0x0000AA00 +#define DDRSS3_PI_98_DATA 0x00000000 +#define DDRSS3_PI_99_DATA 0x00000000 +#define DDRSS3_PI_100_DATA 0x00010000 +#define DDRSS3_PI_101_DATA 0x00000000 +#define DDRSS3_PI_102_DATA 0x00000000 +#define DDRSS3_PI_103_DATA 0x00000000 +#define DDRSS3_PI_104_DATA 0x00000000 +#define DDRSS3_PI_105_DATA 0x00000000 +#define DDRSS3_PI_106_DATA 0x00000000 +#define DDRSS3_PI_107_DATA 0x00000000 +#define DDRSS3_PI_108_DATA 0x00000000 +#define DDRSS3_PI_109_DATA 0x00000000 +#define DDRSS3_PI_110_DATA 0x00000000 +#define DDRSS3_PI_111_DATA 0x00000000 +#define DDRSS3_PI_112_DATA 0x00000000 +#define DDRSS3_PI_113_DATA 0x00000000 +#define DDRSS3_PI_114_DATA 0x00000000 +#define DDRSS3_PI_115_DATA 0x00000000 +#define DDRSS3_PI_116_DATA 0x00000000 +#define DDRSS3_PI_117_DATA 0x00000000 +#define DDRSS3_PI_118_DATA 0x00000000 +#define DDRSS3_PI_119_DATA 0x00000000 +#define DDRSS3_PI_120_DATA 0x00000000 +#define DDRSS3_PI_121_DATA 0x00000000 +#define DDRSS3_PI_122_DATA 0x00000000 +#define DDRSS3_PI_123_DATA 0x00000000 +#define DDRSS3_PI_124_DATA 0x00000000 +#define DDRSS3_PI_125_DATA 0x00000008 +#define DDRSS3_PI_126_DATA 0x00000000 +#define DDRSS3_PI_127_DATA 0x00000000 +#define DDRSS3_PI_128_DATA 0x00000000 +#define DDRSS3_PI_129_DATA 0x00000000 +#define DDRSS3_PI_130_DATA 0x00000000 +#define DDRSS3_PI_131_DATA 0x00000000 +#define DDRSS3_PI_132_DATA 0x00000000 +#define DDRSS3_PI_133_DATA 0x00000000 +#define DDRSS3_PI_134_DATA 0x00000002 +#define DDRSS3_PI_135_DATA 0x00000000 +#define DDRSS3_PI_136_DATA 0x00000000 +#define DDRSS3_PI_137_DATA 0x0000000A +#define DDRSS3_PI_138_DATA 0x00000019 +#define DDRSS3_PI_139_DATA 0x00000100 +#define DDRSS3_PI_140_DATA 0x00000000 +#define DDRSS3_PI_141_DATA 0x00000000 +#define DDRSS3_PI_142_DATA 0x00000000 +#define DDRSS3_PI_143_DATA 0x00000000 +#define DDRSS3_PI_144_DATA 0x01000000 +#define DDRSS3_PI_145_DATA 0x00010003 +#define DDRSS3_PI_146_DATA 0x02000101 +#define DDRSS3_PI_147_DATA 0x01030001 +#define DDRSS3_PI_148_DATA 0x00010400 +#define DDRSS3_PI_149_DATA 0x06000105 +#define DDRSS3_PI_150_DATA 0x01070001 +#define DDRSS3_PI_151_DATA 0x00000000 +#define DDRSS3_PI_152_DATA 0x00000000 +#define DDRSS3_PI_153_DATA 0x00000000 +#define DDRSS3_PI_154_DATA 0x00010001 +#define DDRSS3_PI_155_DATA 0x00000000 +#define DDRSS3_PI_156_DATA 0x00000000 +#define DDRSS3_PI_157_DATA 0x00000000 +#define DDRSS3_PI_158_DATA 0x00000000 +#define DDRSS3_PI_159_DATA 0x00000401 +#define DDRSS3_PI_160_DATA 0x00000000 +#define DDRSS3_PI_161_DATA 0x00010000 +#define DDRSS3_PI_162_DATA 0x00000000 +#define DDRSS3_PI_163_DATA 0x2B2B0200 +#define DDRSS3_PI_164_DATA 0x00000034 +#define DDRSS3_PI_165_DATA 0x00000064 +#define DDRSS3_PI_166_DATA 0x00020064 +#define DDRSS3_PI_167_DATA 0x02000200 +#define DDRSS3_PI_168_DATA 0x48120C04 +#define DDRSS3_PI_169_DATA 0x00154812 +#define DDRSS3_PI_170_DATA 0x00000063 +#define DDRSS3_PI_171_DATA 0x0000032B +#define DDRSS3_PI_172_DATA 0x00001035 +#define DDRSS3_PI_173_DATA 0x0000032B +#define DDRSS3_PI_174_DATA 0x04001035 +#define DDRSS3_PI_175_DATA 0x01010404 +#define DDRSS3_PI_176_DATA 0x00001501 +#define DDRSS3_PI_177_DATA 0x00150015 +#define DDRSS3_PI_178_DATA 0x01000100 +#define DDRSS3_PI_179_DATA 0x00000100 +#define DDRSS3_PI_180_DATA 0x00000000 +#define DDRSS3_PI_181_DATA 0x01010101 +#define DDRSS3_PI_182_DATA 0x00000101 +#define DDRSS3_PI_183_DATA 0x00000000 +#define DDRSS3_PI_184_DATA 0x00000000 +#define DDRSS3_PI_185_DATA 0x15040000 +#define DDRSS3_PI_186_DATA 0x0E0E0215 +#define DDRSS3_PI_187_DATA 0x00040402 +#define DDRSS3_PI_188_DATA 0x000D0035 +#define DDRSS3_PI_189_DATA 0x00218049 +#define DDRSS3_PI_190_DATA 0x00218049 +#define DDRSS3_PI_191_DATA 0x01010101 +#define DDRSS3_PI_192_DATA 0x0004000E +#define DDRSS3_PI_193_DATA 0x00040216 +#define DDRSS3_PI_194_DATA 0x01000216 +#define DDRSS3_PI_195_DATA 0x000F000F +#define DDRSS3_PI_196_DATA 0x02170100 +#define DDRSS3_PI_197_DATA 0x01000217 +#define DDRSS3_PI_198_DATA 0x02170217 +#define DDRSS3_PI_199_DATA 0x32103200 +#define DDRSS3_PI_200_DATA 0x01013210 +#define DDRSS3_PI_201_DATA 0x0A070601 +#define DDRSS3_PI_202_DATA 0x1F130A0D +#define DDRSS3_PI_203_DATA 0x1F130A14 +#define DDRSS3_PI_204_DATA 0x0000C014 +#define DDRSS3_PI_205_DATA 0x00C01000 +#define DDRSS3_PI_206_DATA 0x00C01000 +#define DDRSS3_PI_207_DATA 0x00021000 +#define DDRSS3_PI_208_DATA 0x0024000E +#define DDRSS3_PI_209_DATA 0x00240216 +#define DDRSS3_PI_210_DATA 0x00110216 +#define DDRSS3_PI_211_DATA 0x32000056 +#define DDRSS3_PI_212_DATA 0x00000301 +#define DDRSS3_PI_213_DATA 0x005B0036 +#define DDRSS3_PI_214_DATA 0x03013212 +#define DDRSS3_PI_215_DATA 0x00003600 +#define DDRSS3_PI_216_DATA 0x3212005B +#define DDRSS3_PI_217_DATA 0x09000301 +#define DDRSS3_PI_218_DATA 0x04010504 +#define DDRSS3_PI_219_DATA 0x04000364 +#define DDRSS3_PI_220_DATA 0x0A032001 +#define DDRSS3_PI_221_DATA 0x2C31110A +#define DDRSS3_PI_222_DATA 0x00002918 +#define DDRSS3_PI_223_DATA 0x6000838E +#define DDRSS3_PI_224_DATA 0x1E202008 +#define DDRSS3_PI_225_DATA 0x2C311116 +#define DDRSS3_PI_226_DATA 0x00002918 +#define DDRSS3_PI_227_DATA 0x6000838E +#define DDRSS3_PI_228_DATA 0x1E202008 +#define DDRSS3_PI_229_DATA 0x0000C616 +#define DDRSS3_PI_230_DATA 0x000007BC +#define DDRSS3_PI_231_DATA 0x0000206A +#define DDRSS3_PI_232_DATA 0x00014424 +#define DDRSS3_PI_233_DATA 0x0000206A +#define DDRSS3_PI_234_DATA 0x00014424 +#define DDRSS3_PI_235_DATA 0x033B0016 +#define DDRSS3_PI_236_DATA 0x0303033B +#define DDRSS3_PI_237_DATA 0x002AF803 +#define DDRSS3_PI_238_DATA 0x0001ADAF +#define DDRSS3_PI_239_DATA 0x00000005 +#define DDRSS3_PI_240_DATA 0x0000006E +#define DDRSS3_PI_241_DATA 0x00000016 +#define DDRSS3_PI_242_DATA 0x000681C8 +#define DDRSS3_PI_243_DATA 0x0001ADAF +#define DDRSS3_PI_244_DATA 0x00000005 +#define DDRSS3_PI_245_DATA 0x000010A9 +#define DDRSS3_PI_246_DATA 0x0000033B +#define DDRSS3_PI_247_DATA 0x000681C8 +#define DDRSS3_PI_248_DATA 0x0001ADAF +#define DDRSS3_PI_249_DATA 0x00000005 +#define DDRSS3_PI_250_DATA 0x000010A9 +#define DDRSS3_PI_251_DATA 0x0100033B +#define DDRSS3_PI_252_DATA 0x00370040 +#define DDRSS3_PI_253_DATA 0x00010008 +#define DDRSS3_PI_254_DATA 0x08550040 +#define DDRSS3_PI_255_DATA 0x00010040 +#define DDRSS3_PI_256_DATA 0x08550040 +#define DDRSS3_PI_257_DATA 0x00000340 +#define DDRSS3_PI_258_DATA 0x006B006B +#define DDRSS3_PI_259_DATA 0x08040404 +#define DDRSS3_PI_260_DATA 0x00000055 +#define DDRSS3_PI_261_DATA 0x55083C5A +#define DDRSS3_PI_262_DATA 0x5A000000 +#define DDRSS3_PI_263_DATA 0x0055083C +#define DDRSS3_PI_264_DATA 0x3C5A0000 +#define DDRSS3_PI_265_DATA 0x00005508 +#define DDRSS3_PI_266_DATA 0x0C3C5A00 +#define DDRSS3_PI_267_DATA 0x080F0E0D +#define DDRSS3_PI_268_DATA 0x000B0A09 +#define DDRSS3_PI_269_DATA 0x00030201 +#define DDRSS3_PI_270_DATA 0x01000000 +#define DDRSS3_PI_271_DATA 0x04020201 +#define DDRSS3_PI_272_DATA 0x00080804 +#define DDRSS3_PI_273_DATA 0x00000000 +#define DDRSS3_PI_274_DATA 0x00000000 +#define DDRSS3_PI_275_DATA 0x00330084 +#define DDRSS3_PI_276_DATA 0x00160000 +#define DDRSS3_PI_277_DATA 0x35333FF4 +#define DDRSS3_PI_278_DATA 0x00160F27 +#define DDRSS3_PI_279_DATA 0x35333FF4 +#define DDRSS3_PI_280_DATA 0x00160F27 +#define DDRSS3_PI_281_DATA 0x00330084 +#define DDRSS3_PI_282_DATA 0x00160000 +#define DDRSS3_PI_283_DATA 0x35333FF4 +#define DDRSS3_PI_284_DATA 0x00160F27 +#define DDRSS3_PI_285_DATA 0x35333FF4 +#define DDRSS3_PI_286_DATA 0x00160F27 +#define DDRSS3_PI_287_DATA 0x00330084 +#define DDRSS3_PI_288_DATA 0x00160000 +#define DDRSS3_PI_289_DATA 0x35333FF4 +#define DDRSS3_PI_290_DATA 0x00160F27 +#define DDRSS3_PI_291_DATA 0x35333FF4 +#define DDRSS3_PI_292_DATA 0x00160F27 +#define DDRSS3_PI_293_DATA 0x00330084 +#define DDRSS3_PI_294_DATA 0x00160000 +#define DDRSS3_PI_295_DATA 0x35333FF4 +#define DDRSS3_PI_296_DATA 0x00160F27 +#define DDRSS3_PI_297_DATA 0x35333FF4 +#define DDRSS3_PI_298_DATA 0x00160F27 +#define DDRSS3_PI_299_DATA 0x00000000 + +#define DDRSS3_PHY_00_DATA 0x000004F0 +#define DDRSS3_PHY_01_DATA 0x00000000 +#define DDRSS3_PHY_02_DATA 0x00030200 +#define DDRSS3_PHY_03_DATA 0x00000000 +#define DDRSS3_PHY_04_DATA 0x00000000 +#define DDRSS3_PHY_05_DATA 0x01030000 +#define DDRSS3_PHY_06_DATA 0x00010000 +#define DDRSS3_PHY_07_DATA 0x01030004 +#define DDRSS3_PHY_08_DATA 0x01000000 +#define DDRSS3_PHY_09_DATA 0x00000000 +#define DDRSS3_PHY_10_DATA 0x00000000 +#define DDRSS3_PHY_11_DATA 0x01000001 +#define DDRSS3_PHY_12_DATA 0x00000100 +#define DDRSS3_PHY_13_DATA 0x000800C0 +#define DDRSS3_PHY_14_DATA 0x060100CC +#define DDRSS3_PHY_15_DATA 0x00030066 +#define DDRSS3_PHY_16_DATA 0x00000000 +#define DDRSS3_PHY_17_DATA 0x00000301 +#define DDRSS3_PHY_18_DATA 0x0000AAAA +#define DDRSS3_PHY_19_DATA 0x00005555 +#define DDRSS3_PHY_20_DATA 0x0000B5B5 +#define DDRSS3_PHY_21_DATA 0x00004A4A +#define DDRSS3_PHY_22_DATA 0x00005656 +#define DDRSS3_PHY_23_DATA 0x0000A9A9 +#define DDRSS3_PHY_24_DATA 0x0000A9A9 +#define DDRSS3_PHY_25_DATA 0x0000B5B5 +#define DDRSS3_PHY_26_DATA 0x00000000 +#define DDRSS3_PHY_27_DATA 0x00000000 +#define DDRSS3_PHY_28_DATA 0x2A000000 +#define DDRSS3_PHY_29_DATA 0x00000808 +#define DDRSS3_PHY_30_DATA 0x0F000000 +#define DDRSS3_PHY_31_DATA 0x00000F0F +#define DDRSS3_PHY_32_DATA 0x10400000 +#define DDRSS3_PHY_33_DATA 0x0C002006 +#define DDRSS3_PHY_34_DATA 0x00000000 +#define DDRSS3_PHY_35_DATA 0x00000000 +#define DDRSS3_PHY_36_DATA 0x55555555 +#define DDRSS3_PHY_37_DATA 0xAAAAAAAA +#define DDRSS3_PHY_38_DATA 0x55555555 +#define DDRSS3_PHY_39_DATA 0xAAAAAAAA +#define DDRSS3_PHY_40_DATA 0x00005555 +#define DDRSS3_PHY_41_DATA 0x01000100 +#define DDRSS3_PHY_42_DATA 0x00800180 +#define DDRSS3_PHY_43_DATA 0x00000001 +#define DDRSS3_PHY_44_DATA 0x00000000 +#define DDRSS3_PHY_45_DATA 0x00000000 +#define DDRSS3_PHY_46_DATA 0x00000000 +#define DDRSS3_PHY_47_DATA 0x00000000 +#define DDRSS3_PHY_48_DATA 0x00000000 +#define DDRSS3_PHY_49_DATA 0x00000000 +#define DDRSS3_PHY_50_DATA 0x00000000 +#define DDRSS3_PHY_51_DATA 0x00000000 +#define DDRSS3_PHY_52_DATA 0x00000000 +#define DDRSS3_PHY_53_DATA 0x00000000 +#define DDRSS3_PHY_54_DATA 0x00000000 +#define DDRSS3_PHY_55_DATA 0x00000000 +#define DDRSS3_PHY_56_DATA 0x00000000 +#define DDRSS3_PHY_57_DATA 0x00000000 +#define DDRSS3_PHY_58_DATA 0x00000000 +#define DDRSS3_PHY_59_DATA 0x00000000 +#define DDRSS3_PHY_60_DATA 0x00000000 +#define DDRSS3_PHY_61_DATA 0x00000000 +#define DDRSS3_PHY_62_DATA 0x00000000 +#define DDRSS3_PHY_63_DATA 0x00000000 +#define DDRSS3_PHY_64_DATA 0x00000000 +#define DDRSS3_PHY_65_DATA 0x00000000 +#define DDRSS3_PHY_66_DATA 0x00000104 +#define DDRSS3_PHY_67_DATA 0x00000120 +#define DDRSS3_PHY_68_DATA 0x00000000 +#define DDRSS3_PHY_69_DATA 0x00000000 +#define DDRSS3_PHY_70_DATA 0x00000000 +#define DDRSS3_PHY_71_DATA 0x00000000 +#define DDRSS3_PHY_72_DATA 0x00000000 +#define DDRSS3_PHY_73_DATA 0x00000000 +#define DDRSS3_PHY_74_DATA 0x00000000 +#define DDRSS3_PHY_75_DATA 0x00000001 +#define DDRSS3_PHY_76_DATA 0x07FF0000 +#define DDRSS3_PHY_77_DATA 0x0080081F +#define DDRSS3_PHY_78_DATA 0x00081020 +#define DDRSS3_PHY_79_DATA 0x04010000 +#define DDRSS3_PHY_80_DATA 0x00000000 +#define DDRSS3_PHY_81_DATA 0x00000000 +#define DDRSS3_PHY_82_DATA 0x00000000 +#define DDRSS3_PHY_83_DATA 0x00000100 +#define DDRSS3_PHY_84_DATA 0x01CC0C01 +#define DDRSS3_PHY_85_DATA 0x1003CC0C +#define DDRSS3_PHY_86_DATA 0x20000140 +#define DDRSS3_PHY_87_DATA 0x07FF0200 +#define DDRSS3_PHY_88_DATA 0x0000DD01 +#define DDRSS3_PHY_89_DATA 0x10100303 +#define DDRSS3_PHY_90_DATA 0x10101010 +#define DDRSS3_PHY_91_DATA 0x10101010 +#define DDRSS3_PHY_92_DATA 0x00021010 +#define DDRSS3_PHY_93_DATA 0x00100010 +#define DDRSS3_PHY_94_DATA 0x00100010 +#define DDRSS3_PHY_95_DATA 0x00100010 +#define DDRSS3_PHY_96_DATA 0x00100010 +#define DDRSS3_PHY_97_DATA 0x00050010 +#define DDRSS3_PHY_98_DATA 0x51517041 +#define DDRSS3_PHY_99_DATA 0x31C06001 +#define DDRSS3_PHY_100_DATA 0x07AB0340 +#define DDRSS3_PHY_101_DATA 0x00C0C001 +#define DDRSS3_PHY_102_DATA 0x0E0D0001 +#define DDRSS3_PHY_103_DATA 0x10001000 +#define DDRSS3_PHY_104_DATA 0x0C083E42 +#define DDRSS3_PHY_105_DATA 0x0F0C3701 +#define DDRSS3_PHY_106_DATA 0x01000140 +#define DDRSS3_PHY_107_DATA 0x0C000420 +#define DDRSS3_PHY_108_DATA 0x00000198 +#define DDRSS3_PHY_109_DATA 0x0A0000D0 +#define DDRSS3_PHY_110_DATA 0x00030200 +#define DDRSS3_PHY_111_DATA 0x02800000 +#define DDRSS3_PHY_112_DATA 0x80800000 +#define DDRSS3_PHY_113_DATA 0x000E2010 +#define DDRSS3_PHY_114_DATA 0x76543210 +#define DDRSS3_PHY_115_DATA 0x00000008 +#define DDRSS3_PHY_116_DATA 0x02800280 +#define DDRSS3_PHY_117_DATA 0x02800280 +#define DDRSS3_PHY_118_DATA 0x02800280 +#define DDRSS3_PHY_119_DATA 0x02800280 +#define DDRSS3_PHY_120_DATA 0x00000280 +#define DDRSS3_PHY_121_DATA 0x0000A000 +#define DDRSS3_PHY_122_DATA 0x00A000A0 +#define DDRSS3_PHY_123_DATA 0x00A000A0 +#define DDRSS3_PHY_124_DATA 0x00A000A0 +#define DDRSS3_PHY_125_DATA 0x00A000A0 +#define DDRSS3_PHY_126_DATA 0x00A000A0 +#define DDRSS3_PHY_127_DATA 0x00A000A0 +#define DDRSS3_PHY_128_DATA 0x00A000A0 +#define DDRSS3_PHY_129_DATA 0x00A000A0 +#define DDRSS3_PHY_130_DATA 0x01C200A0 +#define DDRSS3_PHY_131_DATA 0x01A00005 +#define DDRSS3_PHY_132_DATA 0x00000000 +#define DDRSS3_PHY_133_DATA 0x00000000 +#define DDRSS3_PHY_134_DATA 0x00080200 +#define DDRSS3_PHY_135_DATA 0x00000000 +#define DDRSS3_PHY_136_DATA 0x20202000 +#define DDRSS3_PHY_137_DATA 0x20202020 +#define DDRSS3_PHY_138_DATA 0xF0F02020 +#define DDRSS3_PHY_139_DATA 0x00000000 +#define DDRSS3_PHY_140_DATA 0x00000000 +#define DDRSS3_PHY_141_DATA 0x00000000 +#define DDRSS3_PHY_142_DATA 0x00000000 +#define DDRSS3_PHY_143_DATA 0x00000000 +#define DDRSS3_PHY_144_DATA 0x00000000 +#define DDRSS3_PHY_145_DATA 0x00000000 +#define DDRSS3_PHY_146_DATA 0x00000000 +#define DDRSS3_PHY_147_DATA 0x00000000 +#define DDRSS3_PHY_148_DATA 0x00000000 +#define DDRSS3_PHY_149_DATA 0x00000000 +#define DDRSS3_PHY_150_DATA 0x00000000 +#define DDRSS3_PHY_151_DATA 0x00000000 +#define DDRSS3_PHY_152_DATA 0x00000000 +#define DDRSS3_PHY_153_DATA 0x00000000 +#define DDRSS3_PHY_154_DATA 0x00000000 +#define DDRSS3_PHY_155_DATA 0x00000000 +#define DDRSS3_PHY_156_DATA 0x00000000 +#define DDRSS3_PHY_157_DATA 0x00000000 +#define DDRSS3_PHY_158_DATA 0x00000000 +#define DDRSS3_PHY_159_DATA 0x00000000 +#define DDRSS3_PHY_160_DATA 0x00000000 +#define DDRSS3_PHY_161_DATA 0x00000000 +#define DDRSS3_PHY_162_DATA 0x00000000 +#define DDRSS3_PHY_163_DATA 0x00000000 +#define DDRSS3_PHY_164_DATA 0x00000000 +#define DDRSS3_PHY_165_DATA 0x00000000 +#define DDRSS3_PHY_166_DATA 0x00000000 +#define DDRSS3_PHY_167_DATA 0x00000000 +#define DDRSS3_PHY_168_DATA 0x00000000 +#define DDRSS3_PHY_169_DATA 0x00000000 +#define DDRSS3_PHY_170_DATA 0x00000000 +#define DDRSS3_PHY_171_DATA 0x00000000 +#define DDRSS3_PHY_172_DATA 0x00000000 +#define DDRSS3_PHY_173_DATA 0x00000000 +#define DDRSS3_PHY_174_DATA 0x00000000 +#define DDRSS3_PHY_175_DATA 0x00000000 +#define DDRSS3_PHY_176_DATA 0x00000000 +#define DDRSS3_PHY_177_DATA 0x00000000 +#define DDRSS3_PHY_178_DATA 0x00000000 +#define DDRSS3_PHY_179_DATA 0x00000000 +#define DDRSS3_PHY_180_DATA 0x00000000 +#define DDRSS3_PHY_181_DATA 0x00000000 +#define DDRSS3_PHY_182_DATA 0x00000000 +#define DDRSS3_PHY_183_DATA 0x00000000 +#define DDRSS3_PHY_184_DATA 0x00000000 +#define DDRSS3_PHY_185_DATA 0x00000000 +#define DDRSS3_PHY_186_DATA 0x00000000 +#define DDRSS3_PHY_187_DATA 0x00000000 +#define DDRSS3_PHY_188_DATA 0x00000000 +#define DDRSS3_PHY_189_DATA 0x00000000 +#define DDRSS3_PHY_190_DATA 0x00000000 +#define DDRSS3_PHY_191_DATA 0x00000000 +#define DDRSS3_PHY_192_DATA 0x00000000 +#define DDRSS3_PHY_193_DATA 0x00000000 +#define DDRSS3_PHY_194_DATA 0x00000000 +#define DDRSS3_PHY_195_DATA 0x00000000 +#define DDRSS3_PHY_196_DATA 0x00000000 +#define DDRSS3_PHY_197_DATA 0x00000000 +#define DDRSS3_PHY_198_DATA 0x00000000 +#define DDRSS3_PHY_199_DATA 0x00000000 +#define DDRSS3_PHY_200_DATA 0x00000000 +#define DDRSS3_PHY_201_DATA 0x00000000 +#define DDRSS3_PHY_202_DATA 0x00000000 +#define DDRSS3_PHY_203_DATA 0x00000000 +#define DDRSS3_PHY_204_DATA 0x00000000 +#define DDRSS3_PHY_205_DATA 0x00000000 +#define DDRSS3_PHY_206_DATA 0x00000000 +#define DDRSS3_PHY_207_DATA 0x00000000 +#define DDRSS3_PHY_208_DATA 0x00000000 +#define DDRSS3_PHY_209_DATA 0x00000000 +#define DDRSS3_PHY_210_DATA 0x00000000 +#define DDRSS3_PHY_211_DATA 0x00000000 +#define DDRSS3_PHY_212_DATA 0x00000000 +#define DDRSS3_PHY_213_DATA 0x00000000 +#define DDRSS3_PHY_214_DATA 0x00000000 +#define DDRSS3_PHY_215_DATA 0x00000000 +#define DDRSS3_PHY_216_DATA 0x00000000 +#define DDRSS3_PHY_217_DATA 0x00000000 +#define DDRSS3_PHY_218_DATA 0x00000000 +#define DDRSS3_PHY_219_DATA 0x00000000 +#define DDRSS3_PHY_220_DATA 0x00000000 +#define DDRSS3_PHY_221_DATA 0x00000000 +#define DDRSS3_PHY_222_DATA 0x00000000 +#define DDRSS3_PHY_223_DATA 0x00000000 +#define DDRSS3_PHY_224_DATA 0x00000000 +#define DDRSS3_PHY_225_DATA 0x00000000 +#define DDRSS3_PHY_226_DATA 0x00000000 +#define DDRSS3_PHY_227_DATA 0x00000000 +#define DDRSS3_PHY_228_DATA 0x00000000 +#define DDRSS3_PHY_229_DATA 0x00000000 +#define DDRSS3_PHY_230_DATA 0x00000000 +#define DDRSS3_PHY_231_DATA 0x00000000 +#define DDRSS3_PHY_232_DATA 0x00000000 +#define DDRSS3_PHY_233_DATA 0x00000000 +#define DDRSS3_PHY_234_DATA 0x00000000 +#define DDRSS3_PHY_235_DATA 0x00000000 +#define DDRSS3_PHY_236_DATA 0x00000000 +#define DDRSS3_PHY_237_DATA 0x00000000 +#define DDRSS3_PHY_238_DATA 0x00000000 +#define DDRSS3_PHY_239_DATA 0x00000000 +#define DDRSS3_PHY_240_DATA 0x00000000 +#define DDRSS3_PHY_241_DATA 0x00000000 +#define DDRSS3_PHY_242_DATA 0x00000000 +#define DDRSS3_PHY_243_DATA 0x00000000 +#define DDRSS3_PHY_244_DATA 0x00000000 +#define DDRSS3_PHY_245_DATA 0x00000000 +#define DDRSS3_PHY_246_DATA 0x00000000 +#define DDRSS3_PHY_247_DATA 0x00000000 +#define DDRSS3_PHY_248_DATA 0x00000000 +#define DDRSS3_PHY_249_DATA 0x00000000 +#define DDRSS3_PHY_250_DATA 0x00000000 +#define DDRSS3_PHY_251_DATA 0x00000000 +#define DDRSS3_PHY_252_DATA 0x00000000 +#define DDRSS3_PHY_253_DATA 0x00000000 +#define DDRSS3_PHY_254_DATA 0x00000000 +#define DDRSS3_PHY_255_DATA 0x00000000 +#define DDRSS3_PHY_256_DATA 0x000004F0 +#define DDRSS3_PHY_257_DATA 0x00000000 +#define DDRSS3_PHY_258_DATA 0x00030200 +#define DDRSS3_PHY_259_DATA 0x00000000 +#define DDRSS3_PHY_260_DATA 0x00000000 +#define DDRSS3_PHY_261_DATA 0x01030000 +#define DDRSS3_PHY_262_DATA 0x00010000 +#define DDRSS3_PHY_263_DATA 0x01030004 +#define DDRSS3_PHY_264_DATA 0x01000000 +#define DDRSS3_PHY_265_DATA 0x00000000 +#define DDRSS3_PHY_266_DATA 0x00000000 +#define DDRSS3_PHY_267_DATA 0x01000001 +#define DDRSS3_PHY_268_DATA 0x00000100 +#define DDRSS3_PHY_269_DATA 0x000800C0 +#define DDRSS3_PHY_270_DATA 0x060100CC +#define DDRSS3_PHY_271_DATA 0x00030066 +#define DDRSS3_PHY_272_DATA 0x00000000 +#define DDRSS3_PHY_273_DATA 0x00000301 +#define DDRSS3_PHY_274_DATA 0x0000AAAA +#define DDRSS3_PHY_275_DATA 0x00005555 +#define DDRSS3_PHY_276_DATA 0x0000B5B5 +#define DDRSS3_PHY_277_DATA 0x00004A4A +#define DDRSS3_PHY_278_DATA 0x00005656 +#define DDRSS3_PHY_279_DATA 0x0000A9A9 +#define DDRSS3_PHY_280_DATA 0x0000A9A9 +#define DDRSS3_PHY_281_DATA 0x0000B5B5 +#define DDRSS3_PHY_282_DATA 0x00000000 +#define DDRSS3_PHY_283_DATA 0x00000000 +#define DDRSS3_PHY_284_DATA 0x2A000000 +#define DDRSS3_PHY_285_DATA 0x00000808 +#define DDRSS3_PHY_286_DATA 0x0F000000 +#define DDRSS3_PHY_287_DATA 0x00000F0F +#define DDRSS3_PHY_288_DATA 0x10400000 +#define DDRSS3_PHY_289_DATA 0x0C002006 +#define DDRSS3_PHY_290_DATA 0x00000000 +#define DDRSS3_PHY_291_DATA 0x00000000 +#define DDRSS3_PHY_292_DATA 0x55555555 +#define DDRSS3_PHY_293_DATA 0xAAAAAAAA +#define DDRSS3_PHY_294_DATA 0x55555555 +#define DDRSS3_PHY_295_DATA 0xAAAAAAAA +#define DDRSS3_PHY_296_DATA 0x00005555 +#define DDRSS3_PHY_297_DATA 0x01000100 +#define DDRSS3_PHY_298_DATA 0x00800180 +#define DDRSS3_PHY_299_DATA 0x00000000 +#define DDRSS3_PHY_300_DATA 0x00000000 +#define DDRSS3_PHY_301_DATA 0x00000000 +#define DDRSS3_PHY_302_DATA 0x00000000 +#define DDRSS3_PHY_303_DATA 0x00000000 +#define DDRSS3_PHY_304_DATA 0x00000000 +#define DDRSS3_PHY_305_DATA 0x00000000 +#define DDRSS3_PHY_306_DATA 0x00000000 +#define DDRSS3_PHY_307_DATA 0x00000000 +#define DDRSS3_PHY_308_DATA 0x00000000 +#define DDRSS3_PHY_309_DATA 0x00000000 +#define DDRSS3_PHY_310_DATA 0x00000000 +#define DDRSS3_PHY_311_DATA 0x00000000 +#define DDRSS3_PHY_312_DATA 0x00000000 +#define DDRSS3_PHY_313_DATA 0x00000000 +#define DDRSS3_PHY_314_DATA 0x00000000 +#define DDRSS3_PHY_315_DATA 0x00000000 +#define DDRSS3_PHY_316_DATA 0x00000000 +#define DDRSS3_PHY_317_DATA 0x00000000 +#define DDRSS3_PHY_318_DATA 0x00000000 +#define DDRSS3_PHY_319_DATA 0x00000000 +#define DDRSS3_PHY_320_DATA 0x00000000 +#define DDRSS3_PHY_321_DATA 0x00000000 +#define DDRSS3_PHY_322_DATA 0x00000104 +#define DDRSS3_PHY_323_DATA 0x00000120 +#define DDRSS3_PHY_324_DATA 0x00000000 +#define DDRSS3_PHY_325_DATA 0x00000000 +#define DDRSS3_PHY_326_DATA 0x00000000 +#define DDRSS3_PHY_327_DATA 0x00000000 +#define DDRSS3_PHY_328_DATA 0x00000000 +#define DDRSS3_PHY_329_DATA 0x00000000 +#define DDRSS3_PHY_330_DATA 0x00000000 +#define DDRSS3_PHY_331_DATA 0x00000001 +#define DDRSS3_PHY_332_DATA 0x07FF0000 +#define DDRSS3_PHY_333_DATA 0x0080081F +#define DDRSS3_PHY_334_DATA 0x00081020 +#define DDRSS3_PHY_335_DATA 0x04010000 +#define DDRSS3_PHY_336_DATA 0x00000000 +#define DDRSS3_PHY_337_DATA 0x00000000 +#define DDRSS3_PHY_338_DATA 0x00000000 +#define DDRSS3_PHY_339_DATA 0x00000100 +#define DDRSS3_PHY_340_DATA 0x01CC0C01 +#define DDRSS3_PHY_341_DATA 0x1003CC0C +#define DDRSS3_PHY_342_DATA 0x20000140 +#define DDRSS3_PHY_343_DATA 0x07FF0200 +#define DDRSS3_PHY_344_DATA 0x0000DD01 +#define DDRSS3_PHY_345_DATA 0x10100303 +#define DDRSS3_PHY_346_DATA 0x10101010 +#define DDRSS3_PHY_347_DATA 0x10101010 +#define DDRSS3_PHY_348_DATA 0x00021010 +#define DDRSS3_PHY_349_DATA 0x00100010 +#define DDRSS3_PHY_350_DATA 0x00100010 +#define DDRSS3_PHY_351_DATA 0x00100010 +#define DDRSS3_PHY_352_DATA 0x00100010 +#define DDRSS3_PHY_353_DATA 0x00050010 +#define DDRSS3_PHY_354_DATA 0x51517041 +#define DDRSS3_PHY_355_DATA 0x31C06001 +#define DDRSS3_PHY_356_DATA 0x07AB0340 +#define DDRSS3_PHY_357_DATA 0x00C0C001 +#define DDRSS3_PHY_358_DATA 0x0E0D0001 +#define DDRSS3_PHY_359_DATA 0x10001000 +#define DDRSS3_PHY_360_DATA 0x0C083E42 +#define DDRSS3_PHY_361_DATA 0x0F0C3701 +#define DDRSS3_PHY_362_DATA 0x01000140 +#define DDRSS3_PHY_363_DATA 0x0C000420 +#define DDRSS3_PHY_364_DATA 0x00000198 +#define DDRSS3_PHY_365_DATA 0x0A0000D0 +#define DDRSS3_PHY_366_DATA 0x00030200 +#define DDRSS3_PHY_367_DATA 0x02800000 +#define DDRSS3_PHY_368_DATA 0x80800000 +#define DDRSS3_PHY_369_DATA 0x000E2010 +#define DDRSS3_PHY_370_DATA 0x76543210 +#define DDRSS3_PHY_371_DATA 0x00000008 +#define DDRSS3_PHY_372_DATA 0x02800280 +#define DDRSS3_PHY_373_DATA 0x02800280 +#define DDRSS3_PHY_374_DATA 0x02800280 +#define DDRSS3_PHY_375_DATA 0x02800280 +#define DDRSS3_PHY_376_DATA 0x00000280 +#define DDRSS3_PHY_377_DATA 0x0000A000 +#define DDRSS3_PHY_378_DATA 0x00A000A0 +#define DDRSS3_PHY_379_DATA 0x00A000A0 +#define DDRSS3_PHY_380_DATA 0x00A000A0 +#define DDRSS3_PHY_381_DATA 0x00A000A0 +#define DDRSS3_PHY_382_DATA 0x00A000A0 +#define DDRSS3_PHY_383_DATA 0x00A000A0 +#define DDRSS3_PHY_384_DATA 0x00A000A0 +#define DDRSS3_PHY_385_DATA 0x00A000A0 +#define DDRSS3_PHY_386_DATA 0x01C200A0 +#define DDRSS3_PHY_387_DATA 0x01A00005 +#define DDRSS3_PHY_388_DATA 0x00000000 +#define DDRSS3_PHY_389_DATA 0x00000000 +#define DDRSS3_PHY_390_DATA 0x00080200 +#define DDRSS3_PHY_391_DATA 0x00000000 +#define DDRSS3_PHY_392_DATA 0x20202000 +#define DDRSS3_PHY_393_DATA 0x20202020 +#define DDRSS3_PHY_394_DATA 0xF0F02020 +#define DDRSS3_PHY_395_DATA 0x00000000 +#define DDRSS3_PHY_396_DATA 0x00000000 +#define DDRSS3_PHY_397_DATA 0x00000000 +#define DDRSS3_PHY_398_DATA 0x00000000 +#define DDRSS3_PHY_399_DATA 0x00000000 +#define DDRSS3_PHY_400_DATA 0x00000000 +#define DDRSS3_PHY_401_DATA 0x00000000 +#define DDRSS3_PHY_402_DATA 0x00000000 +#define DDRSS3_PHY_403_DATA 0x00000000 +#define DDRSS3_PHY_404_DATA 0x00000000 +#define DDRSS3_PHY_405_DATA 0x00000000 +#define DDRSS3_PHY_406_DATA 0x00000000 +#define DDRSS3_PHY_407_DATA 0x00000000 +#define DDRSS3_PHY_408_DATA 0x00000000 +#define DDRSS3_PHY_409_DATA 0x00000000 +#define DDRSS3_PHY_410_DATA 0x00000000 +#define DDRSS3_PHY_411_DATA 0x00000000 +#define DDRSS3_PHY_412_DATA 0x00000000 +#define DDRSS3_PHY_413_DATA 0x00000000 +#define DDRSS3_PHY_414_DATA 0x00000000 +#define DDRSS3_PHY_415_DATA 0x00000000 +#define DDRSS3_PHY_416_DATA 0x00000000 +#define DDRSS3_PHY_417_DATA 0x00000000 +#define DDRSS3_PHY_418_DATA 0x00000000 +#define DDRSS3_PHY_419_DATA 0x00000000 +#define DDRSS3_PHY_420_DATA 0x00000000 +#define DDRSS3_PHY_421_DATA 0x00000000 +#define DDRSS3_PHY_422_DATA 0x00000000 +#define DDRSS3_PHY_423_DATA 0x00000000 +#define DDRSS3_PHY_424_DATA 0x00000000 +#define DDRSS3_PHY_425_DATA 0x00000000 +#define DDRSS3_PHY_426_DATA 0x00000000 +#define DDRSS3_PHY_427_DATA 0x00000000 +#define DDRSS3_PHY_428_DATA 0x00000000 +#define DDRSS3_PHY_429_DATA 0x00000000 +#define DDRSS3_PHY_430_DATA 0x00000000 +#define DDRSS3_PHY_431_DATA 0x00000000 +#define DDRSS3_PHY_432_DATA 0x00000000 +#define DDRSS3_PHY_433_DATA 0x00000000 +#define DDRSS3_PHY_434_DATA 0x00000000 +#define DDRSS3_PHY_435_DATA 0x00000000 +#define DDRSS3_PHY_436_DATA 0x00000000 +#define DDRSS3_PHY_437_DATA 0x00000000 +#define DDRSS3_PHY_438_DATA 0x00000000 +#define DDRSS3_PHY_439_DATA 0x00000000 +#define DDRSS3_PHY_440_DATA 0x00000000 +#define DDRSS3_PHY_441_DATA 0x00000000 +#define DDRSS3_PHY_442_DATA 0x00000000 +#define DDRSS3_PHY_443_DATA 0x00000000 +#define DDRSS3_PHY_444_DATA 0x00000000 +#define DDRSS3_PHY_445_DATA 0x00000000 +#define DDRSS3_PHY_446_DATA 0x00000000 +#define DDRSS3_PHY_447_DATA 0x00000000 +#define DDRSS3_PHY_448_DATA 0x00000000 +#define DDRSS3_PHY_449_DATA 0x00000000 +#define DDRSS3_PHY_450_DATA 0x00000000 +#define DDRSS3_PHY_451_DATA 0x00000000 +#define DDRSS3_PHY_452_DATA 0x00000000 +#define DDRSS3_PHY_453_DATA 0x00000000 +#define DDRSS3_PHY_454_DATA 0x00000000 +#define DDRSS3_PHY_455_DATA 0x00000000 +#define DDRSS3_PHY_456_DATA 0x00000000 +#define DDRSS3_PHY_457_DATA 0x00000000 +#define DDRSS3_PHY_458_DATA 0x00000000 +#define DDRSS3_PHY_459_DATA 0x00000000 +#define DDRSS3_PHY_460_DATA 0x00000000 +#define DDRSS3_PHY_461_DATA 0x00000000 +#define DDRSS3_PHY_462_DATA 0x00000000 +#define DDRSS3_PHY_463_DATA 0x00000000 +#define DDRSS3_PHY_464_DATA 0x00000000 +#define DDRSS3_PHY_465_DATA 0x00000000 +#define DDRSS3_PHY_466_DATA 0x00000000 +#define DDRSS3_PHY_467_DATA 0x00000000 +#define DDRSS3_PHY_468_DATA 0x00000000 +#define DDRSS3_PHY_469_DATA 0x00000000 +#define DDRSS3_PHY_470_DATA 0x00000000 +#define DDRSS3_PHY_471_DATA 0x00000000 +#define DDRSS3_PHY_472_DATA 0x00000000 +#define DDRSS3_PHY_473_DATA 0x00000000 +#define DDRSS3_PHY_474_DATA 0x00000000 +#define DDRSS3_PHY_475_DATA 0x00000000 +#define DDRSS3_PHY_476_DATA 0x00000000 +#define DDRSS3_PHY_477_DATA 0x00000000 +#define DDRSS3_PHY_478_DATA 0x00000000 +#define DDRSS3_PHY_479_DATA 0x00000000 +#define DDRSS3_PHY_480_DATA 0x00000000 +#define DDRSS3_PHY_481_DATA 0x00000000 +#define DDRSS3_PHY_482_DATA 0x00000000 +#define DDRSS3_PHY_483_DATA 0x00000000 +#define DDRSS3_PHY_484_DATA 0x00000000 +#define DDRSS3_PHY_485_DATA 0x00000000 +#define DDRSS3_PHY_486_DATA 0x00000000 +#define DDRSS3_PHY_487_DATA 0x00000000 +#define DDRSS3_PHY_488_DATA 0x00000000 +#define DDRSS3_PHY_489_DATA 0x00000000 +#define DDRSS3_PHY_490_DATA 0x00000000 +#define DDRSS3_PHY_491_DATA 0x00000000 +#define DDRSS3_PHY_492_DATA 0x00000000 +#define DDRSS3_PHY_493_DATA 0x00000000 +#define DDRSS3_PHY_494_DATA 0x00000000 +#define DDRSS3_PHY_495_DATA 0x00000000 +#define DDRSS3_PHY_496_DATA 0x00000000 +#define DDRSS3_PHY_497_DATA 0x00000000 +#define DDRSS3_PHY_498_DATA 0x00000000 +#define DDRSS3_PHY_499_DATA 0x00000000 +#define DDRSS3_PHY_500_DATA 0x00000000 +#define DDRSS3_PHY_501_DATA 0x00000000 +#define DDRSS3_PHY_502_DATA 0x00000000 +#define DDRSS3_PHY_503_DATA 0x00000000 +#define DDRSS3_PHY_504_DATA 0x00000000 +#define DDRSS3_PHY_505_DATA 0x00000000 +#define DDRSS3_PHY_506_DATA 0x00000000 +#define DDRSS3_PHY_507_DATA 0x00000000 +#define DDRSS3_PHY_508_DATA 0x00000000 +#define DDRSS3_PHY_509_DATA 0x00000000 +#define DDRSS3_PHY_510_DATA 0x00000000 +#define DDRSS3_PHY_511_DATA 0x00000000 +#define DDRSS3_PHY_512_DATA 0x000004F0 +#define DDRSS3_PHY_513_DATA 0x00000000 +#define DDRSS3_PHY_514_DATA 0x00030200 +#define DDRSS3_PHY_515_DATA 0x00000000 +#define DDRSS3_PHY_516_DATA 0x00000000 +#define DDRSS3_PHY_517_DATA 0x01030000 +#define DDRSS3_PHY_518_DATA 0x00010000 +#define DDRSS3_PHY_519_DATA 0x01030004 +#define DDRSS3_PHY_520_DATA 0x01000000 +#define DDRSS3_PHY_521_DATA 0x00000000 +#define DDRSS3_PHY_522_DATA 0x00000000 +#define DDRSS3_PHY_523_DATA 0x01000001 +#define DDRSS3_PHY_524_DATA 0x00000100 +#define DDRSS3_PHY_525_DATA 0x000800C0 +#define DDRSS3_PHY_526_DATA 0x060100CC +#define DDRSS3_PHY_527_DATA 0x00030066 +#define DDRSS3_PHY_528_DATA 0x00000000 +#define DDRSS3_PHY_529_DATA 0x00000301 +#define DDRSS3_PHY_530_DATA 0x0000AAAA +#define DDRSS3_PHY_531_DATA 0x00005555 +#define DDRSS3_PHY_532_DATA 0x0000B5B5 +#define DDRSS3_PHY_533_DATA 0x00004A4A +#define DDRSS3_PHY_534_DATA 0x00005656 +#define DDRSS3_PHY_535_DATA 0x0000A9A9 +#define DDRSS3_PHY_536_DATA 0x0000A9A9 +#define DDRSS3_PHY_537_DATA 0x0000B5B5 +#define DDRSS3_PHY_538_DATA 0x00000000 +#define DDRSS3_PHY_539_DATA 0x00000000 +#define DDRSS3_PHY_540_DATA 0x2A000000 +#define DDRSS3_PHY_541_DATA 0x00000808 +#define DDRSS3_PHY_542_DATA 0x0F000000 +#define DDRSS3_PHY_543_DATA 0x00000F0F +#define DDRSS3_PHY_544_DATA 0x10400000 +#define DDRSS3_PHY_545_DATA 0x0C002006 +#define DDRSS3_PHY_546_DATA 0x00000000 +#define DDRSS3_PHY_547_DATA 0x00000000 +#define DDRSS3_PHY_548_DATA 0x55555555 +#define DDRSS3_PHY_549_DATA 0xAAAAAAAA +#define DDRSS3_PHY_550_DATA 0x55555555 +#define DDRSS3_PHY_551_DATA 0xAAAAAAAA +#define DDRSS3_PHY_552_DATA 0x00005555 +#define DDRSS3_PHY_553_DATA 0x01000100 +#define DDRSS3_PHY_554_DATA 0x00800180 +#define DDRSS3_PHY_555_DATA 0x00000001 +#define DDRSS3_PHY_556_DATA 0x00000000 +#define DDRSS3_PHY_557_DATA 0x00000000 +#define DDRSS3_PHY_558_DATA 0x00000000 +#define DDRSS3_PHY_559_DATA 0x00000000 +#define DDRSS3_PHY_560_DATA 0x00000000 +#define DDRSS3_PHY_561_DATA 0x00000000 +#define DDRSS3_PHY_562_DATA 0x00000000 +#define DDRSS3_PHY_563_DATA 0x00000000 +#define DDRSS3_PHY_564_DATA 0x00000000 +#define DDRSS3_PHY_565_DATA 0x00000000 +#define DDRSS3_PHY_566_DATA 0x00000000 +#define DDRSS3_PHY_567_DATA 0x00000000 +#define DDRSS3_PHY_568_DATA 0x00000000 +#define DDRSS3_PHY_569_DATA 0x00000000 +#define DDRSS3_PHY_570_DATA 0x00000000 +#define DDRSS3_PHY_571_DATA 0x00000000 +#define DDRSS3_PHY_572_DATA 0x00000000 +#define DDRSS3_PHY_573_DATA 0x00000000 +#define DDRSS3_PHY_574_DATA 0x00000000 +#define DDRSS3_PHY_575_DATA 0x00000000 +#define DDRSS3_PHY_576_DATA 0x00000000 +#define DDRSS3_PHY_577_DATA 0x00000000 +#define DDRSS3_PHY_578_DATA 0x00000104 +#define DDRSS3_PHY_579_DATA 0x00000120 +#define DDRSS3_PHY_580_DATA 0x00000000 +#define DDRSS3_PHY_581_DATA 0x00000000 +#define DDRSS3_PHY_582_DATA 0x00000000 +#define DDRSS3_PHY_583_DATA 0x00000000 +#define DDRSS3_PHY_584_DATA 0x00000000 +#define DDRSS3_PHY_585_DATA 0x00000000 +#define DDRSS3_PHY_586_DATA 0x00000000 +#define DDRSS3_PHY_587_DATA 0x00000001 +#define DDRSS3_PHY_588_DATA 0x07FF0000 +#define DDRSS3_PHY_589_DATA 0x0080081F +#define DDRSS3_PHY_590_DATA 0x00081020 +#define DDRSS3_PHY_591_DATA 0x04010000 +#define DDRSS3_PHY_592_DATA 0x00000000 +#define DDRSS3_PHY_593_DATA 0x00000000 +#define DDRSS3_PHY_594_DATA 0x00000000 +#define DDRSS3_PHY_595_DATA 0x00000100 +#define DDRSS3_PHY_596_DATA 0x01CC0C01 +#define DDRSS3_PHY_597_DATA 0x1003CC0C +#define DDRSS3_PHY_598_DATA 0x20000140 +#define DDRSS3_PHY_599_DATA 0x07FF0200 +#define DDRSS3_PHY_600_DATA 0x0000DD01 +#define DDRSS3_PHY_601_DATA 0x10100303 +#define DDRSS3_PHY_602_DATA 0x10101010 +#define DDRSS3_PHY_603_DATA 0x10101010 +#define DDRSS3_PHY_604_DATA 0x00021010 +#define DDRSS3_PHY_605_DATA 0x00100010 +#define DDRSS3_PHY_606_DATA 0x00100010 +#define DDRSS3_PHY_607_DATA 0x00100010 +#define DDRSS3_PHY_608_DATA 0x00100010 +#define DDRSS3_PHY_609_DATA 0x00050010 +#define DDRSS3_PHY_610_DATA 0x51517041 +#define DDRSS3_PHY_611_DATA 0x31C06001 +#define DDRSS3_PHY_612_DATA 0x07AB0340 +#define DDRSS3_PHY_613_DATA 0x00C0C001 +#define DDRSS3_PHY_614_DATA 0x0E0D0001 +#define DDRSS3_PHY_615_DATA 0x10001000 +#define DDRSS3_PHY_616_DATA 0x0C083E42 +#define DDRSS3_PHY_617_DATA 0x0F0C3701 +#define DDRSS3_PHY_618_DATA 0x01000140 +#define DDRSS3_PHY_619_DATA 0x0C000420 +#define DDRSS3_PHY_620_DATA 0x00000198 +#define DDRSS3_PHY_621_DATA 0x0A0000D0 +#define DDRSS3_PHY_622_DATA 0x00030200 +#define DDRSS3_PHY_623_DATA 0x02800000 +#define DDRSS3_PHY_624_DATA 0x80800000 +#define DDRSS3_PHY_625_DATA 0x000E2010 +#define DDRSS3_PHY_626_DATA 0x76543210 +#define DDRSS3_PHY_627_DATA 0x00000008 +#define DDRSS3_PHY_628_DATA 0x02800280 +#define DDRSS3_PHY_629_DATA 0x02800280 +#define DDRSS3_PHY_630_DATA 0x02800280 +#define DDRSS3_PHY_631_DATA 0x02800280 +#define DDRSS3_PHY_632_DATA 0x00000280 +#define DDRSS3_PHY_633_DATA 0x0000A000 +#define DDRSS3_PHY_634_DATA 0x00A000A0 +#define DDRSS3_PHY_635_DATA 0x00A000A0 +#define DDRSS3_PHY_636_DATA 0x00A000A0 +#define DDRSS3_PHY_637_DATA 0x00A000A0 +#define DDRSS3_PHY_638_DATA 0x00A000A0 +#define DDRSS3_PHY_639_DATA 0x00A000A0 +#define DDRSS3_PHY_640_DATA 0x00A000A0 +#define DDRSS3_PHY_641_DATA 0x00A000A0 +#define DDRSS3_PHY_642_DATA 0x01C200A0 +#define DDRSS3_PHY_643_DATA 0x01A00005 +#define DDRSS3_PHY_644_DATA 0x00000000 +#define DDRSS3_PHY_645_DATA 0x00000000 +#define DDRSS3_PHY_646_DATA 0x00080200 +#define DDRSS3_PHY_647_DATA 0x00000000 +#define DDRSS3_PHY_648_DATA 0x20202000 +#define DDRSS3_PHY_649_DATA 0x20202020 +#define DDRSS3_PHY_650_DATA 0xF0F02020 +#define DDRSS3_PHY_651_DATA 0x00000000 +#define DDRSS3_PHY_652_DATA 0x00000000 +#define DDRSS3_PHY_653_DATA 0x00000000 +#define DDRSS3_PHY_654_DATA 0x00000000 +#define DDRSS3_PHY_655_DATA 0x00000000 +#define DDRSS3_PHY_656_DATA 0x00000000 +#define DDRSS3_PHY_657_DATA 0x00000000 +#define DDRSS3_PHY_658_DATA 0x00000000 +#define DDRSS3_PHY_659_DATA 0x00000000 +#define DDRSS3_PHY_660_DATA 0x00000000 +#define DDRSS3_PHY_661_DATA 0x00000000 +#define DDRSS3_PHY_662_DATA 0x00000000 +#define DDRSS3_PHY_663_DATA 0x00000000 +#define DDRSS3_PHY_664_DATA 0x00000000 +#define DDRSS3_PHY_665_DATA 0x00000000 +#define DDRSS3_PHY_666_DATA 0x00000000 +#define DDRSS3_PHY_667_DATA 0x00000000 +#define DDRSS3_PHY_668_DATA 0x00000000 +#define DDRSS3_PHY_669_DATA 0x00000000 +#define DDRSS3_PHY_670_DATA 0x00000000 +#define DDRSS3_PHY_671_DATA 0x00000000 +#define DDRSS3_PHY_672_DATA 0x00000000 +#define DDRSS3_PHY_673_DATA 0x00000000 +#define DDRSS3_PHY_674_DATA 0x00000000 +#define DDRSS3_PHY_675_DATA 0x00000000 +#define DDRSS3_PHY_676_DATA 0x00000000 +#define DDRSS3_PHY_677_DATA 0x00000000 +#define DDRSS3_PHY_678_DATA 0x00000000 +#define DDRSS3_PHY_679_DATA 0x00000000 +#define DDRSS3_PHY_680_DATA 0x00000000 +#define DDRSS3_PHY_681_DATA 0x00000000 +#define DDRSS3_PHY_682_DATA 0x00000000 +#define DDRSS3_PHY_683_DATA 0x00000000 +#define DDRSS3_PHY_684_DATA 0x00000000 +#define DDRSS3_PHY_685_DATA 0x00000000 +#define DDRSS3_PHY_686_DATA 0x00000000 +#define DDRSS3_PHY_687_DATA 0x00000000 +#define DDRSS3_PHY_688_DATA 0x00000000 +#define DDRSS3_PHY_689_DATA 0x00000000 +#define DDRSS3_PHY_690_DATA 0x00000000 +#define DDRSS3_PHY_691_DATA 0x00000000 +#define DDRSS3_PHY_692_DATA 0x00000000 +#define DDRSS3_PHY_693_DATA 0x00000000 +#define DDRSS3_PHY_694_DATA 0x00000000 +#define DDRSS3_PHY_695_DATA 0x00000000 +#define DDRSS3_PHY_696_DATA 0x00000000 +#define DDRSS3_PHY_697_DATA 0x00000000 +#define DDRSS3_PHY_698_DATA 0x00000000 +#define DDRSS3_PHY_699_DATA 0x00000000 +#define DDRSS3_PHY_700_DATA 0x00000000 +#define DDRSS3_PHY_701_DATA 0x00000000 +#define DDRSS3_PHY_702_DATA 0x00000000 +#define DDRSS3_PHY_703_DATA 0x00000000 +#define DDRSS3_PHY_704_DATA 0x00000000 +#define DDRSS3_PHY_705_DATA 0x00000000 +#define DDRSS3_PHY_706_DATA 0x00000000 +#define DDRSS3_PHY_707_DATA 0x00000000 +#define DDRSS3_PHY_708_DATA 0x00000000 +#define DDRSS3_PHY_709_DATA 0x00000000 +#define DDRSS3_PHY_710_DATA 0x00000000 +#define DDRSS3_PHY_711_DATA 0x00000000 +#define DDRSS3_PHY_712_DATA 0x00000000 +#define DDRSS3_PHY_713_DATA 0x00000000 +#define DDRSS3_PHY_714_DATA 0x00000000 +#define DDRSS3_PHY_715_DATA 0x00000000 +#define DDRSS3_PHY_716_DATA 0x00000000 +#define DDRSS3_PHY_717_DATA 0x00000000 +#define DDRSS3_PHY_718_DATA 0x00000000 +#define DDRSS3_PHY_719_DATA 0x00000000 +#define DDRSS3_PHY_720_DATA 0x00000000 +#define DDRSS3_PHY_721_DATA 0x00000000 +#define DDRSS3_PHY_722_DATA 0x00000000 +#define DDRSS3_PHY_723_DATA 0x00000000 +#define DDRSS3_PHY_724_DATA 0x00000000 +#define DDRSS3_PHY_725_DATA 0x00000000 +#define DDRSS3_PHY_726_DATA 0x00000000 +#define DDRSS3_PHY_727_DATA 0x00000000 +#define DDRSS3_PHY_728_DATA 0x00000000 +#define DDRSS3_PHY_729_DATA 0x00000000 +#define DDRSS3_PHY_730_DATA 0x00000000 +#define DDRSS3_PHY_731_DATA 0x00000000 +#define DDRSS3_PHY_732_DATA 0x00000000 +#define DDRSS3_PHY_733_DATA 0x00000000 +#define DDRSS3_PHY_734_DATA 0x00000000 +#define DDRSS3_PHY_735_DATA 0x00000000 +#define DDRSS3_PHY_736_DATA 0x00000000 +#define DDRSS3_PHY_737_DATA 0x00000000 +#define DDRSS3_PHY_738_DATA 0x00000000 +#define DDRSS3_PHY_739_DATA 0x00000000 +#define DDRSS3_PHY_740_DATA 0x00000000 +#define DDRSS3_PHY_741_DATA 0x00000000 +#define DDRSS3_PHY_742_DATA 0x00000000 +#define DDRSS3_PHY_743_DATA 0x00000000 +#define DDRSS3_PHY_744_DATA 0x00000000 +#define DDRSS3_PHY_745_DATA 0x00000000 +#define DDRSS3_PHY_746_DATA 0x00000000 +#define DDRSS3_PHY_747_DATA 0x00000000 +#define DDRSS3_PHY_748_DATA 0x00000000 +#define DDRSS3_PHY_749_DATA 0x00000000 +#define DDRSS3_PHY_750_DATA 0x00000000 +#define DDRSS3_PHY_751_DATA 0x00000000 +#define DDRSS3_PHY_752_DATA 0x00000000 +#define DDRSS3_PHY_753_DATA 0x00000000 +#define DDRSS3_PHY_754_DATA 0x00000000 +#define DDRSS3_PHY_755_DATA 0x00000000 +#define DDRSS3_PHY_756_DATA 0x00000000 +#define DDRSS3_PHY_757_DATA 0x00000000 +#define DDRSS3_PHY_758_DATA 0x00000000 +#define DDRSS3_PHY_759_DATA 0x00000000 +#define DDRSS3_PHY_760_DATA 0x00000000 +#define DDRSS3_PHY_761_DATA 0x00000000 +#define DDRSS3_PHY_762_DATA 0x00000000 +#define DDRSS3_PHY_763_DATA 0x00000000 +#define DDRSS3_PHY_764_DATA 0x00000000 +#define DDRSS3_PHY_765_DATA 0x00000000 +#define DDRSS3_PHY_766_DATA 0x00000000 +#define DDRSS3_PHY_767_DATA 0x00000000 +#define DDRSS3_PHY_768_DATA 0x000004F0 +#define DDRSS3_PHY_769_DATA 0x00000000 +#define DDRSS3_PHY_770_DATA 0x00030200 +#define DDRSS3_PHY_771_DATA 0x00000000 +#define DDRSS3_PHY_772_DATA 0x00000000 +#define DDRSS3_PHY_773_DATA 0x01030000 +#define DDRSS3_PHY_774_DATA 0x00010000 +#define DDRSS3_PHY_775_DATA 0x01030004 +#define DDRSS3_PHY_776_DATA 0x01000000 +#define DDRSS3_PHY_777_DATA 0x00000000 +#define DDRSS3_PHY_778_DATA 0x00000000 +#define DDRSS3_PHY_779_DATA 0x01000001 +#define DDRSS3_PHY_780_DATA 0x00000100 +#define DDRSS3_PHY_781_DATA 0x000800C0 +#define DDRSS3_PHY_782_DATA 0x060100CC +#define DDRSS3_PHY_783_DATA 0x00030066 +#define DDRSS3_PHY_784_DATA 0x00000000 +#define DDRSS3_PHY_785_DATA 0x00000301 +#define DDRSS3_PHY_786_DATA 0x0000AAAA +#define DDRSS3_PHY_787_DATA 0x00005555 +#define DDRSS3_PHY_788_DATA 0x0000B5B5 +#define DDRSS3_PHY_789_DATA 0x00004A4A +#define DDRSS3_PHY_790_DATA 0x00005656 +#define DDRSS3_PHY_791_DATA 0x0000A9A9 +#define DDRSS3_PHY_792_DATA 0x0000A9A9 +#define DDRSS3_PHY_793_DATA 0x0000B5B5 +#define DDRSS3_PHY_794_DATA 0x00000000 +#define DDRSS3_PHY_795_DATA 0x00000000 +#define DDRSS3_PHY_796_DATA 0x2A000000 +#define DDRSS3_PHY_797_DATA 0x00000808 +#define DDRSS3_PHY_798_DATA 0x0F000000 +#define DDRSS3_PHY_799_DATA 0x00000F0F +#define DDRSS3_PHY_800_DATA 0x10400000 +#define DDRSS3_PHY_801_DATA 0x0C002006 +#define DDRSS3_PHY_802_DATA 0x00000000 +#define DDRSS3_PHY_803_DATA 0x00000000 +#define DDRSS3_PHY_804_DATA 0x55555555 +#define DDRSS3_PHY_805_DATA 0xAAAAAAAA +#define DDRSS3_PHY_806_DATA 0x55555555 +#define DDRSS3_PHY_807_DATA 0xAAAAAAAA +#define DDRSS3_PHY_808_DATA 0x00005555 +#define DDRSS3_PHY_809_DATA 0x01000100 +#define DDRSS3_PHY_810_DATA 0x00800180 +#define DDRSS3_PHY_811_DATA 0x00000000 +#define DDRSS3_PHY_812_DATA 0x00000000 +#define DDRSS3_PHY_813_DATA 0x00000000 +#define DDRSS3_PHY_814_DATA 0x00000000 +#define DDRSS3_PHY_815_DATA 0x00000000 +#define DDRSS3_PHY_816_DATA 0x00000000 +#define DDRSS3_PHY_817_DATA 0x00000000 +#define DDRSS3_PHY_818_DATA 0x00000000 +#define DDRSS3_PHY_819_DATA 0x00000000 +#define DDRSS3_PHY_820_DATA 0x00000000 +#define DDRSS3_PHY_821_DATA 0x00000000 +#define DDRSS3_PHY_822_DATA 0x00000000 +#define DDRSS3_PHY_823_DATA 0x00000000 +#define DDRSS3_PHY_824_DATA 0x00000000 +#define DDRSS3_PHY_825_DATA 0x00000000 +#define DDRSS3_PHY_826_DATA 0x00000000 +#define DDRSS3_PHY_827_DATA 0x00000000 +#define DDRSS3_PHY_828_DATA 0x00000000 +#define DDRSS3_PHY_829_DATA 0x00000000 +#define DDRSS3_PHY_830_DATA 0x00000000 +#define DDRSS3_PHY_831_DATA 0x00000000 +#define DDRSS3_PHY_832_DATA 0x00000000 +#define DDRSS3_PHY_833_DATA 0x00000000 +#define DDRSS3_PHY_834_DATA 0x00000104 +#define DDRSS3_PHY_835_DATA 0x00000120 +#define DDRSS3_PHY_836_DATA 0x00000000 +#define DDRSS3_PHY_837_DATA 0x00000000 +#define DDRSS3_PHY_838_DATA 0x00000000 +#define DDRSS3_PHY_839_DATA 0x00000000 +#define DDRSS3_PHY_840_DATA 0x00000000 +#define DDRSS3_PHY_841_DATA 0x00000000 +#define DDRSS3_PHY_842_DATA 0x00000000 +#define DDRSS3_PHY_843_DATA 0x00000001 +#define DDRSS3_PHY_844_DATA 0x07FF0000 +#define DDRSS3_PHY_845_DATA 0x0080081F +#define DDRSS3_PHY_846_DATA 0x00081020 +#define DDRSS3_PHY_847_DATA 0x04010000 +#define DDRSS3_PHY_848_DATA 0x00000000 +#define DDRSS3_PHY_849_DATA 0x00000000 +#define DDRSS3_PHY_850_DATA 0x00000000 +#define DDRSS3_PHY_851_DATA 0x00000100 +#define DDRSS3_PHY_852_DATA 0x01CC0C01 +#define DDRSS3_PHY_853_DATA 0x1003CC0C +#define DDRSS3_PHY_854_DATA 0x20000140 +#define DDRSS3_PHY_855_DATA 0x07FF0200 +#define DDRSS3_PHY_856_DATA 0x0000DD01 +#define DDRSS3_PHY_857_DATA 0x10100303 +#define DDRSS3_PHY_858_DATA 0x10101010 +#define DDRSS3_PHY_859_DATA 0x10101010 +#define DDRSS3_PHY_860_DATA 0x00021010 +#define DDRSS3_PHY_861_DATA 0x00100010 +#define DDRSS3_PHY_862_DATA 0x00100010 +#define DDRSS3_PHY_863_DATA 0x00100010 +#define DDRSS3_PHY_864_DATA 0x00100010 +#define DDRSS3_PHY_865_DATA 0x00050010 +#define DDRSS3_PHY_866_DATA 0x51517041 +#define DDRSS3_PHY_867_DATA 0x31C06001 +#define DDRSS3_PHY_868_DATA 0x07AB0340 +#define DDRSS3_PHY_869_DATA 0x00C0C001 +#define DDRSS3_PHY_870_DATA 0x0E0D0001 +#define DDRSS3_PHY_871_DATA 0x10001000 +#define DDRSS3_PHY_872_DATA 0x0C083E42 +#define DDRSS3_PHY_873_DATA 0x0F0C3701 +#define DDRSS3_PHY_874_DATA 0x01000140 +#define DDRSS3_PHY_875_DATA 0x0C000420 +#define DDRSS3_PHY_876_DATA 0x00000198 +#define DDRSS3_PHY_877_DATA 0x0A0000D0 +#define DDRSS3_PHY_878_DATA 0x00030200 +#define DDRSS3_PHY_879_DATA 0x02800000 +#define DDRSS3_PHY_880_DATA 0x80800000 +#define DDRSS3_PHY_881_DATA 0x000E2010 +#define DDRSS3_PHY_882_DATA 0x76543210 +#define DDRSS3_PHY_883_DATA 0x00000008 +#define DDRSS3_PHY_884_DATA 0x02800280 +#define DDRSS3_PHY_885_DATA 0x02800280 +#define DDRSS3_PHY_886_DATA 0x02800280 +#define DDRSS3_PHY_887_DATA 0x02800280 +#define DDRSS3_PHY_888_DATA 0x00000280 +#define DDRSS3_PHY_889_DATA 0x0000A000 +#define DDRSS3_PHY_890_DATA 0x00A000A0 +#define DDRSS3_PHY_891_DATA 0x00A000A0 +#define DDRSS3_PHY_892_DATA 0x00A000A0 +#define DDRSS3_PHY_893_DATA 0x00A000A0 +#define DDRSS3_PHY_894_DATA 0x00A000A0 +#define DDRSS3_PHY_895_DATA 0x00A000A0 +#define DDRSS3_PHY_896_DATA 0x00A000A0 +#define DDRSS3_PHY_897_DATA 0x00A000A0 +#define DDRSS3_PHY_898_DATA 0x01C200A0 +#define DDRSS3_PHY_899_DATA 0x01A00005 +#define DDRSS3_PHY_900_DATA 0x00000000 +#define DDRSS3_PHY_901_DATA 0x00000000 +#define DDRSS3_PHY_902_DATA 0x00080200 +#define DDRSS3_PHY_903_DATA 0x00000000 +#define DDRSS3_PHY_904_DATA 0x20202000 +#define DDRSS3_PHY_905_DATA 0x20202020 +#define DDRSS3_PHY_906_DATA 0xF0F02020 +#define DDRSS3_PHY_907_DATA 0x00000000 +#define DDRSS3_PHY_908_DATA 0x00000000 +#define DDRSS3_PHY_909_DATA 0x00000000 +#define DDRSS3_PHY_910_DATA 0x00000000 +#define DDRSS3_PHY_911_DATA 0x00000000 +#define DDRSS3_PHY_912_DATA 0x00000000 +#define DDRSS3_PHY_913_DATA 0x00000000 +#define DDRSS3_PHY_914_DATA 0x00000000 +#define DDRSS3_PHY_915_DATA 0x00000000 +#define DDRSS3_PHY_916_DATA 0x00000000 +#define DDRSS3_PHY_917_DATA 0x00000000 +#define DDRSS3_PHY_918_DATA 0x00000000 +#define DDRSS3_PHY_919_DATA 0x00000000 +#define DDRSS3_PHY_920_DATA 0x00000000 +#define DDRSS3_PHY_921_DATA 0x00000000 +#define DDRSS3_PHY_922_DATA 0x00000000 +#define DDRSS3_PHY_923_DATA 0x00000000 +#define DDRSS3_PHY_924_DATA 0x00000000 +#define DDRSS3_PHY_925_DATA 0x00000000 +#define DDRSS3_PHY_926_DATA 0x00000000 +#define DDRSS3_PHY_927_DATA 0x00000000 +#define DDRSS3_PHY_928_DATA 0x00000000 +#define DDRSS3_PHY_929_DATA 0x00000000 +#define DDRSS3_PHY_930_DATA 0x00000000 +#define DDRSS3_PHY_931_DATA 0x00000000 +#define DDRSS3_PHY_932_DATA 0x00000000 +#define DDRSS3_PHY_933_DATA 0x00000000 +#define DDRSS3_PHY_934_DATA 0x00000000 +#define DDRSS3_PHY_935_DATA 0x00000000 +#define DDRSS3_PHY_936_DATA 0x00000000 +#define DDRSS3_PHY_937_DATA 0x00000000 +#define DDRSS3_PHY_938_DATA 0x00000000 +#define DDRSS3_PHY_939_DATA 0x00000000 +#define DDRSS3_PHY_940_DATA 0x00000000 +#define DDRSS3_PHY_941_DATA 0x00000000 +#define DDRSS3_PHY_942_DATA 0x00000000 +#define DDRSS3_PHY_943_DATA 0x00000000 +#define DDRSS3_PHY_944_DATA 0x00000000 +#define DDRSS3_PHY_945_DATA 0x00000000 +#define DDRSS3_PHY_946_DATA 0x00000000 +#define DDRSS3_PHY_947_DATA 0x00000000 +#define DDRSS3_PHY_948_DATA 0x00000000 +#define DDRSS3_PHY_949_DATA 0x00000000 +#define DDRSS3_PHY_950_DATA 0x00000000 +#define DDRSS3_PHY_951_DATA 0x00000000 +#define DDRSS3_PHY_952_DATA 0x00000000 +#define DDRSS3_PHY_953_DATA 0x00000000 +#define DDRSS3_PHY_954_DATA 0x00000000 +#define DDRSS3_PHY_955_DATA 0x00000000 +#define DDRSS3_PHY_956_DATA 0x00000000 +#define DDRSS3_PHY_957_DATA 0x00000000 +#define DDRSS3_PHY_958_DATA 0x00000000 +#define DDRSS3_PHY_959_DATA 0x00000000 +#define DDRSS3_PHY_960_DATA 0x00000000 +#define DDRSS3_PHY_961_DATA 0x00000000 +#define DDRSS3_PHY_962_DATA 0x00000000 +#define DDRSS3_PHY_963_DATA 0x00000000 +#define DDRSS3_PHY_964_DATA 0x00000000 +#define DDRSS3_PHY_965_DATA 0x00000000 +#define DDRSS3_PHY_966_DATA 0x00000000 +#define DDRSS3_PHY_967_DATA 0x00000000 +#define DDRSS3_PHY_968_DATA 0x00000000 +#define DDRSS3_PHY_969_DATA 0x00000000 +#define DDRSS3_PHY_970_DATA 0x00000000 +#define DDRSS3_PHY_971_DATA 0x00000000 +#define DDRSS3_PHY_972_DATA 0x00000000 +#define DDRSS3_PHY_973_DATA 0x00000000 +#define DDRSS3_PHY_974_DATA 0x00000000 +#define DDRSS3_PHY_975_DATA 0x00000000 +#define DDRSS3_PHY_976_DATA 0x00000000 +#define DDRSS3_PHY_977_DATA 0x00000000 +#define DDRSS3_PHY_978_DATA 0x00000000 +#define DDRSS3_PHY_979_DATA 0x00000000 +#define DDRSS3_PHY_980_DATA 0x00000000 +#define DDRSS3_PHY_981_DATA 0x00000000 +#define DDRSS3_PHY_982_DATA 0x00000000 +#define DDRSS3_PHY_983_DATA 0x00000000 +#define DDRSS3_PHY_984_DATA 0x00000000 +#define DDRSS3_PHY_985_DATA 0x00000000 +#define DDRSS3_PHY_986_DATA 0x00000000 +#define DDRSS3_PHY_987_DATA 0x00000000 +#define DDRSS3_PHY_988_DATA 0x00000000 +#define DDRSS3_PHY_989_DATA 0x00000000 +#define DDRSS3_PHY_990_DATA 0x00000000 +#define DDRSS3_PHY_991_DATA 0x00000000 +#define DDRSS3_PHY_992_DATA 0x00000000 +#define DDRSS3_PHY_993_DATA 0x00000000 +#define DDRSS3_PHY_994_DATA 0x00000000 +#define DDRSS3_PHY_995_DATA 0x00000000 +#define DDRSS3_PHY_996_DATA 0x00000000 +#define DDRSS3_PHY_997_DATA 0x00000000 +#define DDRSS3_PHY_998_DATA 0x00000000 +#define DDRSS3_PHY_999_DATA 0x00000000 +#define DDRSS3_PHY_1000_DATA 0x00000000 +#define DDRSS3_PHY_1001_DATA 0x00000000 +#define DDRSS3_PHY_1002_DATA 0x00000000 +#define DDRSS3_PHY_1003_DATA 0x00000000 +#define DDRSS3_PHY_1004_DATA 0x00000000 +#define DDRSS3_PHY_1005_DATA 0x00000000 +#define DDRSS3_PHY_1006_DATA 0x00000000 +#define DDRSS3_PHY_1007_DATA 0x00000000 +#define DDRSS3_PHY_1008_DATA 0x00000000 +#define DDRSS3_PHY_1009_DATA 0x00000000 +#define DDRSS3_PHY_1010_DATA 0x00000000 +#define DDRSS3_PHY_1011_DATA 0x00000000 +#define DDRSS3_PHY_1012_DATA 0x00000000 +#define DDRSS3_PHY_1013_DATA 0x00000000 +#define DDRSS3_PHY_1014_DATA 0x00000000 +#define DDRSS3_PHY_1015_DATA 0x00000000 +#define DDRSS3_PHY_1016_DATA 0x00000000 +#define DDRSS3_PHY_1017_DATA 0x00000000 +#define DDRSS3_PHY_1018_DATA 0x00000000 +#define DDRSS3_PHY_1019_DATA 0x00000000 +#define DDRSS3_PHY_1020_DATA 0x00000000 +#define DDRSS3_PHY_1021_DATA 0x00000000 +#define DDRSS3_PHY_1022_DATA 0x00000000 +#define DDRSS3_PHY_1023_DATA 0x00000000 +#define DDRSS3_PHY_1024_DATA 0x00000000 +#define DDRSS3_PHY_1025_DATA 0x00000000 +#define DDRSS3_PHY_1026_DATA 0x00000000 +#define DDRSS3_PHY_1027_DATA 0x00000000 +#define DDRSS3_PHY_1028_DATA 0x00000000 +#define DDRSS3_PHY_1029_DATA 0x00000100 +#define DDRSS3_PHY_1030_DATA 0x00000200 +#define DDRSS3_PHY_1031_DATA 0x00000000 +#define DDRSS3_PHY_1032_DATA 0x00000000 +#define DDRSS3_PHY_1033_DATA 0x00000000 +#define DDRSS3_PHY_1034_DATA 0x00000000 +#define DDRSS3_PHY_1035_DATA 0x00400000 +#define DDRSS3_PHY_1036_DATA 0x00000080 +#define DDRSS3_PHY_1037_DATA 0x00DCBA98 +#define DDRSS3_PHY_1038_DATA 0x03000000 +#define DDRSS3_PHY_1039_DATA 0x00200000 +#define DDRSS3_PHY_1040_DATA 0x00000000 +#define DDRSS3_PHY_1041_DATA 0x00000000 +#define DDRSS3_PHY_1042_DATA 0x00000000 +#define DDRSS3_PHY_1043_DATA 0x00000000 +#define DDRSS3_PHY_1044_DATA 0x00000000 +#define DDRSS3_PHY_1045_DATA 0x0000002A +#define DDRSS3_PHY_1046_DATA 0x00000015 +#define DDRSS3_PHY_1047_DATA 0x00000015 +#define DDRSS3_PHY_1048_DATA 0x0000002A +#define DDRSS3_PHY_1049_DATA 0x00000033 +#define DDRSS3_PHY_1050_DATA 0x0000000C +#define DDRSS3_PHY_1051_DATA 0x0000000C +#define DDRSS3_PHY_1052_DATA 0x00000033 +#define DDRSS3_PHY_1053_DATA 0x00543210 +#define DDRSS3_PHY_1054_DATA 0x003F0000 +#define DDRSS3_PHY_1055_DATA 0x000F013F +#define DDRSS3_PHY_1056_DATA 0x20202003 +#define DDRSS3_PHY_1057_DATA 0x00202020 +#define DDRSS3_PHY_1058_DATA 0x20008008 +#define DDRSS3_PHY_1059_DATA 0x00000810 +#define DDRSS3_PHY_1060_DATA 0x00000F00 +#define DDRSS3_PHY_1061_DATA 0x00000000 +#define DDRSS3_PHY_1062_DATA 0x00000000 +#define DDRSS3_PHY_1063_DATA 0x00000000 +#define DDRSS3_PHY_1064_DATA 0x000305CC +#define DDRSS3_PHY_1065_DATA 0x00030000 +#define DDRSS3_PHY_1066_DATA 0x00000300 +#define DDRSS3_PHY_1067_DATA 0x00000300 +#define DDRSS3_PHY_1068_DATA 0x00000300 +#define DDRSS3_PHY_1069_DATA 0x00000300 +#define DDRSS3_PHY_1070_DATA 0x00000300 +#define DDRSS3_PHY_1071_DATA 0x42080010 +#define DDRSS3_PHY_1072_DATA 0x0000803E +#define DDRSS3_PHY_1073_DATA 0x00000001 +#define DDRSS3_PHY_1074_DATA 0x01000102 +#define DDRSS3_PHY_1075_DATA 0x00008000 +#define DDRSS3_PHY_1076_DATA 0x00000000 +#define DDRSS3_PHY_1077_DATA 0x00000000 +#define DDRSS3_PHY_1078_DATA 0x00000000 +#define DDRSS3_PHY_1079_DATA 0x00000000 +#define DDRSS3_PHY_1080_DATA 0x00000000 +#define DDRSS3_PHY_1081_DATA 0x00000000 +#define DDRSS3_PHY_1082_DATA 0x00000000 +#define DDRSS3_PHY_1083_DATA 0x00000000 +#define DDRSS3_PHY_1084_DATA 0x00000000 +#define DDRSS3_PHY_1085_DATA 0x00000000 +#define DDRSS3_PHY_1086_DATA 0x00000000 +#define DDRSS3_PHY_1087_DATA 0x00000000 +#define DDRSS3_PHY_1088_DATA 0x00000000 +#define DDRSS3_PHY_1089_DATA 0x00000000 +#define DDRSS3_PHY_1090_DATA 0x00000000 +#define DDRSS3_PHY_1091_DATA 0x00000000 +#define DDRSS3_PHY_1092_DATA 0x00000000 +#define DDRSS3_PHY_1093_DATA 0x00000000 +#define DDRSS3_PHY_1094_DATA 0x00000000 +#define DDRSS3_PHY_1095_DATA 0x00000000 +#define DDRSS3_PHY_1096_DATA 0x00000000 +#define DDRSS3_PHY_1097_DATA 0x00000000 +#define DDRSS3_PHY_1098_DATA 0x00000000 +#define DDRSS3_PHY_1099_DATA 0x00000000 +#define DDRSS3_PHY_1100_DATA 0x00000000 +#define DDRSS3_PHY_1101_DATA 0x00000000 +#define DDRSS3_PHY_1102_DATA 0x00000000 +#define DDRSS3_PHY_1103_DATA 0x00000000 +#define DDRSS3_PHY_1104_DATA 0x00000000 +#define DDRSS3_PHY_1105_DATA 0x00000000 +#define DDRSS3_PHY_1106_DATA 0x00000000 +#define DDRSS3_PHY_1107_DATA 0x00000000 +#define DDRSS3_PHY_1108_DATA 0x00000000 +#define DDRSS3_PHY_1109_DATA 0x00000000 +#define DDRSS3_PHY_1110_DATA 0x00000000 +#define DDRSS3_PHY_1111_DATA 0x00000000 +#define DDRSS3_PHY_1112_DATA 0x00000000 +#define DDRSS3_PHY_1113_DATA 0x00000000 +#define DDRSS3_PHY_1114_DATA 0x00000000 +#define DDRSS3_PHY_1115_DATA 0x00000000 +#define DDRSS3_PHY_1116_DATA 0x00000000 +#define DDRSS3_PHY_1117_DATA 0x00000000 +#define DDRSS3_PHY_1118_DATA 0x00000000 +#define DDRSS3_PHY_1119_DATA 0x00000000 +#define DDRSS3_PHY_1120_DATA 0x00000000 +#define DDRSS3_PHY_1121_DATA 0x00000000 +#define DDRSS3_PHY_1122_DATA 0x00000000 +#define DDRSS3_PHY_1123_DATA 0x00000000 +#define DDRSS3_PHY_1124_DATA 0x00000000 +#define DDRSS3_PHY_1125_DATA 0x00000000 +#define DDRSS3_PHY_1126_DATA 0x00000000 +#define DDRSS3_PHY_1127_DATA 0x00000000 +#define DDRSS3_PHY_1128_DATA 0x00000000 +#define DDRSS3_PHY_1129_DATA 0x00000000 +#define DDRSS3_PHY_1130_DATA 0x00000000 +#define DDRSS3_PHY_1131_DATA 0x00000000 +#define DDRSS3_PHY_1132_DATA 0x00000000 +#define DDRSS3_PHY_1133_DATA 0x00000000 +#define DDRSS3_PHY_1134_DATA 0x00000000 +#define DDRSS3_PHY_1135_DATA 0x00000000 +#define DDRSS3_PHY_1136_DATA 0x00000000 +#define DDRSS3_PHY_1137_DATA 0x00000000 +#define DDRSS3_PHY_1138_DATA 0x00000000 +#define DDRSS3_PHY_1139_DATA 0x00000000 +#define DDRSS3_PHY_1140_DATA 0x00000000 +#define DDRSS3_PHY_1141_DATA 0x00000000 +#define DDRSS3_PHY_1142_DATA 0x00000000 +#define DDRSS3_PHY_1143_DATA 0x00000000 +#define DDRSS3_PHY_1144_DATA 0x00000000 +#define DDRSS3_PHY_1145_DATA 0x00000000 +#define DDRSS3_PHY_1146_DATA 0x00000000 +#define DDRSS3_PHY_1147_DATA 0x00000000 +#define DDRSS3_PHY_1148_DATA 0x00000000 +#define DDRSS3_PHY_1149_DATA 0x00000000 +#define DDRSS3_PHY_1150_DATA 0x00000000 +#define DDRSS3_PHY_1151_DATA 0x00000000 +#define DDRSS3_PHY_1152_DATA 0x00000000 +#define DDRSS3_PHY_1153_DATA 0x00000000 +#define DDRSS3_PHY_1154_DATA 0x00000000 +#define DDRSS3_PHY_1155_DATA 0x00000000 +#define DDRSS3_PHY_1156_DATA 0x00000000 +#define DDRSS3_PHY_1157_DATA 0x00000000 +#define DDRSS3_PHY_1158_DATA 0x00000000 +#define DDRSS3_PHY_1159_DATA 0x00000000 +#define DDRSS3_PHY_1160_DATA 0x00000000 +#define DDRSS3_PHY_1161_DATA 0x00000000 +#define DDRSS3_PHY_1162_DATA 0x00000000 +#define DDRSS3_PHY_1163_DATA 0x00000000 +#define DDRSS3_PHY_1164_DATA 0x00000000 +#define DDRSS3_PHY_1165_DATA 0x00000000 +#define DDRSS3_PHY_1166_DATA 0x00000000 +#define DDRSS3_PHY_1167_DATA 0x00000000 +#define DDRSS3_PHY_1168_DATA 0x00000000 +#define DDRSS3_PHY_1169_DATA 0x00000000 +#define DDRSS3_PHY_1170_DATA 0x00000000 +#define DDRSS3_PHY_1171_DATA 0x00000000 +#define DDRSS3_PHY_1172_DATA 0x00000000 +#define DDRSS3_PHY_1173_DATA 0x00000000 +#define DDRSS3_PHY_1174_DATA 0x00000000 +#define DDRSS3_PHY_1175_DATA 0x00000000 +#define DDRSS3_PHY_1176_DATA 0x00000000 +#define DDRSS3_PHY_1177_DATA 0x00000000 +#define DDRSS3_PHY_1178_DATA 0x00000000 +#define DDRSS3_PHY_1179_DATA 0x00000000 +#define DDRSS3_PHY_1180_DATA 0x00000000 +#define DDRSS3_PHY_1181_DATA 0x00000000 +#define DDRSS3_PHY_1182_DATA 0x00000000 +#define DDRSS3_PHY_1183_DATA 0x00000000 +#define DDRSS3_PHY_1184_DATA 0x00000000 +#define DDRSS3_PHY_1185_DATA 0x00000000 +#define DDRSS3_PHY_1186_DATA 0x00000000 +#define DDRSS3_PHY_1187_DATA 0x00000000 +#define DDRSS3_PHY_1188_DATA 0x00000000 +#define DDRSS3_PHY_1189_DATA 0x00000000 +#define DDRSS3_PHY_1190_DATA 0x00000000 +#define DDRSS3_PHY_1191_DATA 0x00000000 +#define DDRSS3_PHY_1192_DATA 0x00000000 +#define DDRSS3_PHY_1193_DATA 0x00000000 +#define DDRSS3_PHY_1194_DATA 0x00000000 +#define DDRSS3_PHY_1195_DATA 0x00000000 +#define DDRSS3_PHY_1196_DATA 0x00000000 +#define DDRSS3_PHY_1197_DATA 0x00000000 +#define DDRSS3_PHY_1198_DATA 0x00000000 +#define DDRSS3_PHY_1199_DATA 0x00000000 +#define DDRSS3_PHY_1200_DATA 0x00000000 +#define DDRSS3_PHY_1201_DATA 0x00000000 +#define DDRSS3_PHY_1202_DATA 0x00000000 +#define DDRSS3_PHY_1203_DATA 0x00000000 +#define DDRSS3_PHY_1204_DATA 0x00000000 +#define DDRSS3_PHY_1205_DATA 0x00000000 +#define DDRSS3_PHY_1206_DATA 0x00000000 +#define DDRSS3_PHY_1207_DATA 0x00000000 +#define DDRSS3_PHY_1208_DATA 0x00000000 +#define DDRSS3_PHY_1209_DATA 0x00000000 +#define DDRSS3_PHY_1210_DATA 0x00000000 +#define DDRSS3_PHY_1211_DATA 0x00000000 +#define DDRSS3_PHY_1212_DATA 0x00000000 +#define DDRSS3_PHY_1213_DATA 0x00000000 +#define DDRSS3_PHY_1214_DATA 0x00000000 +#define DDRSS3_PHY_1215_DATA 0x00000000 +#define DDRSS3_PHY_1216_DATA 0x00000000 +#define DDRSS3_PHY_1217_DATA 0x00000000 +#define DDRSS3_PHY_1218_DATA 0x00000000 +#define DDRSS3_PHY_1219_DATA 0x00000000 +#define DDRSS3_PHY_1220_DATA 0x00000000 +#define DDRSS3_PHY_1221_DATA 0x00000000 +#define DDRSS3_PHY_1222_DATA 0x00000000 +#define DDRSS3_PHY_1223_DATA 0x00000000 +#define DDRSS3_PHY_1224_DATA 0x00000000 +#define DDRSS3_PHY_1225_DATA 0x00000000 +#define DDRSS3_PHY_1226_DATA 0x00000000 +#define DDRSS3_PHY_1227_DATA 0x00000000 +#define DDRSS3_PHY_1228_DATA 0x00000000 +#define DDRSS3_PHY_1229_DATA 0x00000000 +#define DDRSS3_PHY_1230_DATA 0x00000000 +#define DDRSS3_PHY_1231_DATA 0x00000000 +#define DDRSS3_PHY_1232_DATA 0x00000000 +#define DDRSS3_PHY_1233_DATA 0x00000000 +#define DDRSS3_PHY_1234_DATA 0x00000000 +#define DDRSS3_PHY_1235_DATA 0x00000000 +#define DDRSS3_PHY_1236_DATA 0x00000000 +#define DDRSS3_PHY_1237_DATA 0x00000000 +#define DDRSS3_PHY_1238_DATA 0x00000000 +#define DDRSS3_PHY_1239_DATA 0x00000000 +#define DDRSS3_PHY_1240_DATA 0x00000000 +#define DDRSS3_PHY_1241_DATA 0x00000000 +#define DDRSS3_PHY_1242_DATA 0x00000000 +#define DDRSS3_PHY_1243_DATA 0x00000000 +#define DDRSS3_PHY_1244_DATA 0x00000000 +#define DDRSS3_PHY_1245_DATA 0x00000000 +#define DDRSS3_PHY_1246_DATA 0x00000000 +#define DDRSS3_PHY_1247_DATA 0x00000000 +#define DDRSS3_PHY_1248_DATA 0x00000000 +#define DDRSS3_PHY_1249_DATA 0x00000000 +#define DDRSS3_PHY_1250_DATA 0x00000000 +#define DDRSS3_PHY_1251_DATA 0x00000000 +#define DDRSS3_PHY_1252_DATA 0x00000000 +#define DDRSS3_PHY_1253_DATA 0x00000000 +#define DDRSS3_PHY_1254_DATA 0x00000000 +#define DDRSS3_PHY_1255_DATA 0x00000000 +#define DDRSS3_PHY_1256_DATA 0x00000000 +#define DDRSS3_PHY_1257_DATA 0x00000000 +#define DDRSS3_PHY_1258_DATA 0x00000000 +#define DDRSS3_PHY_1259_DATA 0x00000000 +#define DDRSS3_PHY_1260_DATA 0x00000000 +#define DDRSS3_PHY_1261_DATA 0x00000000 +#define DDRSS3_PHY_1262_DATA 0x00000000 +#define DDRSS3_PHY_1263_DATA 0x00000000 +#define DDRSS3_PHY_1264_DATA 0x00000000 +#define DDRSS3_PHY_1265_DATA 0x00000000 +#define DDRSS3_PHY_1266_DATA 0x00000000 +#define DDRSS3_PHY_1267_DATA 0x00000000 +#define DDRSS3_PHY_1268_DATA 0x00000000 +#define DDRSS3_PHY_1269_DATA 0x00000000 +#define DDRSS3_PHY_1270_DATA 0x00000000 +#define DDRSS3_PHY_1271_DATA 0x00000000 +#define DDRSS3_PHY_1272_DATA 0x00000000 +#define DDRSS3_PHY_1273_DATA 0x00000000 +#define DDRSS3_PHY_1274_DATA 0x00000000 +#define DDRSS3_PHY_1275_DATA 0x00000000 +#define DDRSS3_PHY_1276_DATA 0x00000000 +#define DDRSS3_PHY_1277_DATA 0x00000000 +#define DDRSS3_PHY_1278_DATA 0x00000000 +#define DDRSS3_PHY_1279_DATA 0x00000000 +#define DDRSS3_PHY_1280_DATA 0x00000000 +#define DDRSS3_PHY_1281_DATA 0x00010100 +#define DDRSS3_PHY_1282_DATA 0x00000000 +#define DDRSS3_PHY_1283_DATA 0x00000000 +#define DDRSS3_PHY_1284_DATA 0x00050000 +#define DDRSS3_PHY_1285_DATA 0x04000000 +#define DDRSS3_PHY_1286_DATA 0x00000055 +#define DDRSS3_PHY_1287_DATA 0x00000000 +#define DDRSS3_PHY_1288_DATA 0x00000000 +#define DDRSS3_PHY_1289_DATA 0x00000000 +#define DDRSS3_PHY_1290_DATA 0x00000000 +#define DDRSS3_PHY_1291_DATA 0x00002001 +#define DDRSS3_PHY_1292_DATA 0x0000400F +#define DDRSS3_PHY_1293_DATA 0x50020028 +#define DDRSS3_PHY_1294_DATA 0x01010000 +#define DDRSS3_PHY_1295_DATA 0x80080001 +#define DDRSS3_PHY_1296_DATA 0x10200000 +#define DDRSS3_PHY_1297_DATA 0x00000008 +#define DDRSS3_PHY_1298_DATA 0x00000000 +#define DDRSS3_PHY_1299_DATA 0x01090E00 +#define DDRSS3_PHY_1300_DATA 0x00040101 +#define DDRSS3_PHY_1301_DATA 0x0000010F +#define DDRSS3_PHY_1302_DATA 0x00000000 +#define DDRSS3_PHY_1303_DATA 0x0000FFFF +#define DDRSS3_PHY_1304_DATA 0x00000000 +#define DDRSS3_PHY_1305_DATA 0x01010000 +#define DDRSS3_PHY_1306_DATA 0x01080402 +#define DDRSS3_PHY_1307_DATA 0x01200F02 +#define DDRSS3_PHY_1308_DATA 0x00194280 +#define DDRSS3_PHY_1309_DATA 0x00000004 +#define DDRSS3_PHY_1310_DATA 0x00042000 +#define DDRSS3_PHY_1311_DATA 0x00000000 +#define DDRSS3_PHY_1312_DATA 0x00000000 +#define DDRSS3_PHY_1313_DATA 0x00000000 +#define DDRSS3_PHY_1314_DATA 0x00000000 +#define DDRSS3_PHY_1315_DATA 0x00000000 +#define DDRSS3_PHY_1316_DATA 0x00000000 +#define DDRSS3_PHY_1317_DATA 0x01000000 +#define DDRSS3_PHY_1318_DATA 0x00000705 +#define DDRSS3_PHY_1319_DATA 0x00000054 +#define DDRSS3_PHY_1320_DATA 0x00030820 +#define DDRSS3_PHY_1321_DATA 0x00010820 +#define DDRSS3_PHY_1322_DATA 0x00010820 +#define DDRSS3_PHY_1323_DATA 0x00010820 +#define DDRSS3_PHY_1324_DATA 0x00010820 +#define DDRSS3_PHY_1325_DATA 0x00010820 +#define DDRSS3_PHY_1326_DATA 0x00010820 +#define DDRSS3_PHY_1327_DATA 0x00010820 +#define DDRSS3_PHY_1328_DATA 0x00010820 +#define DDRSS3_PHY_1329_DATA 0x00000000 +#define DDRSS3_PHY_1330_DATA 0x00000074 +#define DDRSS3_PHY_1331_DATA 0x00000400 +#define DDRSS3_PHY_1332_DATA 0x00000108 +#define DDRSS3_PHY_1333_DATA 0x00000000 +#define DDRSS3_PHY_1334_DATA 0x00000000 +#define DDRSS3_PHY_1335_DATA 0x00000000 +#define DDRSS3_PHY_1336_DATA 0x00000000 +#define DDRSS3_PHY_1337_DATA 0x00000000 +#define DDRSS3_PHY_1338_DATA 0x03000000 +#define DDRSS3_PHY_1339_DATA 0x00000000 +#define DDRSS3_PHY_1340_DATA 0x00000000 +#define DDRSS3_PHY_1341_DATA 0x00000000 +#define DDRSS3_PHY_1342_DATA 0x04102006 +#define DDRSS3_PHY_1343_DATA 0x00041020 +#define DDRSS3_PHY_1344_DATA 0x01C98C98 +#define DDRSS3_PHY_1345_DATA 0x3F400000 +#define DDRSS3_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS3_PHY_1347_DATA 0x0000001F +#define DDRSS3_PHY_1348_DATA 0x00000000 +#define DDRSS3_PHY_1349_DATA 0x00000000 +#define DDRSS3_PHY_1350_DATA 0x00000000 +#define DDRSS3_PHY_1351_DATA 0x00010000 +#define DDRSS3_PHY_1352_DATA 0x00000000 +#define DDRSS3_PHY_1353_DATA 0x00000000 +#define DDRSS3_PHY_1354_DATA 0x00000000 +#define DDRSS3_PHY_1355_DATA 0x00000000 +#define DDRSS3_PHY_1356_DATA 0x76543210 +#define DDRSS3_PHY_1357_DATA 0x00010198 +#define DDRSS3_PHY_1358_DATA 0x00000000 +#define DDRSS3_PHY_1359_DATA 0x00000000 +#define DDRSS3_PHY_1360_DATA 0x00000000 +#define DDRSS3_PHY_1361_DATA 0x00040700 +#define DDRSS3_PHY_1362_DATA 0x00000000 +#define DDRSS3_PHY_1363_DATA 0x00000000 +#define DDRSS3_PHY_1364_DATA 0x00000000 +#define DDRSS3_PHY_1365_DATA 0x00000000 +#define DDRSS3_PHY_1366_DATA 0x00000000 +#define DDRSS3_PHY_1367_DATA 0x00000002 +#define DDRSS3_PHY_1368_DATA 0x00000000 +#define DDRSS3_PHY_1369_DATA 0x00000000 +#define DDRSS3_PHY_1370_DATA 0x00000000 +#define DDRSS3_PHY_1371_DATA 0x00000000 +#define DDRSS3_PHY_1372_DATA 0x00000000 +#define DDRSS3_PHY_1373_DATA 0x00000000 +#define DDRSS3_PHY_1374_DATA 0x00080000 +#define DDRSS3_PHY_1375_DATA 0x000007FF +#define DDRSS3_PHY_1376_DATA 0x00000000 +#define DDRSS3_PHY_1377_DATA 0x00000000 +#define DDRSS3_PHY_1378_DATA 0x00000000 +#define DDRSS3_PHY_1379_DATA 0x00000000 +#define DDRSS3_PHY_1380_DATA 0x00000000 +#define DDRSS3_PHY_1381_DATA 0x00000000 +#define DDRSS3_PHY_1382_DATA 0x000FFFFF +#define DDRSS3_PHY_1383_DATA 0x000FFFFF +#define DDRSS3_PHY_1384_DATA 0x0000FFFF +#define DDRSS3_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS3_PHY_1386_DATA 0x030FFFFF +#define DDRSS3_PHY_1387_DATA 0x01FFFFFF +#define DDRSS3_PHY_1388_DATA 0x0000FFFF +#define DDRSS3_PHY_1389_DATA 0x00000000 +#define DDRSS3_PHY_1390_DATA 0x00000000 +#define DDRSS3_PHY_1391_DATA 0x00000000 +#define DDRSS3_PHY_1392_DATA 0x00000000 +#define DDRSS3_PHY_1393_DATA 0x0001F7C0 +#define DDRSS3_PHY_1394_DATA 0x00000003 +#define DDRSS3_PHY_1395_DATA 0x00000000 +#define DDRSS3_PHY_1396_DATA 0x00001142 +#define DDRSS3_PHY_1397_DATA 0x010207AB +#define DDRSS3_PHY_1398_DATA 0x01000080 +#define DDRSS3_PHY_1399_DATA 0x03900390 +#define DDRSS3_PHY_1400_DATA 0x03900390 +#define DDRSS3_PHY_1401_DATA 0x00000390 +#define DDRSS3_PHY_1402_DATA 0x00000390 +#define DDRSS3_PHY_1403_DATA 0x00000390 +#define DDRSS3_PHY_1404_DATA 0x00000390 +#define DDRSS3_PHY_1405_DATA 0x00000005 +#define DDRSS3_PHY_1406_DATA 0x01813FCC +#define DDRSS3_PHY_1407_DATA 0x000000CC +#define DDRSS3_PHY_1408_DATA 0x0C000DFF +#define DDRSS3_PHY_1409_DATA 0x30000DFF +#define DDRSS3_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS3_PHY_1411_DATA 0x000100F0 +#define DDRSS3_PHY_1412_DATA 0x780DFFCC +#define DDRSS3_PHY_1413_DATA 0x00007E31 +#define DDRSS3_PHY_1414_DATA 0x000CBF11 +#define DDRSS3_PHY_1415_DATA 0x01990010 +#define DDRSS3_PHY_1416_DATA 0x000CBF11 +#define DDRSS3_PHY_1417_DATA 0x01990010 +#define DDRSS3_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS3_PHY_1419_DATA 0x00EF00F0 +#define DDRSS3_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS3_PHY_1421_DATA 0x01FF00F0 +#define DDRSS3_PHY_1422_DATA 0x20040006 diff --git a/arch/arm/dts/k3-j784s4-ddr.dtsi b/arch/arm/dts/k3-j784s4-ddr.dtsi new file mode 100644 index 00000000000..1c3242b0870 --- /dev/null +++ b/arch/arm/dts/k3-j784s4-ddr.dtsi @@ -0,0 +1,8858 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&main_navss { + ranges = <0x00 0x00114000 0x00 0x00114000 0x00 0x00000100>, // ctrl_mmr_lpr + <0x00 0x02990000 0x00 0x02990000 0x00 0x00004000>, // ddr0 cfg + <0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg + <0x00 0x029d0000 0x00 0x029d0000 0x00 0x00004000>, // ddr2 cfg + <0x00 0x029f0000 0x00 0x029f0000 0x00 0x00004000>, // ddr3 cfg + <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; + + msmc0: msmc { + compatible = "ti,j721s2-msmc"; + intrlv-gran = <MULTI_DDR_CFG_INTRLV_GRAN>; + intrlv-size = <MULTI_DDR_CFG_INTRLV_SIZE>; + ecc-enable = <MULTI_DDR_CFG_ECC_ENABLE>; + emif-config = <MULTI_DDR_CFG_HYBRID_SELECT>; + emif-active = <MULTI_DDR_CFG_EMIFS_ACTIVE>; + #address-cells = <2>; + #size-cells = <2>; + + bootph-pre-ram; + + memorycontroller0: memorycontroller@2990000 { + compatible = "ti,j721s2-ddrss"; + reg = <0x0 0x02990000 0x0 0x4000>, + <0x0 0x0114000 0x0 0x100>; + reg-names = "cfg", "ctrl_mmr_lp4"; + power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>, + <&k3_pds 131 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 191 1>, <&k3_clks 78 2>; + ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>; + ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>; + ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>; + ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>; + instance = <0>; + + bootph-pre-ram; + + ti,ctl-data = < + DDRSS0_CTL_00_DATA + DDRSS0_CTL_01_DATA + DDRSS0_CTL_02_DATA + DDRSS0_CTL_03_DATA + DDRSS0_CTL_04_DATA + DDRSS0_CTL_05_DATA + DDRSS0_CTL_06_DATA + DDRSS0_CTL_07_DATA + DDRSS0_CTL_08_DATA + DDRSS0_CTL_09_DATA + DDRSS0_CTL_10_DATA + DDRSS0_CTL_11_DATA + DDRSS0_CTL_12_DATA + DDRSS0_CTL_13_DATA + DDRSS0_CTL_14_DATA + DDRSS0_CTL_15_DATA + DDRSS0_CTL_16_DATA + DDRSS0_CTL_17_DATA + DDRSS0_CTL_18_DATA + DDRSS0_CTL_19_DATA + DDRSS0_CTL_20_DATA + DDRSS0_CTL_21_DATA + DDRSS0_CTL_22_DATA + DDRSS0_CTL_23_DATA + DDRSS0_CTL_24_DATA + DDRSS0_CTL_25_DATA + DDRSS0_CTL_26_DATA + DDRSS0_CTL_27_DATA + DDRSS0_CTL_28_DATA + DDRSS0_CTL_29_DATA + DDRSS0_CTL_30_DATA + DDRSS0_CTL_31_DATA + DDRSS0_CTL_32_DATA + DDRSS0_CTL_33_DATA + DDRSS0_CTL_34_DATA + DDRSS0_CTL_35_DATA + DDRSS0_CTL_36_DATA + DDRSS0_CTL_37_DATA + DDRSS0_CTL_38_DATA + DDRSS0_CTL_39_DATA + DDRSS0_CTL_40_DATA + DDRSS0_CTL_41_DATA + DDRSS0_CTL_42_DATA + DDRSS0_CTL_43_DATA + DDRSS0_CTL_44_DATA + DDRSS0_CTL_45_DATA + DDRSS0_CTL_46_DATA + DDRSS0_CTL_47_DATA + DDRSS0_CTL_48_DATA + DDRSS0_CTL_49_DATA + DDRSS0_CTL_50_DATA + DDRSS0_CTL_51_DATA + DDRSS0_CTL_52_DATA + DDRSS0_CTL_53_DATA + DDRSS0_CTL_54_DATA + DDRSS0_CTL_55_DATA + DDRSS0_CTL_56_DATA + DDRSS0_CTL_57_DATA + DDRSS0_CTL_58_DATA + DDRSS0_CTL_59_DATA + DDRSS0_CTL_60_DATA + DDRSS0_CTL_61_DATA + DDRSS0_CTL_62_DATA + DDRSS0_CTL_63_DATA + DDRSS0_CTL_64_DATA + DDRSS0_CTL_65_DATA + DDRSS0_CTL_66_DATA + DDRSS0_CTL_67_DATA + DDRSS0_CTL_68_DATA + DDRSS0_CTL_69_DATA + DDRSS0_CTL_70_DATA + DDRSS0_CTL_71_DATA + DDRSS0_CTL_72_DATA + DDRSS0_CTL_73_DATA + DDRSS0_CTL_74_DATA + DDRSS0_CTL_75_DATA + DDRSS0_CTL_76_DATA + DDRSS0_CTL_77_DATA + DDRSS0_CTL_78_DATA + DDRSS0_CTL_79_DATA + DDRSS0_CTL_80_DATA + DDRSS0_CTL_81_DATA + DDRSS0_CTL_82_DATA + DDRSS0_CTL_83_DATA + DDRSS0_CTL_84_DATA + DDRSS0_CTL_85_DATA + DDRSS0_CTL_86_DATA + DDRSS0_CTL_87_DATA + DDRSS0_CTL_88_DATA + DDRSS0_CTL_89_DATA + DDRSS0_CTL_90_DATA + DDRSS0_CTL_91_DATA + DDRSS0_CTL_92_DATA + DDRSS0_CTL_93_DATA + DDRSS0_CTL_94_DATA + DDRSS0_CTL_95_DATA + DDRSS0_CTL_96_DATA + DDRSS0_CTL_97_DATA + DDRSS0_CTL_98_DATA + DDRSS0_CTL_99_DATA + DDRSS0_CTL_100_DATA + DDRSS0_CTL_101_DATA + DDRSS0_CTL_102_DATA + DDRSS0_CTL_103_DATA + DDRSS0_CTL_104_DATA + DDRSS0_CTL_105_DATA + DDRSS0_CTL_106_DATA + DDRSS0_CTL_107_DATA + DDRSS0_CTL_108_DATA + DDRSS0_CTL_109_DATA + DDRSS0_CTL_110_DATA + DDRSS0_CTL_111_DATA + DDRSS0_CTL_112_DATA + DDRSS0_CTL_113_DATA + DDRSS0_CTL_114_DATA + DDRSS0_CTL_115_DATA + DDRSS0_CTL_116_DATA + DDRSS0_CTL_117_DATA + DDRSS0_CTL_118_DATA + DDRSS0_CTL_119_DATA + DDRSS0_CTL_120_DATA + DDRSS0_CTL_121_DATA + DDRSS0_CTL_122_DATA + DDRSS0_CTL_123_DATA + DDRSS0_CTL_124_DATA + DDRSS0_CTL_125_DATA + DDRSS0_CTL_126_DATA + DDRSS0_CTL_127_DATA + DDRSS0_CTL_128_DATA + DDRSS0_CTL_129_DATA + DDRSS0_CTL_130_DATA + DDRSS0_CTL_131_DATA + DDRSS0_CTL_132_DATA + DDRSS0_CTL_133_DATA + DDRSS0_CTL_134_DATA + DDRSS0_CTL_135_DATA + DDRSS0_CTL_136_DATA + DDRSS0_CTL_137_DATA + DDRSS0_CTL_138_DATA + DDRSS0_CTL_139_DATA + DDRSS0_CTL_140_DATA + DDRSS0_CTL_141_DATA + DDRSS0_CTL_142_DATA + DDRSS0_CTL_143_DATA + DDRSS0_CTL_144_DATA + DDRSS0_CTL_145_DATA + DDRSS0_CTL_146_DATA + DDRSS0_CTL_147_DATA + DDRSS0_CTL_148_DATA + DDRSS0_CTL_149_DATA + DDRSS0_CTL_150_DATA + DDRSS0_CTL_151_DATA + DDRSS0_CTL_152_DATA + DDRSS0_CTL_153_DATA + DDRSS0_CTL_154_DATA + DDRSS0_CTL_155_DATA + DDRSS0_CTL_156_DATA + DDRSS0_CTL_157_DATA + DDRSS0_CTL_158_DATA + DDRSS0_CTL_159_DATA + DDRSS0_CTL_160_DATA + DDRSS0_CTL_161_DATA + DDRSS0_CTL_162_DATA + DDRSS0_CTL_163_DATA + DDRSS0_CTL_164_DATA + DDRSS0_CTL_165_DATA + DDRSS0_CTL_166_DATA + DDRSS0_CTL_167_DATA + DDRSS0_CTL_168_DATA + DDRSS0_CTL_169_DATA + DDRSS0_CTL_170_DATA + DDRSS0_CTL_171_DATA + DDRSS0_CTL_172_DATA + DDRSS0_CTL_173_DATA + DDRSS0_CTL_174_DATA + DDRSS0_CTL_175_DATA + DDRSS0_CTL_176_DATA + DDRSS0_CTL_177_DATA + DDRSS0_CTL_178_DATA + DDRSS0_CTL_179_DATA + DDRSS0_CTL_180_DATA + DDRSS0_CTL_181_DATA + DDRSS0_CTL_182_DATA + DDRSS0_CTL_183_DATA + DDRSS0_CTL_184_DATA + DDRSS0_CTL_185_DATA + DDRSS0_CTL_186_DATA + DDRSS0_CTL_187_DATA + DDRSS0_CTL_188_DATA + DDRSS0_CTL_189_DATA + DDRSS0_CTL_190_DATA + DDRSS0_CTL_191_DATA + DDRSS0_CTL_192_DATA + DDRSS0_CTL_193_DATA + DDRSS0_CTL_194_DATA + DDRSS0_CTL_195_DATA + DDRSS0_CTL_196_DATA + DDRSS0_CTL_197_DATA + DDRSS0_CTL_198_DATA + DDRSS0_CTL_199_DATA + DDRSS0_CTL_200_DATA + DDRSS0_CTL_201_DATA + DDRSS0_CTL_202_DATA + DDRSS0_CTL_203_DATA + DDRSS0_CTL_204_DATA + DDRSS0_CTL_205_DATA + DDRSS0_CTL_206_DATA + DDRSS0_CTL_207_DATA + DDRSS0_CTL_208_DATA + DDRSS0_CTL_209_DATA + DDRSS0_CTL_210_DATA + DDRSS0_CTL_211_DATA + DDRSS0_CTL_212_DATA + DDRSS0_CTL_213_DATA + DDRSS0_CTL_214_DATA + DDRSS0_CTL_215_DATA + DDRSS0_CTL_216_DATA + DDRSS0_CTL_217_DATA + DDRSS0_CTL_218_DATA + DDRSS0_CTL_219_DATA + DDRSS0_CTL_220_DATA + DDRSS0_CTL_221_DATA + DDRSS0_CTL_222_DATA + DDRSS0_CTL_223_DATA + DDRSS0_CTL_224_DATA + DDRSS0_CTL_225_DATA + DDRSS0_CTL_226_DATA + DDRSS0_CTL_227_DATA + DDRSS0_CTL_228_DATA + DDRSS0_CTL_229_DATA + DDRSS0_CTL_230_DATA + DDRSS0_CTL_231_DATA + DDRSS0_CTL_232_DATA + DDRSS0_CTL_233_DATA + DDRSS0_CTL_234_DATA + DDRSS0_CTL_235_DATA + DDRSS0_CTL_236_DATA + DDRSS0_CTL_237_DATA + DDRSS0_CTL_238_DATA + DDRSS0_CTL_239_DATA + DDRSS0_CTL_240_DATA + DDRSS0_CTL_241_DATA + DDRSS0_CTL_242_DATA + DDRSS0_CTL_243_DATA + DDRSS0_CTL_244_DATA + DDRSS0_CTL_245_DATA + DDRSS0_CTL_246_DATA + DDRSS0_CTL_247_DATA + DDRSS0_CTL_248_DATA + DDRSS0_CTL_249_DATA + DDRSS0_CTL_250_DATA + DDRSS0_CTL_251_DATA + DDRSS0_CTL_252_DATA + DDRSS0_CTL_253_DATA + DDRSS0_CTL_254_DATA + DDRSS0_CTL_255_DATA + DDRSS0_CTL_256_DATA + DDRSS0_CTL_257_DATA + DDRSS0_CTL_258_DATA + DDRSS0_CTL_259_DATA + DDRSS0_CTL_260_DATA + DDRSS0_CTL_261_DATA + DDRSS0_CTL_262_DATA + DDRSS0_CTL_263_DATA + DDRSS0_CTL_264_DATA + DDRSS0_CTL_265_DATA + DDRSS0_CTL_266_DATA + DDRSS0_CTL_267_DATA + DDRSS0_CTL_268_DATA + DDRSS0_CTL_269_DATA + DDRSS0_CTL_270_DATA + DDRSS0_CTL_271_DATA + DDRSS0_CTL_272_DATA + DDRSS0_CTL_273_DATA + DDRSS0_CTL_274_DATA + DDRSS0_CTL_275_DATA + DDRSS0_CTL_276_DATA + DDRSS0_CTL_277_DATA + DDRSS0_CTL_278_DATA + DDRSS0_CTL_279_DATA + DDRSS0_CTL_280_DATA + DDRSS0_CTL_281_DATA + DDRSS0_CTL_282_DATA + DDRSS0_CTL_283_DATA + DDRSS0_CTL_284_DATA + DDRSS0_CTL_285_DATA + DDRSS0_CTL_286_DATA + DDRSS0_CTL_287_DATA + DDRSS0_CTL_288_DATA + DDRSS0_CTL_289_DATA + DDRSS0_CTL_290_DATA + DDRSS0_CTL_291_DATA + DDRSS0_CTL_292_DATA + DDRSS0_CTL_293_DATA + DDRSS0_CTL_294_DATA + DDRSS0_CTL_295_DATA + DDRSS0_CTL_296_DATA + DDRSS0_CTL_297_DATA + DDRSS0_CTL_298_DATA + DDRSS0_CTL_299_DATA + DDRSS0_CTL_300_DATA + DDRSS0_CTL_301_DATA + DDRSS0_CTL_302_DATA + DDRSS0_CTL_303_DATA + DDRSS0_CTL_304_DATA + DDRSS0_CTL_305_DATA + DDRSS0_CTL_306_DATA + DDRSS0_CTL_307_DATA + DDRSS0_CTL_308_DATA + DDRSS0_CTL_309_DATA + DDRSS0_CTL_310_DATA + DDRSS0_CTL_311_DATA + DDRSS0_CTL_312_DATA + DDRSS0_CTL_313_DATA + DDRSS0_CTL_314_DATA + DDRSS0_CTL_315_DATA + DDRSS0_CTL_316_DATA + DDRSS0_CTL_317_DATA + DDRSS0_CTL_318_DATA + DDRSS0_CTL_319_DATA + DDRSS0_CTL_320_DATA + DDRSS0_CTL_321_DATA + DDRSS0_CTL_322_DATA + DDRSS0_CTL_323_DATA + DDRSS0_CTL_324_DATA + DDRSS0_CTL_325_DATA + DDRSS0_CTL_326_DATA + DDRSS0_CTL_327_DATA + DDRSS0_CTL_328_DATA + DDRSS0_CTL_329_DATA + DDRSS0_CTL_330_DATA + DDRSS0_CTL_331_DATA + DDRSS0_CTL_332_DATA + DDRSS0_CTL_333_DATA + DDRSS0_CTL_334_DATA + DDRSS0_CTL_335_DATA + DDRSS0_CTL_336_DATA + DDRSS0_CTL_337_DATA + DDRSS0_CTL_338_DATA + DDRSS0_CTL_339_DATA + DDRSS0_CTL_340_DATA + DDRSS0_CTL_341_DATA + DDRSS0_CTL_342_DATA + DDRSS0_CTL_343_DATA + DDRSS0_CTL_344_DATA + DDRSS0_CTL_345_DATA + DDRSS0_CTL_346_DATA + DDRSS0_CTL_347_DATA + DDRSS0_CTL_348_DATA + DDRSS0_CTL_349_DATA + DDRSS0_CTL_350_DATA + DDRSS0_CTL_351_DATA + DDRSS0_CTL_352_DATA + DDRSS0_CTL_353_DATA + DDRSS0_CTL_354_DATA + DDRSS0_CTL_355_DATA + DDRSS0_CTL_356_DATA + DDRSS0_CTL_357_DATA + DDRSS0_CTL_358_DATA + DDRSS0_CTL_359_DATA + DDRSS0_CTL_360_DATA + DDRSS0_CTL_361_DATA + DDRSS0_CTL_362_DATA + DDRSS0_CTL_363_DATA + DDRSS0_CTL_364_DATA + DDRSS0_CTL_365_DATA + DDRSS0_CTL_366_DATA + DDRSS0_CTL_367_DATA + DDRSS0_CTL_368_DATA + DDRSS0_CTL_369_DATA + DDRSS0_CTL_370_DATA + DDRSS0_CTL_371_DATA + DDRSS0_CTL_372_DATA + DDRSS0_CTL_373_DATA + DDRSS0_CTL_374_DATA + DDRSS0_CTL_375_DATA + DDRSS0_CTL_376_DATA + DDRSS0_CTL_377_DATA + DDRSS0_CTL_378_DATA + DDRSS0_CTL_379_DATA + DDRSS0_CTL_380_DATA + DDRSS0_CTL_381_DATA + DDRSS0_CTL_382_DATA + DDRSS0_CTL_383_DATA + DDRSS0_CTL_384_DATA + DDRSS0_CTL_385_DATA + DDRSS0_CTL_386_DATA + DDRSS0_CTL_387_DATA + DDRSS0_CTL_388_DATA + DDRSS0_CTL_389_DATA + DDRSS0_CTL_390_DATA + DDRSS0_CTL_391_DATA + DDRSS0_CTL_392_DATA + DDRSS0_CTL_393_DATA + DDRSS0_CTL_394_DATA + DDRSS0_CTL_395_DATA + DDRSS0_CTL_396_DATA + DDRSS0_CTL_397_DATA + DDRSS0_CTL_398_DATA + DDRSS0_CTL_399_DATA + DDRSS0_CTL_400_DATA + DDRSS0_CTL_401_DATA + DDRSS0_CTL_402_DATA + DDRSS0_CTL_403_DATA + DDRSS0_CTL_404_DATA + DDRSS0_CTL_405_DATA + DDRSS0_CTL_406_DATA + DDRSS0_CTL_407_DATA + DDRSS0_CTL_408_DATA + DDRSS0_CTL_409_DATA + DDRSS0_CTL_410_DATA + DDRSS0_CTL_411_DATA + DDRSS0_CTL_412_DATA + DDRSS0_CTL_413_DATA + DDRSS0_CTL_414_DATA + DDRSS0_CTL_415_DATA + DDRSS0_CTL_416_DATA + DDRSS0_CTL_417_DATA + DDRSS0_CTL_418_DATA + DDRSS0_CTL_419_DATA + DDRSS0_CTL_420_DATA + DDRSS0_CTL_421_DATA + DDRSS0_CTL_422_DATA + DDRSS0_CTL_423_DATA + DDRSS0_CTL_424_DATA + DDRSS0_CTL_425_DATA + DDRSS0_CTL_426_DATA + DDRSS0_CTL_427_DATA + DDRSS0_CTL_428_DATA + DDRSS0_CTL_429_DATA + DDRSS0_CTL_430_DATA + DDRSS0_CTL_431_DATA + DDRSS0_CTL_432_DATA + DDRSS0_CTL_433_DATA + DDRSS0_CTL_434_DATA + DDRSS0_CTL_435_DATA + DDRSS0_CTL_436_DATA + DDRSS0_CTL_437_DATA + DDRSS0_CTL_438_DATA + DDRSS0_CTL_439_DATA + DDRSS0_CTL_440_DATA + DDRSS0_CTL_441_DATA + DDRSS0_CTL_442_DATA + DDRSS0_CTL_443_DATA + DDRSS0_CTL_444_DATA + DDRSS0_CTL_445_DATA + DDRSS0_CTL_446_DATA + DDRSS0_CTL_447_DATA + DDRSS0_CTL_448_DATA + DDRSS0_CTL_449_DATA + DDRSS0_CTL_450_DATA + DDRSS0_CTL_451_DATA + DDRSS0_CTL_452_DATA + DDRSS0_CTL_453_DATA + DDRSS0_CTL_454_DATA + DDRSS0_CTL_455_DATA + DDRSS0_CTL_456_DATA + DDRSS0_CTL_457_DATA + DDRSS0_CTL_458_DATA + >; + + ti,pi-data = < + DDRSS0_PI_00_DATA + DDRSS0_PI_01_DATA + DDRSS0_PI_02_DATA + DDRSS0_PI_03_DATA + DDRSS0_PI_04_DATA + DDRSS0_PI_05_DATA + DDRSS0_PI_06_DATA + DDRSS0_PI_07_DATA + DDRSS0_PI_08_DATA + DDRSS0_PI_09_DATA + DDRSS0_PI_10_DATA + DDRSS0_PI_11_DATA + DDRSS0_PI_12_DATA + DDRSS0_PI_13_DATA + DDRSS0_PI_14_DATA + DDRSS0_PI_15_DATA + DDRSS0_PI_16_DATA + DDRSS0_PI_17_DATA + DDRSS0_PI_18_DATA + DDRSS0_PI_19_DATA + DDRSS0_PI_20_DATA + DDRSS0_PI_21_DATA + DDRSS0_PI_22_DATA + DDRSS0_PI_23_DATA + DDRSS0_PI_24_DATA + DDRSS0_PI_25_DATA + DDRSS0_PI_26_DATA + DDRSS0_PI_27_DATA + DDRSS0_PI_28_DATA + DDRSS0_PI_29_DATA + DDRSS0_PI_30_DATA + DDRSS0_PI_31_DATA + DDRSS0_PI_32_DATA + DDRSS0_PI_33_DATA + DDRSS0_PI_34_DATA + DDRSS0_PI_35_DATA + DDRSS0_PI_36_DATA + DDRSS0_PI_37_DATA + DDRSS0_PI_38_DATA + DDRSS0_PI_39_DATA + DDRSS0_PI_40_DATA + DDRSS0_PI_41_DATA + DDRSS0_PI_42_DATA + DDRSS0_PI_43_DATA + DDRSS0_PI_44_DATA + DDRSS0_PI_45_DATA + DDRSS0_PI_46_DATA + DDRSS0_PI_47_DATA + DDRSS0_PI_48_DATA + DDRSS0_PI_49_DATA + DDRSS0_PI_50_DATA + DDRSS0_PI_51_DATA + DDRSS0_PI_52_DATA + DDRSS0_PI_53_DATA + DDRSS0_PI_54_DATA + DDRSS0_PI_55_DATA + DDRSS0_PI_56_DATA + DDRSS0_PI_57_DATA + DDRSS0_PI_58_DATA + DDRSS0_PI_59_DATA + DDRSS0_PI_60_DATA + DDRSS0_PI_61_DATA + DDRSS0_PI_62_DATA + DDRSS0_PI_63_DATA + DDRSS0_PI_64_DATA + DDRSS0_PI_65_DATA + DDRSS0_PI_66_DATA + DDRSS0_PI_67_DATA + DDRSS0_PI_68_DATA + DDRSS0_PI_69_DATA + DDRSS0_PI_70_DATA + DDRSS0_PI_71_DATA + DDRSS0_PI_72_DATA + DDRSS0_PI_73_DATA + DDRSS0_PI_74_DATA + DDRSS0_PI_75_DATA + DDRSS0_PI_76_DATA + DDRSS0_PI_77_DATA + DDRSS0_PI_78_DATA + DDRSS0_PI_79_DATA + DDRSS0_PI_80_DATA + DDRSS0_PI_81_DATA + DDRSS0_PI_82_DATA + DDRSS0_PI_83_DATA + DDRSS0_PI_84_DATA + DDRSS0_PI_85_DATA + DDRSS0_PI_86_DATA + DDRSS0_PI_87_DATA + DDRSS0_PI_88_DATA + DDRSS0_PI_89_DATA + DDRSS0_PI_90_DATA + DDRSS0_PI_91_DATA + DDRSS0_PI_92_DATA + DDRSS0_PI_93_DATA + DDRSS0_PI_94_DATA + DDRSS0_PI_95_DATA + DDRSS0_PI_96_DATA + DDRSS0_PI_97_DATA + DDRSS0_PI_98_DATA + DDRSS0_PI_99_DATA + DDRSS0_PI_100_DATA + DDRSS0_PI_101_DATA + DDRSS0_PI_102_DATA + DDRSS0_PI_103_DATA + DDRSS0_PI_104_DATA + DDRSS0_PI_105_DATA + DDRSS0_PI_106_DATA + DDRSS0_PI_107_DATA + DDRSS0_PI_108_DATA + DDRSS0_PI_109_DATA + DDRSS0_PI_110_DATA + DDRSS0_PI_111_DATA + DDRSS0_PI_112_DATA + DDRSS0_PI_113_DATA + DDRSS0_PI_114_DATA + DDRSS0_PI_115_DATA + DDRSS0_PI_116_DATA + DDRSS0_PI_117_DATA + DDRSS0_PI_118_DATA + DDRSS0_PI_119_DATA + DDRSS0_PI_120_DATA + DDRSS0_PI_121_DATA + DDRSS0_PI_122_DATA + DDRSS0_PI_123_DATA + DDRSS0_PI_124_DATA + DDRSS0_PI_125_DATA + DDRSS0_PI_126_DATA + DDRSS0_PI_127_DATA + DDRSS0_PI_128_DATA + DDRSS0_PI_129_DATA + DDRSS0_PI_130_DATA + DDRSS0_PI_131_DATA + DDRSS0_PI_132_DATA + DDRSS0_PI_133_DATA + DDRSS0_PI_134_DATA + DDRSS0_PI_135_DATA + DDRSS0_PI_136_DATA + DDRSS0_PI_137_DATA + DDRSS0_PI_138_DATA + DDRSS0_PI_139_DATA + DDRSS0_PI_140_DATA + DDRSS0_PI_141_DATA + DDRSS0_PI_142_DATA + DDRSS0_PI_143_DATA + DDRSS0_PI_144_DATA + DDRSS0_PI_145_DATA + DDRSS0_PI_146_DATA + DDRSS0_PI_147_DATA + DDRSS0_PI_148_DATA + DDRSS0_PI_149_DATA + DDRSS0_PI_150_DATA + DDRSS0_PI_151_DATA + DDRSS0_PI_152_DATA + DDRSS0_PI_153_DATA + DDRSS0_PI_154_DATA + DDRSS0_PI_155_DATA + DDRSS0_PI_156_DATA + DDRSS0_PI_157_DATA + DDRSS0_PI_158_DATA + DDRSS0_PI_159_DATA + DDRSS0_PI_160_DATA + DDRSS0_PI_161_DATA + DDRSS0_PI_162_DATA + DDRSS0_PI_163_DATA + DDRSS0_PI_164_DATA + DDRSS0_PI_165_DATA + DDRSS0_PI_166_DATA + DDRSS0_PI_167_DATA + DDRSS0_PI_168_DATA + DDRSS0_PI_169_DATA + DDRSS0_PI_170_DATA + DDRSS0_PI_171_DATA + DDRSS0_PI_172_DATA + DDRSS0_PI_173_DATA + DDRSS0_PI_174_DATA + DDRSS0_PI_175_DATA + DDRSS0_PI_176_DATA + DDRSS0_PI_177_DATA + DDRSS0_PI_178_DATA + DDRSS0_PI_179_DATA + DDRSS0_PI_180_DATA + DDRSS0_PI_181_DATA + DDRSS0_PI_182_DATA + DDRSS0_PI_183_DATA + DDRSS0_PI_184_DATA + DDRSS0_PI_185_DATA + DDRSS0_PI_186_DATA + DDRSS0_PI_187_DATA + DDRSS0_PI_188_DATA + DDRSS0_PI_189_DATA + DDRSS0_PI_190_DATA + DDRSS0_PI_191_DATA + DDRSS0_PI_192_DATA + DDRSS0_PI_193_DATA + DDRSS0_PI_194_DATA + DDRSS0_PI_195_DATA + DDRSS0_PI_196_DATA + DDRSS0_PI_197_DATA + DDRSS0_PI_198_DATA + DDRSS0_PI_199_DATA + DDRSS0_PI_200_DATA + DDRSS0_PI_201_DATA + DDRSS0_PI_202_DATA + DDRSS0_PI_203_DATA + DDRSS0_PI_204_DATA + DDRSS0_PI_205_DATA + DDRSS0_PI_206_DATA + DDRSS0_PI_207_DATA + DDRSS0_PI_208_DATA + DDRSS0_PI_209_DATA + DDRSS0_PI_210_DATA + DDRSS0_PI_211_DATA + DDRSS0_PI_212_DATA + DDRSS0_PI_213_DATA + DDRSS0_PI_214_DATA + DDRSS0_PI_215_DATA + DDRSS0_PI_216_DATA + DDRSS0_PI_217_DATA + DDRSS0_PI_218_DATA + DDRSS0_PI_219_DATA + DDRSS0_PI_220_DATA + DDRSS0_PI_221_DATA + DDRSS0_PI_222_DATA + DDRSS0_PI_223_DATA + DDRSS0_PI_224_DATA + DDRSS0_PI_225_DATA + DDRSS0_PI_226_DATA + DDRSS0_PI_227_DATA + DDRSS0_PI_228_DATA + DDRSS0_PI_229_DATA + DDRSS0_PI_230_DATA + DDRSS0_PI_231_DATA + DDRSS0_PI_232_DATA + DDRSS0_PI_233_DATA + DDRSS0_PI_234_DATA + DDRSS0_PI_235_DATA + DDRSS0_PI_236_DATA + DDRSS0_PI_237_DATA + DDRSS0_PI_238_DATA + DDRSS0_PI_239_DATA + DDRSS0_PI_240_DATA + DDRSS0_PI_241_DATA + DDRSS0_PI_242_DATA + DDRSS0_PI_243_DATA + DDRSS0_PI_244_DATA + DDRSS0_PI_245_DATA + DDRSS0_PI_246_DATA + DDRSS0_PI_247_DATA + DDRSS0_PI_248_DATA + DDRSS0_PI_249_DATA + DDRSS0_PI_250_DATA + DDRSS0_PI_251_DATA + DDRSS0_PI_252_DATA + DDRSS0_PI_253_DATA + DDRSS0_PI_254_DATA + DDRSS0_PI_255_DATA + DDRSS0_PI_256_DATA + DDRSS0_PI_257_DATA + DDRSS0_PI_258_DATA + DDRSS0_PI_259_DATA + DDRSS0_PI_260_DATA + DDRSS0_PI_261_DATA + DDRSS0_PI_262_DATA + DDRSS0_PI_263_DATA + DDRSS0_PI_264_DATA + DDRSS0_PI_265_DATA + DDRSS0_PI_266_DATA + DDRSS0_PI_267_DATA + DDRSS0_PI_268_DATA + DDRSS0_PI_269_DATA + DDRSS0_PI_270_DATA + DDRSS0_PI_271_DATA + DDRSS0_PI_272_DATA + DDRSS0_PI_273_DATA + DDRSS0_PI_274_DATA + DDRSS0_PI_275_DATA + DDRSS0_PI_276_DATA + DDRSS0_PI_277_DATA + DDRSS0_PI_278_DATA + DDRSS0_PI_279_DATA + DDRSS0_PI_280_DATA + DDRSS0_PI_281_DATA + DDRSS0_PI_282_DATA + DDRSS0_PI_283_DATA + DDRSS0_PI_284_DATA + DDRSS0_PI_285_DATA + DDRSS0_PI_286_DATA + DDRSS0_PI_287_DATA + DDRSS0_PI_288_DATA + DDRSS0_PI_289_DATA + DDRSS0_PI_290_DATA + DDRSS0_PI_291_DATA + DDRSS0_PI_292_DATA + DDRSS0_PI_293_DATA + DDRSS0_PI_294_DATA + DDRSS0_PI_295_DATA + DDRSS0_PI_296_DATA + DDRSS0_PI_297_DATA + DDRSS0_PI_298_DATA + DDRSS0_PI_299_DATA + >; + + ti,phy-data = < + DDRSS0_PHY_00_DATA + DDRSS0_PHY_01_DATA + DDRSS0_PHY_02_DATA + DDRSS0_PHY_03_DATA + DDRSS0_PHY_04_DATA + DDRSS0_PHY_05_DATA + DDRSS0_PHY_06_DATA + DDRSS0_PHY_07_DATA + DDRSS0_PHY_08_DATA + DDRSS0_PHY_09_DATA + DDRSS0_PHY_10_DATA + DDRSS0_PHY_11_DATA + DDRSS0_PHY_12_DATA + DDRSS0_PHY_13_DATA + DDRSS0_PHY_14_DATA + DDRSS0_PHY_15_DATA + DDRSS0_PHY_16_DATA + DDRSS0_PHY_17_DATA + DDRSS0_PHY_18_DATA + DDRSS0_PHY_19_DATA + DDRSS0_PHY_20_DATA + DDRSS0_PHY_21_DATA + DDRSS0_PHY_22_DATA + DDRSS0_PHY_23_DATA + DDRSS0_PHY_24_DATA + DDRSS0_PHY_25_DATA + DDRSS0_PHY_26_DATA + DDRSS0_PHY_27_DATA + DDRSS0_PHY_28_DATA + DDRSS0_PHY_29_DATA + DDRSS0_PHY_30_DATA + DDRSS0_PHY_31_DATA + DDRSS0_PHY_32_DATA + DDRSS0_PHY_33_DATA + DDRSS0_PHY_34_DATA + DDRSS0_PHY_35_DATA + DDRSS0_PHY_36_DATA + DDRSS0_PHY_37_DATA + DDRSS0_PHY_38_DATA + DDRSS0_PHY_39_DATA + DDRSS0_PHY_40_DATA + DDRSS0_PHY_41_DATA + DDRSS0_PHY_42_DATA + DDRSS0_PHY_43_DATA + DDRSS0_PHY_44_DATA + DDRSS0_PHY_45_DATA + DDRSS0_PHY_46_DATA + DDRSS0_PHY_47_DATA + DDRSS0_PHY_48_DATA + DDRSS0_PHY_49_DATA + DDRSS0_PHY_50_DATA + DDRSS0_PHY_51_DATA + DDRSS0_PHY_52_DATA + DDRSS0_PHY_53_DATA + DDRSS0_PHY_54_DATA + DDRSS0_PHY_55_DATA + DDRSS0_PHY_56_DATA + DDRSS0_PHY_57_DATA + DDRSS0_PHY_58_DATA + DDRSS0_PHY_59_DATA + DDRSS0_PHY_60_DATA + DDRSS0_PHY_61_DATA + DDRSS0_PHY_62_DATA + DDRSS0_PHY_63_DATA + DDRSS0_PHY_64_DATA + DDRSS0_PHY_65_DATA + DDRSS0_PHY_66_DATA + DDRSS0_PHY_67_DATA + DDRSS0_PHY_68_DATA + DDRSS0_PHY_69_DATA + DDRSS0_PHY_70_DATA + DDRSS0_PHY_71_DATA + DDRSS0_PHY_72_DATA + DDRSS0_PHY_73_DATA + DDRSS0_PHY_74_DATA + DDRSS0_PHY_75_DATA + DDRSS0_PHY_76_DATA + DDRSS0_PHY_77_DATA + DDRSS0_PHY_78_DATA + DDRSS0_PHY_79_DATA + DDRSS0_PHY_80_DATA + DDRSS0_PHY_81_DATA + DDRSS0_PHY_82_DATA + DDRSS0_PHY_83_DATA + DDRSS0_PHY_84_DATA + DDRSS0_PHY_85_DATA + DDRSS0_PHY_86_DATA + DDRSS0_PHY_87_DATA + DDRSS0_PHY_88_DATA + DDRSS0_PHY_89_DATA + DDRSS0_PHY_90_DATA + DDRSS0_PHY_91_DATA + DDRSS0_PHY_92_DATA + DDRSS0_PHY_93_DATA + DDRSS0_PHY_94_DATA + DDRSS0_PHY_95_DATA + DDRSS0_PHY_96_DATA + DDRSS0_PHY_97_DATA + DDRSS0_PHY_98_DATA + DDRSS0_PHY_99_DATA + DDRSS0_PHY_100_DATA + DDRSS0_PHY_101_DATA + DDRSS0_PHY_102_DATA + DDRSS0_PHY_103_DATA + DDRSS0_PHY_104_DATA + DDRSS0_PHY_105_DATA + DDRSS0_PHY_106_DATA + DDRSS0_PHY_107_DATA + DDRSS0_PHY_108_DATA + DDRSS0_PHY_109_DATA + DDRSS0_PHY_110_DATA + DDRSS0_PHY_111_DATA + DDRSS0_PHY_112_DATA + DDRSS0_PHY_113_DATA + DDRSS0_PHY_114_DATA + DDRSS0_PHY_115_DATA + DDRSS0_PHY_116_DATA + DDRSS0_PHY_117_DATA + DDRSS0_PHY_118_DATA + DDRSS0_PHY_119_DATA + DDRSS0_PHY_120_DATA + DDRSS0_PHY_121_DATA + DDRSS0_PHY_122_DATA + DDRSS0_PHY_123_DATA + DDRSS0_PHY_124_DATA + DDRSS0_PHY_125_DATA + DDRSS0_PHY_126_DATA + DDRSS0_PHY_127_DATA + DDRSS0_PHY_128_DATA + DDRSS0_PHY_129_DATA + DDRSS0_PHY_130_DATA + DDRSS0_PHY_131_DATA + DDRSS0_PHY_132_DATA + DDRSS0_PHY_133_DATA + DDRSS0_PHY_134_DATA + DDRSS0_PHY_135_DATA + DDRSS0_PHY_136_DATA + DDRSS0_PHY_137_DATA + DDRSS0_PHY_138_DATA + DDRSS0_PHY_139_DATA + DDRSS0_PHY_140_DATA + DDRSS0_PHY_141_DATA + DDRSS0_PHY_142_DATA + DDRSS0_PHY_143_DATA + DDRSS0_PHY_144_DATA + DDRSS0_PHY_145_DATA + DDRSS0_PHY_146_DATA + DDRSS0_PHY_147_DATA + DDRSS0_PHY_148_DATA + DDRSS0_PHY_149_DATA + DDRSS0_PHY_150_DATA + DDRSS0_PHY_151_DATA + DDRSS0_PHY_152_DATA + DDRSS0_PHY_153_DATA + DDRSS0_PHY_154_DATA + DDRSS0_PHY_155_DATA + DDRSS0_PHY_156_DATA + DDRSS0_PHY_157_DATA + DDRSS0_PHY_158_DATA + DDRSS0_PHY_159_DATA + DDRSS0_PHY_160_DATA + DDRSS0_PHY_161_DATA + DDRSS0_PHY_162_DATA + DDRSS0_PHY_163_DATA + DDRSS0_PHY_164_DATA + DDRSS0_PHY_165_DATA + DDRSS0_PHY_166_DATA + DDRSS0_PHY_167_DATA + DDRSS0_PHY_168_DATA + DDRSS0_PHY_169_DATA + DDRSS0_PHY_170_DATA + DDRSS0_PHY_171_DATA + DDRSS0_PHY_172_DATA + DDRSS0_PHY_173_DATA + DDRSS0_PHY_174_DATA + DDRSS0_PHY_175_DATA + DDRSS0_PHY_176_DATA + DDRSS0_PHY_177_DATA + DDRSS0_PHY_178_DATA + DDRSS0_PHY_179_DATA + DDRSS0_PHY_180_DATA + DDRSS0_PHY_181_DATA + DDRSS0_PHY_182_DATA + DDRSS0_PHY_183_DATA + DDRSS0_PHY_184_DATA + DDRSS0_PHY_185_DATA + DDRSS0_PHY_186_DATA + DDRSS0_PHY_187_DATA + DDRSS0_PHY_188_DATA + DDRSS0_PHY_189_DATA + DDRSS0_PHY_190_DATA + DDRSS0_PHY_191_DATA + DDRSS0_PHY_192_DATA + DDRSS0_PHY_193_DATA + DDRSS0_PHY_194_DATA + DDRSS0_PHY_195_DATA + DDRSS0_PHY_196_DATA + DDRSS0_PHY_197_DATA + DDRSS0_PHY_198_DATA + DDRSS0_PHY_199_DATA + DDRSS0_PHY_200_DATA + DDRSS0_PHY_201_DATA + DDRSS0_PHY_202_DATA + DDRSS0_PHY_203_DATA + DDRSS0_PHY_204_DATA + DDRSS0_PHY_205_DATA + DDRSS0_PHY_206_DATA + DDRSS0_PHY_207_DATA + DDRSS0_PHY_208_DATA + DDRSS0_PHY_209_DATA + DDRSS0_PHY_210_DATA + DDRSS0_PHY_211_DATA + DDRSS0_PHY_212_DATA + DDRSS0_PHY_213_DATA + DDRSS0_PHY_214_DATA + DDRSS0_PHY_215_DATA + DDRSS0_PHY_216_DATA + DDRSS0_PHY_217_DATA + DDRSS0_PHY_218_DATA + DDRSS0_PHY_219_DATA + DDRSS0_PHY_220_DATA + DDRSS0_PHY_221_DATA + DDRSS0_PHY_222_DATA + DDRSS0_PHY_223_DATA + DDRSS0_PHY_224_DATA + DDRSS0_PHY_225_DATA + DDRSS0_PHY_226_DATA + DDRSS0_PHY_227_DATA + DDRSS0_PHY_228_DATA + DDRSS0_PHY_229_DATA + DDRSS0_PHY_230_DATA + DDRSS0_PHY_231_DATA + DDRSS0_PHY_232_DATA + DDRSS0_PHY_233_DATA + DDRSS0_PHY_234_DATA + DDRSS0_PHY_235_DATA + DDRSS0_PHY_236_DATA + DDRSS0_PHY_237_DATA + DDRSS0_PHY_238_DATA + DDRSS0_PHY_239_DATA + DDRSS0_PHY_240_DATA + DDRSS0_PHY_241_DATA + DDRSS0_PHY_242_DATA + DDRSS0_PHY_243_DATA + DDRSS0_PHY_244_DATA + DDRSS0_PHY_245_DATA + DDRSS0_PHY_246_DATA + DDRSS0_PHY_247_DATA + DDRSS0_PHY_248_DATA + DDRSS0_PHY_249_DATA + DDRSS0_PHY_250_DATA + DDRSS0_PHY_251_DATA + DDRSS0_PHY_252_DATA + DDRSS0_PHY_253_DATA + DDRSS0_PHY_254_DATA + DDRSS0_PHY_255_DATA + DDRSS0_PHY_256_DATA + DDRSS0_PHY_257_DATA + DDRSS0_PHY_258_DATA + DDRSS0_PHY_259_DATA + DDRSS0_PHY_260_DATA + DDRSS0_PHY_261_DATA + DDRSS0_PHY_262_DATA + DDRSS0_PHY_263_DATA + DDRSS0_PHY_264_DATA + DDRSS0_PHY_265_DATA + DDRSS0_PHY_266_DATA + DDRSS0_PHY_267_DATA + DDRSS0_PHY_268_DATA + DDRSS0_PHY_269_DATA + DDRSS0_PHY_270_DATA + DDRSS0_PHY_271_DATA + DDRSS0_PHY_272_DATA + DDRSS0_PHY_273_DATA + DDRSS0_PHY_274_DATA + DDRSS0_PHY_275_DATA + DDRSS0_PHY_276_DATA + DDRSS0_PHY_277_DATA + DDRSS0_PHY_278_DATA + DDRSS0_PHY_279_DATA + DDRSS0_PHY_280_DATA + DDRSS0_PHY_281_DATA + DDRSS0_PHY_282_DATA + DDRSS0_PHY_283_DATA + DDRSS0_PHY_284_DATA + DDRSS0_PHY_285_DATA + DDRSS0_PHY_286_DATA + DDRSS0_PHY_287_DATA + DDRSS0_PHY_288_DATA + DDRSS0_PHY_289_DATA + DDRSS0_PHY_290_DATA + DDRSS0_PHY_291_DATA + DDRSS0_PHY_292_DATA + DDRSS0_PHY_293_DATA + DDRSS0_PHY_294_DATA + DDRSS0_PHY_295_DATA + DDRSS0_PHY_296_DATA + DDRSS0_PHY_297_DATA + DDRSS0_PHY_298_DATA + DDRSS0_PHY_299_DATA + DDRSS0_PHY_300_DATA + DDRSS0_PHY_301_DATA + DDRSS0_PHY_302_DATA + DDRSS0_PHY_303_DATA + DDRSS0_PHY_304_DATA + DDRSS0_PHY_305_DATA + DDRSS0_PHY_306_DATA + DDRSS0_PHY_307_DATA + DDRSS0_PHY_308_DATA + DDRSS0_PHY_309_DATA + DDRSS0_PHY_310_DATA + DDRSS0_PHY_311_DATA + DDRSS0_PHY_312_DATA + DDRSS0_PHY_313_DATA + DDRSS0_PHY_314_DATA + DDRSS0_PHY_315_DATA + DDRSS0_PHY_316_DATA + DDRSS0_PHY_317_DATA + DDRSS0_PHY_318_DATA + DDRSS0_PHY_319_DATA + DDRSS0_PHY_320_DATA + DDRSS0_PHY_321_DATA + DDRSS0_PHY_322_DATA + DDRSS0_PHY_323_DATA + DDRSS0_PHY_324_DATA + DDRSS0_PHY_325_DATA + DDRSS0_PHY_326_DATA + DDRSS0_PHY_327_DATA + DDRSS0_PHY_328_DATA + DDRSS0_PHY_329_DATA + DDRSS0_PHY_330_DATA + DDRSS0_PHY_331_DATA + DDRSS0_PHY_332_DATA + DDRSS0_PHY_333_DATA + DDRSS0_PHY_334_DATA + DDRSS0_PHY_335_DATA + DDRSS0_PHY_336_DATA + DDRSS0_PHY_337_DATA + DDRSS0_PHY_338_DATA + DDRSS0_PHY_339_DATA + DDRSS0_PHY_340_DATA + DDRSS0_PHY_341_DATA + DDRSS0_PHY_342_DATA + DDRSS0_PHY_343_DATA + DDRSS0_PHY_344_DATA + DDRSS0_PHY_345_DATA + DDRSS0_PHY_346_DATA + DDRSS0_PHY_347_DATA + DDRSS0_PHY_348_DATA + DDRSS0_PHY_349_DATA + DDRSS0_PHY_350_DATA + DDRSS0_PHY_351_DATA + DDRSS0_PHY_352_DATA + DDRSS0_PHY_353_DATA + DDRSS0_PHY_354_DATA + DDRSS0_PHY_355_DATA + DDRSS0_PHY_356_DATA + DDRSS0_PHY_357_DATA + DDRSS0_PHY_358_DATA + DDRSS0_PHY_359_DATA + DDRSS0_PHY_360_DATA + DDRSS0_PHY_361_DATA + DDRSS0_PHY_362_DATA + DDRSS0_PHY_363_DATA + DDRSS0_PHY_364_DATA + DDRSS0_PHY_365_DATA + DDRSS0_PHY_366_DATA + DDRSS0_PHY_367_DATA + DDRSS0_PHY_368_DATA + DDRSS0_PHY_369_DATA + DDRSS0_PHY_370_DATA + DDRSS0_PHY_371_DATA + DDRSS0_PHY_372_DATA + DDRSS0_PHY_373_DATA + DDRSS0_PHY_374_DATA + DDRSS0_PHY_375_DATA + DDRSS0_PHY_376_DATA + DDRSS0_PHY_377_DATA + DDRSS0_PHY_378_DATA + DDRSS0_PHY_379_DATA + DDRSS0_PHY_380_DATA + DDRSS0_PHY_381_DATA + DDRSS0_PHY_382_DATA + DDRSS0_PHY_383_DATA + DDRSS0_PHY_384_DATA + DDRSS0_PHY_385_DATA + DDRSS0_PHY_386_DATA + DDRSS0_PHY_387_DATA + DDRSS0_PHY_388_DATA + DDRSS0_PHY_389_DATA + DDRSS0_PHY_390_DATA + DDRSS0_PHY_391_DATA + DDRSS0_PHY_392_DATA + DDRSS0_PHY_393_DATA + DDRSS0_PHY_394_DATA + DDRSS0_PHY_395_DATA + DDRSS0_PHY_396_DATA + DDRSS0_PHY_397_DATA + DDRSS0_PHY_398_DATA + DDRSS0_PHY_399_DATA + DDRSS0_PHY_400_DATA + DDRSS0_PHY_401_DATA + DDRSS0_PHY_402_DATA + DDRSS0_PHY_403_DATA + DDRSS0_PHY_404_DATA + DDRSS0_PHY_405_DATA + DDRSS0_PHY_406_DATA + DDRSS0_PHY_407_DATA + DDRSS0_PHY_408_DATA + DDRSS0_PHY_409_DATA + DDRSS0_PHY_410_DATA + DDRSS0_PHY_411_DATA + DDRSS0_PHY_412_DATA + DDRSS0_PHY_413_DATA + DDRSS0_PHY_414_DATA + DDRSS0_PHY_415_DATA + DDRSS0_PHY_416_DATA + DDRSS0_PHY_417_DATA + DDRSS0_PHY_418_DATA + DDRSS0_PHY_419_DATA + DDRSS0_PHY_420_DATA + DDRSS0_PHY_421_DATA + DDRSS0_PHY_422_DATA + DDRSS0_PHY_423_DATA + DDRSS0_PHY_424_DATA + DDRSS0_PHY_425_DATA + DDRSS0_PHY_426_DATA + DDRSS0_PHY_427_DATA + DDRSS0_PHY_428_DATA + DDRSS0_PHY_429_DATA + DDRSS0_PHY_430_DATA + DDRSS0_PHY_431_DATA + DDRSS0_PHY_432_DATA + DDRSS0_PHY_433_DATA + DDRSS0_PHY_434_DATA + DDRSS0_PHY_435_DATA + DDRSS0_PHY_436_DATA + DDRSS0_PHY_437_DATA + DDRSS0_PHY_438_DATA + DDRSS0_PHY_439_DATA + DDRSS0_PHY_440_DATA + DDRSS0_PHY_441_DATA + DDRSS0_PHY_442_DATA + DDRSS0_PHY_443_DATA + DDRSS0_PHY_444_DATA + DDRSS0_PHY_445_DATA + DDRSS0_PHY_446_DATA + DDRSS0_PHY_447_DATA + DDRSS0_PHY_448_DATA + DDRSS0_PHY_449_DATA + DDRSS0_PHY_450_DATA + DDRSS0_PHY_451_DATA + DDRSS0_PHY_452_DATA + DDRSS0_PHY_453_DATA + DDRSS0_PHY_454_DATA + DDRSS0_PHY_455_DATA + DDRSS0_PHY_456_DATA + DDRSS0_PHY_457_DATA + DDRSS0_PHY_458_DATA + DDRSS0_PHY_459_DATA + DDRSS0_PHY_460_DATA + DDRSS0_PHY_461_DATA + DDRSS0_PHY_462_DATA + DDRSS0_PHY_463_DATA + DDRSS0_PHY_464_DATA + DDRSS0_PHY_465_DATA + DDRSS0_PHY_466_DATA + DDRSS0_PHY_467_DATA + DDRSS0_PHY_468_DATA + DDRSS0_PHY_469_DATA + DDRSS0_PHY_470_DATA + DDRSS0_PHY_471_DATA + DDRSS0_PHY_472_DATA + DDRSS0_PHY_473_DATA + DDRSS0_PHY_474_DATA + DDRSS0_PHY_475_DATA + DDRSS0_PHY_476_DATA + DDRSS0_PHY_477_DATA + DDRSS0_PHY_478_DATA + DDRSS0_PHY_479_DATA + DDRSS0_PHY_480_DATA + DDRSS0_PHY_481_DATA + DDRSS0_PHY_482_DATA + DDRSS0_PHY_483_DATA + DDRSS0_PHY_484_DATA + DDRSS0_PHY_485_DATA + DDRSS0_PHY_486_DATA + DDRSS0_PHY_487_DATA + DDRSS0_PHY_488_DATA + DDRSS0_PHY_489_DATA + DDRSS0_PHY_490_DATA + DDRSS0_PHY_491_DATA + DDRSS0_PHY_492_DATA + DDRSS0_PHY_493_DATA + DDRSS0_PHY_494_DATA + DDRSS0_PHY_495_DATA + DDRSS0_PHY_496_DATA + DDRSS0_PHY_497_DATA + DDRSS0_PHY_498_DATA + DDRSS0_PHY_499_DATA + DDRSS0_PHY_500_DATA + DDRSS0_PHY_501_DATA + DDRSS0_PHY_502_DATA + DDRSS0_PHY_503_DATA + DDRSS0_PHY_504_DATA + DDRSS0_PHY_505_DATA + DDRSS0_PHY_506_DATA + DDRSS0_PHY_507_DATA + DDRSS0_PHY_508_DATA + DDRSS0_PHY_509_DATA + DDRSS0_PHY_510_DATA + DDRSS0_PHY_511_DATA + DDRSS0_PHY_512_DATA + DDRSS0_PHY_513_DATA + DDRSS0_PHY_514_DATA + DDRSS0_PHY_515_DATA + DDRSS0_PHY_516_DATA + DDRSS0_PHY_517_DATA + DDRSS0_PHY_518_DATA + DDRSS0_PHY_519_DATA + DDRSS0_PHY_520_DATA + DDRSS0_PHY_521_DATA + DDRSS0_PHY_522_DATA + DDRSS0_PHY_523_DATA + DDRSS0_PHY_524_DATA + DDRSS0_PHY_525_DATA + DDRSS0_PHY_526_DATA + DDRSS0_PHY_527_DATA + DDRSS0_PHY_528_DATA + DDRSS0_PHY_529_DATA + DDRSS0_PHY_530_DATA + DDRSS0_PHY_531_DATA + DDRSS0_PHY_532_DATA + DDRSS0_PHY_533_DATA + DDRSS0_PHY_534_DATA + DDRSS0_PHY_535_DATA + DDRSS0_PHY_536_DATA + DDRSS0_PHY_537_DATA + DDRSS0_PHY_538_DATA + DDRSS0_PHY_539_DATA + DDRSS0_PHY_540_DATA + DDRSS0_PHY_541_DATA + DDRSS0_PHY_542_DATA + DDRSS0_PHY_543_DATA + DDRSS0_PHY_544_DATA + DDRSS0_PHY_545_DATA + DDRSS0_PHY_546_DATA + DDRSS0_PHY_547_DATA + DDRSS0_PHY_548_DATA + DDRSS0_PHY_549_DATA + DDRSS0_PHY_550_DATA + DDRSS0_PHY_551_DATA + DDRSS0_PHY_552_DATA + DDRSS0_PHY_553_DATA + DDRSS0_PHY_554_DATA + DDRSS0_PHY_555_DATA + DDRSS0_PHY_556_DATA + DDRSS0_PHY_557_DATA + DDRSS0_PHY_558_DATA + DDRSS0_PHY_559_DATA + DDRSS0_PHY_560_DATA + DDRSS0_PHY_561_DATA + DDRSS0_PHY_562_DATA + DDRSS0_PHY_563_DATA + DDRSS0_PHY_564_DATA + DDRSS0_PHY_565_DATA + DDRSS0_PHY_566_DATA + DDRSS0_PHY_567_DATA + DDRSS0_PHY_568_DATA + DDRSS0_PHY_569_DATA + DDRSS0_PHY_570_DATA + DDRSS0_PHY_571_DATA + DDRSS0_PHY_572_DATA + DDRSS0_PHY_573_DATA + DDRSS0_PHY_574_DATA + DDRSS0_PHY_575_DATA + DDRSS0_PHY_576_DATA + DDRSS0_PHY_577_DATA + DDRSS0_PHY_578_DATA + DDRSS0_PHY_579_DATA + DDRSS0_PHY_580_DATA + DDRSS0_PHY_581_DATA + DDRSS0_PHY_582_DATA + DDRSS0_PHY_583_DATA + DDRSS0_PHY_584_DATA + DDRSS0_PHY_585_DATA + DDRSS0_PHY_586_DATA + DDRSS0_PHY_587_DATA + DDRSS0_PHY_588_DATA + DDRSS0_PHY_589_DATA + DDRSS0_PHY_590_DATA + DDRSS0_PHY_591_DATA + DDRSS0_PHY_592_DATA + DDRSS0_PHY_593_DATA + DDRSS0_PHY_594_DATA + DDRSS0_PHY_595_DATA + DDRSS0_PHY_596_DATA + DDRSS0_PHY_597_DATA + DDRSS0_PHY_598_DATA + DDRSS0_PHY_599_DATA + DDRSS0_PHY_600_DATA + DDRSS0_PHY_601_DATA + DDRSS0_PHY_602_DATA + DDRSS0_PHY_603_DATA + DDRSS0_PHY_604_DATA + DDRSS0_PHY_605_DATA + DDRSS0_PHY_606_DATA + DDRSS0_PHY_607_DATA + DDRSS0_PHY_608_DATA + DDRSS0_PHY_609_DATA + DDRSS0_PHY_610_DATA + DDRSS0_PHY_611_DATA + DDRSS0_PHY_612_DATA + DDRSS0_PHY_613_DATA + DDRSS0_PHY_614_DATA + DDRSS0_PHY_615_DATA + DDRSS0_PHY_616_DATA + DDRSS0_PHY_617_DATA + DDRSS0_PHY_618_DATA + DDRSS0_PHY_619_DATA + DDRSS0_PHY_620_DATA + DDRSS0_PHY_621_DATA + DDRSS0_PHY_622_DATA + DDRSS0_PHY_623_DATA + DDRSS0_PHY_624_DATA + DDRSS0_PHY_625_DATA + DDRSS0_PHY_626_DATA + DDRSS0_PHY_627_DATA + DDRSS0_PHY_628_DATA + DDRSS0_PHY_629_DATA + DDRSS0_PHY_630_DATA + DDRSS0_PHY_631_DATA + DDRSS0_PHY_632_DATA + DDRSS0_PHY_633_DATA + DDRSS0_PHY_634_DATA + DDRSS0_PHY_635_DATA + DDRSS0_PHY_636_DATA + DDRSS0_PHY_637_DATA + DDRSS0_PHY_638_DATA + DDRSS0_PHY_639_DATA + DDRSS0_PHY_640_DATA + DDRSS0_PHY_641_DATA + DDRSS0_PHY_642_DATA + DDRSS0_PHY_643_DATA + DDRSS0_PHY_644_DATA + DDRSS0_PHY_645_DATA + DDRSS0_PHY_646_DATA + DDRSS0_PHY_647_DATA + DDRSS0_PHY_648_DATA + DDRSS0_PHY_649_DATA + DDRSS0_PHY_650_DATA + DDRSS0_PHY_651_DATA + DDRSS0_PHY_652_DATA + DDRSS0_PHY_653_DATA + DDRSS0_PHY_654_DATA + DDRSS0_PHY_655_DATA + DDRSS0_PHY_656_DATA + DDRSS0_PHY_657_DATA + DDRSS0_PHY_658_DATA + DDRSS0_PHY_659_DATA + DDRSS0_PHY_660_DATA + DDRSS0_PHY_661_DATA + DDRSS0_PHY_662_DATA + DDRSS0_PHY_663_DATA + DDRSS0_PHY_664_DATA + DDRSS0_PHY_665_DATA + DDRSS0_PHY_666_DATA + DDRSS0_PHY_667_DATA + DDRSS0_PHY_668_DATA + DDRSS0_PHY_669_DATA + DDRSS0_PHY_670_DATA + DDRSS0_PHY_671_DATA + DDRSS0_PHY_672_DATA + DDRSS0_PHY_673_DATA + DDRSS0_PHY_674_DATA + DDRSS0_PHY_675_DATA + DDRSS0_PHY_676_DATA + DDRSS0_PHY_677_DATA + DDRSS0_PHY_678_DATA + DDRSS0_PHY_679_DATA + DDRSS0_PHY_680_DATA + DDRSS0_PHY_681_DATA + DDRSS0_PHY_682_DATA + DDRSS0_PHY_683_DATA + DDRSS0_PHY_684_DATA + DDRSS0_PHY_685_DATA + DDRSS0_PHY_686_DATA + DDRSS0_PHY_687_DATA + DDRSS0_PHY_688_DATA + DDRSS0_PHY_689_DATA + DDRSS0_PHY_690_DATA + DDRSS0_PHY_691_DATA + DDRSS0_PHY_692_DATA + DDRSS0_PHY_693_DATA + DDRSS0_PHY_694_DATA + DDRSS0_PHY_695_DATA + DDRSS0_PHY_696_DATA + DDRSS0_PHY_697_DATA + DDRSS0_PHY_698_DATA + DDRSS0_PHY_699_DATA + DDRSS0_PHY_700_DATA + DDRSS0_PHY_701_DATA + DDRSS0_PHY_702_DATA + DDRSS0_PHY_703_DATA + DDRSS0_PHY_704_DATA + DDRSS0_PHY_705_DATA + DDRSS0_PHY_706_DATA + DDRSS0_PHY_707_DATA + DDRSS0_PHY_708_DATA + DDRSS0_PHY_709_DATA + DDRSS0_PHY_710_DATA + DDRSS0_PHY_711_DATA + DDRSS0_PHY_712_DATA + DDRSS0_PHY_713_DATA + DDRSS0_PHY_714_DATA + DDRSS0_PHY_715_DATA + DDRSS0_PHY_716_DATA + DDRSS0_PHY_717_DATA + DDRSS0_PHY_718_DATA + DDRSS0_PHY_719_DATA + DDRSS0_PHY_720_DATA + DDRSS0_PHY_721_DATA + DDRSS0_PHY_722_DATA + DDRSS0_PHY_723_DATA + DDRSS0_PHY_724_DATA + DDRSS0_PHY_725_DATA + DDRSS0_PHY_726_DATA + DDRSS0_PHY_727_DATA + DDRSS0_PHY_728_DATA + DDRSS0_PHY_729_DATA + DDRSS0_PHY_730_DATA + DDRSS0_PHY_731_DATA + DDRSS0_PHY_732_DATA + DDRSS0_PHY_733_DATA + DDRSS0_PHY_734_DATA + DDRSS0_PHY_735_DATA + DDRSS0_PHY_736_DATA + DDRSS0_PHY_737_DATA + DDRSS0_PHY_738_DATA + DDRSS0_PHY_739_DATA + DDRSS0_PHY_740_DATA + DDRSS0_PHY_741_DATA + DDRSS0_PHY_742_DATA + DDRSS0_PHY_743_DATA + DDRSS0_PHY_744_DATA + DDRSS0_PHY_745_DATA + DDRSS0_PHY_746_DATA + DDRSS0_PHY_747_DATA + DDRSS0_PHY_748_DATA + DDRSS0_PHY_749_DATA + DDRSS0_PHY_750_DATA + DDRSS0_PHY_751_DATA + DDRSS0_PHY_752_DATA + DDRSS0_PHY_753_DATA + DDRSS0_PHY_754_DATA + DDRSS0_PHY_755_DATA + DDRSS0_PHY_756_DATA + DDRSS0_PHY_757_DATA + DDRSS0_PHY_758_DATA + DDRSS0_PHY_759_DATA + DDRSS0_PHY_760_DATA + DDRSS0_PHY_761_DATA + DDRSS0_PHY_762_DATA + DDRSS0_PHY_763_DATA + DDRSS0_PHY_764_DATA + DDRSS0_PHY_765_DATA + DDRSS0_PHY_766_DATA + DDRSS0_PHY_767_DATA + DDRSS0_PHY_768_DATA + DDRSS0_PHY_769_DATA + DDRSS0_PHY_770_DATA + DDRSS0_PHY_771_DATA + DDRSS0_PHY_772_DATA + DDRSS0_PHY_773_DATA + DDRSS0_PHY_774_DATA + DDRSS0_PHY_775_DATA + DDRSS0_PHY_776_DATA + DDRSS0_PHY_777_DATA + DDRSS0_PHY_778_DATA + DDRSS0_PHY_779_DATA + DDRSS0_PHY_780_DATA + DDRSS0_PHY_781_DATA + DDRSS0_PHY_782_DATA + DDRSS0_PHY_783_DATA + DDRSS0_PHY_784_DATA + DDRSS0_PHY_785_DATA + DDRSS0_PHY_786_DATA + DDRSS0_PHY_787_DATA + DDRSS0_PHY_788_DATA + DDRSS0_PHY_789_DATA + DDRSS0_PHY_790_DATA + DDRSS0_PHY_791_DATA + DDRSS0_PHY_792_DATA + DDRSS0_PHY_793_DATA + DDRSS0_PHY_794_DATA + DDRSS0_PHY_795_DATA + DDRSS0_PHY_796_DATA + DDRSS0_PHY_797_DATA + DDRSS0_PHY_798_DATA + DDRSS0_PHY_799_DATA + DDRSS0_PHY_800_DATA + DDRSS0_PHY_801_DATA + DDRSS0_PHY_802_DATA + DDRSS0_PHY_803_DATA + DDRSS0_PHY_804_DATA + DDRSS0_PHY_805_DATA + DDRSS0_PHY_806_DATA + DDRSS0_PHY_807_DATA + DDRSS0_PHY_808_DATA + DDRSS0_PHY_809_DATA + DDRSS0_PHY_810_DATA + DDRSS0_PHY_811_DATA + DDRSS0_PHY_812_DATA + DDRSS0_PHY_813_DATA + DDRSS0_PHY_814_DATA + DDRSS0_PHY_815_DATA + DDRSS0_PHY_816_DATA + DDRSS0_PHY_817_DATA + DDRSS0_PHY_818_DATA + DDRSS0_PHY_819_DATA + DDRSS0_PHY_820_DATA + DDRSS0_PHY_821_DATA + DDRSS0_PHY_822_DATA + DDRSS0_PHY_823_DATA + DDRSS0_PHY_824_DATA + DDRSS0_PHY_825_DATA + DDRSS0_PHY_826_DATA + DDRSS0_PHY_827_DATA + DDRSS0_PHY_828_DATA + DDRSS0_PHY_829_DATA + DDRSS0_PHY_830_DATA + DDRSS0_PHY_831_DATA + DDRSS0_PHY_832_DATA + DDRSS0_PHY_833_DATA + DDRSS0_PHY_834_DATA + DDRSS0_PHY_835_DATA + DDRSS0_PHY_836_DATA + DDRSS0_PHY_837_DATA + DDRSS0_PHY_838_DATA + DDRSS0_PHY_839_DATA + DDRSS0_PHY_840_DATA + DDRSS0_PHY_841_DATA + DDRSS0_PHY_842_DATA + DDRSS0_PHY_843_DATA + DDRSS0_PHY_844_DATA + DDRSS0_PHY_845_DATA + DDRSS0_PHY_846_DATA + DDRSS0_PHY_847_DATA + DDRSS0_PHY_848_DATA + DDRSS0_PHY_849_DATA + DDRSS0_PHY_850_DATA + DDRSS0_PHY_851_DATA + DDRSS0_PHY_852_DATA + DDRSS0_PHY_853_DATA + DDRSS0_PHY_854_DATA + DDRSS0_PHY_855_DATA + DDRSS0_PHY_856_DATA + DDRSS0_PHY_857_DATA + DDRSS0_PHY_858_DATA + DDRSS0_PHY_859_DATA + DDRSS0_PHY_860_DATA + DDRSS0_PHY_861_DATA + DDRSS0_PHY_862_DATA + DDRSS0_PHY_863_DATA + DDRSS0_PHY_864_DATA + DDRSS0_PHY_865_DATA + DDRSS0_PHY_866_DATA + DDRSS0_PHY_867_DATA + DDRSS0_PHY_868_DATA + DDRSS0_PHY_869_DATA + DDRSS0_PHY_870_DATA + DDRSS0_PHY_871_DATA + DDRSS0_PHY_872_DATA + DDRSS0_PHY_873_DATA + DDRSS0_PHY_874_DATA + DDRSS0_PHY_875_DATA + DDRSS0_PHY_876_DATA + DDRSS0_PHY_877_DATA + DDRSS0_PHY_878_DATA + DDRSS0_PHY_879_DATA + DDRSS0_PHY_880_DATA + DDRSS0_PHY_881_DATA + DDRSS0_PHY_882_DATA + DDRSS0_PHY_883_DATA + DDRSS0_PHY_884_DATA + DDRSS0_PHY_885_DATA + DDRSS0_PHY_886_DATA + DDRSS0_PHY_887_DATA + DDRSS0_PHY_888_DATA + DDRSS0_PHY_889_DATA + DDRSS0_PHY_890_DATA + DDRSS0_PHY_891_DATA + DDRSS0_PHY_892_DATA + DDRSS0_PHY_893_DATA + DDRSS0_PHY_894_DATA + DDRSS0_PHY_895_DATA + DDRSS0_PHY_896_DATA + DDRSS0_PHY_897_DATA + DDRSS0_PHY_898_DATA + DDRSS0_PHY_899_DATA + DDRSS0_PHY_900_DATA + DDRSS0_PHY_901_DATA + DDRSS0_PHY_902_DATA + DDRSS0_PHY_903_DATA + DDRSS0_PHY_904_DATA + DDRSS0_PHY_905_DATA + DDRSS0_PHY_906_DATA + DDRSS0_PHY_907_DATA + DDRSS0_PHY_908_DATA + DDRSS0_PHY_909_DATA + DDRSS0_PHY_910_DATA + DDRSS0_PHY_911_DATA + DDRSS0_PHY_912_DATA + DDRSS0_PHY_913_DATA + DDRSS0_PHY_914_DATA + DDRSS0_PHY_915_DATA + DDRSS0_PHY_916_DATA + DDRSS0_PHY_917_DATA + DDRSS0_PHY_918_DATA + DDRSS0_PHY_919_DATA + DDRSS0_PHY_920_DATA + DDRSS0_PHY_921_DATA + DDRSS0_PHY_922_DATA + DDRSS0_PHY_923_DATA + DDRSS0_PHY_924_DATA + DDRSS0_PHY_925_DATA + DDRSS0_PHY_926_DATA + DDRSS0_PHY_927_DATA + DDRSS0_PHY_928_DATA + DDRSS0_PHY_929_DATA + DDRSS0_PHY_930_DATA + DDRSS0_PHY_931_DATA + DDRSS0_PHY_932_DATA + DDRSS0_PHY_933_DATA + DDRSS0_PHY_934_DATA + DDRSS0_PHY_935_DATA + DDRSS0_PHY_936_DATA + DDRSS0_PHY_937_DATA + DDRSS0_PHY_938_DATA + DDRSS0_PHY_939_DATA + DDRSS0_PHY_940_DATA + DDRSS0_PHY_941_DATA + DDRSS0_PHY_942_DATA + DDRSS0_PHY_943_DATA + DDRSS0_PHY_944_DATA + DDRSS0_PHY_945_DATA + DDRSS0_PHY_946_DATA + DDRSS0_PHY_947_DATA + DDRSS0_PHY_948_DATA + DDRSS0_PHY_949_DATA + DDRSS0_PHY_950_DATA + DDRSS0_PHY_951_DATA + DDRSS0_PHY_952_DATA + DDRSS0_PHY_953_DATA + DDRSS0_PHY_954_DATA + DDRSS0_PHY_955_DATA + DDRSS0_PHY_956_DATA + DDRSS0_PHY_957_DATA + DDRSS0_PHY_958_DATA + DDRSS0_PHY_959_DATA + DDRSS0_PHY_960_DATA + DDRSS0_PHY_961_DATA + DDRSS0_PHY_962_DATA + DDRSS0_PHY_963_DATA + DDRSS0_PHY_964_DATA + DDRSS0_PHY_965_DATA + DDRSS0_PHY_966_DATA + DDRSS0_PHY_967_DATA + DDRSS0_PHY_968_DATA + DDRSS0_PHY_969_DATA + DDRSS0_PHY_970_DATA + DDRSS0_PHY_971_DATA + DDRSS0_PHY_972_DATA + DDRSS0_PHY_973_DATA + DDRSS0_PHY_974_DATA + DDRSS0_PHY_975_DATA + DDRSS0_PHY_976_DATA + DDRSS0_PHY_977_DATA + DDRSS0_PHY_978_DATA + DDRSS0_PHY_979_DATA + DDRSS0_PHY_980_DATA + DDRSS0_PHY_981_DATA + DDRSS0_PHY_982_DATA + DDRSS0_PHY_983_DATA + DDRSS0_PHY_984_DATA + DDRSS0_PHY_985_DATA + DDRSS0_PHY_986_DATA + DDRSS0_PHY_987_DATA + DDRSS0_PHY_988_DATA + DDRSS0_PHY_989_DATA + DDRSS0_PHY_990_DATA + DDRSS0_PHY_991_DATA + DDRSS0_PHY_992_DATA + DDRSS0_PHY_993_DATA + DDRSS0_PHY_994_DATA + DDRSS0_PHY_995_DATA + DDRSS0_PHY_996_DATA + DDRSS0_PHY_997_DATA + DDRSS0_PHY_998_DATA + DDRSS0_PHY_999_DATA + DDRSS0_PHY_1000_DATA + DDRSS0_PHY_1001_DATA + DDRSS0_PHY_1002_DATA + DDRSS0_PHY_1003_DATA + DDRSS0_PHY_1004_DATA + DDRSS0_PHY_1005_DATA + DDRSS0_PHY_1006_DATA + DDRSS0_PHY_1007_DATA + DDRSS0_PHY_1008_DATA + DDRSS0_PHY_1009_DATA + DDRSS0_PHY_1010_DATA + DDRSS0_PHY_1011_DATA + DDRSS0_PHY_1012_DATA + DDRSS0_PHY_1013_DATA + DDRSS0_PHY_1014_DATA + DDRSS0_PHY_1015_DATA + DDRSS0_PHY_1016_DATA + DDRSS0_PHY_1017_DATA + DDRSS0_PHY_1018_DATA + DDRSS0_PHY_1019_DATA + DDRSS0_PHY_1020_DATA + DDRSS0_PHY_1021_DATA + DDRSS0_PHY_1022_DATA + DDRSS0_PHY_1023_DATA + DDRSS0_PHY_1024_DATA + DDRSS0_PHY_1025_DATA + DDRSS0_PHY_1026_DATA + DDRSS0_PHY_1027_DATA + DDRSS0_PHY_1028_DATA + DDRSS0_PHY_1029_DATA + DDRSS0_PHY_1030_DATA + DDRSS0_PHY_1031_DATA + DDRSS0_PHY_1032_DATA + DDRSS0_PHY_1033_DATA + DDRSS0_PHY_1034_DATA + DDRSS0_PHY_1035_DATA + DDRSS0_PHY_1036_DATA + DDRSS0_PHY_1037_DATA + DDRSS0_PHY_1038_DATA + DDRSS0_PHY_1039_DATA + DDRSS0_PHY_1040_DATA + DDRSS0_PHY_1041_DATA + DDRSS0_PHY_1042_DATA + DDRSS0_PHY_1043_DATA + DDRSS0_PHY_1044_DATA + DDRSS0_PHY_1045_DATA + DDRSS0_PHY_1046_DATA + DDRSS0_PHY_1047_DATA + DDRSS0_PHY_1048_DATA + DDRSS0_PHY_1049_DATA + DDRSS0_PHY_1050_DATA + DDRSS0_PHY_1051_DATA + DDRSS0_PHY_1052_DATA + DDRSS0_PHY_1053_DATA + DDRSS0_PHY_1054_DATA + DDRSS0_PHY_1055_DATA + DDRSS0_PHY_1056_DATA + DDRSS0_PHY_1057_DATA + DDRSS0_PHY_1058_DATA + DDRSS0_PHY_1059_DATA + DDRSS0_PHY_1060_DATA + DDRSS0_PHY_1061_DATA + DDRSS0_PHY_1062_DATA + DDRSS0_PHY_1063_DATA + DDRSS0_PHY_1064_DATA + DDRSS0_PHY_1065_DATA + DDRSS0_PHY_1066_DATA + DDRSS0_PHY_1067_DATA + DDRSS0_PHY_1068_DATA + DDRSS0_PHY_1069_DATA + DDRSS0_PHY_1070_DATA + DDRSS0_PHY_1071_DATA + DDRSS0_PHY_1072_DATA + DDRSS0_PHY_1073_DATA + DDRSS0_PHY_1074_DATA + DDRSS0_PHY_1075_DATA + DDRSS0_PHY_1076_DATA + DDRSS0_PHY_1077_DATA + DDRSS0_PHY_1078_DATA + DDRSS0_PHY_1079_DATA + DDRSS0_PHY_1080_DATA + DDRSS0_PHY_1081_DATA + DDRSS0_PHY_1082_DATA + DDRSS0_PHY_1083_DATA + DDRSS0_PHY_1084_DATA + DDRSS0_PHY_1085_DATA + DDRSS0_PHY_1086_DATA + DDRSS0_PHY_1087_DATA + DDRSS0_PHY_1088_DATA + DDRSS0_PHY_1089_DATA + DDRSS0_PHY_1090_DATA + DDRSS0_PHY_1091_DATA + DDRSS0_PHY_1092_DATA + DDRSS0_PHY_1093_DATA + DDRSS0_PHY_1094_DATA + DDRSS0_PHY_1095_DATA + DDRSS0_PHY_1096_DATA + DDRSS0_PHY_1097_DATA + DDRSS0_PHY_1098_DATA + DDRSS0_PHY_1099_DATA + DDRSS0_PHY_1100_DATA + DDRSS0_PHY_1101_DATA + DDRSS0_PHY_1102_DATA + DDRSS0_PHY_1103_DATA + DDRSS0_PHY_1104_DATA + DDRSS0_PHY_1105_DATA + DDRSS0_PHY_1106_DATA + DDRSS0_PHY_1107_DATA + DDRSS0_PHY_1108_DATA + DDRSS0_PHY_1109_DATA + DDRSS0_PHY_1110_DATA + DDRSS0_PHY_1111_DATA + DDRSS0_PHY_1112_DATA + DDRSS0_PHY_1113_DATA + DDRSS0_PHY_1114_DATA + DDRSS0_PHY_1115_DATA + DDRSS0_PHY_1116_DATA + DDRSS0_PHY_1117_DATA + DDRSS0_PHY_1118_DATA + DDRSS0_PHY_1119_DATA + DDRSS0_PHY_1120_DATA + DDRSS0_PHY_1121_DATA + DDRSS0_PHY_1122_DATA + DDRSS0_PHY_1123_DATA + DDRSS0_PHY_1124_DATA + DDRSS0_PHY_1125_DATA + DDRSS0_PHY_1126_DATA + DDRSS0_PHY_1127_DATA + DDRSS0_PHY_1128_DATA + DDRSS0_PHY_1129_DATA + DDRSS0_PHY_1130_DATA + DDRSS0_PHY_1131_DATA + DDRSS0_PHY_1132_DATA + DDRSS0_PHY_1133_DATA + DDRSS0_PHY_1134_DATA + DDRSS0_PHY_1135_DATA + DDRSS0_PHY_1136_DATA + DDRSS0_PHY_1137_DATA + DDRSS0_PHY_1138_DATA + DDRSS0_PHY_1139_DATA + DDRSS0_PHY_1140_DATA + DDRSS0_PHY_1141_DATA + DDRSS0_PHY_1142_DATA + DDRSS0_PHY_1143_DATA + DDRSS0_PHY_1144_DATA + DDRSS0_PHY_1145_DATA + DDRSS0_PHY_1146_DATA + DDRSS0_PHY_1147_DATA + DDRSS0_PHY_1148_DATA + DDRSS0_PHY_1149_DATA + DDRSS0_PHY_1150_DATA + DDRSS0_PHY_1151_DATA + DDRSS0_PHY_1152_DATA + DDRSS0_PHY_1153_DATA + DDRSS0_PHY_1154_DATA + DDRSS0_PHY_1155_DATA + DDRSS0_PHY_1156_DATA + DDRSS0_PHY_1157_DATA + DDRSS0_PHY_1158_DATA + DDRSS0_PHY_1159_DATA + DDRSS0_PHY_1160_DATA + DDRSS0_PHY_1161_DATA + DDRSS0_PHY_1162_DATA + DDRSS0_PHY_1163_DATA + DDRSS0_PHY_1164_DATA + DDRSS0_PHY_1165_DATA + DDRSS0_PHY_1166_DATA + DDRSS0_PHY_1167_DATA + DDRSS0_PHY_1168_DATA + DDRSS0_PHY_1169_DATA + DDRSS0_PHY_1170_DATA + DDRSS0_PHY_1171_DATA + DDRSS0_PHY_1172_DATA + DDRSS0_PHY_1173_DATA + DDRSS0_PHY_1174_DATA + DDRSS0_PHY_1175_DATA + DDRSS0_PHY_1176_DATA + DDRSS0_PHY_1177_DATA + DDRSS0_PHY_1178_DATA + DDRSS0_PHY_1179_DATA + DDRSS0_PHY_1180_DATA + DDRSS0_PHY_1181_DATA + DDRSS0_PHY_1182_DATA + DDRSS0_PHY_1183_DATA + DDRSS0_PHY_1184_DATA + DDRSS0_PHY_1185_DATA + DDRSS0_PHY_1186_DATA + DDRSS0_PHY_1187_DATA + DDRSS0_PHY_1188_DATA + DDRSS0_PHY_1189_DATA + DDRSS0_PHY_1190_DATA + DDRSS0_PHY_1191_DATA + DDRSS0_PHY_1192_DATA + DDRSS0_PHY_1193_DATA + DDRSS0_PHY_1194_DATA + DDRSS0_PHY_1195_DATA + DDRSS0_PHY_1196_DATA + DDRSS0_PHY_1197_DATA + DDRSS0_PHY_1198_DATA + DDRSS0_PHY_1199_DATA + DDRSS0_PHY_1200_DATA + DDRSS0_PHY_1201_DATA + DDRSS0_PHY_1202_DATA + DDRSS0_PHY_1203_DATA + DDRSS0_PHY_1204_DATA + DDRSS0_PHY_1205_DATA + DDRSS0_PHY_1206_DATA + DDRSS0_PHY_1207_DATA + DDRSS0_PHY_1208_DATA + DDRSS0_PHY_1209_DATA + DDRSS0_PHY_1210_DATA + DDRSS0_PHY_1211_DATA + DDRSS0_PHY_1212_DATA + DDRSS0_PHY_1213_DATA + DDRSS0_PHY_1214_DATA + DDRSS0_PHY_1215_DATA + DDRSS0_PHY_1216_DATA + DDRSS0_PHY_1217_DATA + DDRSS0_PHY_1218_DATA + DDRSS0_PHY_1219_DATA + DDRSS0_PHY_1220_DATA + DDRSS0_PHY_1221_DATA + DDRSS0_PHY_1222_DATA + DDRSS0_PHY_1223_DATA + DDRSS0_PHY_1224_DATA + DDRSS0_PHY_1225_DATA + DDRSS0_PHY_1226_DATA + DDRSS0_PHY_1227_DATA + DDRSS0_PHY_1228_DATA + DDRSS0_PHY_1229_DATA + DDRSS0_PHY_1230_DATA + DDRSS0_PHY_1231_DATA + DDRSS0_PHY_1232_DATA + DDRSS0_PHY_1233_DATA + DDRSS0_PHY_1234_DATA + DDRSS0_PHY_1235_DATA + DDRSS0_PHY_1236_DATA + DDRSS0_PHY_1237_DATA + DDRSS0_PHY_1238_DATA + DDRSS0_PHY_1239_DATA + DDRSS0_PHY_1240_DATA + DDRSS0_PHY_1241_DATA + DDRSS0_PHY_1242_DATA + DDRSS0_PHY_1243_DATA + DDRSS0_PHY_1244_DATA + DDRSS0_PHY_1245_DATA + DDRSS0_PHY_1246_DATA + DDRSS0_PHY_1247_DATA + DDRSS0_PHY_1248_DATA + DDRSS0_PHY_1249_DATA + DDRSS0_PHY_1250_DATA + DDRSS0_PHY_1251_DATA + DDRSS0_PHY_1252_DATA + DDRSS0_PHY_1253_DATA + DDRSS0_PHY_1254_DATA + DDRSS0_PHY_1255_DATA + DDRSS0_PHY_1256_DATA + DDRSS0_PHY_1257_DATA + DDRSS0_PHY_1258_DATA + DDRSS0_PHY_1259_DATA + DDRSS0_PHY_1260_DATA + DDRSS0_PHY_1261_DATA + DDRSS0_PHY_1262_DATA + DDRSS0_PHY_1263_DATA + DDRSS0_PHY_1264_DATA + DDRSS0_PHY_1265_DATA + DDRSS0_PHY_1266_DATA + DDRSS0_PHY_1267_DATA + DDRSS0_PHY_1268_DATA + DDRSS0_PHY_1269_DATA + DDRSS0_PHY_1270_DATA + DDRSS0_PHY_1271_DATA + DDRSS0_PHY_1272_DATA + DDRSS0_PHY_1273_DATA + DDRSS0_PHY_1274_DATA + DDRSS0_PHY_1275_DATA + DDRSS0_PHY_1276_DATA + DDRSS0_PHY_1277_DATA + DDRSS0_PHY_1278_DATA + DDRSS0_PHY_1279_DATA + DDRSS0_PHY_1280_DATA + DDRSS0_PHY_1281_DATA + DDRSS0_PHY_1282_DATA + DDRSS0_PHY_1283_DATA + DDRSS0_PHY_1284_DATA + DDRSS0_PHY_1285_DATA + DDRSS0_PHY_1286_DATA + DDRSS0_PHY_1287_DATA + DDRSS0_PHY_1288_DATA + DDRSS0_PHY_1289_DATA + DDRSS0_PHY_1290_DATA + DDRSS0_PHY_1291_DATA + DDRSS0_PHY_1292_DATA + DDRSS0_PHY_1293_DATA + DDRSS0_PHY_1294_DATA + DDRSS0_PHY_1295_DATA + DDRSS0_PHY_1296_DATA + DDRSS0_PHY_1297_DATA + DDRSS0_PHY_1298_DATA + DDRSS0_PHY_1299_DATA + DDRSS0_PHY_1300_DATA + DDRSS0_PHY_1301_DATA + DDRSS0_PHY_1302_DATA + DDRSS0_PHY_1303_DATA + DDRSS0_PHY_1304_DATA + DDRSS0_PHY_1305_DATA + DDRSS0_PHY_1306_DATA + DDRSS0_PHY_1307_DATA + DDRSS0_PHY_1308_DATA + DDRSS0_PHY_1309_DATA + DDRSS0_PHY_1310_DATA + DDRSS0_PHY_1311_DATA + DDRSS0_PHY_1312_DATA + DDRSS0_PHY_1313_DATA + DDRSS0_PHY_1314_DATA + DDRSS0_PHY_1315_DATA + DDRSS0_PHY_1316_DATA + DDRSS0_PHY_1317_DATA + DDRSS0_PHY_1318_DATA + DDRSS0_PHY_1319_DATA + DDRSS0_PHY_1320_DATA + DDRSS0_PHY_1321_DATA + DDRSS0_PHY_1322_DATA + DDRSS0_PHY_1323_DATA + DDRSS0_PHY_1324_DATA + DDRSS0_PHY_1325_DATA + DDRSS0_PHY_1326_DATA + DDRSS0_PHY_1327_DATA + DDRSS0_PHY_1328_DATA + DDRSS0_PHY_1329_DATA + DDRSS0_PHY_1330_DATA + DDRSS0_PHY_1331_DATA + DDRSS0_PHY_1332_DATA + DDRSS0_PHY_1333_DATA + DDRSS0_PHY_1334_DATA + DDRSS0_PHY_1335_DATA + DDRSS0_PHY_1336_DATA + DDRSS0_PHY_1337_DATA + DDRSS0_PHY_1338_DATA + DDRSS0_PHY_1339_DATA + DDRSS0_PHY_1340_DATA + DDRSS0_PHY_1341_DATA + DDRSS0_PHY_1342_DATA + DDRSS0_PHY_1343_DATA + DDRSS0_PHY_1344_DATA + DDRSS0_PHY_1345_DATA + DDRSS0_PHY_1346_DATA + DDRSS0_PHY_1347_DATA + DDRSS0_PHY_1348_DATA + DDRSS0_PHY_1349_DATA + DDRSS0_PHY_1350_DATA + DDRSS0_PHY_1351_DATA + DDRSS0_PHY_1352_DATA + DDRSS0_PHY_1353_DATA + DDRSS0_PHY_1354_DATA + DDRSS0_PHY_1355_DATA + DDRSS0_PHY_1356_DATA + DDRSS0_PHY_1357_DATA + DDRSS0_PHY_1358_DATA + DDRSS0_PHY_1359_DATA + DDRSS0_PHY_1360_DATA + DDRSS0_PHY_1361_DATA + DDRSS0_PHY_1362_DATA + DDRSS0_PHY_1363_DATA + DDRSS0_PHY_1364_DATA + DDRSS0_PHY_1365_DATA + DDRSS0_PHY_1366_DATA + DDRSS0_PHY_1367_DATA + DDRSS0_PHY_1368_DATA + DDRSS0_PHY_1369_DATA + DDRSS0_PHY_1370_DATA + DDRSS0_PHY_1371_DATA + DDRSS0_PHY_1372_DATA + DDRSS0_PHY_1373_DATA + DDRSS0_PHY_1374_DATA + DDRSS0_PHY_1375_DATA + DDRSS0_PHY_1376_DATA + DDRSS0_PHY_1377_DATA + DDRSS0_PHY_1378_DATA + DDRSS0_PHY_1379_DATA + DDRSS0_PHY_1380_DATA + DDRSS0_PHY_1381_DATA + DDRSS0_PHY_1382_DATA + DDRSS0_PHY_1383_DATA + DDRSS0_PHY_1384_DATA + DDRSS0_PHY_1385_DATA + DDRSS0_PHY_1386_DATA + DDRSS0_PHY_1387_DATA + DDRSS0_PHY_1388_DATA + DDRSS0_PHY_1389_DATA + DDRSS0_PHY_1390_DATA + DDRSS0_PHY_1391_DATA + DDRSS0_PHY_1392_DATA + DDRSS0_PHY_1393_DATA + DDRSS0_PHY_1394_DATA + DDRSS0_PHY_1395_DATA + DDRSS0_PHY_1396_DATA + DDRSS0_PHY_1397_DATA + DDRSS0_PHY_1398_DATA + DDRSS0_PHY_1399_DATA + DDRSS0_PHY_1400_DATA + DDRSS0_PHY_1401_DATA + DDRSS0_PHY_1402_DATA + DDRSS0_PHY_1403_DATA + DDRSS0_PHY_1404_DATA + DDRSS0_PHY_1405_DATA + DDRSS0_PHY_1406_DATA + DDRSS0_PHY_1407_DATA + DDRSS0_PHY_1408_DATA + DDRSS0_PHY_1409_DATA + DDRSS0_PHY_1410_DATA + DDRSS0_PHY_1411_DATA + DDRSS0_PHY_1412_DATA + DDRSS0_PHY_1413_DATA + DDRSS0_PHY_1414_DATA + DDRSS0_PHY_1415_DATA + DDRSS0_PHY_1416_DATA + DDRSS0_PHY_1417_DATA + DDRSS0_PHY_1418_DATA + DDRSS0_PHY_1419_DATA + DDRSS0_PHY_1420_DATA + DDRSS0_PHY_1421_DATA + DDRSS0_PHY_1422_DATA + >; + }; + + memorycontroller1: memorycontroller@29b0000 { + compatible = "ti,j721s2-ddrss"; + reg = <0x0 0x029b0000 0x0 0x4000>, + <0x0 0x0114000 0x0 0x100>; + reg-names = "cfg", "ctrl_mmr_lp4"; + power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>, + <&k3_pds 132 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 192 1>, <&k3_clks 78 2>; + ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>; + ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>; + ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>; + ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>; + instance = <1>; + + bootph-pre-ram; + + ti,ctl-data = < + DDRSS1_CTL_00_DATA + DDRSS1_CTL_01_DATA + DDRSS1_CTL_02_DATA + DDRSS1_CTL_03_DATA + DDRSS1_CTL_04_DATA + DDRSS1_CTL_05_DATA + DDRSS1_CTL_06_DATA + DDRSS1_CTL_07_DATA + DDRSS1_CTL_08_DATA + DDRSS1_CTL_09_DATA + DDRSS1_CTL_10_DATA + DDRSS1_CTL_11_DATA + DDRSS1_CTL_12_DATA + DDRSS1_CTL_13_DATA + DDRSS1_CTL_14_DATA + DDRSS1_CTL_15_DATA + DDRSS1_CTL_16_DATA + DDRSS1_CTL_17_DATA + DDRSS1_CTL_18_DATA + DDRSS1_CTL_19_DATA + DDRSS1_CTL_20_DATA + DDRSS1_CTL_21_DATA + DDRSS1_CTL_22_DATA + DDRSS1_CTL_23_DATA + DDRSS1_CTL_24_DATA + DDRSS1_CTL_25_DATA + DDRSS1_CTL_26_DATA + DDRSS1_CTL_27_DATA + DDRSS1_CTL_28_DATA + DDRSS1_CTL_29_DATA + DDRSS1_CTL_30_DATA + DDRSS1_CTL_31_DATA + DDRSS1_CTL_32_DATA + DDRSS1_CTL_33_DATA + DDRSS1_CTL_34_DATA + DDRSS1_CTL_35_DATA + DDRSS1_CTL_36_DATA + DDRSS1_CTL_37_DATA + DDRSS1_CTL_38_DATA + DDRSS1_CTL_39_DATA + DDRSS1_CTL_40_DATA + DDRSS1_CTL_41_DATA + DDRSS1_CTL_42_DATA + DDRSS1_CTL_43_DATA + DDRSS1_CTL_44_DATA + DDRSS1_CTL_45_DATA + DDRSS1_CTL_46_DATA + DDRSS1_CTL_47_DATA + DDRSS1_CTL_48_DATA + DDRSS1_CTL_49_DATA + DDRSS1_CTL_50_DATA + DDRSS1_CTL_51_DATA + DDRSS1_CTL_52_DATA + DDRSS1_CTL_53_DATA + DDRSS1_CTL_54_DATA + DDRSS1_CTL_55_DATA + DDRSS1_CTL_56_DATA + DDRSS1_CTL_57_DATA + DDRSS1_CTL_58_DATA + DDRSS1_CTL_59_DATA + DDRSS1_CTL_60_DATA + DDRSS1_CTL_61_DATA + DDRSS1_CTL_62_DATA + DDRSS1_CTL_63_DATA + DDRSS1_CTL_64_DATA + DDRSS1_CTL_65_DATA + DDRSS1_CTL_66_DATA + DDRSS1_CTL_67_DATA + DDRSS1_CTL_68_DATA + DDRSS1_CTL_69_DATA + DDRSS1_CTL_70_DATA + DDRSS1_CTL_71_DATA + DDRSS1_CTL_72_DATA + DDRSS1_CTL_73_DATA + DDRSS1_CTL_74_DATA + DDRSS1_CTL_75_DATA + DDRSS1_CTL_76_DATA + DDRSS1_CTL_77_DATA + DDRSS1_CTL_78_DATA + DDRSS1_CTL_79_DATA + DDRSS1_CTL_80_DATA + DDRSS1_CTL_81_DATA + DDRSS1_CTL_82_DATA + DDRSS1_CTL_83_DATA + DDRSS1_CTL_84_DATA + DDRSS1_CTL_85_DATA + DDRSS1_CTL_86_DATA + DDRSS1_CTL_87_DATA + DDRSS1_CTL_88_DATA + DDRSS1_CTL_89_DATA + DDRSS1_CTL_90_DATA + DDRSS1_CTL_91_DATA + DDRSS1_CTL_92_DATA + DDRSS1_CTL_93_DATA + DDRSS1_CTL_94_DATA + DDRSS1_CTL_95_DATA + DDRSS1_CTL_96_DATA + DDRSS1_CTL_97_DATA + DDRSS1_CTL_98_DATA + DDRSS1_CTL_99_DATA + DDRSS1_CTL_100_DATA + DDRSS1_CTL_101_DATA + DDRSS1_CTL_102_DATA + DDRSS1_CTL_103_DATA + DDRSS1_CTL_104_DATA + DDRSS1_CTL_105_DATA + DDRSS1_CTL_106_DATA + DDRSS1_CTL_107_DATA + DDRSS1_CTL_108_DATA + DDRSS1_CTL_109_DATA + DDRSS1_CTL_110_DATA + DDRSS1_CTL_111_DATA + DDRSS1_CTL_112_DATA + DDRSS1_CTL_113_DATA + DDRSS1_CTL_114_DATA + DDRSS1_CTL_115_DATA + DDRSS1_CTL_116_DATA + DDRSS1_CTL_117_DATA + DDRSS1_CTL_118_DATA + DDRSS1_CTL_119_DATA + DDRSS1_CTL_120_DATA + DDRSS1_CTL_121_DATA + DDRSS1_CTL_122_DATA + DDRSS1_CTL_123_DATA + DDRSS1_CTL_124_DATA + DDRSS1_CTL_125_DATA + DDRSS1_CTL_126_DATA + DDRSS1_CTL_127_DATA + DDRSS1_CTL_128_DATA + DDRSS1_CTL_129_DATA + DDRSS1_CTL_130_DATA + DDRSS1_CTL_131_DATA + DDRSS1_CTL_132_DATA + DDRSS1_CTL_133_DATA + DDRSS1_CTL_134_DATA + DDRSS1_CTL_135_DATA + DDRSS1_CTL_136_DATA + DDRSS1_CTL_137_DATA + DDRSS1_CTL_138_DATA + DDRSS1_CTL_139_DATA + DDRSS1_CTL_140_DATA + DDRSS1_CTL_141_DATA + DDRSS1_CTL_142_DATA + DDRSS1_CTL_143_DATA + DDRSS1_CTL_144_DATA + DDRSS1_CTL_145_DATA + DDRSS1_CTL_146_DATA + DDRSS1_CTL_147_DATA + DDRSS1_CTL_148_DATA + DDRSS1_CTL_149_DATA + DDRSS1_CTL_150_DATA + DDRSS1_CTL_151_DATA + DDRSS1_CTL_152_DATA + DDRSS1_CTL_153_DATA + DDRSS1_CTL_154_DATA + DDRSS1_CTL_155_DATA + DDRSS1_CTL_156_DATA + DDRSS1_CTL_157_DATA + DDRSS1_CTL_158_DATA + DDRSS1_CTL_159_DATA + DDRSS1_CTL_160_DATA + DDRSS1_CTL_161_DATA + DDRSS1_CTL_162_DATA + DDRSS1_CTL_163_DATA + DDRSS1_CTL_164_DATA + DDRSS1_CTL_165_DATA + DDRSS1_CTL_166_DATA + DDRSS1_CTL_167_DATA + DDRSS1_CTL_168_DATA + DDRSS1_CTL_169_DATA + DDRSS1_CTL_170_DATA + DDRSS1_CTL_171_DATA + DDRSS1_CTL_172_DATA + DDRSS1_CTL_173_DATA + DDRSS1_CTL_174_DATA + DDRSS1_CTL_175_DATA + DDRSS1_CTL_176_DATA + DDRSS1_CTL_177_DATA + DDRSS1_CTL_178_DATA + DDRSS1_CTL_179_DATA + DDRSS1_CTL_180_DATA + DDRSS1_CTL_181_DATA + DDRSS1_CTL_182_DATA + DDRSS1_CTL_183_DATA + DDRSS1_CTL_184_DATA + DDRSS1_CTL_185_DATA + DDRSS1_CTL_186_DATA + DDRSS1_CTL_187_DATA + DDRSS1_CTL_188_DATA + DDRSS1_CTL_189_DATA + DDRSS1_CTL_190_DATA + DDRSS1_CTL_191_DATA + DDRSS1_CTL_192_DATA + DDRSS1_CTL_193_DATA + DDRSS1_CTL_194_DATA + DDRSS1_CTL_195_DATA + DDRSS1_CTL_196_DATA + DDRSS1_CTL_197_DATA + DDRSS1_CTL_198_DATA + DDRSS1_CTL_199_DATA + DDRSS1_CTL_200_DATA + DDRSS1_CTL_201_DATA + DDRSS1_CTL_202_DATA + DDRSS1_CTL_203_DATA + DDRSS1_CTL_204_DATA + DDRSS1_CTL_205_DATA + DDRSS1_CTL_206_DATA + DDRSS1_CTL_207_DATA + DDRSS1_CTL_208_DATA + DDRSS1_CTL_209_DATA + DDRSS1_CTL_210_DATA + DDRSS1_CTL_211_DATA + DDRSS1_CTL_212_DATA + DDRSS1_CTL_213_DATA + DDRSS1_CTL_214_DATA + DDRSS1_CTL_215_DATA + DDRSS1_CTL_216_DATA + DDRSS1_CTL_217_DATA + DDRSS1_CTL_218_DATA + DDRSS1_CTL_219_DATA + DDRSS1_CTL_220_DATA + DDRSS1_CTL_221_DATA + DDRSS1_CTL_222_DATA + DDRSS1_CTL_223_DATA + DDRSS1_CTL_224_DATA + DDRSS1_CTL_225_DATA + DDRSS1_CTL_226_DATA + DDRSS1_CTL_227_DATA + DDRSS1_CTL_228_DATA + DDRSS1_CTL_229_DATA + DDRSS1_CTL_230_DATA + DDRSS1_CTL_231_DATA + DDRSS1_CTL_232_DATA + DDRSS1_CTL_233_DATA + DDRSS1_CTL_234_DATA + DDRSS1_CTL_235_DATA + DDRSS1_CTL_236_DATA + DDRSS1_CTL_237_DATA + DDRSS1_CTL_238_DATA + DDRSS1_CTL_239_DATA + DDRSS1_CTL_240_DATA + DDRSS1_CTL_241_DATA + DDRSS1_CTL_242_DATA + DDRSS1_CTL_243_DATA + DDRSS1_CTL_244_DATA + DDRSS1_CTL_245_DATA + DDRSS1_CTL_246_DATA + DDRSS1_CTL_247_DATA + DDRSS1_CTL_248_DATA + DDRSS1_CTL_249_DATA + DDRSS1_CTL_250_DATA + DDRSS1_CTL_251_DATA + DDRSS1_CTL_252_DATA + DDRSS1_CTL_253_DATA + DDRSS1_CTL_254_DATA + DDRSS1_CTL_255_DATA + DDRSS1_CTL_256_DATA + DDRSS1_CTL_257_DATA + DDRSS1_CTL_258_DATA + DDRSS1_CTL_259_DATA + DDRSS1_CTL_260_DATA + DDRSS1_CTL_261_DATA + DDRSS1_CTL_262_DATA + DDRSS1_CTL_263_DATA + DDRSS1_CTL_264_DATA + DDRSS1_CTL_265_DATA + DDRSS1_CTL_266_DATA + DDRSS1_CTL_267_DATA + DDRSS1_CTL_268_DATA + DDRSS1_CTL_269_DATA + DDRSS1_CTL_270_DATA + DDRSS1_CTL_271_DATA + DDRSS1_CTL_272_DATA + DDRSS1_CTL_273_DATA + DDRSS1_CTL_274_DATA + DDRSS1_CTL_275_DATA + DDRSS1_CTL_276_DATA + DDRSS1_CTL_277_DATA + DDRSS1_CTL_278_DATA + DDRSS1_CTL_279_DATA + DDRSS1_CTL_280_DATA + DDRSS1_CTL_281_DATA + DDRSS1_CTL_282_DATA + DDRSS1_CTL_283_DATA + DDRSS1_CTL_284_DATA + DDRSS1_CTL_285_DATA + DDRSS1_CTL_286_DATA + DDRSS1_CTL_287_DATA + DDRSS1_CTL_288_DATA + DDRSS1_CTL_289_DATA + DDRSS1_CTL_290_DATA + DDRSS1_CTL_291_DATA + DDRSS1_CTL_292_DATA + DDRSS1_CTL_293_DATA + DDRSS1_CTL_294_DATA + DDRSS1_CTL_295_DATA + DDRSS1_CTL_296_DATA + DDRSS1_CTL_297_DATA + DDRSS1_CTL_298_DATA + DDRSS1_CTL_299_DATA + DDRSS1_CTL_300_DATA + DDRSS1_CTL_301_DATA + DDRSS1_CTL_302_DATA + DDRSS1_CTL_303_DATA + DDRSS1_CTL_304_DATA + DDRSS1_CTL_305_DATA + DDRSS1_CTL_306_DATA + DDRSS1_CTL_307_DATA + DDRSS1_CTL_308_DATA + DDRSS1_CTL_309_DATA + DDRSS1_CTL_310_DATA + DDRSS1_CTL_311_DATA + DDRSS1_CTL_312_DATA + DDRSS1_CTL_313_DATA + DDRSS1_CTL_314_DATA + DDRSS1_CTL_315_DATA + DDRSS1_CTL_316_DATA + DDRSS1_CTL_317_DATA + DDRSS1_CTL_318_DATA + DDRSS1_CTL_319_DATA + DDRSS1_CTL_320_DATA + DDRSS1_CTL_321_DATA + DDRSS1_CTL_322_DATA + DDRSS1_CTL_323_DATA + DDRSS1_CTL_324_DATA + DDRSS1_CTL_325_DATA + DDRSS1_CTL_326_DATA + DDRSS1_CTL_327_DATA + DDRSS1_CTL_328_DATA + DDRSS1_CTL_329_DATA + DDRSS1_CTL_330_DATA + DDRSS1_CTL_331_DATA + DDRSS1_CTL_332_DATA + DDRSS1_CTL_333_DATA + DDRSS1_CTL_334_DATA + DDRSS1_CTL_335_DATA + DDRSS1_CTL_336_DATA + DDRSS1_CTL_337_DATA + DDRSS1_CTL_338_DATA + DDRSS1_CTL_339_DATA + DDRSS1_CTL_340_DATA + DDRSS1_CTL_341_DATA + DDRSS1_CTL_342_DATA + DDRSS1_CTL_343_DATA + DDRSS1_CTL_344_DATA + DDRSS1_CTL_345_DATA + DDRSS1_CTL_346_DATA + DDRSS1_CTL_347_DATA + DDRSS1_CTL_348_DATA + DDRSS1_CTL_349_DATA + DDRSS1_CTL_350_DATA + DDRSS1_CTL_351_DATA + DDRSS1_CTL_352_DATA + DDRSS1_CTL_353_DATA + DDRSS1_CTL_354_DATA + DDRSS1_CTL_355_DATA + DDRSS1_CTL_356_DATA + DDRSS1_CTL_357_DATA + DDRSS1_CTL_358_DATA + DDRSS1_CTL_359_DATA + DDRSS1_CTL_360_DATA + DDRSS1_CTL_361_DATA + DDRSS1_CTL_362_DATA + DDRSS1_CTL_363_DATA + DDRSS1_CTL_364_DATA + DDRSS1_CTL_365_DATA + DDRSS1_CTL_366_DATA + DDRSS1_CTL_367_DATA + DDRSS1_CTL_368_DATA + DDRSS1_CTL_369_DATA + DDRSS1_CTL_370_DATA + DDRSS1_CTL_371_DATA + DDRSS1_CTL_372_DATA + DDRSS1_CTL_373_DATA + DDRSS1_CTL_374_DATA + DDRSS1_CTL_375_DATA + DDRSS1_CTL_376_DATA + DDRSS1_CTL_377_DATA + DDRSS1_CTL_378_DATA + DDRSS1_CTL_379_DATA + DDRSS1_CTL_380_DATA + DDRSS1_CTL_381_DATA + DDRSS1_CTL_382_DATA + DDRSS1_CTL_383_DATA + DDRSS1_CTL_384_DATA + DDRSS1_CTL_385_DATA + DDRSS1_CTL_386_DATA + DDRSS1_CTL_387_DATA + DDRSS1_CTL_388_DATA + DDRSS1_CTL_389_DATA + DDRSS1_CTL_390_DATA + DDRSS1_CTL_391_DATA + DDRSS1_CTL_392_DATA + DDRSS1_CTL_393_DATA + DDRSS1_CTL_394_DATA + DDRSS1_CTL_395_DATA + DDRSS1_CTL_396_DATA + DDRSS1_CTL_397_DATA + DDRSS1_CTL_398_DATA + DDRSS1_CTL_399_DATA + DDRSS1_CTL_400_DATA + DDRSS1_CTL_401_DATA + DDRSS1_CTL_402_DATA + DDRSS1_CTL_403_DATA + DDRSS1_CTL_404_DATA + DDRSS1_CTL_405_DATA + DDRSS1_CTL_406_DATA + DDRSS1_CTL_407_DATA + DDRSS1_CTL_408_DATA + DDRSS1_CTL_409_DATA + DDRSS1_CTL_410_DATA + DDRSS1_CTL_411_DATA + DDRSS1_CTL_412_DATA + DDRSS1_CTL_413_DATA + DDRSS1_CTL_414_DATA + DDRSS1_CTL_415_DATA + DDRSS1_CTL_416_DATA + DDRSS1_CTL_417_DATA + DDRSS1_CTL_418_DATA + DDRSS1_CTL_419_DATA + DDRSS1_CTL_420_DATA + DDRSS1_CTL_421_DATA + DDRSS1_CTL_422_DATA + DDRSS1_CTL_423_DATA + DDRSS1_CTL_424_DATA + DDRSS1_CTL_425_DATA + DDRSS1_CTL_426_DATA + DDRSS1_CTL_427_DATA + DDRSS1_CTL_428_DATA + DDRSS1_CTL_429_DATA + DDRSS1_CTL_430_DATA + DDRSS1_CTL_431_DATA + DDRSS1_CTL_432_DATA + DDRSS1_CTL_433_DATA + DDRSS1_CTL_434_DATA + DDRSS1_CTL_435_DATA + DDRSS1_CTL_436_DATA + DDRSS1_CTL_437_DATA + DDRSS1_CTL_438_DATA + DDRSS1_CTL_439_DATA + DDRSS1_CTL_440_DATA + DDRSS1_CTL_441_DATA + DDRSS1_CTL_442_DATA + DDRSS1_CTL_443_DATA + DDRSS1_CTL_444_DATA + DDRSS1_CTL_445_DATA + DDRSS1_CTL_446_DATA + DDRSS1_CTL_447_DATA + DDRSS1_CTL_448_DATA + DDRSS1_CTL_449_DATA + DDRSS1_CTL_450_DATA + DDRSS1_CTL_451_DATA + DDRSS1_CTL_452_DATA + DDRSS1_CTL_453_DATA + DDRSS1_CTL_454_DATA + DDRSS1_CTL_455_DATA + DDRSS1_CTL_456_DATA + DDRSS1_CTL_457_DATA + DDRSS1_CTL_458_DATA + >; + + ti,pi-data = < + DDRSS1_PI_00_DATA + DDRSS1_PI_01_DATA + DDRSS1_PI_02_DATA + DDRSS1_PI_03_DATA + DDRSS1_PI_04_DATA + DDRSS1_PI_05_DATA + DDRSS1_PI_06_DATA + DDRSS1_PI_07_DATA + DDRSS1_PI_08_DATA + DDRSS1_PI_09_DATA + DDRSS1_PI_10_DATA + DDRSS1_PI_11_DATA + DDRSS1_PI_12_DATA + DDRSS1_PI_13_DATA + DDRSS1_PI_14_DATA + DDRSS1_PI_15_DATA + DDRSS1_PI_16_DATA + DDRSS1_PI_17_DATA + DDRSS1_PI_18_DATA + DDRSS1_PI_19_DATA + DDRSS1_PI_20_DATA + DDRSS1_PI_21_DATA + DDRSS1_PI_22_DATA + DDRSS1_PI_23_DATA + DDRSS1_PI_24_DATA + DDRSS1_PI_25_DATA + DDRSS1_PI_26_DATA + DDRSS1_PI_27_DATA + DDRSS1_PI_28_DATA + DDRSS1_PI_29_DATA + DDRSS1_PI_30_DATA + DDRSS1_PI_31_DATA + DDRSS1_PI_32_DATA + DDRSS1_PI_33_DATA + DDRSS1_PI_34_DATA + DDRSS1_PI_35_DATA + DDRSS1_PI_36_DATA + DDRSS1_PI_37_DATA + DDRSS1_PI_38_DATA + DDRSS1_PI_39_DATA + DDRSS1_PI_40_DATA + DDRSS1_PI_41_DATA + DDRSS1_PI_42_DATA + DDRSS1_PI_43_DATA + DDRSS1_PI_44_DATA + DDRSS1_PI_45_DATA + DDRSS1_PI_46_DATA + DDRSS1_PI_47_DATA + DDRSS1_PI_48_DATA + DDRSS1_PI_49_DATA + DDRSS1_PI_50_DATA + DDRSS1_PI_51_DATA + DDRSS1_PI_52_DATA + DDRSS1_PI_53_DATA + DDRSS1_PI_54_DATA + DDRSS1_PI_55_DATA + DDRSS1_PI_56_DATA + DDRSS1_PI_57_DATA + DDRSS1_PI_58_DATA + DDRSS1_PI_59_DATA + DDRSS1_PI_60_DATA + DDRSS1_PI_61_DATA + DDRSS1_PI_62_DATA + DDRSS1_PI_63_DATA + DDRSS1_PI_64_DATA + DDRSS1_PI_65_DATA + DDRSS1_PI_66_DATA + DDRSS1_PI_67_DATA + DDRSS1_PI_68_DATA + DDRSS1_PI_69_DATA + DDRSS1_PI_70_DATA + DDRSS1_PI_71_DATA + DDRSS1_PI_72_DATA + DDRSS1_PI_73_DATA + DDRSS1_PI_74_DATA + DDRSS1_PI_75_DATA + DDRSS1_PI_76_DATA + DDRSS1_PI_77_DATA + DDRSS1_PI_78_DATA + DDRSS1_PI_79_DATA + DDRSS1_PI_80_DATA + DDRSS1_PI_81_DATA + DDRSS1_PI_82_DATA + DDRSS1_PI_83_DATA + DDRSS1_PI_84_DATA + DDRSS1_PI_85_DATA + DDRSS1_PI_86_DATA + DDRSS1_PI_87_DATA + DDRSS1_PI_88_DATA + DDRSS1_PI_89_DATA + DDRSS1_PI_90_DATA + DDRSS1_PI_91_DATA + DDRSS1_PI_92_DATA + DDRSS1_PI_93_DATA + DDRSS1_PI_94_DATA + DDRSS1_PI_95_DATA + DDRSS1_PI_96_DATA + DDRSS1_PI_97_DATA + DDRSS1_PI_98_DATA + DDRSS1_PI_99_DATA + DDRSS1_PI_100_DATA + DDRSS1_PI_101_DATA + DDRSS1_PI_102_DATA + DDRSS1_PI_103_DATA + DDRSS1_PI_104_DATA + DDRSS1_PI_105_DATA + DDRSS1_PI_106_DATA + DDRSS1_PI_107_DATA + DDRSS1_PI_108_DATA + DDRSS1_PI_109_DATA + DDRSS1_PI_110_DATA + DDRSS1_PI_111_DATA + DDRSS1_PI_112_DATA + DDRSS1_PI_113_DATA + DDRSS1_PI_114_DATA + DDRSS1_PI_115_DATA + DDRSS1_PI_116_DATA + DDRSS1_PI_117_DATA + DDRSS1_PI_118_DATA + DDRSS1_PI_119_DATA + DDRSS1_PI_120_DATA + DDRSS1_PI_121_DATA + DDRSS1_PI_122_DATA + DDRSS1_PI_123_DATA + DDRSS1_PI_124_DATA + DDRSS1_PI_125_DATA + DDRSS1_PI_126_DATA + DDRSS1_PI_127_DATA + DDRSS1_PI_128_DATA + DDRSS1_PI_129_DATA + DDRSS1_PI_130_DATA + DDRSS1_PI_131_DATA + DDRSS1_PI_132_DATA + DDRSS1_PI_133_DATA + DDRSS1_PI_134_DATA + DDRSS1_PI_135_DATA + DDRSS1_PI_136_DATA + DDRSS1_PI_137_DATA + DDRSS1_PI_138_DATA + DDRSS1_PI_139_DATA + DDRSS1_PI_140_DATA + DDRSS1_PI_141_DATA + DDRSS1_PI_142_DATA + DDRSS1_PI_143_DATA + DDRSS1_PI_144_DATA + DDRSS1_PI_145_DATA + DDRSS1_PI_146_DATA + DDRSS1_PI_147_DATA + DDRSS1_PI_148_DATA + DDRSS1_PI_149_DATA + DDRSS1_PI_150_DATA + DDRSS1_PI_151_DATA + DDRSS1_PI_152_DATA + DDRSS1_PI_153_DATA + DDRSS1_PI_154_DATA + DDRSS1_PI_155_DATA + DDRSS1_PI_156_DATA + DDRSS1_PI_157_DATA + DDRSS1_PI_158_DATA + DDRSS1_PI_159_DATA + DDRSS1_PI_160_DATA + DDRSS1_PI_161_DATA + DDRSS1_PI_162_DATA + DDRSS1_PI_163_DATA + DDRSS1_PI_164_DATA + DDRSS1_PI_165_DATA + DDRSS1_PI_166_DATA + DDRSS1_PI_167_DATA + DDRSS1_PI_168_DATA + DDRSS1_PI_169_DATA + DDRSS1_PI_170_DATA + DDRSS1_PI_171_DATA + DDRSS1_PI_172_DATA + DDRSS1_PI_173_DATA + DDRSS1_PI_174_DATA + DDRSS1_PI_175_DATA + DDRSS1_PI_176_DATA + DDRSS1_PI_177_DATA + DDRSS1_PI_178_DATA + DDRSS1_PI_179_DATA + DDRSS1_PI_180_DATA + DDRSS1_PI_181_DATA + DDRSS1_PI_182_DATA + DDRSS1_PI_183_DATA + DDRSS1_PI_184_DATA + DDRSS1_PI_185_DATA + DDRSS1_PI_186_DATA + DDRSS1_PI_187_DATA + DDRSS1_PI_188_DATA + DDRSS1_PI_189_DATA + DDRSS1_PI_190_DATA + DDRSS1_PI_191_DATA + DDRSS1_PI_192_DATA + DDRSS1_PI_193_DATA + DDRSS1_PI_194_DATA + DDRSS1_PI_195_DATA + DDRSS1_PI_196_DATA + DDRSS1_PI_197_DATA + DDRSS1_PI_198_DATA + DDRSS1_PI_199_DATA + DDRSS1_PI_200_DATA + DDRSS1_PI_201_DATA + DDRSS1_PI_202_DATA + DDRSS1_PI_203_DATA + DDRSS1_PI_204_DATA + DDRSS1_PI_205_DATA + DDRSS1_PI_206_DATA + DDRSS1_PI_207_DATA + DDRSS1_PI_208_DATA + DDRSS1_PI_209_DATA + DDRSS1_PI_210_DATA + DDRSS1_PI_211_DATA + DDRSS1_PI_212_DATA + DDRSS1_PI_213_DATA + DDRSS1_PI_214_DATA + DDRSS1_PI_215_DATA + DDRSS1_PI_216_DATA + DDRSS1_PI_217_DATA + DDRSS1_PI_218_DATA + DDRSS1_PI_219_DATA + DDRSS1_PI_220_DATA + DDRSS1_PI_221_DATA + DDRSS1_PI_222_DATA + DDRSS1_PI_223_DATA + DDRSS1_PI_224_DATA + DDRSS1_PI_225_DATA + DDRSS1_PI_226_DATA + DDRSS1_PI_227_DATA + DDRSS1_PI_228_DATA + DDRSS1_PI_229_DATA + DDRSS1_PI_230_DATA + DDRSS1_PI_231_DATA + DDRSS1_PI_232_DATA + DDRSS1_PI_233_DATA + DDRSS1_PI_234_DATA + DDRSS1_PI_235_DATA + DDRSS1_PI_236_DATA + DDRSS1_PI_237_DATA + DDRSS1_PI_238_DATA + DDRSS1_PI_239_DATA + DDRSS1_PI_240_DATA + DDRSS1_PI_241_DATA + DDRSS1_PI_242_DATA + DDRSS1_PI_243_DATA + DDRSS1_PI_244_DATA + DDRSS1_PI_245_DATA + DDRSS1_PI_246_DATA + DDRSS1_PI_247_DATA + DDRSS1_PI_248_DATA + DDRSS1_PI_249_DATA + DDRSS1_PI_250_DATA + DDRSS1_PI_251_DATA + DDRSS1_PI_252_DATA + DDRSS1_PI_253_DATA + DDRSS1_PI_254_DATA + DDRSS1_PI_255_DATA + DDRSS1_PI_256_DATA + DDRSS1_PI_257_DATA + DDRSS1_PI_258_DATA + DDRSS1_PI_259_DATA + DDRSS1_PI_260_DATA + DDRSS1_PI_261_DATA + DDRSS1_PI_262_DATA + DDRSS1_PI_263_DATA + DDRSS1_PI_264_DATA + DDRSS1_PI_265_DATA + DDRSS1_PI_266_DATA + DDRSS1_PI_267_DATA + DDRSS1_PI_268_DATA + DDRSS1_PI_269_DATA + DDRSS1_PI_270_DATA + DDRSS1_PI_271_DATA + DDRSS1_PI_272_DATA + DDRSS1_PI_273_DATA + DDRSS1_PI_274_DATA + DDRSS1_PI_275_DATA + DDRSS1_PI_276_DATA + DDRSS1_PI_277_DATA + DDRSS1_PI_278_DATA + DDRSS1_PI_279_DATA + DDRSS1_PI_280_DATA + DDRSS1_PI_281_DATA + DDRSS1_PI_282_DATA + DDRSS1_PI_283_DATA + DDRSS1_PI_284_DATA + DDRSS1_PI_285_DATA + DDRSS1_PI_286_DATA + DDRSS1_PI_287_DATA + DDRSS1_PI_288_DATA + DDRSS1_PI_289_DATA + DDRSS1_PI_290_DATA + DDRSS1_PI_291_DATA + DDRSS1_PI_292_DATA + DDRSS1_PI_293_DATA + DDRSS1_PI_294_DATA + DDRSS1_PI_295_DATA + DDRSS1_PI_296_DATA + DDRSS1_PI_297_DATA + DDRSS1_PI_298_DATA + DDRSS1_PI_299_DATA + >; + + ti,phy-data = < + DDRSS1_PHY_00_DATA + DDRSS1_PHY_01_DATA + DDRSS1_PHY_02_DATA + DDRSS1_PHY_03_DATA + DDRSS1_PHY_04_DATA + DDRSS1_PHY_05_DATA + DDRSS1_PHY_06_DATA + DDRSS1_PHY_07_DATA + DDRSS1_PHY_08_DATA + DDRSS1_PHY_09_DATA + DDRSS1_PHY_10_DATA + DDRSS1_PHY_11_DATA + DDRSS1_PHY_12_DATA + DDRSS1_PHY_13_DATA + DDRSS1_PHY_14_DATA + DDRSS1_PHY_15_DATA + DDRSS1_PHY_16_DATA + DDRSS1_PHY_17_DATA + DDRSS1_PHY_18_DATA + DDRSS1_PHY_19_DATA + DDRSS1_PHY_20_DATA + DDRSS1_PHY_21_DATA + DDRSS1_PHY_22_DATA + DDRSS1_PHY_23_DATA + DDRSS1_PHY_24_DATA + DDRSS1_PHY_25_DATA + DDRSS1_PHY_26_DATA + DDRSS1_PHY_27_DATA + DDRSS1_PHY_28_DATA + DDRSS1_PHY_29_DATA + DDRSS1_PHY_30_DATA + DDRSS1_PHY_31_DATA + DDRSS1_PHY_32_DATA + DDRSS1_PHY_33_DATA + DDRSS1_PHY_34_DATA + DDRSS1_PHY_35_DATA + DDRSS1_PHY_36_DATA + DDRSS1_PHY_37_DATA + DDRSS1_PHY_38_DATA + DDRSS1_PHY_39_DATA + DDRSS1_PHY_40_DATA + DDRSS1_PHY_41_DATA + DDRSS1_PHY_42_DATA + DDRSS1_PHY_43_DATA + DDRSS1_PHY_44_DATA + DDRSS1_PHY_45_DATA + DDRSS1_PHY_46_DATA + DDRSS1_PHY_47_DATA + DDRSS1_PHY_48_DATA + DDRSS1_PHY_49_DATA + DDRSS1_PHY_50_DATA + DDRSS1_PHY_51_DATA + DDRSS1_PHY_52_DATA + DDRSS1_PHY_53_DATA + DDRSS1_PHY_54_DATA + DDRSS1_PHY_55_DATA + DDRSS1_PHY_56_DATA + DDRSS1_PHY_57_DATA + DDRSS1_PHY_58_DATA + DDRSS1_PHY_59_DATA + DDRSS1_PHY_60_DATA + DDRSS1_PHY_61_DATA + DDRSS1_PHY_62_DATA + DDRSS1_PHY_63_DATA + DDRSS1_PHY_64_DATA + DDRSS1_PHY_65_DATA + DDRSS1_PHY_66_DATA + DDRSS1_PHY_67_DATA + DDRSS1_PHY_68_DATA + DDRSS1_PHY_69_DATA + DDRSS1_PHY_70_DATA + DDRSS1_PHY_71_DATA + DDRSS1_PHY_72_DATA + DDRSS1_PHY_73_DATA + DDRSS1_PHY_74_DATA + DDRSS1_PHY_75_DATA + DDRSS1_PHY_76_DATA + DDRSS1_PHY_77_DATA + DDRSS1_PHY_78_DATA + DDRSS1_PHY_79_DATA + DDRSS1_PHY_80_DATA + DDRSS1_PHY_81_DATA + DDRSS1_PHY_82_DATA + DDRSS1_PHY_83_DATA + DDRSS1_PHY_84_DATA + DDRSS1_PHY_85_DATA + DDRSS1_PHY_86_DATA + DDRSS1_PHY_87_DATA + DDRSS1_PHY_88_DATA + DDRSS1_PHY_89_DATA + DDRSS1_PHY_90_DATA + DDRSS1_PHY_91_DATA + DDRSS1_PHY_92_DATA + DDRSS1_PHY_93_DATA + DDRSS1_PHY_94_DATA + DDRSS1_PHY_95_DATA + DDRSS1_PHY_96_DATA + DDRSS1_PHY_97_DATA + DDRSS1_PHY_98_DATA + DDRSS1_PHY_99_DATA + DDRSS1_PHY_100_DATA + DDRSS1_PHY_101_DATA + DDRSS1_PHY_102_DATA + DDRSS1_PHY_103_DATA + DDRSS1_PHY_104_DATA + DDRSS1_PHY_105_DATA + DDRSS1_PHY_106_DATA + DDRSS1_PHY_107_DATA + DDRSS1_PHY_108_DATA + DDRSS1_PHY_109_DATA + DDRSS1_PHY_110_DATA + DDRSS1_PHY_111_DATA + DDRSS1_PHY_112_DATA + DDRSS1_PHY_113_DATA + DDRSS1_PHY_114_DATA + DDRSS1_PHY_115_DATA + DDRSS1_PHY_116_DATA + DDRSS1_PHY_117_DATA + DDRSS1_PHY_118_DATA + DDRSS1_PHY_119_DATA + DDRSS1_PHY_120_DATA + DDRSS1_PHY_121_DATA + DDRSS1_PHY_122_DATA + DDRSS1_PHY_123_DATA + DDRSS1_PHY_124_DATA + DDRSS1_PHY_125_DATA + DDRSS1_PHY_126_DATA + DDRSS1_PHY_127_DATA + DDRSS1_PHY_128_DATA + DDRSS1_PHY_129_DATA + DDRSS1_PHY_130_DATA + DDRSS1_PHY_131_DATA + DDRSS1_PHY_132_DATA + DDRSS1_PHY_133_DATA + DDRSS1_PHY_134_DATA + DDRSS1_PHY_135_DATA + DDRSS1_PHY_136_DATA + DDRSS1_PHY_137_DATA + DDRSS1_PHY_138_DATA + DDRSS1_PHY_139_DATA + DDRSS1_PHY_140_DATA + DDRSS1_PHY_141_DATA + DDRSS1_PHY_142_DATA + DDRSS1_PHY_143_DATA + DDRSS1_PHY_144_DATA + DDRSS1_PHY_145_DATA + DDRSS1_PHY_146_DATA + DDRSS1_PHY_147_DATA + DDRSS1_PHY_148_DATA + DDRSS1_PHY_149_DATA + DDRSS1_PHY_150_DATA + DDRSS1_PHY_151_DATA + DDRSS1_PHY_152_DATA + DDRSS1_PHY_153_DATA + DDRSS1_PHY_154_DATA + DDRSS1_PHY_155_DATA + DDRSS1_PHY_156_DATA + DDRSS1_PHY_157_DATA + DDRSS1_PHY_158_DATA + DDRSS1_PHY_159_DATA + DDRSS1_PHY_160_DATA + DDRSS1_PHY_161_DATA + DDRSS1_PHY_162_DATA + DDRSS1_PHY_163_DATA + DDRSS1_PHY_164_DATA + DDRSS1_PHY_165_DATA + DDRSS1_PHY_166_DATA + DDRSS1_PHY_167_DATA + DDRSS1_PHY_168_DATA + DDRSS1_PHY_169_DATA + DDRSS1_PHY_170_DATA + DDRSS1_PHY_171_DATA + DDRSS1_PHY_172_DATA + DDRSS1_PHY_173_DATA + DDRSS1_PHY_174_DATA + DDRSS1_PHY_175_DATA + DDRSS1_PHY_176_DATA + DDRSS1_PHY_177_DATA + DDRSS1_PHY_178_DATA + DDRSS1_PHY_179_DATA + DDRSS1_PHY_180_DATA + DDRSS1_PHY_181_DATA + DDRSS1_PHY_182_DATA + DDRSS1_PHY_183_DATA + DDRSS1_PHY_184_DATA + DDRSS1_PHY_185_DATA + DDRSS1_PHY_186_DATA + DDRSS1_PHY_187_DATA + DDRSS1_PHY_188_DATA + DDRSS1_PHY_189_DATA + DDRSS1_PHY_190_DATA + DDRSS1_PHY_191_DATA + DDRSS1_PHY_192_DATA + DDRSS1_PHY_193_DATA + DDRSS1_PHY_194_DATA + DDRSS1_PHY_195_DATA + DDRSS1_PHY_196_DATA + DDRSS1_PHY_197_DATA + DDRSS1_PHY_198_DATA + DDRSS1_PHY_199_DATA + DDRSS1_PHY_200_DATA + DDRSS1_PHY_201_DATA + DDRSS1_PHY_202_DATA + DDRSS1_PHY_203_DATA + DDRSS1_PHY_204_DATA + DDRSS1_PHY_205_DATA + DDRSS1_PHY_206_DATA + DDRSS1_PHY_207_DATA + DDRSS1_PHY_208_DATA + DDRSS1_PHY_209_DATA + DDRSS1_PHY_210_DATA + DDRSS1_PHY_211_DATA + DDRSS1_PHY_212_DATA + DDRSS1_PHY_213_DATA + DDRSS1_PHY_214_DATA + DDRSS1_PHY_215_DATA + DDRSS1_PHY_216_DATA + DDRSS1_PHY_217_DATA + DDRSS1_PHY_218_DATA + DDRSS1_PHY_219_DATA + DDRSS1_PHY_220_DATA + DDRSS1_PHY_221_DATA + DDRSS1_PHY_222_DATA + DDRSS1_PHY_223_DATA + DDRSS1_PHY_224_DATA + DDRSS1_PHY_225_DATA + DDRSS1_PHY_226_DATA + DDRSS1_PHY_227_DATA + DDRSS1_PHY_228_DATA + DDRSS1_PHY_229_DATA + DDRSS1_PHY_230_DATA + DDRSS1_PHY_231_DATA + DDRSS1_PHY_232_DATA + DDRSS1_PHY_233_DATA + DDRSS1_PHY_234_DATA + DDRSS1_PHY_235_DATA + DDRSS1_PHY_236_DATA + DDRSS1_PHY_237_DATA + DDRSS1_PHY_238_DATA + DDRSS1_PHY_239_DATA + DDRSS1_PHY_240_DATA + DDRSS1_PHY_241_DATA + DDRSS1_PHY_242_DATA + DDRSS1_PHY_243_DATA + DDRSS1_PHY_244_DATA + DDRSS1_PHY_245_DATA + DDRSS1_PHY_246_DATA + DDRSS1_PHY_247_DATA + DDRSS1_PHY_248_DATA + DDRSS1_PHY_249_DATA + DDRSS1_PHY_250_DATA + DDRSS1_PHY_251_DATA + DDRSS1_PHY_252_DATA + DDRSS1_PHY_253_DATA + DDRSS1_PHY_254_DATA + DDRSS1_PHY_255_DATA + DDRSS1_PHY_256_DATA + DDRSS1_PHY_257_DATA + DDRSS1_PHY_258_DATA + DDRSS1_PHY_259_DATA + DDRSS1_PHY_260_DATA + DDRSS1_PHY_261_DATA + DDRSS1_PHY_262_DATA + DDRSS1_PHY_263_DATA + DDRSS1_PHY_264_DATA + DDRSS1_PHY_265_DATA + DDRSS1_PHY_266_DATA + DDRSS1_PHY_267_DATA + DDRSS1_PHY_268_DATA + DDRSS1_PHY_269_DATA + DDRSS1_PHY_270_DATA + DDRSS1_PHY_271_DATA + DDRSS1_PHY_272_DATA + DDRSS1_PHY_273_DATA + DDRSS1_PHY_274_DATA + DDRSS1_PHY_275_DATA + DDRSS1_PHY_276_DATA + DDRSS1_PHY_277_DATA + DDRSS1_PHY_278_DATA + DDRSS1_PHY_279_DATA + DDRSS1_PHY_280_DATA + DDRSS1_PHY_281_DATA + DDRSS1_PHY_282_DATA + DDRSS1_PHY_283_DATA + DDRSS1_PHY_284_DATA + DDRSS1_PHY_285_DATA + DDRSS1_PHY_286_DATA + DDRSS1_PHY_287_DATA + DDRSS1_PHY_288_DATA + DDRSS1_PHY_289_DATA + DDRSS1_PHY_290_DATA + DDRSS1_PHY_291_DATA + DDRSS1_PHY_292_DATA + DDRSS1_PHY_293_DATA + DDRSS1_PHY_294_DATA + DDRSS1_PHY_295_DATA + DDRSS1_PHY_296_DATA + DDRSS1_PHY_297_DATA + DDRSS1_PHY_298_DATA + DDRSS1_PHY_299_DATA + DDRSS1_PHY_300_DATA + DDRSS1_PHY_301_DATA + DDRSS1_PHY_302_DATA + DDRSS1_PHY_303_DATA + DDRSS1_PHY_304_DATA + DDRSS1_PHY_305_DATA + DDRSS1_PHY_306_DATA + DDRSS1_PHY_307_DATA + DDRSS1_PHY_308_DATA + DDRSS1_PHY_309_DATA + DDRSS1_PHY_310_DATA + DDRSS1_PHY_311_DATA + DDRSS1_PHY_312_DATA + DDRSS1_PHY_313_DATA + DDRSS1_PHY_314_DATA + DDRSS1_PHY_315_DATA + DDRSS1_PHY_316_DATA + DDRSS1_PHY_317_DATA + DDRSS1_PHY_318_DATA + DDRSS1_PHY_319_DATA + DDRSS1_PHY_320_DATA + DDRSS1_PHY_321_DATA + DDRSS1_PHY_322_DATA + DDRSS1_PHY_323_DATA + DDRSS1_PHY_324_DATA + DDRSS1_PHY_325_DATA + DDRSS1_PHY_326_DATA + DDRSS1_PHY_327_DATA + DDRSS1_PHY_328_DATA + DDRSS1_PHY_329_DATA + DDRSS1_PHY_330_DATA + DDRSS1_PHY_331_DATA + DDRSS1_PHY_332_DATA + DDRSS1_PHY_333_DATA + DDRSS1_PHY_334_DATA + DDRSS1_PHY_335_DATA + DDRSS1_PHY_336_DATA + DDRSS1_PHY_337_DATA + DDRSS1_PHY_338_DATA + DDRSS1_PHY_339_DATA + DDRSS1_PHY_340_DATA + DDRSS1_PHY_341_DATA + DDRSS1_PHY_342_DATA + DDRSS1_PHY_343_DATA + DDRSS1_PHY_344_DATA + DDRSS1_PHY_345_DATA + DDRSS1_PHY_346_DATA + DDRSS1_PHY_347_DATA + DDRSS1_PHY_348_DATA + DDRSS1_PHY_349_DATA + DDRSS1_PHY_350_DATA + DDRSS1_PHY_351_DATA + DDRSS1_PHY_352_DATA + DDRSS1_PHY_353_DATA + DDRSS1_PHY_354_DATA + DDRSS1_PHY_355_DATA + DDRSS1_PHY_356_DATA + DDRSS1_PHY_357_DATA + DDRSS1_PHY_358_DATA + DDRSS1_PHY_359_DATA + DDRSS1_PHY_360_DATA + DDRSS1_PHY_361_DATA + DDRSS1_PHY_362_DATA + DDRSS1_PHY_363_DATA + DDRSS1_PHY_364_DATA + DDRSS1_PHY_365_DATA + DDRSS1_PHY_366_DATA + DDRSS1_PHY_367_DATA + DDRSS1_PHY_368_DATA + DDRSS1_PHY_369_DATA + DDRSS1_PHY_370_DATA + DDRSS1_PHY_371_DATA + DDRSS1_PHY_372_DATA + DDRSS1_PHY_373_DATA + DDRSS1_PHY_374_DATA + DDRSS1_PHY_375_DATA + DDRSS1_PHY_376_DATA + DDRSS1_PHY_377_DATA + DDRSS1_PHY_378_DATA + DDRSS1_PHY_379_DATA + DDRSS1_PHY_380_DATA + DDRSS1_PHY_381_DATA + DDRSS1_PHY_382_DATA + DDRSS1_PHY_383_DATA + DDRSS1_PHY_384_DATA + DDRSS1_PHY_385_DATA + DDRSS1_PHY_386_DATA + DDRSS1_PHY_387_DATA + DDRSS1_PHY_388_DATA + DDRSS1_PHY_389_DATA + DDRSS1_PHY_390_DATA + DDRSS1_PHY_391_DATA + DDRSS1_PHY_392_DATA + DDRSS1_PHY_393_DATA + DDRSS1_PHY_394_DATA + DDRSS1_PHY_395_DATA + DDRSS1_PHY_396_DATA + DDRSS1_PHY_397_DATA + DDRSS1_PHY_398_DATA + DDRSS1_PHY_399_DATA + DDRSS1_PHY_400_DATA + DDRSS1_PHY_401_DATA + DDRSS1_PHY_402_DATA + DDRSS1_PHY_403_DATA + DDRSS1_PHY_404_DATA + DDRSS1_PHY_405_DATA + DDRSS1_PHY_406_DATA + DDRSS1_PHY_407_DATA + DDRSS1_PHY_408_DATA + DDRSS1_PHY_409_DATA + DDRSS1_PHY_410_DATA + DDRSS1_PHY_411_DATA + DDRSS1_PHY_412_DATA + DDRSS1_PHY_413_DATA + DDRSS1_PHY_414_DATA + DDRSS1_PHY_415_DATA + DDRSS1_PHY_416_DATA + DDRSS1_PHY_417_DATA + DDRSS1_PHY_418_DATA + DDRSS1_PHY_419_DATA + DDRSS1_PHY_420_DATA + DDRSS1_PHY_421_DATA + DDRSS1_PHY_422_DATA + DDRSS1_PHY_423_DATA + DDRSS1_PHY_424_DATA + DDRSS1_PHY_425_DATA + DDRSS1_PHY_426_DATA + DDRSS1_PHY_427_DATA + DDRSS1_PHY_428_DATA + DDRSS1_PHY_429_DATA + DDRSS1_PHY_430_DATA + DDRSS1_PHY_431_DATA + DDRSS1_PHY_432_DATA + DDRSS1_PHY_433_DATA + DDRSS1_PHY_434_DATA + DDRSS1_PHY_435_DATA + DDRSS1_PHY_436_DATA + DDRSS1_PHY_437_DATA + DDRSS1_PHY_438_DATA + DDRSS1_PHY_439_DATA + DDRSS1_PHY_440_DATA + DDRSS1_PHY_441_DATA + DDRSS1_PHY_442_DATA + DDRSS1_PHY_443_DATA + DDRSS1_PHY_444_DATA + DDRSS1_PHY_445_DATA + DDRSS1_PHY_446_DATA + DDRSS1_PHY_447_DATA + DDRSS1_PHY_448_DATA + DDRSS1_PHY_449_DATA + DDRSS1_PHY_450_DATA + DDRSS1_PHY_451_DATA + DDRSS1_PHY_452_DATA + DDRSS1_PHY_453_DATA + DDRSS1_PHY_454_DATA + DDRSS1_PHY_455_DATA + DDRSS1_PHY_456_DATA + DDRSS1_PHY_457_DATA + DDRSS1_PHY_458_DATA + DDRSS1_PHY_459_DATA + DDRSS1_PHY_460_DATA + DDRSS1_PHY_461_DATA + DDRSS1_PHY_462_DATA + DDRSS1_PHY_463_DATA + DDRSS1_PHY_464_DATA + DDRSS1_PHY_465_DATA + DDRSS1_PHY_466_DATA + DDRSS1_PHY_467_DATA + DDRSS1_PHY_468_DATA + DDRSS1_PHY_469_DATA + DDRSS1_PHY_470_DATA + DDRSS1_PHY_471_DATA + DDRSS1_PHY_472_DATA + DDRSS1_PHY_473_DATA + DDRSS1_PHY_474_DATA + DDRSS1_PHY_475_DATA + DDRSS1_PHY_476_DATA + DDRSS1_PHY_477_DATA + DDRSS1_PHY_478_DATA + DDRSS1_PHY_479_DATA + DDRSS1_PHY_480_DATA + DDRSS1_PHY_481_DATA + DDRSS1_PHY_482_DATA + DDRSS1_PHY_483_DATA + DDRSS1_PHY_484_DATA + DDRSS1_PHY_485_DATA + DDRSS1_PHY_486_DATA + DDRSS1_PHY_487_DATA + DDRSS1_PHY_488_DATA + DDRSS1_PHY_489_DATA + DDRSS1_PHY_490_DATA + DDRSS1_PHY_491_DATA + DDRSS1_PHY_492_DATA + DDRSS1_PHY_493_DATA + DDRSS1_PHY_494_DATA + DDRSS1_PHY_495_DATA + DDRSS1_PHY_496_DATA + DDRSS1_PHY_497_DATA + DDRSS1_PHY_498_DATA + DDRSS1_PHY_499_DATA + DDRSS1_PHY_500_DATA + DDRSS1_PHY_501_DATA + DDRSS1_PHY_502_DATA + DDRSS1_PHY_503_DATA + DDRSS1_PHY_504_DATA + DDRSS1_PHY_505_DATA + DDRSS1_PHY_506_DATA + DDRSS1_PHY_507_DATA + DDRSS1_PHY_508_DATA + DDRSS1_PHY_509_DATA + DDRSS1_PHY_510_DATA + DDRSS1_PHY_511_DATA + DDRSS1_PHY_512_DATA + DDRSS1_PHY_513_DATA + DDRSS1_PHY_514_DATA + DDRSS1_PHY_515_DATA + DDRSS1_PHY_516_DATA + DDRSS1_PHY_517_DATA + DDRSS1_PHY_518_DATA + DDRSS1_PHY_519_DATA + DDRSS1_PHY_520_DATA + DDRSS1_PHY_521_DATA + DDRSS1_PHY_522_DATA + DDRSS1_PHY_523_DATA + DDRSS1_PHY_524_DATA + DDRSS1_PHY_525_DATA + DDRSS1_PHY_526_DATA + DDRSS1_PHY_527_DATA + DDRSS1_PHY_528_DATA + DDRSS1_PHY_529_DATA + DDRSS1_PHY_530_DATA + DDRSS1_PHY_531_DATA + DDRSS1_PHY_532_DATA + DDRSS1_PHY_533_DATA + DDRSS1_PHY_534_DATA + DDRSS1_PHY_535_DATA + DDRSS1_PHY_536_DATA + DDRSS1_PHY_537_DATA + DDRSS1_PHY_538_DATA + DDRSS1_PHY_539_DATA + DDRSS1_PHY_540_DATA + DDRSS1_PHY_541_DATA + DDRSS1_PHY_542_DATA + DDRSS1_PHY_543_DATA + DDRSS1_PHY_544_DATA + DDRSS1_PHY_545_DATA + DDRSS1_PHY_546_DATA + DDRSS1_PHY_547_DATA + DDRSS1_PHY_548_DATA + DDRSS1_PHY_549_DATA + DDRSS1_PHY_550_DATA + DDRSS1_PHY_551_DATA + DDRSS1_PHY_552_DATA + DDRSS1_PHY_553_DATA + DDRSS1_PHY_554_DATA + DDRSS1_PHY_555_DATA + DDRSS1_PHY_556_DATA + DDRSS1_PHY_557_DATA + DDRSS1_PHY_558_DATA + DDRSS1_PHY_559_DATA + DDRSS1_PHY_560_DATA + DDRSS1_PHY_561_DATA + DDRSS1_PHY_562_DATA + DDRSS1_PHY_563_DATA + DDRSS1_PHY_564_DATA + DDRSS1_PHY_565_DATA + DDRSS1_PHY_566_DATA + DDRSS1_PHY_567_DATA + DDRSS1_PHY_568_DATA + DDRSS1_PHY_569_DATA + DDRSS1_PHY_570_DATA + DDRSS1_PHY_571_DATA + DDRSS1_PHY_572_DATA + DDRSS1_PHY_573_DATA + DDRSS1_PHY_574_DATA + DDRSS1_PHY_575_DATA + DDRSS1_PHY_576_DATA + DDRSS1_PHY_577_DATA + DDRSS1_PHY_578_DATA + DDRSS1_PHY_579_DATA + DDRSS1_PHY_580_DATA + DDRSS1_PHY_581_DATA + DDRSS1_PHY_582_DATA + DDRSS1_PHY_583_DATA + DDRSS1_PHY_584_DATA + DDRSS1_PHY_585_DATA + DDRSS1_PHY_586_DATA + DDRSS1_PHY_587_DATA + DDRSS1_PHY_588_DATA + DDRSS1_PHY_589_DATA + DDRSS1_PHY_590_DATA + DDRSS1_PHY_591_DATA + DDRSS1_PHY_592_DATA + DDRSS1_PHY_593_DATA + DDRSS1_PHY_594_DATA + DDRSS1_PHY_595_DATA + DDRSS1_PHY_596_DATA + DDRSS1_PHY_597_DATA + DDRSS1_PHY_598_DATA + DDRSS1_PHY_599_DATA + DDRSS1_PHY_600_DATA + DDRSS1_PHY_601_DATA + DDRSS1_PHY_602_DATA + DDRSS1_PHY_603_DATA + DDRSS1_PHY_604_DATA + DDRSS1_PHY_605_DATA + DDRSS1_PHY_606_DATA + DDRSS1_PHY_607_DATA + DDRSS1_PHY_608_DATA + DDRSS1_PHY_609_DATA + DDRSS1_PHY_610_DATA + DDRSS1_PHY_611_DATA + DDRSS1_PHY_612_DATA + DDRSS1_PHY_613_DATA + DDRSS1_PHY_614_DATA + DDRSS1_PHY_615_DATA + DDRSS1_PHY_616_DATA + DDRSS1_PHY_617_DATA + DDRSS1_PHY_618_DATA + DDRSS1_PHY_619_DATA + DDRSS1_PHY_620_DATA + DDRSS1_PHY_621_DATA + DDRSS1_PHY_622_DATA + DDRSS1_PHY_623_DATA + DDRSS1_PHY_624_DATA + DDRSS1_PHY_625_DATA + DDRSS1_PHY_626_DATA + DDRSS1_PHY_627_DATA + DDRSS1_PHY_628_DATA + DDRSS1_PHY_629_DATA + DDRSS1_PHY_630_DATA + DDRSS1_PHY_631_DATA + DDRSS1_PHY_632_DATA + DDRSS1_PHY_633_DATA + DDRSS1_PHY_634_DATA + DDRSS1_PHY_635_DATA + DDRSS1_PHY_636_DATA + DDRSS1_PHY_637_DATA + DDRSS1_PHY_638_DATA + DDRSS1_PHY_639_DATA + DDRSS1_PHY_640_DATA + DDRSS1_PHY_641_DATA + DDRSS1_PHY_642_DATA + DDRSS1_PHY_643_DATA + DDRSS1_PHY_644_DATA + DDRSS1_PHY_645_DATA + DDRSS1_PHY_646_DATA + DDRSS1_PHY_647_DATA + DDRSS1_PHY_648_DATA + DDRSS1_PHY_649_DATA + DDRSS1_PHY_650_DATA + DDRSS1_PHY_651_DATA + DDRSS1_PHY_652_DATA + DDRSS1_PHY_653_DATA + DDRSS1_PHY_654_DATA + DDRSS1_PHY_655_DATA + DDRSS1_PHY_656_DATA + DDRSS1_PHY_657_DATA + DDRSS1_PHY_658_DATA + DDRSS1_PHY_659_DATA + DDRSS1_PHY_660_DATA + DDRSS1_PHY_661_DATA + DDRSS1_PHY_662_DATA + DDRSS1_PHY_663_DATA + DDRSS1_PHY_664_DATA + DDRSS1_PHY_665_DATA + DDRSS1_PHY_666_DATA + DDRSS1_PHY_667_DATA + DDRSS1_PHY_668_DATA + DDRSS1_PHY_669_DATA + DDRSS1_PHY_670_DATA + DDRSS1_PHY_671_DATA + DDRSS1_PHY_672_DATA + DDRSS1_PHY_673_DATA + DDRSS1_PHY_674_DATA + DDRSS1_PHY_675_DATA + DDRSS1_PHY_676_DATA + DDRSS1_PHY_677_DATA + DDRSS1_PHY_678_DATA + DDRSS1_PHY_679_DATA + DDRSS1_PHY_680_DATA + DDRSS1_PHY_681_DATA + DDRSS1_PHY_682_DATA + DDRSS1_PHY_683_DATA + DDRSS1_PHY_684_DATA + DDRSS1_PHY_685_DATA + DDRSS1_PHY_686_DATA + DDRSS1_PHY_687_DATA + DDRSS1_PHY_688_DATA + DDRSS1_PHY_689_DATA + DDRSS1_PHY_690_DATA + DDRSS1_PHY_691_DATA + DDRSS1_PHY_692_DATA + DDRSS1_PHY_693_DATA + DDRSS1_PHY_694_DATA + DDRSS1_PHY_695_DATA + DDRSS1_PHY_696_DATA + DDRSS1_PHY_697_DATA + DDRSS1_PHY_698_DATA + DDRSS1_PHY_699_DATA + DDRSS1_PHY_700_DATA + DDRSS1_PHY_701_DATA + DDRSS1_PHY_702_DATA + DDRSS1_PHY_703_DATA + DDRSS1_PHY_704_DATA + DDRSS1_PHY_705_DATA + DDRSS1_PHY_706_DATA + DDRSS1_PHY_707_DATA + DDRSS1_PHY_708_DATA + DDRSS1_PHY_709_DATA + DDRSS1_PHY_710_DATA + DDRSS1_PHY_711_DATA + DDRSS1_PHY_712_DATA + DDRSS1_PHY_713_DATA + DDRSS1_PHY_714_DATA + DDRSS1_PHY_715_DATA + DDRSS1_PHY_716_DATA + DDRSS1_PHY_717_DATA + DDRSS1_PHY_718_DATA + DDRSS1_PHY_719_DATA + DDRSS1_PHY_720_DATA + DDRSS1_PHY_721_DATA + DDRSS1_PHY_722_DATA + DDRSS1_PHY_723_DATA + DDRSS1_PHY_724_DATA + DDRSS1_PHY_725_DATA + DDRSS1_PHY_726_DATA + DDRSS1_PHY_727_DATA + DDRSS1_PHY_728_DATA + DDRSS1_PHY_729_DATA + DDRSS1_PHY_730_DATA + DDRSS1_PHY_731_DATA + DDRSS1_PHY_732_DATA + DDRSS1_PHY_733_DATA + DDRSS1_PHY_734_DATA + DDRSS1_PHY_735_DATA + DDRSS1_PHY_736_DATA + DDRSS1_PHY_737_DATA + DDRSS1_PHY_738_DATA + DDRSS1_PHY_739_DATA + DDRSS1_PHY_740_DATA + DDRSS1_PHY_741_DATA + DDRSS1_PHY_742_DATA + DDRSS1_PHY_743_DATA + DDRSS1_PHY_744_DATA + DDRSS1_PHY_745_DATA + DDRSS1_PHY_746_DATA + DDRSS1_PHY_747_DATA + DDRSS1_PHY_748_DATA + DDRSS1_PHY_749_DATA + DDRSS1_PHY_750_DATA + DDRSS1_PHY_751_DATA + DDRSS1_PHY_752_DATA + DDRSS1_PHY_753_DATA + DDRSS1_PHY_754_DATA + DDRSS1_PHY_755_DATA + DDRSS1_PHY_756_DATA + DDRSS1_PHY_757_DATA + DDRSS1_PHY_758_DATA + DDRSS1_PHY_759_DATA + DDRSS1_PHY_760_DATA + DDRSS1_PHY_761_DATA + DDRSS1_PHY_762_DATA + DDRSS1_PHY_763_DATA + DDRSS1_PHY_764_DATA + DDRSS1_PHY_765_DATA + DDRSS1_PHY_766_DATA + DDRSS1_PHY_767_DATA + DDRSS1_PHY_768_DATA + DDRSS1_PHY_769_DATA + DDRSS1_PHY_770_DATA + DDRSS1_PHY_771_DATA + DDRSS1_PHY_772_DATA + DDRSS1_PHY_773_DATA + DDRSS1_PHY_774_DATA + DDRSS1_PHY_775_DATA + DDRSS1_PHY_776_DATA + DDRSS1_PHY_777_DATA + DDRSS1_PHY_778_DATA + DDRSS1_PHY_779_DATA + DDRSS1_PHY_780_DATA + DDRSS1_PHY_781_DATA + DDRSS1_PHY_782_DATA + DDRSS1_PHY_783_DATA + DDRSS1_PHY_784_DATA + DDRSS1_PHY_785_DATA + DDRSS1_PHY_786_DATA + DDRSS1_PHY_787_DATA + DDRSS1_PHY_788_DATA + DDRSS1_PHY_789_DATA + DDRSS1_PHY_790_DATA + DDRSS1_PHY_791_DATA + DDRSS1_PHY_792_DATA + DDRSS1_PHY_793_DATA + DDRSS1_PHY_794_DATA + DDRSS1_PHY_795_DATA + DDRSS1_PHY_796_DATA + DDRSS1_PHY_797_DATA + DDRSS1_PHY_798_DATA + DDRSS1_PHY_799_DATA + DDRSS1_PHY_800_DATA + DDRSS1_PHY_801_DATA + DDRSS1_PHY_802_DATA + DDRSS1_PHY_803_DATA + DDRSS1_PHY_804_DATA + DDRSS1_PHY_805_DATA + DDRSS1_PHY_806_DATA + DDRSS1_PHY_807_DATA + DDRSS1_PHY_808_DATA + DDRSS1_PHY_809_DATA + DDRSS1_PHY_810_DATA + DDRSS1_PHY_811_DATA + DDRSS1_PHY_812_DATA + DDRSS1_PHY_813_DATA + DDRSS1_PHY_814_DATA + DDRSS1_PHY_815_DATA + DDRSS1_PHY_816_DATA + DDRSS1_PHY_817_DATA + DDRSS1_PHY_818_DATA + DDRSS1_PHY_819_DATA + DDRSS1_PHY_820_DATA + DDRSS1_PHY_821_DATA + DDRSS1_PHY_822_DATA + DDRSS1_PHY_823_DATA + DDRSS1_PHY_824_DATA + DDRSS1_PHY_825_DATA + DDRSS1_PHY_826_DATA + DDRSS1_PHY_827_DATA + DDRSS1_PHY_828_DATA + DDRSS1_PHY_829_DATA + DDRSS1_PHY_830_DATA + DDRSS1_PHY_831_DATA + DDRSS1_PHY_832_DATA + DDRSS1_PHY_833_DATA + DDRSS1_PHY_834_DATA + DDRSS1_PHY_835_DATA + DDRSS1_PHY_836_DATA + DDRSS1_PHY_837_DATA + DDRSS1_PHY_838_DATA + DDRSS1_PHY_839_DATA + DDRSS1_PHY_840_DATA + DDRSS1_PHY_841_DATA + DDRSS1_PHY_842_DATA + DDRSS1_PHY_843_DATA + DDRSS1_PHY_844_DATA + DDRSS1_PHY_845_DATA + DDRSS1_PHY_846_DATA + DDRSS1_PHY_847_DATA + DDRSS1_PHY_848_DATA + DDRSS1_PHY_849_DATA + DDRSS1_PHY_850_DATA + DDRSS1_PHY_851_DATA + DDRSS1_PHY_852_DATA + DDRSS1_PHY_853_DATA + DDRSS1_PHY_854_DATA + DDRSS1_PHY_855_DATA + DDRSS1_PHY_856_DATA + DDRSS1_PHY_857_DATA + DDRSS1_PHY_858_DATA + DDRSS1_PHY_859_DATA + DDRSS1_PHY_860_DATA + DDRSS1_PHY_861_DATA + DDRSS1_PHY_862_DATA + DDRSS1_PHY_863_DATA + DDRSS1_PHY_864_DATA + DDRSS1_PHY_865_DATA + DDRSS1_PHY_866_DATA + DDRSS1_PHY_867_DATA + DDRSS1_PHY_868_DATA + DDRSS1_PHY_869_DATA + DDRSS1_PHY_870_DATA + DDRSS1_PHY_871_DATA + DDRSS1_PHY_872_DATA + DDRSS1_PHY_873_DATA + DDRSS1_PHY_874_DATA + DDRSS1_PHY_875_DATA + DDRSS1_PHY_876_DATA + DDRSS1_PHY_877_DATA + DDRSS1_PHY_878_DATA + DDRSS1_PHY_879_DATA + DDRSS1_PHY_880_DATA + DDRSS1_PHY_881_DATA + DDRSS1_PHY_882_DATA + DDRSS1_PHY_883_DATA + DDRSS1_PHY_884_DATA + DDRSS1_PHY_885_DATA + DDRSS1_PHY_886_DATA + DDRSS1_PHY_887_DATA + DDRSS1_PHY_888_DATA + DDRSS1_PHY_889_DATA + DDRSS1_PHY_890_DATA + DDRSS1_PHY_891_DATA + DDRSS1_PHY_892_DATA + DDRSS1_PHY_893_DATA + DDRSS1_PHY_894_DATA + DDRSS1_PHY_895_DATA + DDRSS1_PHY_896_DATA + DDRSS1_PHY_897_DATA + DDRSS1_PHY_898_DATA + DDRSS1_PHY_899_DATA + DDRSS1_PHY_900_DATA + DDRSS1_PHY_901_DATA + DDRSS1_PHY_902_DATA + DDRSS1_PHY_903_DATA + DDRSS1_PHY_904_DATA + DDRSS1_PHY_905_DATA + DDRSS1_PHY_906_DATA + DDRSS1_PHY_907_DATA + DDRSS1_PHY_908_DATA + DDRSS1_PHY_909_DATA + DDRSS1_PHY_910_DATA + DDRSS1_PHY_911_DATA + DDRSS1_PHY_912_DATA + DDRSS1_PHY_913_DATA + DDRSS1_PHY_914_DATA + DDRSS1_PHY_915_DATA + DDRSS1_PHY_916_DATA + DDRSS1_PHY_917_DATA + DDRSS1_PHY_918_DATA + DDRSS1_PHY_919_DATA + DDRSS1_PHY_920_DATA + DDRSS1_PHY_921_DATA + DDRSS1_PHY_922_DATA + DDRSS1_PHY_923_DATA + DDRSS1_PHY_924_DATA + DDRSS1_PHY_925_DATA + DDRSS1_PHY_926_DATA + DDRSS1_PHY_927_DATA + DDRSS1_PHY_928_DATA + DDRSS1_PHY_929_DATA + DDRSS1_PHY_930_DATA + DDRSS1_PHY_931_DATA + DDRSS1_PHY_932_DATA + DDRSS1_PHY_933_DATA + DDRSS1_PHY_934_DATA + DDRSS1_PHY_935_DATA + DDRSS1_PHY_936_DATA + DDRSS1_PHY_937_DATA + DDRSS1_PHY_938_DATA + DDRSS1_PHY_939_DATA + DDRSS1_PHY_940_DATA + DDRSS1_PHY_941_DATA + DDRSS1_PHY_942_DATA + DDRSS1_PHY_943_DATA + DDRSS1_PHY_944_DATA + DDRSS1_PHY_945_DATA + DDRSS1_PHY_946_DATA + DDRSS1_PHY_947_DATA + DDRSS1_PHY_948_DATA + DDRSS1_PHY_949_DATA + DDRSS1_PHY_950_DATA + DDRSS1_PHY_951_DATA + DDRSS1_PHY_952_DATA + DDRSS1_PHY_953_DATA + DDRSS1_PHY_954_DATA + DDRSS1_PHY_955_DATA + DDRSS1_PHY_956_DATA + DDRSS1_PHY_957_DATA + DDRSS1_PHY_958_DATA + DDRSS1_PHY_959_DATA + DDRSS1_PHY_960_DATA + DDRSS1_PHY_961_DATA + DDRSS1_PHY_962_DATA + DDRSS1_PHY_963_DATA + DDRSS1_PHY_964_DATA + DDRSS1_PHY_965_DATA + DDRSS1_PHY_966_DATA + DDRSS1_PHY_967_DATA + DDRSS1_PHY_968_DATA + DDRSS1_PHY_969_DATA + DDRSS1_PHY_970_DATA + DDRSS1_PHY_971_DATA + DDRSS1_PHY_972_DATA + DDRSS1_PHY_973_DATA + DDRSS1_PHY_974_DATA + DDRSS1_PHY_975_DATA + DDRSS1_PHY_976_DATA + DDRSS1_PHY_977_DATA + DDRSS1_PHY_978_DATA + DDRSS1_PHY_979_DATA + DDRSS1_PHY_980_DATA + DDRSS1_PHY_981_DATA + DDRSS1_PHY_982_DATA + DDRSS1_PHY_983_DATA + DDRSS1_PHY_984_DATA + DDRSS1_PHY_985_DATA + DDRSS1_PHY_986_DATA + DDRSS1_PHY_987_DATA + DDRSS1_PHY_988_DATA + DDRSS1_PHY_989_DATA + DDRSS1_PHY_990_DATA + DDRSS1_PHY_991_DATA + DDRSS1_PHY_992_DATA + DDRSS1_PHY_993_DATA + DDRSS1_PHY_994_DATA + DDRSS1_PHY_995_DATA + DDRSS1_PHY_996_DATA + DDRSS1_PHY_997_DATA + DDRSS1_PHY_998_DATA + DDRSS1_PHY_999_DATA + DDRSS1_PHY_1000_DATA + DDRSS1_PHY_1001_DATA + DDRSS1_PHY_1002_DATA + DDRSS1_PHY_1003_DATA + DDRSS1_PHY_1004_DATA + DDRSS1_PHY_1005_DATA + DDRSS1_PHY_1006_DATA + DDRSS1_PHY_1007_DATA + DDRSS1_PHY_1008_DATA + DDRSS1_PHY_1009_DATA + DDRSS1_PHY_1010_DATA + DDRSS1_PHY_1011_DATA + DDRSS1_PHY_1012_DATA + DDRSS1_PHY_1013_DATA + DDRSS1_PHY_1014_DATA + DDRSS1_PHY_1015_DATA + DDRSS1_PHY_1016_DATA + DDRSS1_PHY_1017_DATA + DDRSS1_PHY_1018_DATA + DDRSS1_PHY_1019_DATA + DDRSS1_PHY_1020_DATA + DDRSS1_PHY_1021_DATA + DDRSS1_PHY_1022_DATA + DDRSS1_PHY_1023_DATA + DDRSS1_PHY_1024_DATA + DDRSS1_PHY_1025_DATA + DDRSS1_PHY_1026_DATA + DDRSS1_PHY_1027_DATA + DDRSS1_PHY_1028_DATA + DDRSS1_PHY_1029_DATA + DDRSS1_PHY_1030_DATA + DDRSS1_PHY_1031_DATA + DDRSS1_PHY_1032_DATA + DDRSS1_PHY_1033_DATA + DDRSS1_PHY_1034_DATA + DDRSS1_PHY_1035_DATA + DDRSS1_PHY_1036_DATA + DDRSS1_PHY_1037_DATA + DDRSS1_PHY_1038_DATA + DDRSS1_PHY_1039_DATA + DDRSS1_PHY_1040_DATA + DDRSS1_PHY_1041_DATA + DDRSS1_PHY_1042_DATA + DDRSS1_PHY_1043_DATA + DDRSS1_PHY_1044_DATA + DDRSS1_PHY_1045_DATA + DDRSS1_PHY_1046_DATA + DDRSS1_PHY_1047_DATA + DDRSS1_PHY_1048_DATA + DDRSS1_PHY_1049_DATA + DDRSS1_PHY_1050_DATA + DDRSS1_PHY_1051_DATA + DDRSS1_PHY_1052_DATA + DDRSS1_PHY_1053_DATA + DDRSS1_PHY_1054_DATA + DDRSS1_PHY_1055_DATA + DDRSS1_PHY_1056_DATA + DDRSS1_PHY_1057_DATA + DDRSS1_PHY_1058_DATA + DDRSS1_PHY_1059_DATA + DDRSS1_PHY_1060_DATA + DDRSS1_PHY_1061_DATA + DDRSS1_PHY_1062_DATA + DDRSS1_PHY_1063_DATA + DDRSS1_PHY_1064_DATA + DDRSS1_PHY_1065_DATA + DDRSS1_PHY_1066_DATA + DDRSS1_PHY_1067_DATA + DDRSS1_PHY_1068_DATA + DDRSS1_PHY_1069_DATA + DDRSS1_PHY_1070_DATA + DDRSS1_PHY_1071_DATA + DDRSS1_PHY_1072_DATA + DDRSS1_PHY_1073_DATA + DDRSS1_PHY_1074_DATA + DDRSS1_PHY_1075_DATA + DDRSS1_PHY_1076_DATA + DDRSS1_PHY_1077_DATA + DDRSS1_PHY_1078_DATA + DDRSS1_PHY_1079_DATA + DDRSS1_PHY_1080_DATA + DDRSS1_PHY_1081_DATA + DDRSS1_PHY_1082_DATA + DDRSS1_PHY_1083_DATA + DDRSS1_PHY_1084_DATA + DDRSS1_PHY_1085_DATA + DDRSS1_PHY_1086_DATA + DDRSS1_PHY_1087_DATA + DDRSS1_PHY_1088_DATA + DDRSS1_PHY_1089_DATA + DDRSS1_PHY_1090_DATA + DDRSS1_PHY_1091_DATA + DDRSS1_PHY_1092_DATA + DDRSS1_PHY_1093_DATA + DDRSS1_PHY_1094_DATA + DDRSS1_PHY_1095_DATA + DDRSS1_PHY_1096_DATA + DDRSS1_PHY_1097_DATA + DDRSS1_PHY_1098_DATA + DDRSS1_PHY_1099_DATA + DDRSS1_PHY_1100_DATA + DDRSS1_PHY_1101_DATA + DDRSS1_PHY_1102_DATA + DDRSS1_PHY_1103_DATA + DDRSS1_PHY_1104_DATA + DDRSS1_PHY_1105_DATA + DDRSS1_PHY_1106_DATA + DDRSS1_PHY_1107_DATA + DDRSS1_PHY_1108_DATA + DDRSS1_PHY_1109_DATA + DDRSS1_PHY_1110_DATA + DDRSS1_PHY_1111_DATA + DDRSS1_PHY_1112_DATA + DDRSS1_PHY_1113_DATA + DDRSS1_PHY_1114_DATA + DDRSS1_PHY_1115_DATA + DDRSS1_PHY_1116_DATA + DDRSS1_PHY_1117_DATA + DDRSS1_PHY_1118_DATA + DDRSS1_PHY_1119_DATA + DDRSS1_PHY_1120_DATA + DDRSS1_PHY_1121_DATA + DDRSS1_PHY_1122_DATA + DDRSS1_PHY_1123_DATA + DDRSS1_PHY_1124_DATA + DDRSS1_PHY_1125_DATA + DDRSS1_PHY_1126_DATA + DDRSS1_PHY_1127_DATA + DDRSS1_PHY_1128_DATA + DDRSS1_PHY_1129_DATA + DDRSS1_PHY_1130_DATA + DDRSS1_PHY_1131_DATA + DDRSS1_PHY_1132_DATA + DDRSS1_PHY_1133_DATA + DDRSS1_PHY_1134_DATA + DDRSS1_PHY_1135_DATA + DDRSS1_PHY_1136_DATA + DDRSS1_PHY_1137_DATA + DDRSS1_PHY_1138_DATA + DDRSS1_PHY_1139_DATA + DDRSS1_PHY_1140_DATA + DDRSS1_PHY_1141_DATA + DDRSS1_PHY_1142_DATA + DDRSS1_PHY_1143_DATA + DDRSS1_PHY_1144_DATA + DDRSS1_PHY_1145_DATA + DDRSS1_PHY_1146_DATA + DDRSS1_PHY_1147_DATA + DDRSS1_PHY_1148_DATA + DDRSS1_PHY_1149_DATA + DDRSS1_PHY_1150_DATA + DDRSS1_PHY_1151_DATA + DDRSS1_PHY_1152_DATA + DDRSS1_PHY_1153_DATA + DDRSS1_PHY_1154_DATA + DDRSS1_PHY_1155_DATA + DDRSS1_PHY_1156_DATA + DDRSS1_PHY_1157_DATA + DDRSS1_PHY_1158_DATA + DDRSS1_PHY_1159_DATA + DDRSS1_PHY_1160_DATA + DDRSS1_PHY_1161_DATA + DDRSS1_PHY_1162_DATA + DDRSS1_PHY_1163_DATA + DDRSS1_PHY_1164_DATA + DDRSS1_PHY_1165_DATA + DDRSS1_PHY_1166_DATA + DDRSS1_PHY_1167_DATA + DDRSS1_PHY_1168_DATA + DDRSS1_PHY_1169_DATA + DDRSS1_PHY_1170_DATA + DDRSS1_PHY_1171_DATA + DDRSS1_PHY_1172_DATA + DDRSS1_PHY_1173_DATA + DDRSS1_PHY_1174_DATA + DDRSS1_PHY_1175_DATA + DDRSS1_PHY_1176_DATA + DDRSS1_PHY_1177_DATA + DDRSS1_PHY_1178_DATA + DDRSS1_PHY_1179_DATA + DDRSS1_PHY_1180_DATA + DDRSS1_PHY_1181_DATA + DDRSS1_PHY_1182_DATA + DDRSS1_PHY_1183_DATA + DDRSS1_PHY_1184_DATA + DDRSS1_PHY_1185_DATA + DDRSS1_PHY_1186_DATA + DDRSS1_PHY_1187_DATA + DDRSS1_PHY_1188_DATA + DDRSS1_PHY_1189_DATA + DDRSS1_PHY_1190_DATA + DDRSS1_PHY_1191_DATA + DDRSS1_PHY_1192_DATA + DDRSS1_PHY_1193_DATA + DDRSS1_PHY_1194_DATA + DDRSS1_PHY_1195_DATA + DDRSS1_PHY_1196_DATA + DDRSS1_PHY_1197_DATA + DDRSS1_PHY_1198_DATA + DDRSS1_PHY_1199_DATA + DDRSS1_PHY_1200_DATA + DDRSS1_PHY_1201_DATA + DDRSS1_PHY_1202_DATA + DDRSS1_PHY_1203_DATA + DDRSS1_PHY_1204_DATA + DDRSS1_PHY_1205_DATA + DDRSS1_PHY_1206_DATA + DDRSS1_PHY_1207_DATA + DDRSS1_PHY_1208_DATA + DDRSS1_PHY_1209_DATA + DDRSS1_PHY_1210_DATA + DDRSS1_PHY_1211_DATA + DDRSS1_PHY_1212_DATA + DDRSS1_PHY_1213_DATA + DDRSS1_PHY_1214_DATA + DDRSS1_PHY_1215_DATA + DDRSS1_PHY_1216_DATA + DDRSS1_PHY_1217_DATA + DDRSS1_PHY_1218_DATA + DDRSS1_PHY_1219_DATA + DDRSS1_PHY_1220_DATA + DDRSS1_PHY_1221_DATA + DDRSS1_PHY_1222_DATA + DDRSS1_PHY_1223_DATA + DDRSS1_PHY_1224_DATA + DDRSS1_PHY_1225_DATA + DDRSS1_PHY_1226_DATA + DDRSS1_PHY_1227_DATA + DDRSS1_PHY_1228_DATA + DDRSS1_PHY_1229_DATA + DDRSS1_PHY_1230_DATA + DDRSS1_PHY_1231_DATA + DDRSS1_PHY_1232_DATA + DDRSS1_PHY_1233_DATA + DDRSS1_PHY_1234_DATA + DDRSS1_PHY_1235_DATA + DDRSS1_PHY_1236_DATA + DDRSS1_PHY_1237_DATA + DDRSS1_PHY_1238_DATA + DDRSS1_PHY_1239_DATA + DDRSS1_PHY_1240_DATA + DDRSS1_PHY_1241_DATA + DDRSS1_PHY_1242_DATA + DDRSS1_PHY_1243_DATA + DDRSS1_PHY_1244_DATA + DDRSS1_PHY_1245_DATA + DDRSS1_PHY_1246_DATA + DDRSS1_PHY_1247_DATA + DDRSS1_PHY_1248_DATA + DDRSS1_PHY_1249_DATA + DDRSS1_PHY_1250_DATA + DDRSS1_PHY_1251_DATA + DDRSS1_PHY_1252_DATA + DDRSS1_PHY_1253_DATA + DDRSS1_PHY_1254_DATA + DDRSS1_PHY_1255_DATA + DDRSS1_PHY_1256_DATA + DDRSS1_PHY_1257_DATA + DDRSS1_PHY_1258_DATA + DDRSS1_PHY_1259_DATA + DDRSS1_PHY_1260_DATA + DDRSS1_PHY_1261_DATA + DDRSS1_PHY_1262_DATA + DDRSS1_PHY_1263_DATA + DDRSS1_PHY_1264_DATA + DDRSS1_PHY_1265_DATA + DDRSS1_PHY_1266_DATA + DDRSS1_PHY_1267_DATA + DDRSS1_PHY_1268_DATA + DDRSS1_PHY_1269_DATA + DDRSS1_PHY_1270_DATA + DDRSS1_PHY_1271_DATA + DDRSS1_PHY_1272_DATA + DDRSS1_PHY_1273_DATA + DDRSS1_PHY_1274_DATA + DDRSS1_PHY_1275_DATA + DDRSS1_PHY_1276_DATA + DDRSS1_PHY_1277_DATA + DDRSS1_PHY_1278_DATA + DDRSS1_PHY_1279_DATA + DDRSS1_PHY_1280_DATA + DDRSS1_PHY_1281_DATA + DDRSS1_PHY_1282_DATA + DDRSS1_PHY_1283_DATA + DDRSS1_PHY_1284_DATA + DDRSS1_PHY_1285_DATA + DDRSS1_PHY_1286_DATA + DDRSS1_PHY_1287_DATA + DDRSS1_PHY_1288_DATA + DDRSS1_PHY_1289_DATA + DDRSS1_PHY_1290_DATA + DDRSS1_PHY_1291_DATA + DDRSS1_PHY_1292_DATA + DDRSS1_PHY_1293_DATA + DDRSS1_PHY_1294_DATA + DDRSS1_PHY_1295_DATA + DDRSS1_PHY_1296_DATA + DDRSS1_PHY_1297_DATA + DDRSS1_PHY_1298_DATA + DDRSS1_PHY_1299_DATA + DDRSS1_PHY_1300_DATA + DDRSS1_PHY_1301_DATA + DDRSS1_PHY_1302_DATA + DDRSS1_PHY_1303_DATA + DDRSS1_PHY_1304_DATA + DDRSS1_PHY_1305_DATA + DDRSS1_PHY_1306_DATA + DDRSS1_PHY_1307_DATA + DDRSS1_PHY_1308_DATA + DDRSS1_PHY_1309_DATA + DDRSS1_PHY_1310_DATA + DDRSS1_PHY_1311_DATA + DDRSS1_PHY_1312_DATA + DDRSS1_PHY_1313_DATA + DDRSS1_PHY_1314_DATA + DDRSS1_PHY_1315_DATA + DDRSS1_PHY_1316_DATA + DDRSS1_PHY_1317_DATA + DDRSS1_PHY_1318_DATA + DDRSS1_PHY_1319_DATA + DDRSS1_PHY_1320_DATA + DDRSS1_PHY_1321_DATA + DDRSS1_PHY_1322_DATA + DDRSS1_PHY_1323_DATA + DDRSS1_PHY_1324_DATA + DDRSS1_PHY_1325_DATA + DDRSS1_PHY_1326_DATA + DDRSS1_PHY_1327_DATA + DDRSS1_PHY_1328_DATA + DDRSS1_PHY_1329_DATA + DDRSS1_PHY_1330_DATA + DDRSS1_PHY_1331_DATA + DDRSS1_PHY_1332_DATA + DDRSS1_PHY_1333_DATA + DDRSS1_PHY_1334_DATA + DDRSS1_PHY_1335_DATA + DDRSS1_PHY_1336_DATA + DDRSS1_PHY_1337_DATA + DDRSS1_PHY_1338_DATA + DDRSS1_PHY_1339_DATA + DDRSS1_PHY_1340_DATA + DDRSS1_PHY_1341_DATA + DDRSS1_PHY_1342_DATA + DDRSS1_PHY_1343_DATA + DDRSS1_PHY_1344_DATA + DDRSS1_PHY_1345_DATA + DDRSS1_PHY_1346_DATA + DDRSS1_PHY_1347_DATA + DDRSS1_PHY_1348_DATA + DDRSS1_PHY_1349_DATA + DDRSS1_PHY_1350_DATA + DDRSS1_PHY_1351_DATA + DDRSS1_PHY_1352_DATA + DDRSS1_PHY_1353_DATA + DDRSS1_PHY_1354_DATA + DDRSS1_PHY_1355_DATA + DDRSS1_PHY_1356_DATA + DDRSS1_PHY_1357_DATA + DDRSS1_PHY_1358_DATA + DDRSS1_PHY_1359_DATA + DDRSS1_PHY_1360_DATA + DDRSS1_PHY_1361_DATA + DDRSS1_PHY_1362_DATA + DDRSS1_PHY_1363_DATA + DDRSS1_PHY_1364_DATA + DDRSS1_PHY_1365_DATA + DDRSS1_PHY_1366_DATA + DDRSS1_PHY_1367_DATA + DDRSS1_PHY_1368_DATA + DDRSS1_PHY_1369_DATA + DDRSS1_PHY_1370_DATA + DDRSS1_PHY_1371_DATA + DDRSS1_PHY_1372_DATA + DDRSS1_PHY_1373_DATA + DDRSS1_PHY_1374_DATA + DDRSS1_PHY_1375_DATA + DDRSS1_PHY_1376_DATA + DDRSS1_PHY_1377_DATA + DDRSS1_PHY_1378_DATA + DDRSS1_PHY_1379_DATA + DDRSS1_PHY_1380_DATA + DDRSS1_PHY_1381_DATA + DDRSS1_PHY_1382_DATA + DDRSS1_PHY_1383_DATA + DDRSS1_PHY_1384_DATA + DDRSS1_PHY_1385_DATA + DDRSS1_PHY_1386_DATA + DDRSS1_PHY_1387_DATA + DDRSS1_PHY_1388_DATA + DDRSS1_PHY_1389_DATA + DDRSS1_PHY_1390_DATA + DDRSS1_PHY_1391_DATA + DDRSS1_PHY_1392_DATA + DDRSS1_PHY_1393_DATA + DDRSS1_PHY_1394_DATA + DDRSS1_PHY_1395_DATA + DDRSS1_PHY_1396_DATA + DDRSS1_PHY_1397_DATA + DDRSS1_PHY_1398_DATA + DDRSS1_PHY_1399_DATA + DDRSS1_PHY_1400_DATA + DDRSS1_PHY_1401_DATA + DDRSS1_PHY_1402_DATA + DDRSS1_PHY_1403_DATA + DDRSS1_PHY_1404_DATA + DDRSS1_PHY_1405_DATA + DDRSS1_PHY_1406_DATA + DDRSS1_PHY_1407_DATA + DDRSS1_PHY_1408_DATA + DDRSS1_PHY_1409_DATA + DDRSS1_PHY_1410_DATA + DDRSS1_PHY_1411_DATA + DDRSS1_PHY_1412_DATA + DDRSS1_PHY_1413_DATA + DDRSS1_PHY_1414_DATA + DDRSS1_PHY_1415_DATA + DDRSS1_PHY_1416_DATA + DDRSS1_PHY_1417_DATA + DDRSS1_PHY_1418_DATA + DDRSS1_PHY_1419_DATA + DDRSS1_PHY_1420_DATA + DDRSS1_PHY_1421_DATA + DDRSS1_PHY_1422_DATA + >; + }; + + memorycontroller2: memorycontroller@29d0000 { + compatible = "ti,j721s2-ddrss"; + reg = <0x0 0x029d0000 0x0 0x4000>, + <0x0 0x0114000 0x0 0x100>; + reg-names = "cfg", "ctrl_mmr_lp4"; + power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>, + <&k3_pds 133 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 193 1>, <&k3_clks 78 2>; + ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>; + ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>; + ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>; + ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>; + instance = <2>; + + bootph-pre-ram; + + ti,ctl-data = < + DDRSS2_CTL_00_DATA + DDRSS2_CTL_01_DATA + DDRSS2_CTL_02_DATA + DDRSS2_CTL_03_DATA + DDRSS2_CTL_04_DATA + DDRSS2_CTL_05_DATA + DDRSS2_CTL_06_DATA + DDRSS2_CTL_07_DATA + DDRSS2_CTL_08_DATA + DDRSS2_CTL_09_DATA + DDRSS2_CTL_10_DATA + DDRSS2_CTL_11_DATA + DDRSS2_CTL_12_DATA + DDRSS2_CTL_13_DATA + DDRSS2_CTL_14_DATA + DDRSS2_CTL_15_DATA + DDRSS2_CTL_16_DATA + DDRSS2_CTL_17_DATA + DDRSS2_CTL_18_DATA + DDRSS2_CTL_19_DATA + DDRSS2_CTL_20_DATA + DDRSS2_CTL_21_DATA + DDRSS2_CTL_22_DATA + DDRSS2_CTL_23_DATA + DDRSS2_CTL_24_DATA + DDRSS2_CTL_25_DATA + DDRSS2_CTL_26_DATA + DDRSS2_CTL_27_DATA + DDRSS2_CTL_28_DATA + DDRSS2_CTL_29_DATA + DDRSS2_CTL_30_DATA + DDRSS2_CTL_31_DATA + DDRSS2_CTL_32_DATA + DDRSS2_CTL_33_DATA + DDRSS2_CTL_34_DATA + DDRSS2_CTL_35_DATA + DDRSS2_CTL_36_DATA + DDRSS2_CTL_37_DATA + DDRSS2_CTL_38_DATA + DDRSS2_CTL_39_DATA + DDRSS2_CTL_40_DATA + DDRSS2_CTL_41_DATA + DDRSS2_CTL_42_DATA + DDRSS2_CTL_43_DATA + DDRSS2_CTL_44_DATA + DDRSS2_CTL_45_DATA + DDRSS2_CTL_46_DATA + DDRSS2_CTL_47_DATA + DDRSS2_CTL_48_DATA + DDRSS2_CTL_49_DATA + DDRSS2_CTL_50_DATA + DDRSS2_CTL_51_DATA + DDRSS2_CTL_52_DATA + DDRSS2_CTL_53_DATA + DDRSS2_CTL_54_DATA + DDRSS2_CTL_55_DATA + DDRSS2_CTL_56_DATA + DDRSS2_CTL_57_DATA + DDRSS2_CTL_58_DATA + DDRSS2_CTL_59_DATA + DDRSS2_CTL_60_DATA + DDRSS2_CTL_61_DATA + DDRSS2_CTL_62_DATA + DDRSS2_CTL_63_DATA + DDRSS2_CTL_64_DATA + DDRSS2_CTL_65_DATA + DDRSS2_CTL_66_DATA + DDRSS2_CTL_67_DATA + DDRSS2_CTL_68_DATA + DDRSS2_CTL_69_DATA + DDRSS2_CTL_70_DATA + DDRSS2_CTL_71_DATA + DDRSS2_CTL_72_DATA + DDRSS2_CTL_73_DATA + DDRSS2_CTL_74_DATA + DDRSS2_CTL_75_DATA + DDRSS2_CTL_76_DATA + DDRSS2_CTL_77_DATA + DDRSS2_CTL_78_DATA + DDRSS2_CTL_79_DATA + DDRSS2_CTL_80_DATA + DDRSS2_CTL_81_DATA + DDRSS2_CTL_82_DATA + DDRSS2_CTL_83_DATA + DDRSS2_CTL_84_DATA + DDRSS2_CTL_85_DATA + DDRSS2_CTL_86_DATA + DDRSS2_CTL_87_DATA + DDRSS2_CTL_88_DATA + DDRSS2_CTL_89_DATA + DDRSS2_CTL_90_DATA + DDRSS2_CTL_91_DATA + DDRSS2_CTL_92_DATA + DDRSS2_CTL_93_DATA + DDRSS2_CTL_94_DATA + DDRSS2_CTL_95_DATA + DDRSS2_CTL_96_DATA + DDRSS2_CTL_97_DATA + DDRSS2_CTL_98_DATA + DDRSS2_CTL_99_DATA + DDRSS2_CTL_100_DATA + DDRSS2_CTL_101_DATA + DDRSS2_CTL_102_DATA + DDRSS2_CTL_103_DATA + DDRSS2_CTL_104_DATA + DDRSS2_CTL_105_DATA + DDRSS2_CTL_106_DATA + DDRSS2_CTL_107_DATA + DDRSS2_CTL_108_DATA + DDRSS2_CTL_109_DATA + DDRSS2_CTL_110_DATA + DDRSS2_CTL_111_DATA + DDRSS2_CTL_112_DATA + DDRSS2_CTL_113_DATA + DDRSS2_CTL_114_DATA + DDRSS2_CTL_115_DATA + DDRSS2_CTL_116_DATA + DDRSS2_CTL_117_DATA + DDRSS2_CTL_118_DATA + DDRSS2_CTL_119_DATA + DDRSS2_CTL_120_DATA + DDRSS2_CTL_121_DATA + DDRSS2_CTL_122_DATA + DDRSS2_CTL_123_DATA + DDRSS2_CTL_124_DATA + DDRSS2_CTL_125_DATA + DDRSS2_CTL_126_DATA + DDRSS2_CTL_127_DATA + DDRSS2_CTL_128_DATA + DDRSS2_CTL_129_DATA + DDRSS2_CTL_130_DATA + DDRSS2_CTL_131_DATA + DDRSS2_CTL_132_DATA + DDRSS2_CTL_133_DATA + DDRSS2_CTL_134_DATA + DDRSS2_CTL_135_DATA + DDRSS2_CTL_136_DATA + DDRSS2_CTL_137_DATA + DDRSS2_CTL_138_DATA + DDRSS2_CTL_139_DATA + DDRSS2_CTL_140_DATA + DDRSS2_CTL_141_DATA + DDRSS2_CTL_142_DATA + DDRSS2_CTL_143_DATA + DDRSS2_CTL_144_DATA + DDRSS2_CTL_145_DATA + DDRSS2_CTL_146_DATA + DDRSS2_CTL_147_DATA + DDRSS2_CTL_148_DATA + DDRSS2_CTL_149_DATA + DDRSS2_CTL_150_DATA + DDRSS2_CTL_151_DATA + DDRSS2_CTL_152_DATA + DDRSS2_CTL_153_DATA + DDRSS2_CTL_154_DATA + DDRSS2_CTL_155_DATA + DDRSS2_CTL_156_DATA + DDRSS2_CTL_157_DATA + DDRSS2_CTL_158_DATA + DDRSS2_CTL_159_DATA + DDRSS2_CTL_160_DATA + DDRSS2_CTL_161_DATA + DDRSS2_CTL_162_DATA + DDRSS2_CTL_163_DATA + DDRSS2_CTL_164_DATA + DDRSS2_CTL_165_DATA + DDRSS2_CTL_166_DATA + DDRSS2_CTL_167_DATA + DDRSS2_CTL_168_DATA + DDRSS2_CTL_169_DATA + DDRSS2_CTL_170_DATA + DDRSS2_CTL_171_DATA + DDRSS2_CTL_172_DATA + DDRSS2_CTL_173_DATA + DDRSS2_CTL_174_DATA + DDRSS2_CTL_175_DATA + DDRSS2_CTL_176_DATA + DDRSS2_CTL_177_DATA + DDRSS2_CTL_178_DATA + DDRSS2_CTL_179_DATA + DDRSS2_CTL_180_DATA + DDRSS2_CTL_181_DATA + DDRSS2_CTL_182_DATA + DDRSS2_CTL_183_DATA + DDRSS2_CTL_184_DATA + DDRSS2_CTL_185_DATA + DDRSS2_CTL_186_DATA + DDRSS2_CTL_187_DATA + DDRSS2_CTL_188_DATA + DDRSS2_CTL_189_DATA + DDRSS2_CTL_190_DATA + DDRSS2_CTL_191_DATA + DDRSS2_CTL_192_DATA + DDRSS2_CTL_193_DATA + DDRSS2_CTL_194_DATA + DDRSS2_CTL_195_DATA + DDRSS2_CTL_196_DATA + DDRSS2_CTL_197_DATA + DDRSS2_CTL_198_DATA + DDRSS2_CTL_199_DATA + DDRSS2_CTL_200_DATA + DDRSS2_CTL_201_DATA + DDRSS2_CTL_202_DATA + DDRSS2_CTL_203_DATA + DDRSS2_CTL_204_DATA + DDRSS2_CTL_205_DATA + DDRSS2_CTL_206_DATA + DDRSS2_CTL_207_DATA + DDRSS2_CTL_208_DATA + DDRSS2_CTL_209_DATA + DDRSS2_CTL_210_DATA + DDRSS2_CTL_211_DATA + DDRSS2_CTL_212_DATA + DDRSS2_CTL_213_DATA + DDRSS2_CTL_214_DATA + DDRSS2_CTL_215_DATA + DDRSS2_CTL_216_DATA + DDRSS2_CTL_217_DATA + DDRSS2_CTL_218_DATA + DDRSS2_CTL_219_DATA + DDRSS2_CTL_220_DATA + DDRSS2_CTL_221_DATA + DDRSS2_CTL_222_DATA + DDRSS2_CTL_223_DATA + DDRSS2_CTL_224_DATA + DDRSS2_CTL_225_DATA + DDRSS2_CTL_226_DATA + DDRSS2_CTL_227_DATA + DDRSS2_CTL_228_DATA + DDRSS2_CTL_229_DATA + DDRSS2_CTL_230_DATA + DDRSS2_CTL_231_DATA + DDRSS2_CTL_232_DATA + DDRSS2_CTL_233_DATA + DDRSS2_CTL_234_DATA + DDRSS2_CTL_235_DATA + DDRSS2_CTL_236_DATA + DDRSS2_CTL_237_DATA + DDRSS2_CTL_238_DATA + DDRSS2_CTL_239_DATA + DDRSS2_CTL_240_DATA + DDRSS2_CTL_241_DATA + DDRSS2_CTL_242_DATA + DDRSS2_CTL_243_DATA + DDRSS2_CTL_244_DATA + DDRSS2_CTL_245_DATA + DDRSS2_CTL_246_DATA + DDRSS2_CTL_247_DATA + DDRSS2_CTL_248_DATA + DDRSS2_CTL_249_DATA + DDRSS2_CTL_250_DATA + DDRSS2_CTL_251_DATA + DDRSS2_CTL_252_DATA + DDRSS2_CTL_253_DATA + DDRSS2_CTL_254_DATA + DDRSS2_CTL_255_DATA + DDRSS2_CTL_256_DATA + DDRSS2_CTL_257_DATA + DDRSS2_CTL_258_DATA + DDRSS2_CTL_259_DATA + DDRSS2_CTL_260_DATA + DDRSS2_CTL_261_DATA + DDRSS2_CTL_262_DATA + DDRSS2_CTL_263_DATA + DDRSS2_CTL_264_DATA + DDRSS2_CTL_265_DATA + DDRSS2_CTL_266_DATA + DDRSS2_CTL_267_DATA + DDRSS2_CTL_268_DATA + DDRSS2_CTL_269_DATA + DDRSS2_CTL_270_DATA + DDRSS2_CTL_271_DATA + DDRSS2_CTL_272_DATA + DDRSS2_CTL_273_DATA + DDRSS2_CTL_274_DATA + DDRSS2_CTL_275_DATA + DDRSS2_CTL_276_DATA + DDRSS2_CTL_277_DATA + DDRSS2_CTL_278_DATA + DDRSS2_CTL_279_DATA + DDRSS2_CTL_280_DATA + DDRSS2_CTL_281_DATA + DDRSS2_CTL_282_DATA + DDRSS2_CTL_283_DATA + DDRSS2_CTL_284_DATA + DDRSS2_CTL_285_DATA + DDRSS2_CTL_286_DATA + DDRSS2_CTL_287_DATA + DDRSS2_CTL_288_DATA + DDRSS2_CTL_289_DATA + DDRSS2_CTL_290_DATA + DDRSS2_CTL_291_DATA + DDRSS2_CTL_292_DATA + DDRSS2_CTL_293_DATA + DDRSS2_CTL_294_DATA + DDRSS2_CTL_295_DATA + DDRSS2_CTL_296_DATA + DDRSS2_CTL_297_DATA + DDRSS2_CTL_298_DATA + DDRSS2_CTL_299_DATA + DDRSS2_CTL_300_DATA + DDRSS2_CTL_301_DATA + DDRSS2_CTL_302_DATA + DDRSS2_CTL_303_DATA + DDRSS2_CTL_304_DATA + DDRSS2_CTL_305_DATA + DDRSS2_CTL_306_DATA + DDRSS2_CTL_307_DATA + DDRSS2_CTL_308_DATA + DDRSS2_CTL_309_DATA + DDRSS2_CTL_310_DATA + DDRSS2_CTL_311_DATA + DDRSS2_CTL_312_DATA + DDRSS2_CTL_313_DATA + DDRSS2_CTL_314_DATA + DDRSS2_CTL_315_DATA + DDRSS2_CTL_316_DATA + DDRSS2_CTL_317_DATA + DDRSS2_CTL_318_DATA + DDRSS2_CTL_319_DATA + DDRSS2_CTL_320_DATA + DDRSS2_CTL_321_DATA + DDRSS2_CTL_322_DATA + DDRSS2_CTL_323_DATA + DDRSS2_CTL_324_DATA + DDRSS2_CTL_325_DATA + DDRSS2_CTL_326_DATA + DDRSS2_CTL_327_DATA + DDRSS2_CTL_328_DATA + DDRSS2_CTL_329_DATA + DDRSS2_CTL_330_DATA + DDRSS2_CTL_331_DATA + DDRSS2_CTL_332_DATA + DDRSS2_CTL_333_DATA + DDRSS2_CTL_334_DATA + DDRSS2_CTL_335_DATA + DDRSS2_CTL_336_DATA + DDRSS2_CTL_337_DATA + DDRSS2_CTL_338_DATA + DDRSS2_CTL_339_DATA + DDRSS2_CTL_340_DATA + DDRSS2_CTL_341_DATA + DDRSS2_CTL_342_DATA + DDRSS2_CTL_343_DATA + DDRSS2_CTL_344_DATA + DDRSS2_CTL_345_DATA + DDRSS2_CTL_346_DATA + DDRSS2_CTL_347_DATA + DDRSS2_CTL_348_DATA + DDRSS2_CTL_349_DATA + DDRSS2_CTL_350_DATA + DDRSS2_CTL_351_DATA + DDRSS2_CTL_352_DATA + DDRSS2_CTL_353_DATA + DDRSS2_CTL_354_DATA + DDRSS2_CTL_355_DATA + DDRSS2_CTL_356_DATA + DDRSS2_CTL_357_DATA + DDRSS2_CTL_358_DATA + DDRSS2_CTL_359_DATA + DDRSS2_CTL_360_DATA + DDRSS2_CTL_361_DATA + DDRSS2_CTL_362_DATA + DDRSS2_CTL_363_DATA + DDRSS2_CTL_364_DATA + DDRSS2_CTL_365_DATA + DDRSS2_CTL_366_DATA + DDRSS2_CTL_367_DATA + DDRSS2_CTL_368_DATA + DDRSS2_CTL_369_DATA + DDRSS2_CTL_370_DATA + DDRSS2_CTL_371_DATA + DDRSS2_CTL_372_DATA + DDRSS2_CTL_373_DATA + DDRSS2_CTL_374_DATA + DDRSS2_CTL_375_DATA + DDRSS2_CTL_376_DATA + DDRSS2_CTL_377_DATA + DDRSS2_CTL_378_DATA + DDRSS2_CTL_379_DATA + DDRSS2_CTL_380_DATA + DDRSS2_CTL_381_DATA + DDRSS2_CTL_382_DATA + DDRSS2_CTL_383_DATA + DDRSS2_CTL_384_DATA + DDRSS2_CTL_385_DATA + DDRSS2_CTL_386_DATA + DDRSS2_CTL_387_DATA + DDRSS2_CTL_388_DATA + DDRSS2_CTL_389_DATA + DDRSS2_CTL_390_DATA + DDRSS2_CTL_391_DATA + DDRSS2_CTL_392_DATA + DDRSS2_CTL_393_DATA + DDRSS2_CTL_394_DATA + DDRSS2_CTL_395_DATA + DDRSS2_CTL_396_DATA + DDRSS2_CTL_397_DATA + DDRSS2_CTL_398_DATA + DDRSS2_CTL_399_DATA + DDRSS2_CTL_400_DATA + DDRSS2_CTL_401_DATA + DDRSS2_CTL_402_DATA + DDRSS2_CTL_403_DATA + DDRSS2_CTL_404_DATA + DDRSS2_CTL_405_DATA + DDRSS2_CTL_406_DATA + DDRSS2_CTL_407_DATA + DDRSS2_CTL_408_DATA + DDRSS2_CTL_409_DATA + DDRSS2_CTL_410_DATA + DDRSS2_CTL_411_DATA + DDRSS2_CTL_412_DATA + DDRSS2_CTL_413_DATA + DDRSS2_CTL_414_DATA + DDRSS2_CTL_415_DATA + DDRSS2_CTL_416_DATA + DDRSS2_CTL_417_DATA + DDRSS2_CTL_418_DATA + DDRSS2_CTL_419_DATA + DDRSS2_CTL_420_DATA + DDRSS2_CTL_421_DATA + DDRSS2_CTL_422_DATA + DDRSS2_CTL_423_DATA + DDRSS2_CTL_424_DATA + DDRSS2_CTL_425_DATA + DDRSS2_CTL_426_DATA + DDRSS2_CTL_427_DATA + DDRSS2_CTL_428_DATA + DDRSS2_CTL_429_DATA + DDRSS2_CTL_430_DATA + DDRSS2_CTL_431_DATA + DDRSS2_CTL_432_DATA + DDRSS2_CTL_433_DATA + DDRSS2_CTL_434_DATA + DDRSS2_CTL_435_DATA + DDRSS2_CTL_436_DATA + DDRSS2_CTL_437_DATA + DDRSS2_CTL_438_DATA + DDRSS2_CTL_439_DATA + DDRSS2_CTL_440_DATA + DDRSS2_CTL_441_DATA + DDRSS2_CTL_442_DATA + DDRSS2_CTL_443_DATA + DDRSS2_CTL_444_DATA + DDRSS2_CTL_445_DATA + DDRSS2_CTL_446_DATA + DDRSS2_CTL_447_DATA + DDRSS2_CTL_448_DATA + DDRSS2_CTL_449_DATA + DDRSS2_CTL_450_DATA + DDRSS2_CTL_451_DATA + DDRSS2_CTL_452_DATA + DDRSS2_CTL_453_DATA + DDRSS2_CTL_454_DATA + DDRSS2_CTL_455_DATA + DDRSS2_CTL_456_DATA + DDRSS2_CTL_457_DATA + DDRSS2_CTL_458_DATA + >; + + ti,pi-data = < + DDRSS2_PI_00_DATA + DDRSS2_PI_01_DATA + DDRSS2_PI_02_DATA + DDRSS2_PI_03_DATA + DDRSS2_PI_04_DATA + DDRSS2_PI_05_DATA + DDRSS2_PI_06_DATA + DDRSS2_PI_07_DATA + DDRSS2_PI_08_DATA + DDRSS2_PI_09_DATA + DDRSS2_PI_10_DATA + DDRSS2_PI_11_DATA + DDRSS2_PI_12_DATA + DDRSS2_PI_13_DATA + DDRSS2_PI_14_DATA + DDRSS2_PI_15_DATA + DDRSS2_PI_16_DATA + DDRSS2_PI_17_DATA + DDRSS2_PI_18_DATA + DDRSS2_PI_19_DATA + DDRSS2_PI_20_DATA + DDRSS2_PI_21_DATA + DDRSS2_PI_22_DATA + DDRSS2_PI_23_DATA + DDRSS2_PI_24_DATA + DDRSS2_PI_25_DATA + DDRSS2_PI_26_DATA + DDRSS2_PI_27_DATA + DDRSS2_PI_28_DATA + DDRSS2_PI_29_DATA + DDRSS2_PI_30_DATA + DDRSS2_PI_31_DATA + DDRSS2_PI_32_DATA + DDRSS2_PI_33_DATA + DDRSS2_PI_34_DATA + DDRSS2_PI_35_DATA + DDRSS2_PI_36_DATA + DDRSS2_PI_37_DATA + DDRSS2_PI_38_DATA + DDRSS2_PI_39_DATA + DDRSS2_PI_40_DATA + DDRSS2_PI_41_DATA + DDRSS2_PI_42_DATA + DDRSS2_PI_43_DATA + DDRSS2_PI_44_DATA + DDRSS2_PI_45_DATA + DDRSS2_PI_46_DATA + DDRSS2_PI_47_DATA + DDRSS2_PI_48_DATA + DDRSS2_PI_49_DATA + DDRSS2_PI_50_DATA + DDRSS2_PI_51_DATA + DDRSS2_PI_52_DATA + DDRSS2_PI_53_DATA + DDRSS2_PI_54_DATA + DDRSS2_PI_55_DATA + DDRSS2_PI_56_DATA + DDRSS2_PI_57_DATA + DDRSS2_PI_58_DATA + DDRSS2_PI_59_DATA + DDRSS2_PI_60_DATA + DDRSS2_PI_61_DATA + DDRSS2_PI_62_DATA + DDRSS2_PI_63_DATA + DDRSS2_PI_64_DATA + DDRSS2_PI_65_DATA + DDRSS2_PI_66_DATA + DDRSS2_PI_67_DATA + DDRSS2_PI_68_DATA + DDRSS2_PI_69_DATA + DDRSS2_PI_70_DATA + DDRSS2_PI_71_DATA + DDRSS2_PI_72_DATA + DDRSS2_PI_73_DATA + DDRSS2_PI_74_DATA + DDRSS2_PI_75_DATA + DDRSS2_PI_76_DATA + DDRSS2_PI_77_DATA + DDRSS2_PI_78_DATA + DDRSS2_PI_79_DATA + DDRSS2_PI_80_DATA + DDRSS2_PI_81_DATA + DDRSS2_PI_82_DATA + DDRSS2_PI_83_DATA + DDRSS2_PI_84_DATA + DDRSS2_PI_85_DATA + DDRSS2_PI_86_DATA + DDRSS2_PI_87_DATA + DDRSS2_PI_88_DATA + DDRSS2_PI_89_DATA + DDRSS2_PI_90_DATA + DDRSS2_PI_91_DATA + DDRSS2_PI_92_DATA + DDRSS2_PI_93_DATA + DDRSS2_PI_94_DATA + DDRSS2_PI_95_DATA + DDRSS2_PI_96_DATA + DDRSS2_PI_97_DATA + DDRSS2_PI_98_DATA + DDRSS2_PI_99_DATA + DDRSS2_PI_100_DATA + DDRSS2_PI_101_DATA + DDRSS2_PI_102_DATA + DDRSS2_PI_103_DATA + DDRSS2_PI_104_DATA + DDRSS2_PI_105_DATA + DDRSS2_PI_106_DATA + DDRSS2_PI_107_DATA + DDRSS2_PI_108_DATA + DDRSS2_PI_109_DATA + DDRSS2_PI_110_DATA + DDRSS2_PI_111_DATA + DDRSS2_PI_112_DATA + DDRSS2_PI_113_DATA + DDRSS2_PI_114_DATA + DDRSS2_PI_115_DATA + DDRSS2_PI_116_DATA + DDRSS2_PI_117_DATA + DDRSS2_PI_118_DATA + DDRSS2_PI_119_DATA + DDRSS2_PI_120_DATA + DDRSS2_PI_121_DATA + DDRSS2_PI_122_DATA + DDRSS2_PI_123_DATA + DDRSS2_PI_124_DATA + DDRSS2_PI_125_DATA + DDRSS2_PI_126_DATA + DDRSS2_PI_127_DATA + DDRSS2_PI_128_DATA + DDRSS2_PI_129_DATA + DDRSS2_PI_130_DATA + DDRSS2_PI_131_DATA + DDRSS2_PI_132_DATA + DDRSS2_PI_133_DATA + DDRSS2_PI_134_DATA + DDRSS2_PI_135_DATA + DDRSS2_PI_136_DATA + DDRSS2_PI_137_DATA + DDRSS2_PI_138_DATA + DDRSS2_PI_139_DATA + DDRSS2_PI_140_DATA + DDRSS2_PI_141_DATA + DDRSS2_PI_142_DATA + DDRSS2_PI_143_DATA + DDRSS2_PI_144_DATA + DDRSS2_PI_145_DATA + DDRSS2_PI_146_DATA + DDRSS2_PI_147_DATA + DDRSS2_PI_148_DATA + DDRSS2_PI_149_DATA + DDRSS2_PI_150_DATA + DDRSS2_PI_151_DATA + DDRSS2_PI_152_DATA + DDRSS2_PI_153_DATA + DDRSS2_PI_154_DATA + DDRSS2_PI_155_DATA + DDRSS2_PI_156_DATA + DDRSS2_PI_157_DATA + DDRSS2_PI_158_DATA + DDRSS2_PI_159_DATA + DDRSS2_PI_160_DATA + DDRSS2_PI_161_DATA + DDRSS2_PI_162_DATA + DDRSS2_PI_163_DATA + DDRSS2_PI_164_DATA + DDRSS2_PI_165_DATA + DDRSS2_PI_166_DATA + DDRSS2_PI_167_DATA + DDRSS2_PI_168_DATA + DDRSS2_PI_169_DATA + DDRSS2_PI_170_DATA + DDRSS2_PI_171_DATA + DDRSS2_PI_172_DATA + DDRSS2_PI_173_DATA + DDRSS2_PI_174_DATA + DDRSS2_PI_175_DATA + DDRSS2_PI_176_DATA + DDRSS2_PI_177_DATA + DDRSS2_PI_178_DATA + DDRSS2_PI_179_DATA + DDRSS2_PI_180_DATA + DDRSS2_PI_181_DATA + DDRSS2_PI_182_DATA + DDRSS2_PI_183_DATA + DDRSS2_PI_184_DATA + DDRSS2_PI_185_DATA + DDRSS2_PI_186_DATA + DDRSS2_PI_187_DATA + DDRSS2_PI_188_DATA + DDRSS2_PI_189_DATA + DDRSS2_PI_190_DATA + DDRSS2_PI_191_DATA + DDRSS2_PI_192_DATA + DDRSS2_PI_193_DATA + DDRSS2_PI_194_DATA + DDRSS2_PI_195_DATA + DDRSS2_PI_196_DATA + DDRSS2_PI_197_DATA + DDRSS2_PI_198_DATA + DDRSS2_PI_199_DATA + DDRSS2_PI_200_DATA + DDRSS2_PI_201_DATA + DDRSS2_PI_202_DATA + DDRSS2_PI_203_DATA + DDRSS2_PI_204_DATA + DDRSS2_PI_205_DATA + DDRSS2_PI_206_DATA + DDRSS2_PI_207_DATA + DDRSS2_PI_208_DATA + DDRSS2_PI_209_DATA + DDRSS2_PI_210_DATA + DDRSS2_PI_211_DATA + DDRSS2_PI_212_DATA + DDRSS2_PI_213_DATA + DDRSS2_PI_214_DATA + DDRSS2_PI_215_DATA + DDRSS2_PI_216_DATA + DDRSS2_PI_217_DATA + DDRSS2_PI_218_DATA + DDRSS2_PI_219_DATA + DDRSS2_PI_220_DATA + DDRSS2_PI_221_DATA + DDRSS2_PI_222_DATA + DDRSS2_PI_223_DATA + DDRSS2_PI_224_DATA + DDRSS2_PI_225_DATA + DDRSS2_PI_226_DATA + DDRSS2_PI_227_DATA + DDRSS2_PI_228_DATA + DDRSS2_PI_229_DATA + DDRSS2_PI_230_DATA + DDRSS2_PI_231_DATA + DDRSS2_PI_232_DATA + DDRSS2_PI_233_DATA + DDRSS2_PI_234_DATA + DDRSS2_PI_235_DATA + DDRSS2_PI_236_DATA + DDRSS2_PI_237_DATA + DDRSS2_PI_238_DATA + DDRSS2_PI_239_DATA + DDRSS2_PI_240_DATA + DDRSS2_PI_241_DATA + DDRSS2_PI_242_DATA + DDRSS2_PI_243_DATA + DDRSS2_PI_244_DATA + DDRSS2_PI_245_DATA + DDRSS2_PI_246_DATA + DDRSS2_PI_247_DATA + DDRSS2_PI_248_DATA + DDRSS2_PI_249_DATA + DDRSS2_PI_250_DATA + DDRSS2_PI_251_DATA + DDRSS2_PI_252_DATA + DDRSS2_PI_253_DATA + DDRSS2_PI_254_DATA + DDRSS2_PI_255_DATA + DDRSS2_PI_256_DATA + DDRSS2_PI_257_DATA + DDRSS2_PI_258_DATA + DDRSS2_PI_259_DATA + DDRSS2_PI_260_DATA + DDRSS2_PI_261_DATA + DDRSS2_PI_262_DATA + DDRSS2_PI_263_DATA + DDRSS2_PI_264_DATA + DDRSS2_PI_265_DATA + DDRSS2_PI_266_DATA + DDRSS2_PI_267_DATA + DDRSS2_PI_268_DATA + DDRSS2_PI_269_DATA + DDRSS2_PI_270_DATA + DDRSS2_PI_271_DATA + DDRSS2_PI_272_DATA + DDRSS2_PI_273_DATA + DDRSS2_PI_274_DATA + DDRSS2_PI_275_DATA + DDRSS2_PI_276_DATA + DDRSS2_PI_277_DATA + DDRSS2_PI_278_DATA + DDRSS2_PI_279_DATA + DDRSS2_PI_280_DATA + DDRSS2_PI_281_DATA + DDRSS2_PI_282_DATA + DDRSS2_PI_283_DATA + DDRSS2_PI_284_DATA + DDRSS2_PI_285_DATA + DDRSS2_PI_286_DATA + DDRSS2_PI_287_DATA + DDRSS2_PI_288_DATA + DDRSS2_PI_289_DATA + DDRSS2_PI_290_DATA + DDRSS2_PI_291_DATA + DDRSS2_PI_292_DATA + DDRSS2_PI_293_DATA + DDRSS2_PI_294_DATA + DDRSS2_PI_295_DATA + DDRSS2_PI_296_DATA + DDRSS2_PI_297_DATA + DDRSS2_PI_298_DATA + DDRSS2_PI_299_DATA + >; + + ti,phy-data = < + DDRSS2_PHY_00_DATA + DDRSS2_PHY_01_DATA + DDRSS2_PHY_02_DATA + DDRSS2_PHY_03_DATA + DDRSS2_PHY_04_DATA + DDRSS2_PHY_05_DATA + DDRSS2_PHY_06_DATA + DDRSS2_PHY_07_DATA + DDRSS2_PHY_08_DATA + DDRSS2_PHY_09_DATA + DDRSS2_PHY_10_DATA + DDRSS2_PHY_11_DATA + DDRSS2_PHY_12_DATA + DDRSS2_PHY_13_DATA + DDRSS2_PHY_14_DATA + DDRSS2_PHY_15_DATA + DDRSS2_PHY_16_DATA + DDRSS2_PHY_17_DATA + DDRSS2_PHY_18_DATA + DDRSS2_PHY_19_DATA + DDRSS2_PHY_20_DATA + DDRSS2_PHY_21_DATA + DDRSS2_PHY_22_DATA + DDRSS2_PHY_23_DATA + DDRSS2_PHY_24_DATA + DDRSS2_PHY_25_DATA + DDRSS2_PHY_26_DATA + DDRSS2_PHY_27_DATA + DDRSS2_PHY_28_DATA + DDRSS2_PHY_29_DATA + DDRSS2_PHY_30_DATA + DDRSS2_PHY_31_DATA + DDRSS2_PHY_32_DATA + DDRSS2_PHY_33_DATA + DDRSS2_PHY_34_DATA + DDRSS2_PHY_35_DATA + DDRSS2_PHY_36_DATA + DDRSS2_PHY_37_DATA + DDRSS2_PHY_38_DATA + DDRSS2_PHY_39_DATA + DDRSS2_PHY_40_DATA + DDRSS2_PHY_41_DATA + DDRSS2_PHY_42_DATA + DDRSS2_PHY_43_DATA + DDRSS2_PHY_44_DATA + DDRSS2_PHY_45_DATA + DDRSS2_PHY_46_DATA + DDRSS2_PHY_47_DATA + DDRSS2_PHY_48_DATA + DDRSS2_PHY_49_DATA + DDRSS2_PHY_50_DATA + DDRSS2_PHY_51_DATA + DDRSS2_PHY_52_DATA + DDRSS2_PHY_53_DATA + DDRSS2_PHY_54_DATA + DDRSS2_PHY_55_DATA + DDRSS2_PHY_56_DATA + DDRSS2_PHY_57_DATA + DDRSS2_PHY_58_DATA + DDRSS2_PHY_59_DATA + DDRSS2_PHY_60_DATA + DDRSS2_PHY_61_DATA + DDRSS2_PHY_62_DATA + DDRSS2_PHY_63_DATA + DDRSS2_PHY_64_DATA + DDRSS2_PHY_65_DATA + DDRSS2_PHY_66_DATA + DDRSS2_PHY_67_DATA + DDRSS2_PHY_68_DATA + DDRSS2_PHY_69_DATA + DDRSS2_PHY_70_DATA + DDRSS2_PHY_71_DATA + DDRSS2_PHY_72_DATA + DDRSS2_PHY_73_DATA + DDRSS2_PHY_74_DATA + DDRSS2_PHY_75_DATA + DDRSS2_PHY_76_DATA + DDRSS2_PHY_77_DATA + DDRSS2_PHY_78_DATA + DDRSS2_PHY_79_DATA + DDRSS2_PHY_80_DATA + DDRSS2_PHY_81_DATA + DDRSS2_PHY_82_DATA + DDRSS2_PHY_83_DATA + DDRSS2_PHY_84_DATA + DDRSS2_PHY_85_DATA + DDRSS2_PHY_86_DATA + DDRSS2_PHY_87_DATA + DDRSS2_PHY_88_DATA + DDRSS2_PHY_89_DATA + DDRSS2_PHY_90_DATA + DDRSS2_PHY_91_DATA + DDRSS2_PHY_92_DATA + DDRSS2_PHY_93_DATA + DDRSS2_PHY_94_DATA + DDRSS2_PHY_95_DATA + DDRSS2_PHY_96_DATA + DDRSS2_PHY_97_DATA + DDRSS2_PHY_98_DATA + DDRSS2_PHY_99_DATA + DDRSS2_PHY_100_DATA + DDRSS2_PHY_101_DATA + DDRSS2_PHY_102_DATA + DDRSS2_PHY_103_DATA + DDRSS2_PHY_104_DATA + DDRSS2_PHY_105_DATA + DDRSS2_PHY_106_DATA + DDRSS2_PHY_107_DATA + DDRSS2_PHY_108_DATA + DDRSS2_PHY_109_DATA + DDRSS2_PHY_110_DATA + DDRSS2_PHY_111_DATA + DDRSS2_PHY_112_DATA + DDRSS2_PHY_113_DATA + DDRSS2_PHY_114_DATA + DDRSS2_PHY_115_DATA + DDRSS2_PHY_116_DATA + DDRSS2_PHY_117_DATA + DDRSS2_PHY_118_DATA + DDRSS2_PHY_119_DATA + DDRSS2_PHY_120_DATA + DDRSS2_PHY_121_DATA + DDRSS2_PHY_122_DATA + DDRSS2_PHY_123_DATA + DDRSS2_PHY_124_DATA + DDRSS2_PHY_125_DATA + DDRSS2_PHY_126_DATA + DDRSS2_PHY_127_DATA + DDRSS2_PHY_128_DATA + DDRSS2_PHY_129_DATA + DDRSS2_PHY_130_DATA + DDRSS2_PHY_131_DATA + DDRSS2_PHY_132_DATA + DDRSS2_PHY_133_DATA + DDRSS2_PHY_134_DATA + DDRSS2_PHY_135_DATA + DDRSS2_PHY_136_DATA + DDRSS2_PHY_137_DATA + DDRSS2_PHY_138_DATA + DDRSS2_PHY_139_DATA + DDRSS2_PHY_140_DATA + DDRSS2_PHY_141_DATA + DDRSS2_PHY_142_DATA + DDRSS2_PHY_143_DATA + DDRSS2_PHY_144_DATA + DDRSS2_PHY_145_DATA + DDRSS2_PHY_146_DATA + DDRSS2_PHY_147_DATA + DDRSS2_PHY_148_DATA + DDRSS2_PHY_149_DATA + DDRSS2_PHY_150_DATA + DDRSS2_PHY_151_DATA + DDRSS2_PHY_152_DATA + DDRSS2_PHY_153_DATA + DDRSS2_PHY_154_DATA + DDRSS2_PHY_155_DATA + DDRSS2_PHY_156_DATA + DDRSS2_PHY_157_DATA + DDRSS2_PHY_158_DATA + DDRSS2_PHY_159_DATA + DDRSS2_PHY_160_DATA + DDRSS2_PHY_161_DATA + DDRSS2_PHY_162_DATA + DDRSS2_PHY_163_DATA + DDRSS2_PHY_164_DATA + DDRSS2_PHY_165_DATA + DDRSS2_PHY_166_DATA + DDRSS2_PHY_167_DATA + DDRSS2_PHY_168_DATA + DDRSS2_PHY_169_DATA + DDRSS2_PHY_170_DATA + DDRSS2_PHY_171_DATA + DDRSS2_PHY_172_DATA + DDRSS2_PHY_173_DATA + DDRSS2_PHY_174_DATA + DDRSS2_PHY_175_DATA + DDRSS2_PHY_176_DATA + DDRSS2_PHY_177_DATA + DDRSS2_PHY_178_DATA + DDRSS2_PHY_179_DATA + DDRSS2_PHY_180_DATA + DDRSS2_PHY_181_DATA + DDRSS2_PHY_182_DATA + DDRSS2_PHY_183_DATA + DDRSS2_PHY_184_DATA + DDRSS2_PHY_185_DATA + DDRSS2_PHY_186_DATA + DDRSS2_PHY_187_DATA + DDRSS2_PHY_188_DATA + DDRSS2_PHY_189_DATA + DDRSS2_PHY_190_DATA + DDRSS2_PHY_191_DATA + DDRSS2_PHY_192_DATA + DDRSS2_PHY_193_DATA + DDRSS2_PHY_194_DATA + DDRSS2_PHY_195_DATA + DDRSS2_PHY_196_DATA + DDRSS2_PHY_197_DATA + DDRSS2_PHY_198_DATA + DDRSS2_PHY_199_DATA + DDRSS2_PHY_200_DATA + DDRSS2_PHY_201_DATA + DDRSS2_PHY_202_DATA + DDRSS2_PHY_203_DATA + DDRSS2_PHY_204_DATA + DDRSS2_PHY_205_DATA + DDRSS2_PHY_206_DATA + DDRSS2_PHY_207_DATA + DDRSS2_PHY_208_DATA + DDRSS2_PHY_209_DATA + DDRSS2_PHY_210_DATA + DDRSS2_PHY_211_DATA + DDRSS2_PHY_212_DATA + DDRSS2_PHY_213_DATA + DDRSS2_PHY_214_DATA + DDRSS2_PHY_215_DATA + DDRSS2_PHY_216_DATA + DDRSS2_PHY_217_DATA + DDRSS2_PHY_218_DATA + DDRSS2_PHY_219_DATA + DDRSS2_PHY_220_DATA + DDRSS2_PHY_221_DATA + DDRSS2_PHY_222_DATA + DDRSS2_PHY_223_DATA + DDRSS2_PHY_224_DATA + DDRSS2_PHY_225_DATA + DDRSS2_PHY_226_DATA + DDRSS2_PHY_227_DATA + DDRSS2_PHY_228_DATA + DDRSS2_PHY_229_DATA + DDRSS2_PHY_230_DATA + DDRSS2_PHY_231_DATA + DDRSS2_PHY_232_DATA + DDRSS2_PHY_233_DATA + DDRSS2_PHY_234_DATA + DDRSS2_PHY_235_DATA + DDRSS2_PHY_236_DATA + DDRSS2_PHY_237_DATA + DDRSS2_PHY_238_DATA + DDRSS2_PHY_239_DATA + DDRSS2_PHY_240_DATA + DDRSS2_PHY_241_DATA + DDRSS2_PHY_242_DATA + DDRSS2_PHY_243_DATA + DDRSS2_PHY_244_DATA + DDRSS2_PHY_245_DATA + DDRSS2_PHY_246_DATA + DDRSS2_PHY_247_DATA + DDRSS2_PHY_248_DATA + DDRSS2_PHY_249_DATA + DDRSS2_PHY_250_DATA + DDRSS2_PHY_251_DATA + DDRSS2_PHY_252_DATA + DDRSS2_PHY_253_DATA + DDRSS2_PHY_254_DATA + DDRSS2_PHY_255_DATA + DDRSS2_PHY_256_DATA + DDRSS2_PHY_257_DATA + DDRSS2_PHY_258_DATA + DDRSS2_PHY_259_DATA + DDRSS2_PHY_260_DATA + DDRSS2_PHY_261_DATA + DDRSS2_PHY_262_DATA + DDRSS2_PHY_263_DATA + DDRSS2_PHY_264_DATA + DDRSS2_PHY_265_DATA + DDRSS2_PHY_266_DATA + DDRSS2_PHY_267_DATA + DDRSS2_PHY_268_DATA + DDRSS2_PHY_269_DATA + DDRSS2_PHY_270_DATA + DDRSS2_PHY_271_DATA + DDRSS2_PHY_272_DATA + DDRSS2_PHY_273_DATA + DDRSS2_PHY_274_DATA + DDRSS2_PHY_275_DATA + DDRSS2_PHY_276_DATA + DDRSS2_PHY_277_DATA + DDRSS2_PHY_278_DATA + DDRSS2_PHY_279_DATA + DDRSS2_PHY_280_DATA + DDRSS2_PHY_281_DATA + DDRSS2_PHY_282_DATA + DDRSS2_PHY_283_DATA + DDRSS2_PHY_284_DATA + DDRSS2_PHY_285_DATA + DDRSS2_PHY_286_DATA + DDRSS2_PHY_287_DATA + DDRSS2_PHY_288_DATA + DDRSS2_PHY_289_DATA + DDRSS2_PHY_290_DATA + DDRSS2_PHY_291_DATA + DDRSS2_PHY_292_DATA + DDRSS2_PHY_293_DATA + DDRSS2_PHY_294_DATA + DDRSS2_PHY_295_DATA + DDRSS2_PHY_296_DATA + DDRSS2_PHY_297_DATA + DDRSS2_PHY_298_DATA + DDRSS2_PHY_299_DATA + DDRSS2_PHY_300_DATA + DDRSS2_PHY_301_DATA + DDRSS2_PHY_302_DATA + DDRSS2_PHY_303_DATA + DDRSS2_PHY_304_DATA + DDRSS2_PHY_305_DATA + DDRSS2_PHY_306_DATA + DDRSS2_PHY_307_DATA + DDRSS2_PHY_308_DATA + DDRSS2_PHY_309_DATA + DDRSS2_PHY_310_DATA + DDRSS2_PHY_311_DATA + DDRSS2_PHY_312_DATA + DDRSS2_PHY_313_DATA + DDRSS2_PHY_314_DATA + DDRSS2_PHY_315_DATA + DDRSS2_PHY_316_DATA + DDRSS2_PHY_317_DATA + DDRSS2_PHY_318_DATA + DDRSS2_PHY_319_DATA + DDRSS2_PHY_320_DATA + DDRSS2_PHY_321_DATA + DDRSS2_PHY_322_DATA + DDRSS2_PHY_323_DATA + DDRSS2_PHY_324_DATA + DDRSS2_PHY_325_DATA + DDRSS2_PHY_326_DATA + DDRSS2_PHY_327_DATA + DDRSS2_PHY_328_DATA + DDRSS2_PHY_329_DATA + DDRSS2_PHY_330_DATA + DDRSS2_PHY_331_DATA + DDRSS2_PHY_332_DATA + DDRSS2_PHY_333_DATA + DDRSS2_PHY_334_DATA + DDRSS2_PHY_335_DATA + DDRSS2_PHY_336_DATA + DDRSS2_PHY_337_DATA + DDRSS2_PHY_338_DATA + DDRSS2_PHY_339_DATA + DDRSS2_PHY_340_DATA + DDRSS2_PHY_341_DATA + DDRSS2_PHY_342_DATA + DDRSS2_PHY_343_DATA + DDRSS2_PHY_344_DATA + DDRSS2_PHY_345_DATA + DDRSS2_PHY_346_DATA + DDRSS2_PHY_347_DATA + DDRSS2_PHY_348_DATA + DDRSS2_PHY_349_DATA + DDRSS2_PHY_350_DATA + DDRSS2_PHY_351_DATA + DDRSS2_PHY_352_DATA + DDRSS2_PHY_353_DATA + DDRSS2_PHY_354_DATA + DDRSS2_PHY_355_DATA + DDRSS2_PHY_356_DATA + DDRSS2_PHY_357_DATA + DDRSS2_PHY_358_DATA + DDRSS2_PHY_359_DATA + DDRSS2_PHY_360_DATA + DDRSS2_PHY_361_DATA + DDRSS2_PHY_362_DATA + DDRSS2_PHY_363_DATA + DDRSS2_PHY_364_DATA + DDRSS2_PHY_365_DATA + DDRSS2_PHY_366_DATA + DDRSS2_PHY_367_DATA + DDRSS2_PHY_368_DATA + DDRSS2_PHY_369_DATA + DDRSS2_PHY_370_DATA + DDRSS2_PHY_371_DATA + DDRSS2_PHY_372_DATA + DDRSS2_PHY_373_DATA + DDRSS2_PHY_374_DATA + DDRSS2_PHY_375_DATA + DDRSS2_PHY_376_DATA + DDRSS2_PHY_377_DATA + DDRSS2_PHY_378_DATA + DDRSS2_PHY_379_DATA + DDRSS2_PHY_380_DATA + DDRSS2_PHY_381_DATA + DDRSS2_PHY_382_DATA + DDRSS2_PHY_383_DATA + DDRSS2_PHY_384_DATA + DDRSS2_PHY_385_DATA + DDRSS2_PHY_386_DATA + DDRSS2_PHY_387_DATA + DDRSS2_PHY_388_DATA + DDRSS2_PHY_389_DATA + DDRSS2_PHY_390_DATA + DDRSS2_PHY_391_DATA + DDRSS2_PHY_392_DATA + DDRSS2_PHY_393_DATA + DDRSS2_PHY_394_DATA + DDRSS2_PHY_395_DATA + DDRSS2_PHY_396_DATA + DDRSS2_PHY_397_DATA + DDRSS2_PHY_398_DATA + DDRSS2_PHY_399_DATA + DDRSS2_PHY_400_DATA + DDRSS2_PHY_401_DATA + DDRSS2_PHY_402_DATA + DDRSS2_PHY_403_DATA + DDRSS2_PHY_404_DATA + DDRSS2_PHY_405_DATA + DDRSS2_PHY_406_DATA + DDRSS2_PHY_407_DATA + DDRSS2_PHY_408_DATA + DDRSS2_PHY_409_DATA + DDRSS2_PHY_410_DATA + DDRSS2_PHY_411_DATA + DDRSS2_PHY_412_DATA + DDRSS2_PHY_413_DATA + DDRSS2_PHY_414_DATA + DDRSS2_PHY_415_DATA + DDRSS2_PHY_416_DATA + DDRSS2_PHY_417_DATA + DDRSS2_PHY_418_DATA + DDRSS2_PHY_419_DATA + DDRSS2_PHY_420_DATA + DDRSS2_PHY_421_DATA + DDRSS2_PHY_422_DATA + DDRSS2_PHY_423_DATA + DDRSS2_PHY_424_DATA + DDRSS2_PHY_425_DATA + DDRSS2_PHY_426_DATA + DDRSS2_PHY_427_DATA + DDRSS2_PHY_428_DATA + DDRSS2_PHY_429_DATA + DDRSS2_PHY_430_DATA + DDRSS2_PHY_431_DATA + DDRSS2_PHY_432_DATA + DDRSS2_PHY_433_DATA + DDRSS2_PHY_434_DATA + DDRSS2_PHY_435_DATA + DDRSS2_PHY_436_DATA + DDRSS2_PHY_437_DATA + DDRSS2_PHY_438_DATA + DDRSS2_PHY_439_DATA + DDRSS2_PHY_440_DATA + DDRSS2_PHY_441_DATA + DDRSS2_PHY_442_DATA + DDRSS2_PHY_443_DATA + DDRSS2_PHY_444_DATA + DDRSS2_PHY_445_DATA + DDRSS2_PHY_446_DATA + DDRSS2_PHY_447_DATA + DDRSS2_PHY_448_DATA + DDRSS2_PHY_449_DATA + DDRSS2_PHY_450_DATA + DDRSS2_PHY_451_DATA + DDRSS2_PHY_452_DATA + DDRSS2_PHY_453_DATA + DDRSS2_PHY_454_DATA + DDRSS2_PHY_455_DATA + DDRSS2_PHY_456_DATA + DDRSS2_PHY_457_DATA + DDRSS2_PHY_458_DATA + DDRSS2_PHY_459_DATA + DDRSS2_PHY_460_DATA + DDRSS2_PHY_461_DATA + DDRSS2_PHY_462_DATA + DDRSS2_PHY_463_DATA + DDRSS2_PHY_464_DATA + DDRSS2_PHY_465_DATA + DDRSS2_PHY_466_DATA + DDRSS2_PHY_467_DATA + DDRSS2_PHY_468_DATA + DDRSS2_PHY_469_DATA + DDRSS2_PHY_470_DATA + DDRSS2_PHY_471_DATA + DDRSS2_PHY_472_DATA + DDRSS2_PHY_473_DATA + DDRSS2_PHY_474_DATA + DDRSS2_PHY_475_DATA + DDRSS2_PHY_476_DATA + DDRSS2_PHY_477_DATA + DDRSS2_PHY_478_DATA + DDRSS2_PHY_479_DATA + DDRSS2_PHY_480_DATA + DDRSS2_PHY_481_DATA + DDRSS2_PHY_482_DATA + DDRSS2_PHY_483_DATA + DDRSS2_PHY_484_DATA + DDRSS2_PHY_485_DATA + DDRSS2_PHY_486_DATA + DDRSS2_PHY_487_DATA + DDRSS2_PHY_488_DATA + DDRSS2_PHY_489_DATA + DDRSS2_PHY_490_DATA + DDRSS2_PHY_491_DATA + DDRSS2_PHY_492_DATA + DDRSS2_PHY_493_DATA + DDRSS2_PHY_494_DATA + DDRSS2_PHY_495_DATA + DDRSS2_PHY_496_DATA + DDRSS2_PHY_497_DATA + DDRSS2_PHY_498_DATA + DDRSS2_PHY_499_DATA + DDRSS2_PHY_500_DATA + DDRSS2_PHY_501_DATA + DDRSS2_PHY_502_DATA + DDRSS2_PHY_503_DATA + DDRSS2_PHY_504_DATA + DDRSS2_PHY_505_DATA + DDRSS2_PHY_506_DATA + DDRSS2_PHY_507_DATA + DDRSS2_PHY_508_DATA + DDRSS2_PHY_509_DATA + DDRSS2_PHY_510_DATA + DDRSS2_PHY_511_DATA + DDRSS2_PHY_512_DATA + DDRSS2_PHY_513_DATA + DDRSS2_PHY_514_DATA + DDRSS2_PHY_515_DATA + DDRSS2_PHY_516_DATA + DDRSS2_PHY_517_DATA + DDRSS2_PHY_518_DATA + DDRSS2_PHY_519_DATA + DDRSS2_PHY_520_DATA + DDRSS2_PHY_521_DATA + DDRSS2_PHY_522_DATA + DDRSS2_PHY_523_DATA + DDRSS2_PHY_524_DATA + DDRSS2_PHY_525_DATA + DDRSS2_PHY_526_DATA + DDRSS2_PHY_527_DATA + DDRSS2_PHY_528_DATA + DDRSS2_PHY_529_DATA + DDRSS2_PHY_530_DATA + DDRSS2_PHY_531_DATA + DDRSS2_PHY_532_DATA + DDRSS2_PHY_533_DATA + DDRSS2_PHY_534_DATA + DDRSS2_PHY_535_DATA + DDRSS2_PHY_536_DATA + DDRSS2_PHY_537_DATA + DDRSS2_PHY_538_DATA + DDRSS2_PHY_539_DATA + DDRSS2_PHY_540_DATA + DDRSS2_PHY_541_DATA + DDRSS2_PHY_542_DATA + DDRSS2_PHY_543_DATA + DDRSS2_PHY_544_DATA + DDRSS2_PHY_545_DATA + DDRSS2_PHY_546_DATA + DDRSS2_PHY_547_DATA + DDRSS2_PHY_548_DATA + DDRSS2_PHY_549_DATA + DDRSS2_PHY_550_DATA + DDRSS2_PHY_551_DATA + DDRSS2_PHY_552_DATA + DDRSS2_PHY_553_DATA + DDRSS2_PHY_554_DATA + DDRSS2_PHY_555_DATA + DDRSS2_PHY_556_DATA + DDRSS2_PHY_557_DATA + DDRSS2_PHY_558_DATA + DDRSS2_PHY_559_DATA + DDRSS2_PHY_560_DATA + DDRSS2_PHY_561_DATA + DDRSS2_PHY_562_DATA + DDRSS2_PHY_563_DATA + DDRSS2_PHY_564_DATA + DDRSS2_PHY_565_DATA + DDRSS2_PHY_566_DATA + DDRSS2_PHY_567_DATA + DDRSS2_PHY_568_DATA + DDRSS2_PHY_569_DATA + DDRSS2_PHY_570_DATA + DDRSS2_PHY_571_DATA + DDRSS2_PHY_572_DATA + DDRSS2_PHY_573_DATA + DDRSS2_PHY_574_DATA + DDRSS2_PHY_575_DATA + DDRSS2_PHY_576_DATA + DDRSS2_PHY_577_DATA + DDRSS2_PHY_578_DATA + DDRSS2_PHY_579_DATA + DDRSS2_PHY_580_DATA + DDRSS2_PHY_581_DATA + DDRSS2_PHY_582_DATA + DDRSS2_PHY_583_DATA + DDRSS2_PHY_584_DATA + DDRSS2_PHY_585_DATA + DDRSS2_PHY_586_DATA + DDRSS2_PHY_587_DATA + DDRSS2_PHY_588_DATA + DDRSS2_PHY_589_DATA + DDRSS2_PHY_590_DATA + DDRSS2_PHY_591_DATA + DDRSS2_PHY_592_DATA + DDRSS2_PHY_593_DATA + DDRSS2_PHY_594_DATA + DDRSS2_PHY_595_DATA + DDRSS2_PHY_596_DATA + DDRSS2_PHY_597_DATA + DDRSS2_PHY_598_DATA + DDRSS2_PHY_599_DATA + DDRSS2_PHY_600_DATA + DDRSS2_PHY_601_DATA + DDRSS2_PHY_602_DATA + DDRSS2_PHY_603_DATA + DDRSS2_PHY_604_DATA + DDRSS2_PHY_605_DATA + DDRSS2_PHY_606_DATA + DDRSS2_PHY_607_DATA + DDRSS2_PHY_608_DATA + DDRSS2_PHY_609_DATA + DDRSS2_PHY_610_DATA + DDRSS2_PHY_611_DATA + DDRSS2_PHY_612_DATA + DDRSS2_PHY_613_DATA + DDRSS2_PHY_614_DATA + DDRSS2_PHY_615_DATA + DDRSS2_PHY_616_DATA + DDRSS2_PHY_617_DATA + DDRSS2_PHY_618_DATA + DDRSS2_PHY_619_DATA + DDRSS2_PHY_620_DATA + DDRSS2_PHY_621_DATA + DDRSS2_PHY_622_DATA + DDRSS2_PHY_623_DATA + DDRSS2_PHY_624_DATA + DDRSS2_PHY_625_DATA + DDRSS2_PHY_626_DATA + DDRSS2_PHY_627_DATA + DDRSS2_PHY_628_DATA + DDRSS2_PHY_629_DATA + DDRSS2_PHY_630_DATA + DDRSS2_PHY_631_DATA + DDRSS2_PHY_632_DATA + DDRSS2_PHY_633_DATA + DDRSS2_PHY_634_DATA + DDRSS2_PHY_635_DATA + DDRSS2_PHY_636_DATA + DDRSS2_PHY_637_DATA + DDRSS2_PHY_638_DATA + DDRSS2_PHY_639_DATA + DDRSS2_PHY_640_DATA + DDRSS2_PHY_641_DATA + DDRSS2_PHY_642_DATA + DDRSS2_PHY_643_DATA + DDRSS2_PHY_644_DATA + DDRSS2_PHY_645_DATA + DDRSS2_PHY_646_DATA + DDRSS2_PHY_647_DATA + DDRSS2_PHY_648_DATA + DDRSS2_PHY_649_DATA + DDRSS2_PHY_650_DATA + DDRSS2_PHY_651_DATA + DDRSS2_PHY_652_DATA + DDRSS2_PHY_653_DATA + DDRSS2_PHY_654_DATA + DDRSS2_PHY_655_DATA + DDRSS2_PHY_656_DATA + DDRSS2_PHY_657_DATA + DDRSS2_PHY_658_DATA + DDRSS2_PHY_659_DATA + DDRSS2_PHY_660_DATA + DDRSS2_PHY_661_DATA + DDRSS2_PHY_662_DATA + DDRSS2_PHY_663_DATA + DDRSS2_PHY_664_DATA + DDRSS2_PHY_665_DATA + DDRSS2_PHY_666_DATA + DDRSS2_PHY_667_DATA + DDRSS2_PHY_668_DATA + DDRSS2_PHY_669_DATA + DDRSS2_PHY_670_DATA + DDRSS2_PHY_671_DATA + DDRSS2_PHY_672_DATA + DDRSS2_PHY_673_DATA + DDRSS2_PHY_674_DATA + DDRSS2_PHY_675_DATA + DDRSS2_PHY_676_DATA + DDRSS2_PHY_677_DATA + DDRSS2_PHY_678_DATA + DDRSS2_PHY_679_DATA + DDRSS2_PHY_680_DATA + DDRSS2_PHY_681_DATA + DDRSS2_PHY_682_DATA + DDRSS2_PHY_683_DATA + DDRSS2_PHY_684_DATA + DDRSS2_PHY_685_DATA + DDRSS2_PHY_686_DATA + DDRSS2_PHY_687_DATA + DDRSS2_PHY_688_DATA + DDRSS2_PHY_689_DATA + DDRSS2_PHY_690_DATA + DDRSS2_PHY_691_DATA + DDRSS2_PHY_692_DATA + DDRSS2_PHY_693_DATA + DDRSS2_PHY_694_DATA + DDRSS2_PHY_695_DATA + DDRSS2_PHY_696_DATA + DDRSS2_PHY_697_DATA + DDRSS2_PHY_698_DATA + DDRSS2_PHY_699_DATA + DDRSS2_PHY_700_DATA + DDRSS2_PHY_701_DATA + DDRSS2_PHY_702_DATA + DDRSS2_PHY_703_DATA + DDRSS2_PHY_704_DATA + DDRSS2_PHY_705_DATA + DDRSS2_PHY_706_DATA + DDRSS2_PHY_707_DATA + DDRSS2_PHY_708_DATA + DDRSS2_PHY_709_DATA + DDRSS2_PHY_710_DATA + DDRSS2_PHY_711_DATA + DDRSS2_PHY_712_DATA + DDRSS2_PHY_713_DATA + DDRSS2_PHY_714_DATA + DDRSS2_PHY_715_DATA + DDRSS2_PHY_716_DATA + DDRSS2_PHY_717_DATA + DDRSS2_PHY_718_DATA + DDRSS2_PHY_719_DATA + DDRSS2_PHY_720_DATA + DDRSS2_PHY_721_DATA + DDRSS2_PHY_722_DATA + DDRSS2_PHY_723_DATA + DDRSS2_PHY_724_DATA + DDRSS2_PHY_725_DATA + DDRSS2_PHY_726_DATA + DDRSS2_PHY_727_DATA + DDRSS2_PHY_728_DATA + DDRSS2_PHY_729_DATA + DDRSS2_PHY_730_DATA + DDRSS2_PHY_731_DATA + DDRSS2_PHY_732_DATA + DDRSS2_PHY_733_DATA + DDRSS2_PHY_734_DATA + DDRSS2_PHY_735_DATA + DDRSS2_PHY_736_DATA + DDRSS2_PHY_737_DATA + DDRSS2_PHY_738_DATA + DDRSS2_PHY_739_DATA + DDRSS2_PHY_740_DATA + DDRSS2_PHY_741_DATA + DDRSS2_PHY_742_DATA + DDRSS2_PHY_743_DATA + DDRSS2_PHY_744_DATA + DDRSS2_PHY_745_DATA + DDRSS2_PHY_746_DATA + DDRSS2_PHY_747_DATA + DDRSS2_PHY_748_DATA + DDRSS2_PHY_749_DATA + DDRSS2_PHY_750_DATA + DDRSS2_PHY_751_DATA + DDRSS2_PHY_752_DATA + DDRSS2_PHY_753_DATA + DDRSS2_PHY_754_DATA + DDRSS2_PHY_755_DATA + DDRSS2_PHY_756_DATA + DDRSS2_PHY_757_DATA + DDRSS2_PHY_758_DATA + DDRSS2_PHY_759_DATA + DDRSS2_PHY_760_DATA + DDRSS2_PHY_761_DATA + DDRSS2_PHY_762_DATA + DDRSS2_PHY_763_DATA + DDRSS2_PHY_764_DATA + DDRSS2_PHY_765_DATA + DDRSS2_PHY_766_DATA + DDRSS2_PHY_767_DATA + DDRSS2_PHY_768_DATA + DDRSS2_PHY_769_DATA + DDRSS2_PHY_770_DATA + DDRSS2_PHY_771_DATA + DDRSS2_PHY_772_DATA + DDRSS2_PHY_773_DATA + DDRSS2_PHY_774_DATA + DDRSS2_PHY_775_DATA + DDRSS2_PHY_776_DATA + DDRSS2_PHY_777_DATA + DDRSS2_PHY_778_DATA + DDRSS2_PHY_779_DATA + DDRSS2_PHY_780_DATA + DDRSS2_PHY_781_DATA + DDRSS2_PHY_782_DATA + DDRSS2_PHY_783_DATA + DDRSS2_PHY_784_DATA + DDRSS2_PHY_785_DATA + DDRSS2_PHY_786_DATA + DDRSS2_PHY_787_DATA + DDRSS2_PHY_788_DATA + DDRSS2_PHY_789_DATA + DDRSS2_PHY_790_DATA + DDRSS2_PHY_791_DATA + DDRSS2_PHY_792_DATA + DDRSS2_PHY_793_DATA + DDRSS2_PHY_794_DATA + DDRSS2_PHY_795_DATA + DDRSS2_PHY_796_DATA + DDRSS2_PHY_797_DATA + DDRSS2_PHY_798_DATA + DDRSS2_PHY_799_DATA + DDRSS2_PHY_800_DATA + DDRSS2_PHY_801_DATA + DDRSS2_PHY_802_DATA + DDRSS2_PHY_803_DATA + DDRSS2_PHY_804_DATA + DDRSS2_PHY_805_DATA + DDRSS2_PHY_806_DATA + DDRSS2_PHY_807_DATA + DDRSS2_PHY_808_DATA + DDRSS2_PHY_809_DATA + DDRSS2_PHY_810_DATA + DDRSS2_PHY_811_DATA + DDRSS2_PHY_812_DATA + DDRSS2_PHY_813_DATA + DDRSS2_PHY_814_DATA + DDRSS2_PHY_815_DATA + DDRSS2_PHY_816_DATA + DDRSS2_PHY_817_DATA + DDRSS2_PHY_818_DATA + DDRSS2_PHY_819_DATA + DDRSS2_PHY_820_DATA + DDRSS2_PHY_821_DATA + DDRSS2_PHY_822_DATA + DDRSS2_PHY_823_DATA + DDRSS2_PHY_824_DATA + DDRSS2_PHY_825_DATA + DDRSS2_PHY_826_DATA + DDRSS2_PHY_827_DATA + DDRSS2_PHY_828_DATA + DDRSS2_PHY_829_DATA + DDRSS2_PHY_830_DATA + DDRSS2_PHY_831_DATA + DDRSS2_PHY_832_DATA + DDRSS2_PHY_833_DATA + DDRSS2_PHY_834_DATA + DDRSS2_PHY_835_DATA + DDRSS2_PHY_836_DATA + DDRSS2_PHY_837_DATA + DDRSS2_PHY_838_DATA + DDRSS2_PHY_839_DATA + DDRSS2_PHY_840_DATA + DDRSS2_PHY_841_DATA + DDRSS2_PHY_842_DATA + DDRSS2_PHY_843_DATA + DDRSS2_PHY_844_DATA + DDRSS2_PHY_845_DATA + DDRSS2_PHY_846_DATA + DDRSS2_PHY_847_DATA + DDRSS2_PHY_848_DATA + DDRSS2_PHY_849_DATA + DDRSS2_PHY_850_DATA + DDRSS2_PHY_851_DATA + DDRSS2_PHY_852_DATA + DDRSS2_PHY_853_DATA + DDRSS2_PHY_854_DATA + DDRSS2_PHY_855_DATA + DDRSS2_PHY_856_DATA + DDRSS2_PHY_857_DATA + DDRSS2_PHY_858_DATA + DDRSS2_PHY_859_DATA + DDRSS2_PHY_860_DATA + DDRSS2_PHY_861_DATA + DDRSS2_PHY_862_DATA + DDRSS2_PHY_863_DATA + DDRSS2_PHY_864_DATA + DDRSS2_PHY_865_DATA + DDRSS2_PHY_866_DATA + DDRSS2_PHY_867_DATA + DDRSS2_PHY_868_DATA + DDRSS2_PHY_869_DATA + DDRSS2_PHY_870_DATA + DDRSS2_PHY_871_DATA + DDRSS2_PHY_872_DATA + DDRSS2_PHY_873_DATA + DDRSS2_PHY_874_DATA + DDRSS2_PHY_875_DATA + DDRSS2_PHY_876_DATA + DDRSS2_PHY_877_DATA + DDRSS2_PHY_878_DATA + DDRSS2_PHY_879_DATA + DDRSS2_PHY_880_DATA + DDRSS2_PHY_881_DATA + DDRSS2_PHY_882_DATA + DDRSS2_PHY_883_DATA + DDRSS2_PHY_884_DATA + DDRSS2_PHY_885_DATA + DDRSS2_PHY_886_DATA + DDRSS2_PHY_887_DATA + DDRSS2_PHY_888_DATA + DDRSS2_PHY_889_DATA + DDRSS2_PHY_890_DATA + DDRSS2_PHY_891_DATA + DDRSS2_PHY_892_DATA + DDRSS2_PHY_893_DATA + DDRSS2_PHY_894_DATA + DDRSS2_PHY_895_DATA + DDRSS2_PHY_896_DATA + DDRSS2_PHY_897_DATA + DDRSS2_PHY_898_DATA + DDRSS2_PHY_899_DATA + DDRSS2_PHY_900_DATA + DDRSS2_PHY_901_DATA + DDRSS2_PHY_902_DATA + DDRSS2_PHY_903_DATA + DDRSS2_PHY_904_DATA + DDRSS2_PHY_905_DATA + DDRSS2_PHY_906_DATA + DDRSS2_PHY_907_DATA + DDRSS2_PHY_908_DATA + DDRSS2_PHY_909_DATA + DDRSS2_PHY_910_DATA + DDRSS2_PHY_911_DATA + DDRSS2_PHY_912_DATA + DDRSS2_PHY_913_DATA + DDRSS2_PHY_914_DATA + DDRSS2_PHY_915_DATA + DDRSS2_PHY_916_DATA + DDRSS2_PHY_917_DATA + DDRSS2_PHY_918_DATA + DDRSS2_PHY_919_DATA + DDRSS2_PHY_920_DATA + DDRSS2_PHY_921_DATA + DDRSS2_PHY_922_DATA + DDRSS2_PHY_923_DATA + DDRSS2_PHY_924_DATA + DDRSS2_PHY_925_DATA + DDRSS2_PHY_926_DATA + DDRSS2_PHY_927_DATA + DDRSS2_PHY_928_DATA + DDRSS2_PHY_929_DATA + DDRSS2_PHY_930_DATA + DDRSS2_PHY_931_DATA + DDRSS2_PHY_932_DATA + DDRSS2_PHY_933_DATA + DDRSS2_PHY_934_DATA + DDRSS2_PHY_935_DATA + DDRSS2_PHY_936_DATA + DDRSS2_PHY_937_DATA + DDRSS2_PHY_938_DATA + DDRSS2_PHY_939_DATA + DDRSS2_PHY_940_DATA + DDRSS2_PHY_941_DATA + DDRSS2_PHY_942_DATA + DDRSS2_PHY_943_DATA + DDRSS2_PHY_944_DATA + DDRSS2_PHY_945_DATA + DDRSS2_PHY_946_DATA + DDRSS2_PHY_947_DATA + DDRSS2_PHY_948_DATA + DDRSS2_PHY_949_DATA + DDRSS2_PHY_950_DATA + DDRSS2_PHY_951_DATA + DDRSS2_PHY_952_DATA + DDRSS2_PHY_953_DATA + DDRSS2_PHY_954_DATA + DDRSS2_PHY_955_DATA + DDRSS2_PHY_956_DATA + DDRSS2_PHY_957_DATA + DDRSS2_PHY_958_DATA + DDRSS2_PHY_959_DATA + DDRSS2_PHY_960_DATA + DDRSS2_PHY_961_DATA + DDRSS2_PHY_962_DATA + DDRSS2_PHY_963_DATA + DDRSS2_PHY_964_DATA + DDRSS2_PHY_965_DATA + DDRSS2_PHY_966_DATA + DDRSS2_PHY_967_DATA + DDRSS2_PHY_968_DATA + DDRSS2_PHY_969_DATA + DDRSS2_PHY_970_DATA + DDRSS2_PHY_971_DATA + DDRSS2_PHY_972_DATA + DDRSS2_PHY_973_DATA + DDRSS2_PHY_974_DATA + DDRSS2_PHY_975_DATA + DDRSS2_PHY_976_DATA + DDRSS2_PHY_977_DATA + DDRSS2_PHY_978_DATA + DDRSS2_PHY_979_DATA + DDRSS2_PHY_980_DATA + DDRSS2_PHY_981_DATA + DDRSS2_PHY_982_DATA + DDRSS2_PHY_983_DATA + DDRSS2_PHY_984_DATA + DDRSS2_PHY_985_DATA + DDRSS2_PHY_986_DATA + DDRSS2_PHY_987_DATA + DDRSS2_PHY_988_DATA + DDRSS2_PHY_989_DATA + DDRSS2_PHY_990_DATA + DDRSS2_PHY_991_DATA + DDRSS2_PHY_992_DATA + DDRSS2_PHY_993_DATA + DDRSS2_PHY_994_DATA + DDRSS2_PHY_995_DATA + DDRSS2_PHY_996_DATA + DDRSS2_PHY_997_DATA + DDRSS2_PHY_998_DATA + DDRSS2_PHY_999_DATA + DDRSS2_PHY_1000_DATA + DDRSS2_PHY_1001_DATA + DDRSS2_PHY_1002_DATA + DDRSS2_PHY_1003_DATA + DDRSS2_PHY_1004_DATA + DDRSS2_PHY_1005_DATA + DDRSS2_PHY_1006_DATA + DDRSS2_PHY_1007_DATA + DDRSS2_PHY_1008_DATA + DDRSS2_PHY_1009_DATA + DDRSS2_PHY_1010_DATA + DDRSS2_PHY_1011_DATA + DDRSS2_PHY_1012_DATA + DDRSS2_PHY_1013_DATA + DDRSS2_PHY_1014_DATA + DDRSS2_PHY_1015_DATA + DDRSS2_PHY_1016_DATA + DDRSS2_PHY_1017_DATA + DDRSS2_PHY_1018_DATA + DDRSS2_PHY_1019_DATA + DDRSS2_PHY_1020_DATA + DDRSS2_PHY_1021_DATA + DDRSS2_PHY_1022_DATA + DDRSS2_PHY_1023_DATA + DDRSS2_PHY_1024_DATA + DDRSS2_PHY_1025_DATA + DDRSS2_PHY_1026_DATA + DDRSS2_PHY_1027_DATA + DDRSS2_PHY_1028_DATA + DDRSS2_PHY_1029_DATA + DDRSS2_PHY_1030_DATA + DDRSS2_PHY_1031_DATA + DDRSS2_PHY_1032_DATA + DDRSS2_PHY_1033_DATA + DDRSS2_PHY_1034_DATA + DDRSS2_PHY_1035_DATA + DDRSS2_PHY_1036_DATA + DDRSS2_PHY_1037_DATA + DDRSS2_PHY_1038_DATA + DDRSS2_PHY_1039_DATA + DDRSS2_PHY_1040_DATA + DDRSS2_PHY_1041_DATA + DDRSS2_PHY_1042_DATA + DDRSS2_PHY_1043_DATA + DDRSS2_PHY_1044_DATA + DDRSS2_PHY_1045_DATA + DDRSS2_PHY_1046_DATA + DDRSS2_PHY_1047_DATA + DDRSS2_PHY_1048_DATA + DDRSS2_PHY_1049_DATA + DDRSS2_PHY_1050_DATA + DDRSS2_PHY_1051_DATA + DDRSS2_PHY_1052_DATA + DDRSS2_PHY_1053_DATA + DDRSS2_PHY_1054_DATA + DDRSS2_PHY_1055_DATA + DDRSS2_PHY_1056_DATA + DDRSS2_PHY_1057_DATA + DDRSS2_PHY_1058_DATA + DDRSS2_PHY_1059_DATA + DDRSS2_PHY_1060_DATA + DDRSS2_PHY_1061_DATA + DDRSS2_PHY_1062_DATA + DDRSS2_PHY_1063_DATA + DDRSS2_PHY_1064_DATA + DDRSS2_PHY_1065_DATA + DDRSS2_PHY_1066_DATA + DDRSS2_PHY_1067_DATA + DDRSS2_PHY_1068_DATA + DDRSS2_PHY_1069_DATA + DDRSS2_PHY_1070_DATA + DDRSS2_PHY_1071_DATA + DDRSS2_PHY_1072_DATA + DDRSS2_PHY_1073_DATA + DDRSS2_PHY_1074_DATA + DDRSS2_PHY_1075_DATA + DDRSS2_PHY_1076_DATA + DDRSS2_PHY_1077_DATA + DDRSS2_PHY_1078_DATA + DDRSS2_PHY_1079_DATA + DDRSS2_PHY_1080_DATA + DDRSS2_PHY_1081_DATA + DDRSS2_PHY_1082_DATA + DDRSS2_PHY_1083_DATA + DDRSS2_PHY_1084_DATA + DDRSS2_PHY_1085_DATA + DDRSS2_PHY_1086_DATA + DDRSS2_PHY_1087_DATA + DDRSS2_PHY_1088_DATA + DDRSS2_PHY_1089_DATA + DDRSS2_PHY_1090_DATA + DDRSS2_PHY_1091_DATA + DDRSS2_PHY_1092_DATA + DDRSS2_PHY_1093_DATA + DDRSS2_PHY_1094_DATA + DDRSS2_PHY_1095_DATA + DDRSS2_PHY_1096_DATA + DDRSS2_PHY_1097_DATA + DDRSS2_PHY_1098_DATA + DDRSS2_PHY_1099_DATA + DDRSS2_PHY_1100_DATA + DDRSS2_PHY_1101_DATA + DDRSS2_PHY_1102_DATA + DDRSS2_PHY_1103_DATA + DDRSS2_PHY_1104_DATA + DDRSS2_PHY_1105_DATA + DDRSS2_PHY_1106_DATA + DDRSS2_PHY_1107_DATA + DDRSS2_PHY_1108_DATA + DDRSS2_PHY_1109_DATA + DDRSS2_PHY_1110_DATA + DDRSS2_PHY_1111_DATA + DDRSS2_PHY_1112_DATA + DDRSS2_PHY_1113_DATA + DDRSS2_PHY_1114_DATA + DDRSS2_PHY_1115_DATA + DDRSS2_PHY_1116_DATA + DDRSS2_PHY_1117_DATA + DDRSS2_PHY_1118_DATA + DDRSS2_PHY_1119_DATA + DDRSS2_PHY_1120_DATA + DDRSS2_PHY_1121_DATA + DDRSS2_PHY_1122_DATA + DDRSS2_PHY_1123_DATA + DDRSS2_PHY_1124_DATA + DDRSS2_PHY_1125_DATA + DDRSS2_PHY_1126_DATA + DDRSS2_PHY_1127_DATA + DDRSS2_PHY_1128_DATA + DDRSS2_PHY_1129_DATA + DDRSS2_PHY_1130_DATA + DDRSS2_PHY_1131_DATA + DDRSS2_PHY_1132_DATA + DDRSS2_PHY_1133_DATA + DDRSS2_PHY_1134_DATA + DDRSS2_PHY_1135_DATA + DDRSS2_PHY_1136_DATA + DDRSS2_PHY_1137_DATA + DDRSS2_PHY_1138_DATA + DDRSS2_PHY_1139_DATA + DDRSS2_PHY_1140_DATA + DDRSS2_PHY_1141_DATA + DDRSS2_PHY_1142_DATA + DDRSS2_PHY_1143_DATA + DDRSS2_PHY_1144_DATA + DDRSS2_PHY_1145_DATA + DDRSS2_PHY_1146_DATA + DDRSS2_PHY_1147_DATA + DDRSS2_PHY_1148_DATA + DDRSS2_PHY_1149_DATA + DDRSS2_PHY_1150_DATA + DDRSS2_PHY_1151_DATA + DDRSS2_PHY_1152_DATA + DDRSS2_PHY_1153_DATA + DDRSS2_PHY_1154_DATA + DDRSS2_PHY_1155_DATA + DDRSS2_PHY_1156_DATA + DDRSS2_PHY_1157_DATA + DDRSS2_PHY_1158_DATA + DDRSS2_PHY_1159_DATA + DDRSS2_PHY_1160_DATA + DDRSS2_PHY_1161_DATA + DDRSS2_PHY_1162_DATA + DDRSS2_PHY_1163_DATA + DDRSS2_PHY_1164_DATA + DDRSS2_PHY_1165_DATA + DDRSS2_PHY_1166_DATA + DDRSS2_PHY_1167_DATA + DDRSS2_PHY_1168_DATA + DDRSS2_PHY_1169_DATA + DDRSS2_PHY_1170_DATA + DDRSS2_PHY_1171_DATA + DDRSS2_PHY_1172_DATA + DDRSS2_PHY_1173_DATA + DDRSS2_PHY_1174_DATA + DDRSS2_PHY_1175_DATA + DDRSS2_PHY_1176_DATA + DDRSS2_PHY_1177_DATA + DDRSS2_PHY_1178_DATA + DDRSS2_PHY_1179_DATA + DDRSS2_PHY_1180_DATA + DDRSS2_PHY_1181_DATA + DDRSS2_PHY_1182_DATA + DDRSS2_PHY_1183_DATA + DDRSS2_PHY_1184_DATA + DDRSS2_PHY_1185_DATA + DDRSS2_PHY_1186_DATA + DDRSS2_PHY_1187_DATA + DDRSS2_PHY_1188_DATA + DDRSS2_PHY_1189_DATA + DDRSS2_PHY_1190_DATA + DDRSS2_PHY_1191_DATA + DDRSS2_PHY_1192_DATA + DDRSS2_PHY_1193_DATA + DDRSS2_PHY_1194_DATA + DDRSS2_PHY_1195_DATA + DDRSS2_PHY_1196_DATA + DDRSS2_PHY_1197_DATA + DDRSS2_PHY_1198_DATA + DDRSS2_PHY_1199_DATA + DDRSS2_PHY_1200_DATA + DDRSS2_PHY_1201_DATA + DDRSS2_PHY_1202_DATA + DDRSS2_PHY_1203_DATA + DDRSS2_PHY_1204_DATA + DDRSS2_PHY_1205_DATA + DDRSS2_PHY_1206_DATA + DDRSS2_PHY_1207_DATA + DDRSS2_PHY_1208_DATA + DDRSS2_PHY_1209_DATA + DDRSS2_PHY_1210_DATA + DDRSS2_PHY_1211_DATA + DDRSS2_PHY_1212_DATA + DDRSS2_PHY_1213_DATA + DDRSS2_PHY_1214_DATA + DDRSS2_PHY_1215_DATA + DDRSS2_PHY_1216_DATA + DDRSS2_PHY_1217_DATA + DDRSS2_PHY_1218_DATA + DDRSS2_PHY_1219_DATA + DDRSS2_PHY_1220_DATA + DDRSS2_PHY_1221_DATA + DDRSS2_PHY_1222_DATA + DDRSS2_PHY_1223_DATA + DDRSS2_PHY_1224_DATA + DDRSS2_PHY_1225_DATA + DDRSS2_PHY_1226_DATA + DDRSS2_PHY_1227_DATA + DDRSS2_PHY_1228_DATA + DDRSS2_PHY_1229_DATA + DDRSS2_PHY_1230_DATA + DDRSS2_PHY_1231_DATA + DDRSS2_PHY_1232_DATA + DDRSS2_PHY_1233_DATA + DDRSS2_PHY_1234_DATA + DDRSS2_PHY_1235_DATA + DDRSS2_PHY_1236_DATA + DDRSS2_PHY_1237_DATA + DDRSS2_PHY_1238_DATA + DDRSS2_PHY_1239_DATA + DDRSS2_PHY_1240_DATA + DDRSS2_PHY_1241_DATA + DDRSS2_PHY_1242_DATA + DDRSS2_PHY_1243_DATA + DDRSS2_PHY_1244_DATA + DDRSS2_PHY_1245_DATA + DDRSS2_PHY_1246_DATA + DDRSS2_PHY_1247_DATA + DDRSS2_PHY_1248_DATA + DDRSS2_PHY_1249_DATA + DDRSS2_PHY_1250_DATA + DDRSS2_PHY_1251_DATA + DDRSS2_PHY_1252_DATA + DDRSS2_PHY_1253_DATA + DDRSS2_PHY_1254_DATA + DDRSS2_PHY_1255_DATA + DDRSS2_PHY_1256_DATA + DDRSS2_PHY_1257_DATA + DDRSS2_PHY_1258_DATA + DDRSS2_PHY_1259_DATA + DDRSS2_PHY_1260_DATA + DDRSS2_PHY_1261_DATA + DDRSS2_PHY_1262_DATA + DDRSS2_PHY_1263_DATA + DDRSS2_PHY_1264_DATA + DDRSS2_PHY_1265_DATA + DDRSS2_PHY_1266_DATA + DDRSS2_PHY_1267_DATA + DDRSS2_PHY_1268_DATA + DDRSS2_PHY_1269_DATA + DDRSS2_PHY_1270_DATA + DDRSS2_PHY_1271_DATA + DDRSS2_PHY_1272_DATA + DDRSS2_PHY_1273_DATA + DDRSS2_PHY_1274_DATA + DDRSS2_PHY_1275_DATA + DDRSS2_PHY_1276_DATA + DDRSS2_PHY_1277_DATA + DDRSS2_PHY_1278_DATA + DDRSS2_PHY_1279_DATA + DDRSS2_PHY_1280_DATA + DDRSS2_PHY_1281_DATA + DDRSS2_PHY_1282_DATA + DDRSS2_PHY_1283_DATA + DDRSS2_PHY_1284_DATA + DDRSS2_PHY_1285_DATA + DDRSS2_PHY_1286_DATA + DDRSS2_PHY_1287_DATA + DDRSS2_PHY_1288_DATA + DDRSS2_PHY_1289_DATA + DDRSS2_PHY_1290_DATA + DDRSS2_PHY_1291_DATA + DDRSS2_PHY_1292_DATA + DDRSS2_PHY_1293_DATA + DDRSS2_PHY_1294_DATA + DDRSS2_PHY_1295_DATA + DDRSS2_PHY_1296_DATA + DDRSS2_PHY_1297_DATA + DDRSS2_PHY_1298_DATA + DDRSS2_PHY_1299_DATA + DDRSS2_PHY_1300_DATA + DDRSS2_PHY_1301_DATA + DDRSS2_PHY_1302_DATA + DDRSS2_PHY_1303_DATA + DDRSS2_PHY_1304_DATA + DDRSS2_PHY_1305_DATA + DDRSS2_PHY_1306_DATA + DDRSS2_PHY_1307_DATA + DDRSS2_PHY_1308_DATA + DDRSS2_PHY_1309_DATA + DDRSS2_PHY_1310_DATA + DDRSS2_PHY_1311_DATA + DDRSS2_PHY_1312_DATA + DDRSS2_PHY_1313_DATA + DDRSS2_PHY_1314_DATA + DDRSS2_PHY_1315_DATA + DDRSS2_PHY_1316_DATA + DDRSS2_PHY_1317_DATA + DDRSS2_PHY_1318_DATA + DDRSS2_PHY_1319_DATA + DDRSS2_PHY_1320_DATA + DDRSS2_PHY_1321_DATA + DDRSS2_PHY_1322_DATA + DDRSS2_PHY_1323_DATA + DDRSS2_PHY_1324_DATA + DDRSS2_PHY_1325_DATA + DDRSS2_PHY_1326_DATA + DDRSS2_PHY_1327_DATA + DDRSS2_PHY_1328_DATA + DDRSS2_PHY_1329_DATA + DDRSS2_PHY_1330_DATA + DDRSS2_PHY_1331_DATA + DDRSS2_PHY_1332_DATA + DDRSS2_PHY_1333_DATA + DDRSS2_PHY_1334_DATA + DDRSS2_PHY_1335_DATA + DDRSS2_PHY_1336_DATA + DDRSS2_PHY_1337_DATA + DDRSS2_PHY_1338_DATA + DDRSS2_PHY_1339_DATA + DDRSS2_PHY_1340_DATA + DDRSS2_PHY_1341_DATA + DDRSS2_PHY_1342_DATA + DDRSS2_PHY_1343_DATA + DDRSS2_PHY_1344_DATA + DDRSS2_PHY_1345_DATA + DDRSS2_PHY_1346_DATA + DDRSS2_PHY_1347_DATA + DDRSS2_PHY_1348_DATA + DDRSS2_PHY_1349_DATA + DDRSS2_PHY_1350_DATA + DDRSS2_PHY_1351_DATA + DDRSS2_PHY_1352_DATA + DDRSS2_PHY_1353_DATA + DDRSS2_PHY_1354_DATA + DDRSS2_PHY_1355_DATA + DDRSS2_PHY_1356_DATA + DDRSS2_PHY_1357_DATA + DDRSS2_PHY_1358_DATA + DDRSS2_PHY_1359_DATA + DDRSS2_PHY_1360_DATA + DDRSS2_PHY_1361_DATA + DDRSS2_PHY_1362_DATA + DDRSS2_PHY_1363_DATA + DDRSS2_PHY_1364_DATA + DDRSS2_PHY_1365_DATA + DDRSS2_PHY_1366_DATA + DDRSS2_PHY_1367_DATA + DDRSS2_PHY_1368_DATA + DDRSS2_PHY_1369_DATA + DDRSS2_PHY_1370_DATA + DDRSS2_PHY_1371_DATA + DDRSS2_PHY_1372_DATA + DDRSS2_PHY_1373_DATA + DDRSS2_PHY_1374_DATA + DDRSS2_PHY_1375_DATA + DDRSS2_PHY_1376_DATA + DDRSS2_PHY_1377_DATA + DDRSS2_PHY_1378_DATA + DDRSS2_PHY_1379_DATA + DDRSS2_PHY_1380_DATA + DDRSS2_PHY_1381_DATA + DDRSS2_PHY_1382_DATA + DDRSS2_PHY_1383_DATA + DDRSS2_PHY_1384_DATA + DDRSS2_PHY_1385_DATA + DDRSS2_PHY_1386_DATA + DDRSS2_PHY_1387_DATA + DDRSS2_PHY_1388_DATA + DDRSS2_PHY_1389_DATA + DDRSS2_PHY_1390_DATA + DDRSS2_PHY_1391_DATA + DDRSS2_PHY_1392_DATA + DDRSS2_PHY_1393_DATA + DDRSS2_PHY_1394_DATA + DDRSS2_PHY_1395_DATA + DDRSS2_PHY_1396_DATA + DDRSS2_PHY_1397_DATA + DDRSS2_PHY_1398_DATA + DDRSS2_PHY_1399_DATA + DDRSS2_PHY_1400_DATA + DDRSS2_PHY_1401_DATA + DDRSS2_PHY_1402_DATA + DDRSS2_PHY_1403_DATA + DDRSS2_PHY_1404_DATA + DDRSS2_PHY_1405_DATA + DDRSS2_PHY_1406_DATA + DDRSS2_PHY_1407_DATA + DDRSS2_PHY_1408_DATA + DDRSS2_PHY_1409_DATA + DDRSS2_PHY_1410_DATA + DDRSS2_PHY_1411_DATA + DDRSS2_PHY_1412_DATA + DDRSS2_PHY_1413_DATA + DDRSS2_PHY_1414_DATA + DDRSS2_PHY_1415_DATA + DDRSS2_PHY_1416_DATA + DDRSS2_PHY_1417_DATA + DDRSS2_PHY_1418_DATA + DDRSS2_PHY_1419_DATA + DDRSS2_PHY_1420_DATA + DDRSS2_PHY_1421_DATA + DDRSS2_PHY_1422_DATA + >; + }; + + memorycontroller3: memorycontroller@29f0000 { + compatible = "ti,j721s2-ddrss"; + reg = <0x0 0x029f0000 0x0 0x4000>, + <0x0 0x0114000 0x0 0x100>; + reg-names = "cfg", "ctrl_mmr_lp4"; + power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>, + <&k3_pds 139 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 194 1>, <&k3_clks 78 2>; + ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>; + ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>; + ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>; + ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>; + instance = <3>; + + bootph-pre-ram; + + ti,ctl-data = < + DDRSS3_CTL_00_DATA + DDRSS3_CTL_01_DATA + DDRSS3_CTL_02_DATA + DDRSS3_CTL_03_DATA + DDRSS3_CTL_04_DATA + DDRSS3_CTL_05_DATA + DDRSS3_CTL_06_DATA + DDRSS3_CTL_07_DATA + DDRSS3_CTL_08_DATA + DDRSS3_CTL_09_DATA + DDRSS3_CTL_10_DATA + DDRSS3_CTL_11_DATA + DDRSS3_CTL_12_DATA + DDRSS3_CTL_13_DATA + DDRSS3_CTL_14_DATA + DDRSS3_CTL_15_DATA + DDRSS3_CTL_16_DATA + DDRSS3_CTL_17_DATA + DDRSS3_CTL_18_DATA + DDRSS3_CTL_19_DATA + DDRSS3_CTL_20_DATA + DDRSS3_CTL_21_DATA + DDRSS3_CTL_22_DATA + DDRSS3_CTL_23_DATA + DDRSS3_CTL_24_DATA + DDRSS3_CTL_25_DATA + DDRSS3_CTL_26_DATA + DDRSS3_CTL_27_DATA + DDRSS3_CTL_28_DATA + DDRSS3_CTL_29_DATA + DDRSS3_CTL_30_DATA + DDRSS3_CTL_31_DATA + DDRSS3_CTL_32_DATA + DDRSS3_CTL_33_DATA + DDRSS3_CTL_34_DATA + DDRSS3_CTL_35_DATA + DDRSS3_CTL_36_DATA + DDRSS3_CTL_37_DATA + DDRSS3_CTL_38_DATA + DDRSS3_CTL_39_DATA + DDRSS3_CTL_40_DATA + DDRSS3_CTL_41_DATA + DDRSS3_CTL_42_DATA + DDRSS3_CTL_43_DATA + DDRSS3_CTL_44_DATA + DDRSS3_CTL_45_DATA + DDRSS3_CTL_46_DATA + DDRSS3_CTL_47_DATA + DDRSS3_CTL_48_DATA + DDRSS3_CTL_49_DATA + DDRSS3_CTL_50_DATA + DDRSS3_CTL_51_DATA + DDRSS3_CTL_52_DATA + DDRSS3_CTL_53_DATA + DDRSS3_CTL_54_DATA + DDRSS3_CTL_55_DATA + DDRSS3_CTL_56_DATA + DDRSS3_CTL_57_DATA + DDRSS3_CTL_58_DATA + DDRSS3_CTL_59_DATA + DDRSS3_CTL_60_DATA + DDRSS3_CTL_61_DATA + DDRSS3_CTL_62_DATA + DDRSS3_CTL_63_DATA + DDRSS3_CTL_64_DATA + DDRSS3_CTL_65_DATA + DDRSS3_CTL_66_DATA + DDRSS3_CTL_67_DATA + DDRSS3_CTL_68_DATA + DDRSS3_CTL_69_DATA + DDRSS3_CTL_70_DATA + DDRSS3_CTL_71_DATA + DDRSS3_CTL_72_DATA + DDRSS3_CTL_73_DATA + DDRSS3_CTL_74_DATA + DDRSS3_CTL_75_DATA + DDRSS3_CTL_76_DATA + DDRSS3_CTL_77_DATA + DDRSS3_CTL_78_DATA + DDRSS3_CTL_79_DATA + DDRSS3_CTL_80_DATA + DDRSS3_CTL_81_DATA + DDRSS3_CTL_82_DATA + DDRSS3_CTL_83_DATA + DDRSS3_CTL_84_DATA + DDRSS3_CTL_85_DATA + DDRSS3_CTL_86_DATA + DDRSS3_CTL_87_DATA + DDRSS3_CTL_88_DATA + DDRSS3_CTL_89_DATA + DDRSS3_CTL_90_DATA + DDRSS3_CTL_91_DATA + DDRSS3_CTL_92_DATA + DDRSS3_CTL_93_DATA + DDRSS3_CTL_94_DATA + DDRSS3_CTL_95_DATA + DDRSS3_CTL_96_DATA + DDRSS3_CTL_97_DATA + DDRSS3_CTL_98_DATA + DDRSS3_CTL_99_DATA + DDRSS3_CTL_100_DATA + DDRSS3_CTL_101_DATA + DDRSS3_CTL_102_DATA + DDRSS3_CTL_103_DATA + DDRSS3_CTL_104_DATA + DDRSS3_CTL_105_DATA + DDRSS3_CTL_106_DATA + DDRSS3_CTL_107_DATA + DDRSS3_CTL_108_DATA + DDRSS3_CTL_109_DATA + DDRSS3_CTL_110_DATA + DDRSS3_CTL_111_DATA + DDRSS3_CTL_112_DATA + DDRSS3_CTL_113_DATA + DDRSS3_CTL_114_DATA + DDRSS3_CTL_115_DATA + DDRSS3_CTL_116_DATA + DDRSS3_CTL_117_DATA + DDRSS3_CTL_118_DATA + DDRSS3_CTL_119_DATA + DDRSS3_CTL_120_DATA + DDRSS3_CTL_121_DATA + DDRSS3_CTL_122_DATA + DDRSS3_CTL_123_DATA + DDRSS3_CTL_124_DATA + DDRSS3_CTL_125_DATA + DDRSS3_CTL_126_DATA + DDRSS3_CTL_127_DATA + DDRSS3_CTL_128_DATA + DDRSS3_CTL_129_DATA + DDRSS3_CTL_130_DATA + DDRSS3_CTL_131_DATA + DDRSS3_CTL_132_DATA + DDRSS3_CTL_133_DATA + DDRSS3_CTL_134_DATA + DDRSS3_CTL_135_DATA + DDRSS3_CTL_136_DATA + DDRSS3_CTL_137_DATA + DDRSS3_CTL_138_DATA + DDRSS3_CTL_139_DATA + DDRSS3_CTL_140_DATA + DDRSS3_CTL_141_DATA + DDRSS3_CTL_142_DATA + DDRSS3_CTL_143_DATA + DDRSS3_CTL_144_DATA + DDRSS3_CTL_145_DATA + DDRSS3_CTL_146_DATA + DDRSS3_CTL_147_DATA + DDRSS3_CTL_148_DATA + DDRSS3_CTL_149_DATA + DDRSS3_CTL_150_DATA + DDRSS3_CTL_151_DATA + DDRSS3_CTL_152_DATA + DDRSS3_CTL_153_DATA + DDRSS3_CTL_154_DATA + DDRSS3_CTL_155_DATA + DDRSS3_CTL_156_DATA + DDRSS3_CTL_157_DATA + DDRSS3_CTL_158_DATA + DDRSS3_CTL_159_DATA + DDRSS3_CTL_160_DATA + DDRSS3_CTL_161_DATA + DDRSS3_CTL_162_DATA + DDRSS3_CTL_163_DATA + DDRSS3_CTL_164_DATA + DDRSS3_CTL_165_DATA + DDRSS3_CTL_166_DATA + DDRSS3_CTL_167_DATA + DDRSS3_CTL_168_DATA + DDRSS3_CTL_169_DATA + DDRSS3_CTL_170_DATA + DDRSS3_CTL_171_DATA + DDRSS3_CTL_172_DATA + DDRSS3_CTL_173_DATA + DDRSS3_CTL_174_DATA + DDRSS3_CTL_175_DATA + DDRSS3_CTL_176_DATA + DDRSS3_CTL_177_DATA + DDRSS3_CTL_178_DATA + DDRSS3_CTL_179_DATA + DDRSS3_CTL_180_DATA + DDRSS3_CTL_181_DATA + DDRSS3_CTL_182_DATA + DDRSS3_CTL_183_DATA + DDRSS3_CTL_184_DATA + DDRSS3_CTL_185_DATA + DDRSS3_CTL_186_DATA + DDRSS3_CTL_187_DATA + DDRSS3_CTL_188_DATA + DDRSS3_CTL_189_DATA + DDRSS3_CTL_190_DATA + DDRSS3_CTL_191_DATA + DDRSS3_CTL_192_DATA + DDRSS3_CTL_193_DATA + DDRSS3_CTL_194_DATA + DDRSS3_CTL_195_DATA + DDRSS3_CTL_196_DATA + DDRSS3_CTL_197_DATA + DDRSS3_CTL_198_DATA + DDRSS3_CTL_199_DATA + DDRSS3_CTL_200_DATA + DDRSS3_CTL_201_DATA + DDRSS3_CTL_202_DATA + DDRSS3_CTL_203_DATA + DDRSS3_CTL_204_DATA + DDRSS3_CTL_205_DATA + DDRSS3_CTL_206_DATA + DDRSS3_CTL_207_DATA + DDRSS3_CTL_208_DATA + DDRSS3_CTL_209_DATA + DDRSS3_CTL_210_DATA + DDRSS3_CTL_211_DATA + DDRSS3_CTL_212_DATA + DDRSS3_CTL_213_DATA + DDRSS3_CTL_214_DATA + DDRSS3_CTL_215_DATA + DDRSS3_CTL_216_DATA + DDRSS3_CTL_217_DATA + DDRSS3_CTL_218_DATA + DDRSS3_CTL_219_DATA + DDRSS3_CTL_220_DATA + DDRSS3_CTL_221_DATA + DDRSS3_CTL_222_DATA + DDRSS3_CTL_223_DATA + DDRSS3_CTL_224_DATA + DDRSS3_CTL_225_DATA + DDRSS3_CTL_226_DATA + DDRSS3_CTL_227_DATA + DDRSS3_CTL_228_DATA + DDRSS3_CTL_229_DATA + DDRSS3_CTL_230_DATA + DDRSS3_CTL_231_DATA + DDRSS3_CTL_232_DATA + DDRSS3_CTL_233_DATA + DDRSS3_CTL_234_DATA + DDRSS3_CTL_235_DATA + DDRSS3_CTL_236_DATA + DDRSS3_CTL_237_DATA + DDRSS3_CTL_238_DATA + DDRSS3_CTL_239_DATA + DDRSS3_CTL_240_DATA + DDRSS3_CTL_241_DATA + DDRSS3_CTL_242_DATA + DDRSS3_CTL_243_DATA + DDRSS3_CTL_244_DATA + DDRSS3_CTL_245_DATA + DDRSS3_CTL_246_DATA + DDRSS3_CTL_247_DATA + DDRSS3_CTL_248_DATA + DDRSS3_CTL_249_DATA + DDRSS3_CTL_250_DATA + DDRSS3_CTL_251_DATA + DDRSS3_CTL_252_DATA + DDRSS3_CTL_253_DATA + DDRSS3_CTL_254_DATA + DDRSS3_CTL_255_DATA + DDRSS3_CTL_256_DATA + DDRSS3_CTL_257_DATA + DDRSS3_CTL_258_DATA + DDRSS3_CTL_259_DATA + DDRSS3_CTL_260_DATA + DDRSS3_CTL_261_DATA + DDRSS3_CTL_262_DATA + DDRSS3_CTL_263_DATA + DDRSS3_CTL_264_DATA + DDRSS3_CTL_265_DATA + DDRSS3_CTL_266_DATA + DDRSS3_CTL_267_DATA + DDRSS3_CTL_268_DATA + DDRSS3_CTL_269_DATA + DDRSS3_CTL_270_DATA + DDRSS3_CTL_271_DATA + DDRSS3_CTL_272_DATA + DDRSS3_CTL_273_DATA + DDRSS3_CTL_274_DATA + DDRSS3_CTL_275_DATA + DDRSS3_CTL_276_DATA + DDRSS3_CTL_277_DATA + DDRSS3_CTL_278_DATA + DDRSS3_CTL_279_DATA + DDRSS3_CTL_280_DATA + DDRSS3_CTL_281_DATA + DDRSS3_CTL_282_DATA + DDRSS3_CTL_283_DATA + DDRSS3_CTL_284_DATA + DDRSS3_CTL_285_DATA + DDRSS3_CTL_286_DATA + DDRSS3_CTL_287_DATA + DDRSS3_CTL_288_DATA + DDRSS3_CTL_289_DATA + DDRSS3_CTL_290_DATA + DDRSS3_CTL_291_DATA + DDRSS3_CTL_292_DATA + DDRSS3_CTL_293_DATA + DDRSS3_CTL_294_DATA + DDRSS3_CTL_295_DATA + DDRSS3_CTL_296_DATA + DDRSS3_CTL_297_DATA + DDRSS3_CTL_298_DATA + DDRSS3_CTL_299_DATA + DDRSS3_CTL_300_DATA + DDRSS3_CTL_301_DATA + DDRSS3_CTL_302_DATA + DDRSS3_CTL_303_DATA + DDRSS3_CTL_304_DATA + DDRSS3_CTL_305_DATA + DDRSS3_CTL_306_DATA + DDRSS3_CTL_307_DATA + DDRSS3_CTL_308_DATA + DDRSS3_CTL_309_DATA + DDRSS3_CTL_310_DATA + DDRSS3_CTL_311_DATA + DDRSS3_CTL_312_DATA + DDRSS3_CTL_313_DATA + DDRSS3_CTL_314_DATA + DDRSS3_CTL_315_DATA + DDRSS3_CTL_316_DATA + DDRSS3_CTL_317_DATA + DDRSS3_CTL_318_DATA + DDRSS3_CTL_319_DATA + DDRSS3_CTL_320_DATA + DDRSS3_CTL_321_DATA + DDRSS3_CTL_322_DATA + DDRSS3_CTL_323_DATA + DDRSS3_CTL_324_DATA + DDRSS3_CTL_325_DATA + DDRSS3_CTL_326_DATA + DDRSS3_CTL_327_DATA + DDRSS3_CTL_328_DATA + DDRSS3_CTL_329_DATA + DDRSS3_CTL_330_DATA + DDRSS3_CTL_331_DATA + DDRSS3_CTL_332_DATA + DDRSS3_CTL_333_DATA + DDRSS3_CTL_334_DATA + DDRSS3_CTL_335_DATA + DDRSS3_CTL_336_DATA + DDRSS3_CTL_337_DATA + DDRSS3_CTL_338_DATA + DDRSS3_CTL_339_DATA + DDRSS3_CTL_340_DATA + DDRSS3_CTL_341_DATA + DDRSS3_CTL_342_DATA + DDRSS3_CTL_343_DATA + DDRSS3_CTL_344_DATA + DDRSS3_CTL_345_DATA + DDRSS3_CTL_346_DATA + DDRSS3_CTL_347_DATA + DDRSS3_CTL_348_DATA + DDRSS3_CTL_349_DATA + DDRSS3_CTL_350_DATA + DDRSS3_CTL_351_DATA + DDRSS3_CTL_352_DATA + DDRSS3_CTL_353_DATA + DDRSS3_CTL_354_DATA + DDRSS3_CTL_355_DATA + DDRSS3_CTL_356_DATA + DDRSS3_CTL_357_DATA + DDRSS3_CTL_358_DATA + DDRSS3_CTL_359_DATA + DDRSS3_CTL_360_DATA + DDRSS3_CTL_361_DATA + DDRSS3_CTL_362_DATA + DDRSS3_CTL_363_DATA + DDRSS3_CTL_364_DATA + DDRSS3_CTL_365_DATA + DDRSS3_CTL_366_DATA + DDRSS3_CTL_367_DATA + DDRSS3_CTL_368_DATA + DDRSS3_CTL_369_DATA + DDRSS3_CTL_370_DATA + DDRSS3_CTL_371_DATA + DDRSS3_CTL_372_DATA + DDRSS3_CTL_373_DATA + DDRSS3_CTL_374_DATA + DDRSS3_CTL_375_DATA + DDRSS3_CTL_376_DATA + DDRSS3_CTL_377_DATA + DDRSS3_CTL_378_DATA + DDRSS3_CTL_379_DATA + DDRSS3_CTL_380_DATA + DDRSS3_CTL_381_DATA + DDRSS3_CTL_382_DATA + DDRSS3_CTL_383_DATA + DDRSS3_CTL_384_DATA + DDRSS3_CTL_385_DATA + DDRSS3_CTL_386_DATA + DDRSS3_CTL_387_DATA + DDRSS3_CTL_388_DATA + DDRSS3_CTL_389_DATA + DDRSS3_CTL_390_DATA + DDRSS3_CTL_391_DATA + DDRSS3_CTL_392_DATA + DDRSS3_CTL_393_DATA + DDRSS3_CTL_394_DATA + DDRSS3_CTL_395_DATA + DDRSS3_CTL_396_DATA + DDRSS3_CTL_397_DATA + DDRSS3_CTL_398_DATA + DDRSS3_CTL_399_DATA + DDRSS3_CTL_400_DATA + DDRSS3_CTL_401_DATA + DDRSS3_CTL_402_DATA + DDRSS3_CTL_403_DATA + DDRSS3_CTL_404_DATA + DDRSS3_CTL_405_DATA + DDRSS3_CTL_406_DATA + DDRSS3_CTL_407_DATA + DDRSS3_CTL_408_DATA + DDRSS3_CTL_409_DATA + DDRSS3_CTL_410_DATA + DDRSS3_CTL_411_DATA + DDRSS3_CTL_412_DATA + DDRSS3_CTL_413_DATA + DDRSS3_CTL_414_DATA + DDRSS3_CTL_415_DATA + DDRSS3_CTL_416_DATA + DDRSS3_CTL_417_DATA + DDRSS3_CTL_418_DATA + DDRSS3_CTL_419_DATA + DDRSS3_CTL_420_DATA + DDRSS3_CTL_421_DATA + DDRSS3_CTL_422_DATA + DDRSS3_CTL_423_DATA + DDRSS3_CTL_424_DATA + DDRSS3_CTL_425_DATA + DDRSS3_CTL_426_DATA + DDRSS3_CTL_427_DATA + DDRSS3_CTL_428_DATA + DDRSS3_CTL_429_DATA + DDRSS3_CTL_430_DATA + DDRSS3_CTL_431_DATA + DDRSS3_CTL_432_DATA + DDRSS3_CTL_433_DATA + DDRSS3_CTL_434_DATA + DDRSS3_CTL_435_DATA + DDRSS3_CTL_436_DATA + DDRSS3_CTL_437_DATA + DDRSS3_CTL_438_DATA + DDRSS3_CTL_439_DATA + DDRSS3_CTL_440_DATA + DDRSS3_CTL_441_DATA + DDRSS3_CTL_442_DATA + DDRSS3_CTL_443_DATA + DDRSS3_CTL_444_DATA + DDRSS3_CTL_445_DATA + DDRSS3_CTL_446_DATA + DDRSS3_CTL_447_DATA + DDRSS3_CTL_448_DATA + DDRSS3_CTL_449_DATA + DDRSS3_CTL_450_DATA + DDRSS3_CTL_451_DATA + DDRSS3_CTL_452_DATA + DDRSS3_CTL_453_DATA + DDRSS3_CTL_454_DATA + DDRSS3_CTL_455_DATA + DDRSS3_CTL_456_DATA + DDRSS3_CTL_457_DATA + DDRSS3_CTL_458_DATA + >; + + ti,pi-data = < + DDRSS3_PI_00_DATA + DDRSS3_PI_01_DATA + DDRSS3_PI_02_DATA + DDRSS3_PI_03_DATA + DDRSS3_PI_04_DATA + DDRSS3_PI_05_DATA + DDRSS3_PI_06_DATA + DDRSS3_PI_07_DATA + DDRSS3_PI_08_DATA + DDRSS3_PI_09_DATA + DDRSS3_PI_10_DATA + DDRSS3_PI_11_DATA + DDRSS3_PI_12_DATA + DDRSS3_PI_13_DATA + DDRSS3_PI_14_DATA + DDRSS3_PI_15_DATA + DDRSS3_PI_16_DATA + DDRSS3_PI_17_DATA + DDRSS3_PI_18_DATA + DDRSS3_PI_19_DATA + DDRSS3_PI_20_DATA + DDRSS3_PI_21_DATA + DDRSS3_PI_22_DATA + DDRSS3_PI_23_DATA + DDRSS3_PI_24_DATA + DDRSS3_PI_25_DATA + DDRSS3_PI_26_DATA + DDRSS3_PI_27_DATA + DDRSS3_PI_28_DATA + DDRSS3_PI_29_DATA + DDRSS3_PI_30_DATA + DDRSS3_PI_31_DATA + DDRSS3_PI_32_DATA + DDRSS3_PI_33_DATA + DDRSS3_PI_34_DATA + DDRSS3_PI_35_DATA + DDRSS3_PI_36_DATA + DDRSS3_PI_37_DATA + DDRSS3_PI_38_DATA + DDRSS3_PI_39_DATA + DDRSS3_PI_40_DATA + DDRSS3_PI_41_DATA + DDRSS3_PI_42_DATA + DDRSS3_PI_43_DATA + DDRSS3_PI_44_DATA + DDRSS3_PI_45_DATA + DDRSS3_PI_46_DATA + DDRSS3_PI_47_DATA + DDRSS3_PI_48_DATA + DDRSS3_PI_49_DATA + DDRSS3_PI_50_DATA + DDRSS3_PI_51_DATA + DDRSS3_PI_52_DATA + DDRSS3_PI_53_DATA + DDRSS3_PI_54_DATA + DDRSS3_PI_55_DATA + DDRSS3_PI_56_DATA + DDRSS3_PI_57_DATA + DDRSS3_PI_58_DATA + DDRSS3_PI_59_DATA + DDRSS3_PI_60_DATA + DDRSS3_PI_61_DATA + DDRSS3_PI_62_DATA + DDRSS3_PI_63_DATA + DDRSS3_PI_64_DATA + DDRSS3_PI_65_DATA + DDRSS3_PI_66_DATA + DDRSS3_PI_67_DATA + DDRSS3_PI_68_DATA + DDRSS3_PI_69_DATA + DDRSS3_PI_70_DATA + DDRSS3_PI_71_DATA + DDRSS3_PI_72_DATA + DDRSS3_PI_73_DATA + DDRSS3_PI_74_DATA + DDRSS3_PI_75_DATA + DDRSS3_PI_76_DATA + DDRSS3_PI_77_DATA + DDRSS3_PI_78_DATA + DDRSS3_PI_79_DATA + DDRSS3_PI_80_DATA + DDRSS3_PI_81_DATA + DDRSS3_PI_82_DATA + DDRSS3_PI_83_DATA + DDRSS3_PI_84_DATA + DDRSS3_PI_85_DATA + DDRSS3_PI_86_DATA + DDRSS3_PI_87_DATA + DDRSS3_PI_88_DATA + DDRSS3_PI_89_DATA + DDRSS3_PI_90_DATA + DDRSS3_PI_91_DATA + DDRSS3_PI_92_DATA + DDRSS3_PI_93_DATA + DDRSS3_PI_94_DATA + DDRSS3_PI_95_DATA + DDRSS3_PI_96_DATA + DDRSS3_PI_97_DATA + DDRSS3_PI_98_DATA + DDRSS3_PI_99_DATA + DDRSS3_PI_100_DATA + DDRSS3_PI_101_DATA + DDRSS3_PI_102_DATA + DDRSS3_PI_103_DATA + DDRSS3_PI_104_DATA + DDRSS3_PI_105_DATA + DDRSS3_PI_106_DATA + DDRSS3_PI_107_DATA + DDRSS3_PI_108_DATA + DDRSS3_PI_109_DATA + DDRSS3_PI_110_DATA + DDRSS3_PI_111_DATA + DDRSS3_PI_112_DATA + DDRSS3_PI_113_DATA + DDRSS3_PI_114_DATA + DDRSS3_PI_115_DATA + DDRSS3_PI_116_DATA + DDRSS3_PI_117_DATA + DDRSS3_PI_118_DATA + DDRSS3_PI_119_DATA + DDRSS3_PI_120_DATA + DDRSS3_PI_121_DATA + DDRSS3_PI_122_DATA + DDRSS3_PI_123_DATA + DDRSS3_PI_124_DATA + DDRSS3_PI_125_DATA + DDRSS3_PI_126_DATA + DDRSS3_PI_127_DATA + DDRSS3_PI_128_DATA + DDRSS3_PI_129_DATA + DDRSS3_PI_130_DATA + DDRSS3_PI_131_DATA + DDRSS3_PI_132_DATA + DDRSS3_PI_133_DATA + DDRSS3_PI_134_DATA + DDRSS3_PI_135_DATA + DDRSS3_PI_136_DATA + DDRSS3_PI_137_DATA + DDRSS3_PI_138_DATA + DDRSS3_PI_139_DATA + DDRSS3_PI_140_DATA + DDRSS3_PI_141_DATA + DDRSS3_PI_142_DATA + DDRSS3_PI_143_DATA + DDRSS3_PI_144_DATA + DDRSS3_PI_145_DATA + DDRSS3_PI_146_DATA + DDRSS3_PI_147_DATA + DDRSS3_PI_148_DATA + DDRSS3_PI_149_DATA + DDRSS3_PI_150_DATA + DDRSS3_PI_151_DATA + DDRSS3_PI_152_DATA + DDRSS3_PI_153_DATA + DDRSS3_PI_154_DATA + DDRSS3_PI_155_DATA + DDRSS3_PI_156_DATA + DDRSS3_PI_157_DATA + DDRSS3_PI_158_DATA + DDRSS3_PI_159_DATA + DDRSS3_PI_160_DATA + DDRSS3_PI_161_DATA + DDRSS3_PI_162_DATA + DDRSS3_PI_163_DATA + DDRSS3_PI_164_DATA + DDRSS3_PI_165_DATA + DDRSS3_PI_166_DATA + DDRSS3_PI_167_DATA + DDRSS3_PI_168_DATA + DDRSS3_PI_169_DATA + DDRSS3_PI_170_DATA + DDRSS3_PI_171_DATA + DDRSS3_PI_172_DATA + DDRSS3_PI_173_DATA + DDRSS3_PI_174_DATA + DDRSS3_PI_175_DATA + DDRSS3_PI_176_DATA + DDRSS3_PI_177_DATA + DDRSS3_PI_178_DATA + DDRSS3_PI_179_DATA + DDRSS3_PI_180_DATA + DDRSS3_PI_181_DATA + DDRSS3_PI_182_DATA + DDRSS3_PI_183_DATA + DDRSS3_PI_184_DATA + DDRSS3_PI_185_DATA + DDRSS3_PI_186_DATA + DDRSS3_PI_187_DATA + DDRSS3_PI_188_DATA + DDRSS3_PI_189_DATA + DDRSS3_PI_190_DATA + DDRSS3_PI_191_DATA + DDRSS3_PI_192_DATA + DDRSS3_PI_193_DATA + DDRSS3_PI_194_DATA + DDRSS3_PI_195_DATA + DDRSS3_PI_196_DATA + DDRSS3_PI_197_DATA + DDRSS3_PI_198_DATA + DDRSS3_PI_199_DATA + DDRSS3_PI_200_DATA + DDRSS3_PI_201_DATA + DDRSS3_PI_202_DATA + DDRSS3_PI_203_DATA + DDRSS3_PI_204_DATA + DDRSS3_PI_205_DATA + DDRSS3_PI_206_DATA + DDRSS3_PI_207_DATA + DDRSS3_PI_208_DATA + DDRSS3_PI_209_DATA + DDRSS3_PI_210_DATA + DDRSS3_PI_211_DATA + DDRSS3_PI_212_DATA + DDRSS3_PI_213_DATA + DDRSS3_PI_214_DATA + DDRSS3_PI_215_DATA + DDRSS3_PI_216_DATA + DDRSS3_PI_217_DATA + DDRSS3_PI_218_DATA + DDRSS3_PI_219_DATA + DDRSS3_PI_220_DATA + DDRSS3_PI_221_DATA + DDRSS3_PI_222_DATA + DDRSS3_PI_223_DATA + DDRSS3_PI_224_DATA + DDRSS3_PI_225_DATA + DDRSS3_PI_226_DATA + DDRSS3_PI_227_DATA + DDRSS3_PI_228_DATA + DDRSS3_PI_229_DATA + DDRSS3_PI_230_DATA + DDRSS3_PI_231_DATA + DDRSS3_PI_232_DATA + DDRSS3_PI_233_DATA + DDRSS3_PI_234_DATA + DDRSS3_PI_235_DATA + DDRSS3_PI_236_DATA + DDRSS3_PI_237_DATA + DDRSS3_PI_238_DATA + DDRSS3_PI_239_DATA + DDRSS3_PI_240_DATA + DDRSS3_PI_241_DATA + DDRSS3_PI_242_DATA + DDRSS3_PI_243_DATA + DDRSS3_PI_244_DATA + DDRSS3_PI_245_DATA + DDRSS3_PI_246_DATA + DDRSS3_PI_247_DATA + DDRSS3_PI_248_DATA + DDRSS3_PI_249_DATA + DDRSS3_PI_250_DATA + DDRSS3_PI_251_DATA + DDRSS3_PI_252_DATA + DDRSS3_PI_253_DATA + DDRSS3_PI_254_DATA + DDRSS3_PI_255_DATA + DDRSS3_PI_256_DATA + DDRSS3_PI_257_DATA + DDRSS3_PI_258_DATA + DDRSS3_PI_259_DATA + DDRSS3_PI_260_DATA + DDRSS3_PI_261_DATA + DDRSS3_PI_262_DATA + DDRSS3_PI_263_DATA + DDRSS3_PI_264_DATA + DDRSS3_PI_265_DATA + DDRSS3_PI_266_DATA + DDRSS3_PI_267_DATA + DDRSS3_PI_268_DATA + DDRSS3_PI_269_DATA + DDRSS3_PI_270_DATA + DDRSS3_PI_271_DATA + DDRSS3_PI_272_DATA + DDRSS3_PI_273_DATA + DDRSS3_PI_274_DATA + DDRSS3_PI_275_DATA + DDRSS3_PI_276_DATA + DDRSS3_PI_277_DATA + DDRSS3_PI_278_DATA + DDRSS3_PI_279_DATA + DDRSS3_PI_280_DATA + DDRSS3_PI_281_DATA + DDRSS3_PI_282_DATA + DDRSS3_PI_283_DATA + DDRSS3_PI_284_DATA + DDRSS3_PI_285_DATA + DDRSS3_PI_286_DATA + DDRSS3_PI_287_DATA + DDRSS3_PI_288_DATA + DDRSS3_PI_289_DATA + DDRSS3_PI_290_DATA + DDRSS3_PI_291_DATA + DDRSS3_PI_292_DATA + DDRSS3_PI_293_DATA + DDRSS3_PI_294_DATA + DDRSS3_PI_295_DATA + DDRSS3_PI_296_DATA + DDRSS3_PI_297_DATA + DDRSS3_PI_298_DATA + DDRSS3_PI_299_DATA + >; + + ti,phy-data = < + DDRSS3_PHY_00_DATA + DDRSS3_PHY_01_DATA + DDRSS3_PHY_02_DATA + DDRSS3_PHY_03_DATA + DDRSS3_PHY_04_DATA + DDRSS3_PHY_05_DATA + DDRSS3_PHY_06_DATA + DDRSS3_PHY_07_DATA + DDRSS3_PHY_08_DATA + DDRSS3_PHY_09_DATA + DDRSS3_PHY_10_DATA + DDRSS3_PHY_11_DATA + DDRSS3_PHY_12_DATA + DDRSS3_PHY_13_DATA + DDRSS3_PHY_14_DATA + DDRSS3_PHY_15_DATA + DDRSS3_PHY_16_DATA + DDRSS3_PHY_17_DATA + DDRSS3_PHY_18_DATA + DDRSS3_PHY_19_DATA + DDRSS3_PHY_20_DATA + DDRSS3_PHY_21_DATA + DDRSS3_PHY_22_DATA + DDRSS3_PHY_23_DATA + DDRSS3_PHY_24_DATA + DDRSS3_PHY_25_DATA + DDRSS3_PHY_26_DATA + DDRSS3_PHY_27_DATA + DDRSS3_PHY_28_DATA + DDRSS3_PHY_29_DATA + DDRSS3_PHY_30_DATA + DDRSS3_PHY_31_DATA + DDRSS3_PHY_32_DATA + DDRSS3_PHY_33_DATA + DDRSS3_PHY_34_DATA + DDRSS3_PHY_35_DATA + DDRSS3_PHY_36_DATA + DDRSS3_PHY_37_DATA + DDRSS3_PHY_38_DATA + DDRSS3_PHY_39_DATA + DDRSS3_PHY_40_DATA + DDRSS3_PHY_41_DATA + DDRSS3_PHY_42_DATA + DDRSS3_PHY_43_DATA + DDRSS3_PHY_44_DATA + DDRSS3_PHY_45_DATA + DDRSS3_PHY_46_DATA + DDRSS3_PHY_47_DATA + DDRSS3_PHY_48_DATA + DDRSS3_PHY_49_DATA + DDRSS3_PHY_50_DATA + DDRSS3_PHY_51_DATA + DDRSS3_PHY_52_DATA + DDRSS3_PHY_53_DATA + DDRSS3_PHY_54_DATA + DDRSS3_PHY_55_DATA + DDRSS3_PHY_56_DATA + DDRSS3_PHY_57_DATA + DDRSS3_PHY_58_DATA + DDRSS3_PHY_59_DATA + DDRSS3_PHY_60_DATA + DDRSS3_PHY_61_DATA + DDRSS3_PHY_62_DATA + DDRSS3_PHY_63_DATA + DDRSS3_PHY_64_DATA + DDRSS3_PHY_65_DATA + DDRSS3_PHY_66_DATA + DDRSS3_PHY_67_DATA + DDRSS3_PHY_68_DATA + DDRSS3_PHY_69_DATA + DDRSS3_PHY_70_DATA + DDRSS3_PHY_71_DATA + DDRSS3_PHY_72_DATA + DDRSS3_PHY_73_DATA + DDRSS3_PHY_74_DATA + DDRSS3_PHY_75_DATA + DDRSS3_PHY_76_DATA + DDRSS3_PHY_77_DATA + DDRSS3_PHY_78_DATA + DDRSS3_PHY_79_DATA + DDRSS3_PHY_80_DATA + DDRSS3_PHY_81_DATA + DDRSS3_PHY_82_DATA + DDRSS3_PHY_83_DATA + DDRSS3_PHY_84_DATA + DDRSS3_PHY_85_DATA + DDRSS3_PHY_86_DATA + DDRSS3_PHY_87_DATA + DDRSS3_PHY_88_DATA + DDRSS3_PHY_89_DATA + DDRSS3_PHY_90_DATA + DDRSS3_PHY_91_DATA + DDRSS3_PHY_92_DATA + DDRSS3_PHY_93_DATA + DDRSS3_PHY_94_DATA + DDRSS3_PHY_95_DATA + DDRSS3_PHY_96_DATA + DDRSS3_PHY_97_DATA + DDRSS3_PHY_98_DATA + DDRSS3_PHY_99_DATA + DDRSS3_PHY_100_DATA + DDRSS3_PHY_101_DATA + DDRSS3_PHY_102_DATA + DDRSS3_PHY_103_DATA + DDRSS3_PHY_104_DATA + DDRSS3_PHY_105_DATA + DDRSS3_PHY_106_DATA + DDRSS3_PHY_107_DATA + DDRSS3_PHY_108_DATA + DDRSS3_PHY_109_DATA + DDRSS3_PHY_110_DATA + DDRSS3_PHY_111_DATA + DDRSS3_PHY_112_DATA + DDRSS3_PHY_113_DATA + DDRSS3_PHY_114_DATA + DDRSS3_PHY_115_DATA + DDRSS3_PHY_116_DATA + DDRSS3_PHY_117_DATA + DDRSS3_PHY_118_DATA + DDRSS3_PHY_119_DATA + DDRSS3_PHY_120_DATA + DDRSS3_PHY_121_DATA + DDRSS3_PHY_122_DATA + DDRSS3_PHY_123_DATA + DDRSS3_PHY_124_DATA + DDRSS3_PHY_125_DATA + DDRSS3_PHY_126_DATA + DDRSS3_PHY_127_DATA + DDRSS3_PHY_128_DATA + DDRSS3_PHY_129_DATA + DDRSS3_PHY_130_DATA + DDRSS3_PHY_131_DATA + DDRSS3_PHY_132_DATA + DDRSS3_PHY_133_DATA + DDRSS3_PHY_134_DATA + DDRSS3_PHY_135_DATA + DDRSS3_PHY_136_DATA + DDRSS3_PHY_137_DATA + DDRSS3_PHY_138_DATA + DDRSS3_PHY_139_DATA + DDRSS3_PHY_140_DATA + DDRSS3_PHY_141_DATA + DDRSS3_PHY_142_DATA + DDRSS3_PHY_143_DATA + DDRSS3_PHY_144_DATA + DDRSS3_PHY_145_DATA + DDRSS3_PHY_146_DATA + DDRSS3_PHY_147_DATA + DDRSS3_PHY_148_DATA + DDRSS3_PHY_149_DATA + DDRSS3_PHY_150_DATA + DDRSS3_PHY_151_DATA + DDRSS3_PHY_152_DATA + DDRSS3_PHY_153_DATA + DDRSS3_PHY_154_DATA + DDRSS3_PHY_155_DATA + DDRSS3_PHY_156_DATA + DDRSS3_PHY_157_DATA + DDRSS3_PHY_158_DATA + DDRSS3_PHY_159_DATA + DDRSS3_PHY_160_DATA + DDRSS3_PHY_161_DATA + DDRSS3_PHY_162_DATA + DDRSS3_PHY_163_DATA + DDRSS3_PHY_164_DATA + DDRSS3_PHY_165_DATA + DDRSS3_PHY_166_DATA + DDRSS3_PHY_167_DATA + DDRSS3_PHY_168_DATA + DDRSS3_PHY_169_DATA + DDRSS3_PHY_170_DATA + DDRSS3_PHY_171_DATA + DDRSS3_PHY_172_DATA + DDRSS3_PHY_173_DATA + DDRSS3_PHY_174_DATA + DDRSS3_PHY_175_DATA + DDRSS3_PHY_176_DATA + DDRSS3_PHY_177_DATA + DDRSS3_PHY_178_DATA + DDRSS3_PHY_179_DATA + DDRSS3_PHY_180_DATA + DDRSS3_PHY_181_DATA + DDRSS3_PHY_182_DATA + DDRSS3_PHY_183_DATA + DDRSS3_PHY_184_DATA + DDRSS3_PHY_185_DATA + DDRSS3_PHY_186_DATA + DDRSS3_PHY_187_DATA + DDRSS3_PHY_188_DATA + DDRSS3_PHY_189_DATA + DDRSS3_PHY_190_DATA + DDRSS3_PHY_191_DATA + DDRSS3_PHY_192_DATA + DDRSS3_PHY_193_DATA + DDRSS3_PHY_194_DATA + DDRSS3_PHY_195_DATA + DDRSS3_PHY_196_DATA + DDRSS3_PHY_197_DATA + DDRSS3_PHY_198_DATA + DDRSS3_PHY_199_DATA + DDRSS3_PHY_200_DATA + DDRSS3_PHY_201_DATA + DDRSS3_PHY_202_DATA + DDRSS3_PHY_203_DATA + DDRSS3_PHY_204_DATA + DDRSS3_PHY_205_DATA + DDRSS3_PHY_206_DATA + DDRSS3_PHY_207_DATA + DDRSS3_PHY_208_DATA + DDRSS3_PHY_209_DATA + DDRSS3_PHY_210_DATA + DDRSS3_PHY_211_DATA + DDRSS3_PHY_212_DATA + DDRSS3_PHY_213_DATA + DDRSS3_PHY_214_DATA + DDRSS3_PHY_215_DATA + DDRSS3_PHY_216_DATA + DDRSS3_PHY_217_DATA + DDRSS3_PHY_218_DATA + DDRSS3_PHY_219_DATA + DDRSS3_PHY_220_DATA + DDRSS3_PHY_221_DATA + DDRSS3_PHY_222_DATA + DDRSS3_PHY_223_DATA + DDRSS3_PHY_224_DATA + DDRSS3_PHY_225_DATA + DDRSS3_PHY_226_DATA + DDRSS3_PHY_227_DATA + DDRSS3_PHY_228_DATA + DDRSS3_PHY_229_DATA + DDRSS3_PHY_230_DATA + DDRSS3_PHY_231_DATA + DDRSS3_PHY_232_DATA + DDRSS3_PHY_233_DATA + DDRSS3_PHY_234_DATA + DDRSS3_PHY_235_DATA + DDRSS3_PHY_236_DATA + DDRSS3_PHY_237_DATA + DDRSS3_PHY_238_DATA + DDRSS3_PHY_239_DATA + DDRSS3_PHY_240_DATA + DDRSS3_PHY_241_DATA + DDRSS3_PHY_242_DATA + DDRSS3_PHY_243_DATA + DDRSS3_PHY_244_DATA + DDRSS3_PHY_245_DATA + DDRSS3_PHY_246_DATA + DDRSS3_PHY_247_DATA + DDRSS3_PHY_248_DATA + DDRSS3_PHY_249_DATA + DDRSS3_PHY_250_DATA + DDRSS3_PHY_251_DATA + DDRSS3_PHY_252_DATA + DDRSS3_PHY_253_DATA + DDRSS3_PHY_254_DATA + DDRSS3_PHY_255_DATA + DDRSS3_PHY_256_DATA + DDRSS3_PHY_257_DATA + DDRSS3_PHY_258_DATA + DDRSS3_PHY_259_DATA + DDRSS3_PHY_260_DATA + DDRSS3_PHY_261_DATA + DDRSS3_PHY_262_DATA + DDRSS3_PHY_263_DATA + DDRSS3_PHY_264_DATA + DDRSS3_PHY_265_DATA + DDRSS3_PHY_266_DATA + DDRSS3_PHY_267_DATA + DDRSS3_PHY_268_DATA + DDRSS3_PHY_269_DATA + DDRSS3_PHY_270_DATA + DDRSS3_PHY_271_DATA + DDRSS3_PHY_272_DATA + DDRSS3_PHY_273_DATA + DDRSS3_PHY_274_DATA + DDRSS3_PHY_275_DATA + DDRSS3_PHY_276_DATA + DDRSS3_PHY_277_DATA + DDRSS3_PHY_278_DATA + DDRSS3_PHY_279_DATA + DDRSS3_PHY_280_DATA + DDRSS3_PHY_281_DATA + DDRSS3_PHY_282_DATA + DDRSS3_PHY_283_DATA + DDRSS3_PHY_284_DATA + DDRSS3_PHY_285_DATA + DDRSS3_PHY_286_DATA + DDRSS3_PHY_287_DATA + DDRSS3_PHY_288_DATA + DDRSS3_PHY_289_DATA + DDRSS3_PHY_290_DATA + DDRSS3_PHY_291_DATA + DDRSS3_PHY_292_DATA + DDRSS3_PHY_293_DATA + DDRSS3_PHY_294_DATA + DDRSS3_PHY_295_DATA + DDRSS3_PHY_296_DATA + DDRSS3_PHY_297_DATA + DDRSS3_PHY_298_DATA + DDRSS3_PHY_299_DATA + DDRSS3_PHY_300_DATA + DDRSS3_PHY_301_DATA + DDRSS3_PHY_302_DATA + DDRSS3_PHY_303_DATA + DDRSS3_PHY_304_DATA + DDRSS3_PHY_305_DATA + DDRSS3_PHY_306_DATA + DDRSS3_PHY_307_DATA + DDRSS3_PHY_308_DATA + DDRSS3_PHY_309_DATA + DDRSS3_PHY_310_DATA + DDRSS3_PHY_311_DATA + DDRSS3_PHY_312_DATA + DDRSS3_PHY_313_DATA + DDRSS3_PHY_314_DATA + DDRSS3_PHY_315_DATA + DDRSS3_PHY_316_DATA + DDRSS3_PHY_317_DATA + DDRSS3_PHY_318_DATA + DDRSS3_PHY_319_DATA + DDRSS3_PHY_320_DATA + DDRSS3_PHY_321_DATA + DDRSS3_PHY_322_DATA + DDRSS3_PHY_323_DATA + DDRSS3_PHY_324_DATA + DDRSS3_PHY_325_DATA + DDRSS3_PHY_326_DATA + DDRSS3_PHY_327_DATA + DDRSS3_PHY_328_DATA + DDRSS3_PHY_329_DATA + DDRSS3_PHY_330_DATA + DDRSS3_PHY_331_DATA + DDRSS3_PHY_332_DATA + DDRSS3_PHY_333_DATA + DDRSS3_PHY_334_DATA + DDRSS3_PHY_335_DATA + DDRSS3_PHY_336_DATA + DDRSS3_PHY_337_DATA + DDRSS3_PHY_338_DATA + DDRSS3_PHY_339_DATA + DDRSS3_PHY_340_DATA + DDRSS3_PHY_341_DATA + DDRSS3_PHY_342_DATA + DDRSS3_PHY_343_DATA + DDRSS3_PHY_344_DATA + DDRSS3_PHY_345_DATA + DDRSS3_PHY_346_DATA + DDRSS3_PHY_347_DATA + DDRSS3_PHY_348_DATA + DDRSS3_PHY_349_DATA + DDRSS3_PHY_350_DATA + DDRSS3_PHY_351_DATA + DDRSS3_PHY_352_DATA + DDRSS3_PHY_353_DATA + DDRSS3_PHY_354_DATA + DDRSS3_PHY_355_DATA + DDRSS3_PHY_356_DATA + DDRSS3_PHY_357_DATA + DDRSS3_PHY_358_DATA + DDRSS3_PHY_359_DATA + DDRSS3_PHY_360_DATA + DDRSS3_PHY_361_DATA + DDRSS3_PHY_362_DATA + DDRSS3_PHY_363_DATA + DDRSS3_PHY_364_DATA + DDRSS3_PHY_365_DATA + DDRSS3_PHY_366_DATA + DDRSS3_PHY_367_DATA + DDRSS3_PHY_368_DATA + DDRSS3_PHY_369_DATA + DDRSS3_PHY_370_DATA + DDRSS3_PHY_371_DATA + DDRSS3_PHY_372_DATA + DDRSS3_PHY_373_DATA + DDRSS3_PHY_374_DATA + DDRSS3_PHY_375_DATA + DDRSS3_PHY_376_DATA + DDRSS3_PHY_377_DATA + DDRSS3_PHY_378_DATA + DDRSS3_PHY_379_DATA + DDRSS3_PHY_380_DATA + DDRSS3_PHY_381_DATA + DDRSS3_PHY_382_DATA + DDRSS3_PHY_383_DATA + DDRSS3_PHY_384_DATA + DDRSS3_PHY_385_DATA + DDRSS3_PHY_386_DATA + DDRSS3_PHY_387_DATA + DDRSS3_PHY_388_DATA + DDRSS3_PHY_389_DATA + DDRSS3_PHY_390_DATA + DDRSS3_PHY_391_DATA + DDRSS3_PHY_392_DATA + DDRSS3_PHY_393_DATA + DDRSS3_PHY_394_DATA + DDRSS3_PHY_395_DATA + DDRSS3_PHY_396_DATA + DDRSS3_PHY_397_DATA + DDRSS3_PHY_398_DATA + DDRSS3_PHY_399_DATA + DDRSS3_PHY_400_DATA + DDRSS3_PHY_401_DATA + DDRSS3_PHY_402_DATA + DDRSS3_PHY_403_DATA + DDRSS3_PHY_404_DATA + DDRSS3_PHY_405_DATA + DDRSS3_PHY_406_DATA + DDRSS3_PHY_407_DATA + DDRSS3_PHY_408_DATA + DDRSS3_PHY_409_DATA + DDRSS3_PHY_410_DATA + DDRSS3_PHY_411_DATA + DDRSS3_PHY_412_DATA + DDRSS3_PHY_413_DATA + DDRSS3_PHY_414_DATA + DDRSS3_PHY_415_DATA + DDRSS3_PHY_416_DATA + DDRSS3_PHY_417_DATA + DDRSS3_PHY_418_DATA + DDRSS3_PHY_419_DATA + DDRSS3_PHY_420_DATA + DDRSS3_PHY_421_DATA + DDRSS3_PHY_422_DATA + DDRSS3_PHY_423_DATA + DDRSS3_PHY_424_DATA + DDRSS3_PHY_425_DATA + DDRSS3_PHY_426_DATA + DDRSS3_PHY_427_DATA + DDRSS3_PHY_428_DATA + DDRSS3_PHY_429_DATA + DDRSS3_PHY_430_DATA + DDRSS3_PHY_431_DATA + DDRSS3_PHY_432_DATA + DDRSS3_PHY_433_DATA + DDRSS3_PHY_434_DATA + DDRSS3_PHY_435_DATA + DDRSS3_PHY_436_DATA + DDRSS3_PHY_437_DATA + DDRSS3_PHY_438_DATA + DDRSS3_PHY_439_DATA + DDRSS3_PHY_440_DATA + DDRSS3_PHY_441_DATA + DDRSS3_PHY_442_DATA + DDRSS3_PHY_443_DATA + DDRSS3_PHY_444_DATA + DDRSS3_PHY_445_DATA + DDRSS3_PHY_446_DATA + DDRSS3_PHY_447_DATA + DDRSS3_PHY_448_DATA + DDRSS3_PHY_449_DATA + DDRSS3_PHY_450_DATA + DDRSS3_PHY_451_DATA + DDRSS3_PHY_452_DATA + DDRSS3_PHY_453_DATA + DDRSS3_PHY_454_DATA + DDRSS3_PHY_455_DATA + DDRSS3_PHY_456_DATA + DDRSS3_PHY_457_DATA + DDRSS3_PHY_458_DATA + DDRSS3_PHY_459_DATA + DDRSS3_PHY_460_DATA + DDRSS3_PHY_461_DATA + DDRSS3_PHY_462_DATA + DDRSS3_PHY_463_DATA + DDRSS3_PHY_464_DATA + DDRSS3_PHY_465_DATA + DDRSS3_PHY_466_DATA + DDRSS3_PHY_467_DATA + DDRSS3_PHY_468_DATA + DDRSS3_PHY_469_DATA + DDRSS3_PHY_470_DATA + DDRSS3_PHY_471_DATA + DDRSS3_PHY_472_DATA + DDRSS3_PHY_473_DATA + DDRSS3_PHY_474_DATA + DDRSS3_PHY_475_DATA + DDRSS3_PHY_476_DATA + DDRSS3_PHY_477_DATA + DDRSS3_PHY_478_DATA + DDRSS3_PHY_479_DATA + DDRSS3_PHY_480_DATA + DDRSS3_PHY_481_DATA + DDRSS3_PHY_482_DATA + DDRSS3_PHY_483_DATA + DDRSS3_PHY_484_DATA + DDRSS3_PHY_485_DATA + DDRSS3_PHY_486_DATA + DDRSS3_PHY_487_DATA + DDRSS3_PHY_488_DATA + DDRSS3_PHY_489_DATA + DDRSS3_PHY_490_DATA + DDRSS3_PHY_491_DATA + DDRSS3_PHY_492_DATA + DDRSS3_PHY_493_DATA + DDRSS3_PHY_494_DATA + DDRSS3_PHY_495_DATA + DDRSS3_PHY_496_DATA + DDRSS3_PHY_497_DATA + DDRSS3_PHY_498_DATA + DDRSS3_PHY_499_DATA + DDRSS3_PHY_500_DATA + DDRSS3_PHY_501_DATA + DDRSS3_PHY_502_DATA + DDRSS3_PHY_503_DATA + DDRSS3_PHY_504_DATA + DDRSS3_PHY_505_DATA + DDRSS3_PHY_506_DATA + DDRSS3_PHY_507_DATA + DDRSS3_PHY_508_DATA + DDRSS3_PHY_509_DATA + DDRSS3_PHY_510_DATA + DDRSS3_PHY_511_DATA + DDRSS3_PHY_512_DATA + DDRSS3_PHY_513_DATA + DDRSS3_PHY_514_DATA + DDRSS3_PHY_515_DATA + DDRSS3_PHY_516_DATA + DDRSS3_PHY_517_DATA + DDRSS3_PHY_518_DATA + DDRSS3_PHY_519_DATA + DDRSS3_PHY_520_DATA + DDRSS3_PHY_521_DATA + DDRSS3_PHY_522_DATA + DDRSS3_PHY_523_DATA + DDRSS3_PHY_524_DATA + DDRSS3_PHY_525_DATA + DDRSS3_PHY_526_DATA + DDRSS3_PHY_527_DATA + DDRSS3_PHY_528_DATA + DDRSS3_PHY_529_DATA + DDRSS3_PHY_530_DATA + DDRSS3_PHY_531_DATA + DDRSS3_PHY_532_DATA + DDRSS3_PHY_533_DATA + DDRSS3_PHY_534_DATA + DDRSS3_PHY_535_DATA + DDRSS3_PHY_536_DATA + DDRSS3_PHY_537_DATA + DDRSS3_PHY_538_DATA + DDRSS3_PHY_539_DATA + DDRSS3_PHY_540_DATA + DDRSS3_PHY_541_DATA + DDRSS3_PHY_542_DATA + DDRSS3_PHY_543_DATA + DDRSS3_PHY_544_DATA + DDRSS3_PHY_545_DATA + DDRSS3_PHY_546_DATA + DDRSS3_PHY_547_DATA + DDRSS3_PHY_548_DATA + DDRSS3_PHY_549_DATA + DDRSS3_PHY_550_DATA + DDRSS3_PHY_551_DATA + DDRSS3_PHY_552_DATA + DDRSS3_PHY_553_DATA + DDRSS3_PHY_554_DATA + DDRSS3_PHY_555_DATA + DDRSS3_PHY_556_DATA + DDRSS3_PHY_557_DATA + DDRSS3_PHY_558_DATA + DDRSS3_PHY_559_DATA + DDRSS3_PHY_560_DATA + DDRSS3_PHY_561_DATA + DDRSS3_PHY_562_DATA + DDRSS3_PHY_563_DATA + DDRSS3_PHY_564_DATA + DDRSS3_PHY_565_DATA + DDRSS3_PHY_566_DATA + DDRSS3_PHY_567_DATA + DDRSS3_PHY_568_DATA + DDRSS3_PHY_569_DATA + DDRSS3_PHY_570_DATA + DDRSS3_PHY_571_DATA + DDRSS3_PHY_572_DATA + DDRSS3_PHY_573_DATA + DDRSS3_PHY_574_DATA + DDRSS3_PHY_575_DATA + DDRSS3_PHY_576_DATA + DDRSS3_PHY_577_DATA + DDRSS3_PHY_578_DATA + DDRSS3_PHY_579_DATA + DDRSS3_PHY_580_DATA + DDRSS3_PHY_581_DATA + DDRSS3_PHY_582_DATA + DDRSS3_PHY_583_DATA + DDRSS3_PHY_584_DATA + DDRSS3_PHY_585_DATA + DDRSS3_PHY_586_DATA + DDRSS3_PHY_587_DATA + DDRSS3_PHY_588_DATA + DDRSS3_PHY_589_DATA + DDRSS3_PHY_590_DATA + DDRSS3_PHY_591_DATA + DDRSS3_PHY_592_DATA + DDRSS3_PHY_593_DATA + DDRSS3_PHY_594_DATA + DDRSS3_PHY_595_DATA + DDRSS3_PHY_596_DATA + DDRSS3_PHY_597_DATA + DDRSS3_PHY_598_DATA + DDRSS3_PHY_599_DATA + DDRSS3_PHY_600_DATA + DDRSS3_PHY_601_DATA + DDRSS3_PHY_602_DATA + DDRSS3_PHY_603_DATA + DDRSS3_PHY_604_DATA + DDRSS3_PHY_605_DATA + DDRSS3_PHY_606_DATA + DDRSS3_PHY_607_DATA + DDRSS3_PHY_608_DATA + DDRSS3_PHY_609_DATA + DDRSS3_PHY_610_DATA + DDRSS3_PHY_611_DATA + DDRSS3_PHY_612_DATA + DDRSS3_PHY_613_DATA + DDRSS3_PHY_614_DATA + DDRSS3_PHY_615_DATA + DDRSS3_PHY_616_DATA + DDRSS3_PHY_617_DATA + DDRSS3_PHY_618_DATA + DDRSS3_PHY_619_DATA + DDRSS3_PHY_620_DATA + DDRSS3_PHY_621_DATA + DDRSS3_PHY_622_DATA + DDRSS3_PHY_623_DATA + DDRSS3_PHY_624_DATA + DDRSS3_PHY_625_DATA + DDRSS3_PHY_626_DATA + DDRSS3_PHY_627_DATA + DDRSS3_PHY_628_DATA + DDRSS3_PHY_629_DATA + DDRSS3_PHY_630_DATA + DDRSS3_PHY_631_DATA + DDRSS3_PHY_632_DATA + DDRSS3_PHY_633_DATA + DDRSS3_PHY_634_DATA + DDRSS3_PHY_635_DATA + DDRSS3_PHY_636_DATA + DDRSS3_PHY_637_DATA + DDRSS3_PHY_638_DATA + DDRSS3_PHY_639_DATA + DDRSS3_PHY_640_DATA + DDRSS3_PHY_641_DATA + DDRSS3_PHY_642_DATA + DDRSS3_PHY_643_DATA + DDRSS3_PHY_644_DATA + DDRSS3_PHY_645_DATA + DDRSS3_PHY_646_DATA + DDRSS3_PHY_647_DATA + DDRSS3_PHY_648_DATA + DDRSS3_PHY_649_DATA + DDRSS3_PHY_650_DATA + DDRSS3_PHY_651_DATA + DDRSS3_PHY_652_DATA + DDRSS3_PHY_653_DATA + DDRSS3_PHY_654_DATA + DDRSS3_PHY_655_DATA + DDRSS3_PHY_656_DATA + DDRSS3_PHY_657_DATA + DDRSS3_PHY_658_DATA + DDRSS3_PHY_659_DATA + DDRSS3_PHY_660_DATA + DDRSS3_PHY_661_DATA + DDRSS3_PHY_662_DATA + DDRSS3_PHY_663_DATA + DDRSS3_PHY_664_DATA + DDRSS3_PHY_665_DATA + DDRSS3_PHY_666_DATA + DDRSS3_PHY_667_DATA + DDRSS3_PHY_668_DATA + DDRSS3_PHY_669_DATA + DDRSS3_PHY_670_DATA + DDRSS3_PHY_671_DATA + DDRSS3_PHY_672_DATA + DDRSS3_PHY_673_DATA + DDRSS3_PHY_674_DATA + DDRSS3_PHY_675_DATA + DDRSS3_PHY_676_DATA + DDRSS3_PHY_677_DATA + DDRSS3_PHY_678_DATA + DDRSS3_PHY_679_DATA + DDRSS3_PHY_680_DATA + DDRSS3_PHY_681_DATA + DDRSS3_PHY_682_DATA + DDRSS3_PHY_683_DATA + DDRSS3_PHY_684_DATA + DDRSS3_PHY_685_DATA + DDRSS3_PHY_686_DATA + DDRSS3_PHY_687_DATA + DDRSS3_PHY_688_DATA + DDRSS3_PHY_689_DATA + DDRSS3_PHY_690_DATA + DDRSS3_PHY_691_DATA + DDRSS3_PHY_692_DATA + DDRSS3_PHY_693_DATA + DDRSS3_PHY_694_DATA + DDRSS3_PHY_695_DATA + DDRSS3_PHY_696_DATA + DDRSS3_PHY_697_DATA + DDRSS3_PHY_698_DATA + DDRSS3_PHY_699_DATA + DDRSS3_PHY_700_DATA + DDRSS3_PHY_701_DATA + DDRSS3_PHY_702_DATA + DDRSS3_PHY_703_DATA + DDRSS3_PHY_704_DATA + DDRSS3_PHY_705_DATA + DDRSS3_PHY_706_DATA + DDRSS3_PHY_707_DATA + DDRSS3_PHY_708_DATA + DDRSS3_PHY_709_DATA + DDRSS3_PHY_710_DATA + DDRSS3_PHY_711_DATA + DDRSS3_PHY_712_DATA + DDRSS3_PHY_713_DATA + DDRSS3_PHY_714_DATA + DDRSS3_PHY_715_DATA + DDRSS3_PHY_716_DATA + DDRSS3_PHY_717_DATA + DDRSS3_PHY_718_DATA + DDRSS3_PHY_719_DATA + DDRSS3_PHY_720_DATA + DDRSS3_PHY_721_DATA + DDRSS3_PHY_722_DATA + DDRSS3_PHY_723_DATA + DDRSS3_PHY_724_DATA + DDRSS3_PHY_725_DATA + DDRSS3_PHY_726_DATA + DDRSS3_PHY_727_DATA + DDRSS3_PHY_728_DATA + DDRSS3_PHY_729_DATA + DDRSS3_PHY_730_DATA + DDRSS3_PHY_731_DATA + DDRSS3_PHY_732_DATA + DDRSS3_PHY_733_DATA + DDRSS3_PHY_734_DATA + DDRSS3_PHY_735_DATA + DDRSS3_PHY_736_DATA + DDRSS3_PHY_737_DATA + DDRSS3_PHY_738_DATA + DDRSS3_PHY_739_DATA + DDRSS3_PHY_740_DATA + DDRSS3_PHY_741_DATA + DDRSS3_PHY_742_DATA + DDRSS3_PHY_743_DATA + DDRSS3_PHY_744_DATA + DDRSS3_PHY_745_DATA + DDRSS3_PHY_746_DATA + DDRSS3_PHY_747_DATA + DDRSS3_PHY_748_DATA + DDRSS3_PHY_749_DATA + DDRSS3_PHY_750_DATA + DDRSS3_PHY_751_DATA + DDRSS3_PHY_752_DATA + DDRSS3_PHY_753_DATA + DDRSS3_PHY_754_DATA + DDRSS3_PHY_755_DATA + DDRSS3_PHY_756_DATA + DDRSS3_PHY_757_DATA + DDRSS3_PHY_758_DATA + DDRSS3_PHY_759_DATA + DDRSS3_PHY_760_DATA + DDRSS3_PHY_761_DATA + DDRSS3_PHY_762_DATA + DDRSS3_PHY_763_DATA + DDRSS3_PHY_764_DATA + DDRSS3_PHY_765_DATA + DDRSS3_PHY_766_DATA + DDRSS3_PHY_767_DATA + DDRSS3_PHY_768_DATA + DDRSS3_PHY_769_DATA + DDRSS3_PHY_770_DATA + DDRSS3_PHY_771_DATA + DDRSS3_PHY_772_DATA + DDRSS3_PHY_773_DATA + DDRSS3_PHY_774_DATA + DDRSS3_PHY_775_DATA + DDRSS3_PHY_776_DATA + DDRSS3_PHY_777_DATA + DDRSS3_PHY_778_DATA + DDRSS3_PHY_779_DATA + DDRSS3_PHY_780_DATA + DDRSS3_PHY_781_DATA + DDRSS3_PHY_782_DATA + DDRSS3_PHY_783_DATA + DDRSS3_PHY_784_DATA + DDRSS3_PHY_785_DATA + DDRSS3_PHY_786_DATA + DDRSS3_PHY_787_DATA + DDRSS3_PHY_788_DATA + DDRSS3_PHY_789_DATA + DDRSS3_PHY_790_DATA + DDRSS3_PHY_791_DATA + DDRSS3_PHY_792_DATA + DDRSS3_PHY_793_DATA + DDRSS3_PHY_794_DATA + DDRSS3_PHY_795_DATA + DDRSS3_PHY_796_DATA + DDRSS3_PHY_797_DATA + DDRSS3_PHY_798_DATA + DDRSS3_PHY_799_DATA + DDRSS3_PHY_800_DATA + DDRSS3_PHY_801_DATA + DDRSS3_PHY_802_DATA + DDRSS3_PHY_803_DATA + DDRSS3_PHY_804_DATA + DDRSS3_PHY_805_DATA + DDRSS3_PHY_806_DATA + DDRSS3_PHY_807_DATA + DDRSS3_PHY_808_DATA + DDRSS3_PHY_809_DATA + DDRSS3_PHY_810_DATA + DDRSS3_PHY_811_DATA + DDRSS3_PHY_812_DATA + DDRSS3_PHY_813_DATA + DDRSS3_PHY_814_DATA + DDRSS3_PHY_815_DATA + DDRSS3_PHY_816_DATA + DDRSS3_PHY_817_DATA + DDRSS3_PHY_818_DATA + DDRSS3_PHY_819_DATA + DDRSS3_PHY_820_DATA + DDRSS3_PHY_821_DATA + DDRSS3_PHY_822_DATA + DDRSS3_PHY_823_DATA + DDRSS3_PHY_824_DATA + DDRSS3_PHY_825_DATA + DDRSS3_PHY_826_DATA + DDRSS3_PHY_827_DATA + DDRSS3_PHY_828_DATA + DDRSS3_PHY_829_DATA + DDRSS3_PHY_830_DATA + DDRSS3_PHY_831_DATA + DDRSS3_PHY_832_DATA + DDRSS3_PHY_833_DATA + DDRSS3_PHY_834_DATA + DDRSS3_PHY_835_DATA + DDRSS3_PHY_836_DATA + DDRSS3_PHY_837_DATA + DDRSS3_PHY_838_DATA + DDRSS3_PHY_839_DATA + DDRSS3_PHY_840_DATA + DDRSS3_PHY_841_DATA + DDRSS3_PHY_842_DATA + DDRSS3_PHY_843_DATA + DDRSS3_PHY_844_DATA + DDRSS3_PHY_845_DATA + DDRSS3_PHY_846_DATA + DDRSS3_PHY_847_DATA + DDRSS3_PHY_848_DATA + DDRSS3_PHY_849_DATA + DDRSS3_PHY_850_DATA + DDRSS3_PHY_851_DATA + DDRSS3_PHY_852_DATA + DDRSS3_PHY_853_DATA + DDRSS3_PHY_854_DATA + DDRSS3_PHY_855_DATA + DDRSS3_PHY_856_DATA + DDRSS3_PHY_857_DATA + DDRSS3_PHY_858_DATA + DDRSS3_PHY_859_DATA + DDRSS3_PHY_860_DATA + DDRSS3_PHY_861_DATA + DDRSS3_PHY_862_DATA + DDRSS3_PHY_863_DATA + DDRSS3_PHY_864_DATA + DDRSS3_PHY_865_DATA + DDRSS3_PHY_866_DATA + DDRSS3_PHY_867_DATA + DDRSS3_PHY_868_DATA + DDRSS3_PHY_869_DATA + DDRSS3_PHY_870_DATA + DDRSS3_PHY_871_DATA + DDRSS3_PHY_872_DATA + DDRSS3_PHY_873_DATA + DDRSS3_PHY_874_DATA + DDRSS3_PHY_875_DATA + DDRSS3_PHY_876_DATA + DDRSS3_PHY_877_DATA + DDRSS3_PHY_878_DATA + DDRSS3_PHY_879_DATA + DDRSS3_PHY_880_DATA + DDRSS3_PHY_881_DATA + DDRSS3_PHY_882_DATA + DDRSS3_PHY_883_DATA + DDRSS3_PHY_884_DATA + DDRSS3_PHY_885_DATA + DDRSS3_PHY_886_DATA + DDRSS3_PHY_887_DATA + DDRSS3_PHY_888_DATA + DDRSS3_PHY_889_DATA + DDRSS3_PHY_890_DATA + DDRSS3_PHY_891_DATA + DDRSS3_PHY_892_DATA + DDRSS3_PHY_893_DATA + DDRSS3_PHY_894_DATA + DDRSS3_PHY_895_DATA + DDRSS3_PHY_896_DATA + DDRSS3_PHY_897_DATA + DDRSS3_PHY_898_DATA + DDRSS3_PHY_899_DATA + DDRSS3_PHY_900_DATA + DDRSS3_PHY_901_DATA + DDRSS3_PHY_902_DATA + DDRSS3_PHY_903_DATA + DDRSS3_PHY_904_DATA + DDRSS3_PHY_905_DATA + DDRSS3_PHY_906_DATA + DDRSS3_PHY_907_DATA + DDRSS3_PHY_908_DATA + DDRSS3_PHY_909_DATA + DDRSS3_PHY_910_DATA + DDRSS3_PHY_911_DATA + DDRSS3_PHY_912_DATA + DDRSS3_PHY_913_DATA + DDRSS3_PHY_914_DATA + DDRSS3_PHY_915_DATA + DDRSS3_PHY_916_DATA + DDRSS3_PHY_917_DATA + DDRSS3_PHY_918_DATA + DDRSS3_PHY_919_DATA + DDRSS3_PHY_920_DATA + DDRSS3_PHY_921_DATA + DDRSS3_PHY_922_DATA + DDRSS3_PHY_923_DATA + DDRSS3_PHY_924_DATA + DDRSS3_PHY_925_DATA + DDRSS3_PHY_926_DATA + DDRSS3_PHY_927_DATA + DDRSS3_PHY_928_DATA + DDRSS3_PHY_929_DATA + DDRSS3_PHY_930_DATA + DDRSS3_PHY_931_DATA + DDRSS3_PHY_932_DATA + DDRSS3_PHY_933_DATA + DDRSS3_PHY_934_DATA + DDRSS3_PHY_935_DATA + DDRSS3_PHY_936_DATA + DDRSS3_PHY_937_DATA + DDRSS3_PHY_938_DATA + DDRSS3_PHY_939_DATA + DDRSS3_PHY_940_DATA + DDRSS3_PHY_941_DATA + DDRSS3_PHY_942_DATA + DDRSS3_PHY_943_DATA + DDRSS3_PHY_944_DATA + DDRSS3_PHY_945_DATA + DDRSS3_PHY_946_DATA + DDRSS3_PHY_947_DATA + DDRSS3_PHY_948_DATA + DDRSS3_PHY_949_DATA + DDRSS3_PHY_950_DATA + DDRSS3_PHY_951_DATA + DDRSS3_PHY_952_DATA + DDRSS3_PHY_953_DATA + DDRSS3_PHY_954_DATA + DDRSS3_PHY_955_DATA + DDRSS3_PHY_956_DATA + DDRSS3_PHY_957_DATA + DDRSS3_PHY_958_DATA + DDRSS3_PHY_959_DATA + DDRSS3_PHY_960_DATA + DDRSS3_PHY_961_DATA + DDRSS3_PHY_962_DATA + DDRSS3_PHY_963_DATA + DDRSS3_PHY_964_DATA + DDRSS3_PHY_965_DATA + DDRSS3_PHY_966_DATA + DDRSS3_PHY_967_DATA + DDRSS3_PHY_968_DATA + DDRSS3_PHY_969_DATA + DDRSS3_PHY_970_DATA + DDRSS3_PHY_971_DATA + DDRSS3_PHY_972_DATA + DDRSS3_PHY_973_DATA + DDRSS3_PHY_974_DATA + DDRSS3_PHY_975_DATA + DDRSS3_PHY_976_DATA + DDRSS3_PHY_977_DATA + DDRSS3_PHY_978_DATA + DDRSS3_PHY_979_DATA + DDRSS3_PHY_980_DATA + DDRSS3_PHY_981_DATA + DDRSS3_PHY_982_DATA + DDRSS3_PHY_983_DATA + DDRSS3_PHY_984_DATA + DDRSS3_PHY_985_DATA + DDRSS3_PHY_986_DATA + DDRSS3_PHY_987_DATA + DDRSS3_PHY_988_DATA + DDRSS3_PHY_989_DATA + DDRSS3_PHY_990_DATA + DDRSS3_PHY_991_DATA + DDRSS3_PHY_992_DATA + DDRSS3_PHY_993_DATA + DDRSS3_PHY_994_DATA + DDRSS3_PHY_995_DATA + DDRSS3_PHY_996_DATA + DDRSS3_PHY_997_DATA + DDRSS3_PHY_998_DATA + DDRSS3_PHY_999_DATA + DDRSS3_PHY_1000_DATA + DDRSS3_PHY_1001_DATA + DDRSS3_PHY_1002_DATA + DDRSS3_PHY_1003_DATA + DDRSS3_PHY_1004_DATA + DDRSS3_PHY_1005_DATA + DDRSS3_PHY_1006_DATA + DDRSS3_PHY_1007_DATA + DDRSS3_PHY_1008_DATA + DDRSS3_PHY_1009_DATA + DDRSS3_PHY_1010_DATA + DDRSS3_PHY_1011_DATA + DDRSS3_PHY_1012_DATA + DDRSS3_PHY_1013_DATA + DDRSS3_PHY_1014_DATA + DDRSS3_PHY_1015_DATA + DDRSS3_PHY_1016_DATA + DDRSS3_PHY_1017_DATA + DDRSS3_PHY_1018_DATA + DDRSS3_PHY_1019_DATA + DDRSS3_PHY_1020_DATA + DDRSS3_PHY_1021_DATA + DDRSS3_PHY_1022_DATA + DDRSS3_PHY_1023_DATA + DDRSS3_PHY_1024_DATA + DDRSS3_PHY_1025_DATA + DDRSS3_PHY_1026_DATA + DDRSS3_PHY_1027_DATA + DDRSS3_PHY_1028_DATA + DDRSS3_PHY_1029_DATA + DDRSS3_PHY_1030_DATA + DDRSS3_PHY_1031_DATA + DDRSS3_PHY_1032_DATA + DDRSS3_PHY_1033_DATA + DDRSS3_PHY_1034_DATA + DDRSS3_PHY_1035_DATA + DDRSS3_PHY_1036_DATA + DDRSS3_PHY_1037_DATA + DDRSS3_PHY_1038_DATA + DDRSS3_PHY_1039_DATA + DDRSS3_PHY_1040_DATA + DDRSS3_PHY_1041_DATA + DDRSS3_PHY_1042_DATA + DDRSS3_PHY_1043_DATA + DDRSS3_PHY_1044_DATA + DDRSS3_PHY_1045_DATA + DDRSS3_PHY_1046_DATA + DDRSS3_PHY_1047_DATA + DDRSS3_PHY_1048_DATA + DDRSS3_PHY_1049_DATA + DDRSS3_PHY_1050_DATA + DDRSS3_PHY_1051_DATA + DDRSS3_PHY_1052_DATA + DDRSS3_PHY_1053_DATA + DDRSS3_PHY_1054_DATA + DDRSS3_PHY_1055_DATA + DDRSS3_PHY_1056_DATA + DDRSS3_PHY_1057_DATA + DDRSS3_PHY_1058_DATA + DDRSS3_PHY_1059_DATA + DDRSS3_PHY_1060_DATA + DDRSS3_PHY_1061_DATA + DDRSS3_PHY_1062_DATA + DDRSS3_PHY_1063_DATA + DDRSS3_PHY_1064_DATA + DDRSS3_PHY_1065_DATA + DDRSS3_PHY_1066_DATA + DDRSS3_PHY_1067_DATA + DDRSS3_PHY_1068_DATA + DDRSS3_PHY_1069_DATA + DDRSS3_PHY_1070_DATA + DDRSS3_PHY_1071_DATA + DDRSS3_PHY_1072_DATA + DDRSS3_PHY_1073_DATA + DDRSS3_PHY_1074_DATA + DDRSS3_PHY_1075_DATA + DDRSS3_PHY_1076_DATA + DDRSS3_PHY_1077_DATA + DDRSS3_PHY_1078_DATA + DDRSS3_PHY_1079_DATA + DDRSS3_PHY_1080_DATA + DDRSS3_PHY_1081_DATA + DDRSS3_PHY_1082_DATA + DDRSS3_PHY_1083_DATA + DDRSS3_PHY_1084_DATA + DDRSS3_PHY_1085_DATA + DDRSS3_PHY_1086_DATA + DDRSS3_PHY_1087_DATA + DDRSS3_PHY_1088_DATA + DDRSS3_PHY_1089_DATA + DDRSS3_PHY_1090_DATA + DDRSS3_PHY_1091_DATA + DDRSS3_PHY_1092_DATA + DDRSS3_PHY_1093_DATA + DDRSS3_PHY_1094_DATA + DDRSS3_PHY_1095_DATA + DDRSS3_PHY_1096_DATA + DDRSS3_PHY_1097_DATA + DDRSS3_PHY_1098_DATA + DDRSS3_PHY_1099_DATA + DDRSS3_PHY_1100_DATA + DDRSS3_PHY_1101_DATA + DDRSS3_PHY_1102_DATA + DDRSS3_PHY_1103_DATA + DDRSS3_PHY_1104_DATA + DDRSS3_PHY_1105_DATA + DDRSS3_PHY_1106_DATA + DDRSS3_PHY_1107_DATA + DDRSS3_PHY_1108_DATA + DDRSS3_PHY_1109_DATA + DDRSS3_PHY_1110_DATA + DDRSS3_PHY_1111_DATA + DDRSS3_PHY_1112_DATA + DDRSS3_PHY_1113_DATA + DDRSS3_PHY_1114_DATA + DDRSS3_PHY_1115_DATA + DDRSS3_PHY_1116_DATA + DDRSS3_PHY_1117_DATA + DDRSS3_PHY_1118_DATA + DDRSS3_PHY_1119_DATA + DDRSS3_PHY_1120_DATA + DDRSS3_PHY_1121_DATA + DDRSS3_PHY_1122_DATA + DDRSS3_PHY_1123_DATA + DDRSS3_PHY_1124_DATA + DDRSS3_PHY_1125_DATA + DDRSS3_PHY_1126_DATA + DDRSS3_PHY_1127_DATA + DDRSS3_PHY_1128_DATA + DDRSS3_PHY_1129_DATA + DDRSS3_PHY_1130_DATA + DDRSS3_PHY_1131_DATA + DDRSS3_PHY_1132_DATA + DDRSS3_PHY_1133_DATA + DDRSS3_PHY_1134_DATA + DDRSS3_PHY_1135_DATA + DDRSS3_PHY_1136_DATA + DDRSS3_PHY_1137_DATA + DDRSS3_PHY_1138_DATA + DDRSS3_PHY_1139_DATA + DDRSS3_PHY_1140_DATA + DDRSS3_PHY_1141_DATA + DDRSS3_PHY_1142_DATA + DDRSS3_PHY_1143_DATA + DDRSS3_PHY_1144_DATA + DDRSS3_PHY_1145_DATA + DDRSS3_PHY_1146_DATA + DDRSS3_PHY_1147_DATA + DDRSS3_PHY_1148_DATA + DDRSS3_PHY_1149_DATA + DDRSS3_PHY_1150_DATA + DDRSS3_PHY_1151_DATA + DDRSS3_PHY_1152_DATA + DDRSS3_PHY_1153_DATA + DDRSS3_PHY_1154_DATA + DDRSS3_PHY_1155_DATA + DDRSS3_PHY_1156_DATA + DDRSS3_PHY_1157_DATA + DDRSS3_PHY_1158_DATA + DDRSS3_PHY_1159_DATA + DDRSS3_PHY_1160_DATA + DDRSS3_PHY_1161_DATA + DDRSS3_PHY_1162_DATA + DDRSS3_PHY_1163_DATA + DDRSS3_PHY_1164_DATA + DDRSS3_PHY_1165_DATA + DDRSS3_PHY_1166_DATA + DDRSS3_PHY_1167_DATA + DDRSS3_PHY_1168_DATA + DDRSS3_PHY_1169_DATA + DDRSS3_PHY_1170_DATA + DDRSS3_PHY_1171_DATA + DDRSS3_PHY_1172_DATA + DDRSS3_PHY_1173_DATA + DDRSS3_PHY_1174_DATA + DDRSS3_PHY_1175_DATA + DDRSS3_PHY_1176_DATA + DDRSS3_PHY_1177_DATA + DDRSS3_PHY_1178_DATA + DDRSS3_PHY_1179_DATA + DDRSS3_PHY_1180_DATA + DDRSS3_PHY_1181_DATA + DDRSS3_PHY_1182_DATA + DDRSS3_PHY_1183_DATA + DDRSS3_PHY_1184_DATA + DDRSS3_PHY_1185_DATA + DDRSS3_PHY_1186_DATA + DDRSS3_PHY_1187_DATA + DDRSS3_PHY_1188_DATA + DDRSS3_PHY_1189_DATA + DDRSS3_PHY_1190_DATA + DDRSS3_PHY_1191_DATA + DDRSS3_PHY_1192_DATA + DDRSS3_PHY_1193_DATA + DDRSS3_PHY_1194_DATA + DDRSS3_PHY_1195_DATA + DDRSS3_PHY_1196_DATA + DDRSS3_PHY_1197_DATA + DDRSS3_PHY_1198_DATA + DDRSS3_PHY_1199_DATA + DDRSS3_PHY_1200_DATA + DDRSS3_PHY_1201_DATA + DDRSS3_PHY_1202_DATA + DDRSS3_PHY_1203_DATA + DDRSS3_PHY_1204_DATA + DDRSS3_PHY_1205_DATA + DDRSS3_PHY_1206_DATA + DDRSS3_PHY_1207_DATA + DDRSS3_PHY_1208_DATA + DDRSS3_PHY_1209_DATA + DDRSS3_PHY_1210_DATA + DDRSS3_PHY_1211_DATA + DDRSS3_PHY_1212_DATA + DDRSS3_PHY_1213_DATA + DDRSS3_PHY_1214_DATA + DDRSS3_PHY_1215_DATA + DDRSS3_PHY_1216_DATA + DDRSS3_PHY_1217_DATA + DDRSS3_PHY_1218_DATA + DDRSS3_PHY_1219_DATA + DDRSS3_PHY_1220_DATA + DDRSS3_PHY_1221_DATA + DDRSS3_PHY_1222_DATA + DDRSS3_PHY_1223_DATA + DDRSS3_PHY_1224_DATA + DDRSS3_PHY_1225_DATA + DDRSS3_PHY_1226_DATA + DDRSS3_PHY_1227_DATA + DDRSS3_PHY_1228_DATA + DDRSS3_PHY_1229_DATA + DDRSS3_PHY_1230_DATA + DDRSS3_PHY_1231_DATA + DDRSS3_PHY_1232_DATA + DDRSS3_PHY_1233_DATA + DDRSS3_PHY_1234_DATA + DDRSS3_PHY_1235_DATA + DDRSS3_PHY_1236_DATA + DDRSS3_PHY_1237_DATA + DDRSS3_PHY_1238_DATA + DDRSS3_PHY_1239_DATA + DDRSS3_PHY_1240_DATA + DDRSS3_PHY_1241_DATA + DDRSS3_PHY_1242_DATA + DDRSS3_PHY_1243_DATA + DDRSS3_PHY_1244_DATA + DDRSS3_PHY_1245_DATA + DDRSS3_PHY_1246_DATA + DDRSS3_PHY_1247_DATA + DDRSS3_PHY_1248_DATA + DDRSS3_PHY_1249_DATA + DDRSS3_PHY_1250_DATA + DDRSS3_PHY_1251_DATA + DDRSS3_PHY_1252_DATA + DDRSS3_PHY_1253_DATA + DDRSS3_PHY_1254_DATA + DDRSS3_PHY_1255_DATA + DDRSS3_PHY_1256_DATA + DDRSS3_PHY_1257_DATA + DDRSS3_PHY_1258_DATA + DDRSS3_PHY_1259_DATA + DDRSS3_PHY_1260_DATA + DDRSS3_PHY_1261_DATA + DDRSS3_PHY_1262_DATA + DDRSS3_PHY_1263_DATA + DDRSS3_PHY_1264_DATA + DDRSS3_PHY_1265_DATA + DDRSS3_PHY_1266_DATA + DDRSS3_PHY_1267_DATA + DDRSS3_PHY_1268_DATA + DDRSS3_PHY_1269_DATA + DDRSS3_PHY_1270_DATA + DDRSS3_PHY_1271_DATA + DDRSS3_PHY_1272_DATA + DDRSS3_PHY_1273_DATA + DDRSS3_PHY_1274_DATA + DDRSS3_PHY_1275_DATA + DDRSS3_PHY_1276_DATA + DDRSS3_PHY_1277_DATA + DDRSS3_PHY_1278_DATA + DDRSS3_PHY_1279_DATA + DDRSS3_PHY_1280_DATA + DDRSS3_PHY_1281_DATA + DDRSS3_PHY_1282_DATA + DDRSS3_PHY_1283_DATA + DDRSS3_PHY_1284_DATA + DDRSS3_PHY_1285_DATA + DDRSS3_PHY_1286_DATA + DDRSS3_PHY_1287_DATA + DDRSS3_PHY_1288_DATA + DDRSS3_PHY_1289_DATA + DDRSS3_PHY_1290_DATA + DDRSS3_PHY_1291_DATA + DDRSS3_PHY_1292_DATA + DDRSS3_PHY_1293_DATA + DDRSS3_PHY_1294_DATA + DDRSS3_PHY_1295_DATA + DDRSS3_PHY_1296_DATA + DDRSS3_PHY_1297_DATA + DDRSS3_PHY_1298_DATA + DDRSS3_PHY_1299_DATA + DDRSS3_PHY_1300_DATA + DDRSS3_PHY_1301_DATA + DDRSS3_PHY_1302_DATA + DDRSS3_PHY_1303_DATA + DDRSS3_PHY_1304_DATA + DDRSS3_PHY_1305_DATA + DDRSS3_PHY_1306_DATA + DDRSS3_PHY_1307_DATA + DDRSS3_PHY_1308_DATA + DDRSS3_PHY_1309_DATA + DDRSS3_PHY_1310_DATA + DDRSS3_PHY_1311_DATA + DDRSS3_PHY_1312_DATA + DDRSS3_PHY_1313_DATA + DDRSS3_PHY_1314_DATA + DDRSS3_PHY_1315_DATA + DDRSS3_PHY_1316_DATA + DDRSS3_PHY_1317_DATA + DDRSS3_PHY_1318_DATA + DDRSS3_PHY_1319_DATA + DDRSS3_PHY_1320_DATA + DDRSS3_PHY_1321_DATA + DDRSS3_PHY_1322_DATA + DDRSS3_PHY_1323_DATA + DDRSS3_PHY_1324_DATA + DDRSS3_PHY_1325_DATA + DDRSS3_PHY_1326_DATA + DDRSS3_PHY_1327_DATA + DDRSS3_PHY_1328_DATA + DDRSS3_PHY_1329_DATA + DDRSS3_PHY_1330_DATA + DDRSS3_PHY_1331_DATA + DDRSS3_PHY_1332_DATA + DDRSS3_PHY_1333_DATA + DDRSS3_PHY_1334_DATA + DDRSS3_PHY_1335_DATA + DDRSS3_PHY_1336_DATA + DDRSS3_PHY_1337_DATA + DDRSS3_PHY_1338_DATA + DDRSS3_PHY_1339_DATA + DDRSS3_PHY_1340_DATA + DDRSS3_PHY_1341_DATA + DDRSS3_PHY_1342_DATA + DDRSS3_PHY_1343_DATA + DDRSS3_PHY_1344_DATA + DDRSS3_PHY_1345_DATA + DDRSS3_PHY_1346_DATA + DDRSS3_PHY_1347_DATA + DDRSS3_PHY_1348_DATA + DDRSS3_PHY_1349_DATA + DDRSS3_PHY_1350_DATA + DDRSS3_PHY_1351_DATA + DDRSS3_PHY_1352_DATA + DDRSS3_PHY_1353_DATA + DDRSS3_PHY_1354_DATA + DDRSS3_PHY_1355_DATA + DDRSS3_PHY_1356_DATA + DDRSS3_PHY_1357_DATA + DDRSS3_PHY_1358_DATA + DDRSS3_PHY_1359_DATA + DDRSS3_PHY_1360_DATA + DDRSS3_PHY_1361_DATA + DDRSS3_PHY_1362_DATA + DDRSS3_PHY_1363_DATA + DDRSS3_PHY_1364_DATA + DDRSS3_PHY_1365_DATA + DDRSS3_PHY_1366_DATA + DDRSS3_PHY_1367_DATA + DDRSS3_PHY_1368_DATA + DDRSS3_PHY_1369_DATA + DDRSS3_PHY_1370_DATA + DDRSS3_PHY_1371_DATA + DDRSS3_PHY_1372_DATA + DDRSS3_PHY_1373_DATA + DDRSS3_PHY_1374_DATA + DDRSS3_PHY_1375_DATA + DDRSS3_PHY_1376_DATA + DDRSS3_PHY_1377_DATA + DDRSS3_PHY_1378_DATA + DDRSS3_PHY_1379_DATA + DDRSS3_PHY_1380_DATA + DDRSS3_PHY_1381_DATA + DDRSS3_PHY_1382_DATA + DDRSS3_PHY_1383_DATA + DDRSS3_PHY_1384_DATA + DDRSS3_PHY_1385_DATA + DDRSS3_PHY_1386_DATA + DDRSS3_PHY_1387_DATA + DDRSS3_PHY_1388_DATA + DDRSS3_PHY_1389_DATA + DDRSS3_PHY_1390_DATA + DDRSS3_PHY_1391_DATA + DDRSS3_PHY_1392_DATA + DDRSS3_PHY_1393_DATA + DDRSS3_PHY_1394_DATA + DDRSS3_PHY_1395_DATA + DDRSS3_PHY_1396_DATA + DDRSS3_PHY_1397_DATA + DDRSS3_PHY_1398_DATA + DDRSS3_PHY_1399_DATA + DDRSS3_PHY_1400_DATA + DDRSS3_PHY_1401_DATA + DDRSS3_PHY_1402_DATA + DDRSS3_PHY_1403_DATA + DDRSS3_PHY_1404_DATA + DDRSS3_PHY_1405_DATA + DDRSS3_PHY_1406_DATA + DDRSS3_PHY_1407_DATA + DDRSS3_PHY_1408_DATA + DDRSS3_PHY_1409_DATA + DDRSS3_PHY_1410_DATA + DDRSS3_PHY_1411_DATA + DDRSS3_PHY_1412_DATA + DDRSS3_PHY_1413_DATA + DDRSS3_PHY_1414_DATA + DDRSS3_PHY_1415_DATA + DDRSS3_PHY_1416_DATA + DDRSS3_PHY_1417_DATA + DDRSS3_PHY_1418_DATA + DDRSS3_PHY_1419_DATA + DDRSS3_PHY_1420_DATA + DDRSS3_PHY_1421_DATA + DDRSS3_PHY_1422_DATA + >; + }; + }; +}; diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi new file mode 100644 index 00000000000..8f0307321e8 --- /dev/null +++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-j784s4-binman.dtsi" + +/ { + memory@80000000 { + bootph-all; + }; +}; + +&mcu_udmap { + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x284c0000 0x0 0x4000>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x284a0000 0x0 0x4000>, + <0x0 0x2aa00000 0x0 0x40000>, + <0x0 0x28400000 0x0 0x2000>; + reg-names = "gcfg", "rchan", "rchanrt", "tchan", + "tchanrt", "rflow"; + bootph-pre-ram; +}; diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts new file mode 100644 index 00000000000..bef4573d3d2 --- /dev/null +++ b/arch/arm/dts/k3-j784s4-r5-evm.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-j784s4-evm.dts" +#include "k3-j784s4-ddr-evm-lp4-4266.dtsi" +#include "k3-j784s4-ddr.dtsi" +#include "k3-j784s4-evm-u-boot.dtsi" + +/ { + chosen { + tick-timer = &mcu_timer0; + }; + + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a72_0; + }; + + a72_0: a72@0 { + compatible = "ti,am654-rproc"; + reg = <0x0 0x00a90000 0x0 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 202 0>; + clocks = <&k3_clks 61 0>; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 202 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <2000000000>; + ti,sci = <&sms>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-pre-ram; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_mcu 21>, <&secure_proxy_mcu 23>; + bootph-pre-ram; + }; +}; + +&mcu_timer0 { + status = "okay"; + clock-frequency = <250000000>; + bootph-pre-ram; +}; + +&secure_proxy_sa3 { + status = "okay"; + bootph-pre-ram; +}; + +&secure_proxy_mcu { + status = "okay"; + bootph-pre-ram; +}; + +&cbass_mcu_wakeup { + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_mcu 4>, + <&secure_proxy_mcu 5>, + <&secure_proxy_sa3 5>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-pre-ram; + }; +}; + +&sms { + mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; + mbox-names = "tx", "rx", "notify"; + ti,host-id = <4>; + ti,secure-host; + bootph-pre-ram; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + bootph-pre-ram; + status = "okay"; +}; + +&ospi0 { + reg = <0x0 0x47040000 0x0 0x100>, + <0x0 0x50000000 0x0 0x8000000>; +}; + +&ospi1 { + reg = <0x0 0x47050000 0x0 0x100>, + <0x0 0x58000000 0x0 0x8000000>; +}; + +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; diff --git a/arch/arm/dts/kirkwood-6192.dtsi b/arch/arm/dts/kirkwood-6192.dtsi deleted file mode 100644 index 396bcba08ad..00000000000 --- a/arch/arm/dts/kirkwood-6192.dtsi +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - mbus@f1000000 { - pciec: pcie@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - }; - }; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - compatible = "marvell,88f6192-pinctrl"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp5", "mpp21", "mpp23"; - marvell,function = "sata0"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp4", "mpp20", "mpp22"; - marvell,function = "sata1"; - }; - pmx_sdio: pmx-sdio { - marvell,pins = "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "sdio"; - }; - }; - - rtc: rtc@10300 { - compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <53>; - clocks = <&gate_clk 7>; - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - clocks = <&gate_clk 14>, <&gate_clk 15>; - clock-names = "0", "1"; - phys = <&sata_phy0>, <&sata_phy1>; - phy-names = "port0", "port1"; - status = "disabled"; - }; - - sdio: mvsdio@90000 { - compatible = "marvell,orion-sdio"; - reg = <0x90000 0x200>; - interrupts = <28>; - clocks = <&gate_clk 4>; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/kirkwood-6281.dtsi b/arch/arm/dts/kirkwood-6281.dtsi deleted file mode 100644 index faa05849a40..00000000000 --- a/arch/arm/dts/kirkwood-6281.dtsi +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - mbus@f1000000 { - pciec: pcie@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - }; - }; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - compatible = "marvell,88f6281-pinctrl"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp5", "mpp21", "mpp23"; - marvell,function = "sata0"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp4", "mpp20", "mpp22"; - marvell,function = "sata1"; - }; - pmx_sdio: pmx-sdio { - marvell,pins = "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "sdio"; - }; - }; - - rtc: rtc@10300 { - compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <53>; - clocks = <&gate_clk 7>; - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - clocks = <&gate_clk 14>, <&gate_clk 15>; - clock-names = "0", "1"; - phys = <&sata_phy0>, <&sata_phy1>; - phy-names = "port0", "port1"; - status = "disabled"; - }; - - sdio: mvsdio@90000 { - compatible = "marvell,orion-sdio"; - reg = <0x90000 0x200>; - interrupts = <28>; - clocks = <&gate_clk 4>; - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/kirkwood-6282.dtsi b/arch/arm/dts/kirkwood-6282.dtsi deleted file mode 100644 index e732c501ea8..00000000000 --- a/arch/arm/dts/kirkwood-6282.dtsi +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - mbus@f1000000 { - pciec: pcie@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-names = "intx", "error"; - interrupts = <9>, <44>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie0_intc 0>, - <0 0 0 2 &pcie0_intc 1>, - <0 0 0 3 &pcie0_intc 2>, - <0 0 0 4 &pcie0_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - - pcie0_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie1: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-names = "intx", "error"; - interrupts = <10>, <45>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 18>; - status = "disabled"; - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - }; - ocp@f1000000 { - - pinctrl: pin-controller@10000 { - compatible = "marvell,88f6282-pinctrl"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp5", "mpp21", "mpp23"; - marvell,function = "sata0"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp4", "mpp20", "mpp22"; - marvell,function = "sata1"; - }; - - /* - * Default I2C1 pinctrl setting on mpp36/mpp37, - * overwrite marvell,pins on board level if required. - */ - pmx_twsi1: pmx-twsi1 { - marvell,pins = "mpp36", "mpp37"; - marvell,function = "twsi1"; - }; - - pmx_sdio: pmx-sdio { - marvell,pins = "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "sdio"; - }; - }; - - thermal: thermal@10078 { - compatible = "marvell,kirkwood-thermal"; - reg = <0x10078 0x4>; - status = "okay"; - }; - - rtc: rtc@10300 { - compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <53>; - clocks = <&gate_clk 7>; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <32>; - clock-frequency = <100000>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_twsi1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - clocks = <&gate_clk 14>, <&gate_clk 15>; - clock-names = "0", "1"; - phys = <&sata_phy0>, <&sata_phy1>; - phy-names = "port0", "port1"; - status = "disabled"; - }; - - sdio: mvsdio@90000 { - compatible = "marvell,orion-sdio"; - reg = <0x90000 0x200>; - interrupts = <28>; - clocks = <&gate_clk 4>; - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/kirkwood-98dx4122.dtsi b/arch/arm/dts/kirkwood-98dx4122.dtsi deleted file mode 100644 index 299c147298c..00000000000 --- a/arch/arm/dts/kirkwood-98dx4122.dtsi +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - mbus@f1000000 { - pciec: pcie@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - }; - }; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - compatible = "marvell,98dx4122-pinctrl"; - - }; - }; -}; - -&sata_phy0 { - status = "disabled"; -}; - -&sata_phy1 { - status = "disabled"; -}; diff --git a/arch/arm/dts/kirkwood-blackarmor-nas220.dts b/arch/arm/dts/kirkwood-blackarmor-nas220.dts deleted file mode 100644 index 07fbfca444d..00000000000 --- a/arch/arm/dts/kirkwood-blackarmor-nas220.dts +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for Seagate Blackarmor NAS220 - * - * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com> - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include "kirkwood.dtsi" -#include "kirkwood-6192.dtsi" - -/ { - model = "Seagate Blackarmor NAS220"; - compatible = "seagate,blackarmor-nas220","marvell,kirkwood-88f6192", - "marvell,kirkwood"; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - }; - - gpio_keys { - compatible = "gpio-keys"; - - reset { - label = "Reset"; - linux,code = <KEY_POWER>; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - - button { - label = "Power"; - linux,code = <KEY_SLEEP>; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue-power { - label = "nas220:blue:power"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; - pinctrl-names = "default"; - - sata0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - }; -}; - -/* - * Serial port routed to connector CN5 - * - * pin 1 - TX (CPU's TX) - * pin 4 - RX (CPU's RX) - * pin 6 - GND - */ -&uart0 { - status = "okay"; -}; - -&pinctrl { - pinctrl-0 = <&pmx_button_reset &pmx_button_power>; - pinctrl-names = "default"; - - pmx_act_sata0: pmx-act-sata0 { - marvell,pins = "mpp15"; - marvell,function = "sata0"; - }; - - pmx_act_sata1: pmx-act-sata1 { - marvell,pins = "mpp16"; - marvell,function = "sata1"; - }; - - pmx_power_sata0: pmx-power-sata0 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - pmx_power_sata1: pmx-power-sata1 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_button_power: pmx-button-power { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; -}; - -&sata { - status = "okay"; - nr-ports = <2>; -}; - -&i2c0 { - status = "okay"; - - adt7476: thermal@2e { - compatible = "adi,adt7476"; - reg = <0x2e>; - }; -}; - -&nand { - status = "okay"; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-d2net.dts b/arch/arm/dts/kirkwood-d2net.dts deleted file mode 100644 index bd3b266dd76..00000000000 --- a/arch/arm/dts/kirkwood-d2net.dts +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for d2 Network v2 - * - * Copyright (C) 2014 Simon Guinot <simon.guinot@sequanux.org> - * -*/ - -/dts-v1/; - -#include <dt-bindings/leds/leds-ns2.h> -#include "kirkwood-netxbig.dtsi" - -/ { - model = "LaCie d2 Network v2"; - compatible = "lacie,d2net_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "d2net_v2:blue:sata"; - slow-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - cmd-gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - modes-map = <NS_V2_LED_OFF 1 0 - NS_V2_LED_ON 0 1 - NS_V2_LED_ON 1 1 - NS_V2_LED_SATA 0 0>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-fail { - label = "d2net_v2:red:fail"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/arch/arm/dts/kirkwood-dns325.dts b/arch/arm/dts/kirkwood-dns325.dts deleted file mode 100644 index 94d9c06cbbf..00000000000 --- a/arch/arm/dts/kirkwood-dns325.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-dnskw.dtsi" - -/ { - model = "D-Link DNS-325 NAS (Rev A1)"; - compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325 - &pmx_led_red_left_hdd &pmx_led_red_right_hdd - &pmx_led_white_usb>; - pinctrl-names = "default"; - - white-power { - label = "dns325:white:power"; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - white-usb { - label = "dns325:white:usb"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO 43 */ - }; - red-l_hdd { - label = "dns325:red:l_hdd"; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - red-r_hdd { - label = "dns325:red:r_hdd"; - gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - }; - red-usb { - label = "dns325:red:usb"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - ocp@f1000000 { - i2c@11000 { - status = "okay"; - - lm75: lm75@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - }; - serial@12000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/dts/kirkwood-dnskw.dtsi b/arch/arm/dts/kirkwood-dnskw.dtsi deleted file mode 100644 index cbaf06f2f78..00000000000 --- a/arch/arm/dts/kirkwood-dnskw.dtsi +++ /dev/null @@ -1,235 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "D-Link DNS NASes (kirkwood-based)"; - compatible = "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_power &pmx_button_unmount - &pmx_button_reset>; - pinctrl-names = "default"; - - power { - label = "Power button"; - linux,code = <KEY_POWER>; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - eject { - label = "USB unmount button"; - linux,code = <KEY_EJECTCD>; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset button"; - linux,code = <KEY_RESTART>; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_fan { - /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */ - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>; - pinctrl-names = "default"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW - &gpio1 13 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = <0 0 - 3000 1 - 6000 2>; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_power_off>; - pinctrl-names = "default"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0 - &pmx_present_sata1 &pmx_fan_tacho - &pmx_temp_alarm>; - pinctrl-names = "default"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp20"; - marvell,function = "sata1"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp21"; - marvell,function = "sata0"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - pmx_led_red_right_hdd: pmx-led-red-right-hdd { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - pmx_led_red_left_hdd: pmx-led-red-left-hdd { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_led_red_usb_325: pmx-led-red-usb-325 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_button_power: pmx-button-power { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_led_red_usb_320: pmx-led-red-usb-320 { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - pmx_power_off: pmx-power-off { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_power_back_on: pmx-power-back-on { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_power_sata0: pmx-power-sata0 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_power_sata1: pmx-power-sata1 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_present_sata0: pmx-present-sata0 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_present_sata1: pmx-present-sata1 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_white_usb: pmx-led-white-usb { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_fan_tacho: pmx-fan-tacho { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_fan_high_speed: pmx-fan-high-speed { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_fan_low_speed: pmx-fan-low-speed { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_button_unmount: pmx-button-unmount { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_temp_alarm: pmx-temp-alarm { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - sata@80000 { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; - pinctrl-names = "default"; - - sata0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 7 0>; - }; - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 8 0>; - }; - }; -}; - -&nand { - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x500000>; - }; - - partition@600000 { - label = "ramdisk"; - reg = <0x0600000 0x500000>; - }; - - partition@b00000 { - label = "image"; - reg = <0x0b00000 0x6600000>; - }; - - partition@7100000 { - label = "mini firmware"; - reg = <0x7100000 0xa00000>; - }; - - partition@7b00000 { - label = "config"; - reg = <0x7b00000 0x500000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-dockstar.dts b/arch/arm/dts/kirkwood-dockstar.dts deleted file mode 100644 index 6a3f1bf6d9f..00000000000 --- a/arch/arm/dts/kirkwood-dockstar.dts +++ /dev/null @@ -1,110 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Seagate FreeAgent Dockstar"; - compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_led_green: pmx-led-green { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_orange: pmx-led-orange { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "ok"; - }; - }; - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_green &pmx_led_orange>; - pinctrl-names = "default"; - - health { - label = "status:green:health"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - fault { - label = "status:orange:fault"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 0>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "data"; - reg = <0x0500000 0xfb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - compatible = "marvell,88e1116"; - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-dreamplug-u-boot.dtsi b/arch/arm/dts/kirkwood-dreamplug-u-boot.dtsi new file mode 100644 index 00000000000..59f19a211fa --- /dev/null +++ b/arch/arm/dts/kirkwood-dreamplug-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/arch/arm/dts/kirkwood-dreamplug.dts b/arch/arm/dts/kirkwood-dreamplug.dts deleted file mode 100644 index e9eea22fc93..00000000000 --- a/arch/arm/dts/kirkwood-dreamplug.dts +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Globalscale Technologies Dreamplug"; - compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - aliases { - spi0 = &spi0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_bluetooth: pmx-led-bluetooth { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_wifi: pmx-led-wifi { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_led_wifi_ap: pmx-led-wifi-ap { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "ok"; - }; - - spi@10600 { - status = "okay"; - - m25p40@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - - partition@100000 { - reg = <0x100000 0x10000>; - label = "u-boot env"; - }; - - partition@180000 { - reg = <0x180000 0x10000>; - label = "dtb"; - }; - }; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_bluetooth &pmx_led_wifi - &pmx_led_wifi_ap >; - pinctrl-names = "default"; - - bluetooth { - label = "dreamplug:blue:bluetooth"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - wifi { - label = "dreamplug:green:wifi"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - wifi-ap { - label = "dreamplug:green:wifi_ap"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/dts/kirkwood-ds109.dts b/arch/arm/dts/kirkwood-ds109.dts deleted file mode 100644 index 29982e7acb7..00000000000 --- a/arch/arm/dts/kirkwood-ds109.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn <andrew@lunn.ch> - * Ben Peddell <klightspeed@killerwolves.net> - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS109, DS110, DS110jv20"; - compatible = "synology,ds109", "synology,ds110jv20", - "synology,ds110", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-21-1 { - status = "okay"; - }; -}; - -&rs5c372 { - status = "okay"; -}; diff --git a/arch/arm/dts/kirkwood-goflexnet.dts b/arch/arm/dts/kirkwood-goflexnet.dts deleted file mode 100644 index 02d87e0a106..00000000000 --- a/arch/arm/dts/kirkwood-goflexnet.dts +++ /dev/null @@ -1,190 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Seagate GoFlex Net"; - compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_0: pmx-led_right_cap_0 { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_1: pmx-led_right_cap_1 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_2: pmx-led_right_cap_2 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_3: pmx-led_right_cap_3 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_0: pmx-led_left_cap_0 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_1: pmx-led_left_cap_1 { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_2: pmx-led_left_cap_2 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_3: pmx-led_left_cap_3 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_led_green: pmx-led_green { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_orange: pmx-led_orange { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "ok"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - }; - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_orange - &pmx_led_left_cap_0 &pmx_led_left_cap_1 - &pmx_led_left_cap_2 &pmx_led_left_cap_3 - &pmx_led_right_cap_0 &pmx_led_right_cap_1 - &pmx_led_right_cap_2 &pmx_led_right_cap_3 - >; - pinctrl-names = "default"; - - health { - label = "status:green:health"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - fault { - label = "status:orange:fault"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - left0 { - label = "status:white:left0"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - left1 { - label = "status:white:left1"; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - left2 { - label = "status:white:left2"; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - left3 { - label = "status:white:left3"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - right0 { - label = "status:white:right0"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - right1 { - label = "status:white:right1"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - right2 { - label = "status:white:right2"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - right3 { - label = "status:white:right3"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - chip-delay = <40>; - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "pogoplug"; - reg = <0x0500000 0x2000000>; - }; - - partition@2500000 { - label = "root"; - reg = <0x02500000 0xd800000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/dts/kirkwood-guruplug-server-plus.dts deleted file mode 100644 index ff1260ee3fe..00000000000 --- a/arch/arm/dts/kirkwood-guruplug-server-plus.dts +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Globalscale Technologies Guruplug Server Plus"; - compatible = "globalscale,guruplug-server-plus", "globalscale,guruplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_health_r: pmx-led-health-r { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_health_g: pmx-led-health-g { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_wmode_r: pmx-led-wmode-r { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_led_wmode_g: pmx-led-wmode-g { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "ok"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - /* AzureWave AW-GH381 WiFi/BT */ - mvsdio@90000 { - status = "okay"; - non-removable; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g - &pmx_led_wmode_r &pmx_led_wmode_g >; - pinctrl-names = "default"; - - health-r { - label = "guruplug:red:health"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - health-g { - label = "guruplug:green:health"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - wmode-r { - label = "guruplug:red:wmode"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - wmode-g { - label = "guruplug:green:wmode"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x00100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x00100000 0x00400000>; - }; - - partition@500000 { - label = "data"; - reg = <0x00500000 0x1fb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - /* Marvell 88E1121R */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - /* Marvell 88E1121R */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - phy-connection-type = "rgmii-id"; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - phy-connection-type = "rgmii-id"; - }; -}; diff --git a/arch/arm/dts/kirkwood-ib62x0.dts b/arch/arm/dts/kirkwood-ib62x0.dts deleted file mode 100644 index 962a910a6f5..00000000000 --- a/arch/arm/dts/kirkwood-ib62x0.dts +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; - compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_os_red: pmx-led-os-red { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - pmx_power_off: pmx-power-off { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - pmx_led_os_green: pmx-led-os-green { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - pmx_led_usb_transfer: pmx-led-usb-transfer { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_button_usb_copy: pmx-button-usb-copy { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>; - pinctrl-names = "default"; - - copy { - label = "USB Copy"; - linux,code = <KEY_COPY>; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset"; - linux,code = <KEY_RESTART>; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green - &pmx_led_usb_transfer>; - pinctrl-names = "default"; - - green-os { - label = "ib62x0:green:os"; - gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - red-os { - label = "ib62x0:red:os"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; - }; - usb-copy { - label = "ib62x0:red:usb_copy"; - gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_power_off>; - pinctrl-names = "default"; - gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0xe0000>; - }; - - partition@e0000 { - label = "u-boot environment"; - reg = <0xe0000 0x20000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x600000>; - }; - - partition@700000 { - label = "root"; - reg = <0x0700000 0xf900000>; - }; - -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-iconnect.dts b/arch/arm/dts/kirkwood-iconnect.dts deleted file mode 100644 index 4a512d80912..00000000000 --- a/arch/arm/dts/kirkwood-iconnect.dts +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Iomega Iconnect"; - compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - linux,initrd-start = <0x4500040>; - linux,initrd-end = <0x4800000>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - pmx_button_otb: pmx-button-otb { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - pmx_led_level: pmx-led-level { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_led_power_blue: pmx-led-power-blue { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_power_red: pmx-power-red { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_usb1: pmx-led-usb1 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_led_usb2: pmx-led-usb2 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_led_usb3: pmx-led-usb3 { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_usb4: pmx-led-usb4 { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_otb: pmx-led-otb { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - }; - i2c@11000 { - status = "okay"; - - lm63: lm63@4c { - compatible = "national,lm63"; - reg = <0x4c>; - }; - }; - serial@12000 { - status = "ok"; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_level &pmx_led_power_blue - &pmx_led_power_red &pmx_led_usb1 - &pmx_led_usb2 &pmx_led_usb3 - &pmx_led_usb4 &pmx_led_otb >; - pinctrl-names = "default"; - - led-level { - label = "led_level"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - power-blue { - label = "power:blue"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - power-red { - label = "power:red"; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - usb1 { - label = "usb1:blue"; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - usb2 { - label = "usb2:blue"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - usb3 { - label = "usb3:blue"; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - usb4 { - label = "usb4:blue"; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - otb { - label = "otb:blue"; - gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = < &pmx_button_reset &pmx_button_otb >; - pinctrl-names = "default"; - - otb { - label = "OTB Button"; - linux,code = <KEY_COPY>; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - reset { - label = "Reset"; - linux,code = <KEY_RESTART>; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0xc0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0xa0000 0x20000>; - }; - - partition@100000 { - label = "zImage"; - reg = <0x100000 0x300000>; - }; - - partition@540000 { - label = "initrd"; - reg = <0x540000 0x300000>; - }; - - partition@980000 { - label = "boot"; - reg = <0x980000 0x1f400000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@11 { - reg = <11>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/dts/kirkwood-is2.dts b/arch/arm/dts/kirkwood-is2.dts deleted file mode 100644 index 1bc16a5cdba..00000000000 --- a/arch/arm/dts/kirkwood-is2.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include <dt-bindings/leds/leds-ns2.h> -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Internet Space v2"; - compatible = "lacie,inetspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = <NS_V2_LED_OFF 1 0 - NS_V2_LED_ON 0 1 - NS_V2_LED_ON 1 1 - NS_V2_LED_SATA 0 0>; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi b/arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi index 7fc2d7d3b41..cf33ff822ee 100644 --- a/arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi +++ b/arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi @@ -1,7 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ -ð0 { - status = "disabled"; +/ { + aliases { + spi0 = &spi0; + }; }; &hdd_power { diff --git a/arch/arm/dts/kirkwood-lschlv2.dts b/arch/arm/dts/kirkwood-lschlv2.dts deleted file mode 100644 index 1d737d903f5..00000000000 --- a/arch/arm/dts/kirkwood-lschlv2.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-lsxl.dtsi" - -/ { - model = "Buffalo Linkstation LS-CHLv2"; - compatible = "buffalo,lschlv2", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/dts/kirkwood-lsxhl-u-boot.dtsi b/arch/arm/dts/kirkwood-lsxhl-u-boot.dtsi index 7fc2d7d3b41..cf33ff822ee 100644 --- a/arch/arm/dts/kirkwood-lsxhl-u-boot.dtsi +++ b/arch/arm/dts/kirkwood-lsxhl-u-boot.dtsi @@ -1,7 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ -ð0 { - status = "disabled"; +/ { + aliases { + spi0 = &spi0; + }; }; &hdd_power { diff --git a/arch/arm/dts/kirkwood-lsxhl.dts b/arch/arm/dts/kirkwood-lsxhl.dts deleted file mode 100644 index a56e0d79777..00000000000 --- a/arch/arm/dts/kirkwood-lsxhl.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-lsxl.dtsi" - -/ { - model = "Buffalo Linkstation LS-XHL"; - compatible = "buffalo,lsxhl", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/dts/kirkwood-lsxl.dtsi b/arch/arm/dts/kirkwood-lsxl.dtsi deleted file mode 100644 index c99c0da0937..00000000000 --- a/arch/arm/dts/kirkwood-lsxl.dtsi +++ /dev/null @@ -1,241 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - aliases { - spi0 = &spi0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd: pmx-power-hdd { - marvell,pins = "mpp10"; - marvell,function = "gpo"; - }; - pmx_usb_vbus: pmx-usb-vbus { - marvell,pins = "mpp11"; - marvell,function = "gpio"; - }; - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp18"; - marvell,function = "gpo"; - }; - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp19"; - marvell,function = "gpo"; - }; - pmx_led_function_blue: pmx-led-function-blue { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_led_alarm: pmx-led-alarm { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_led_info: pmx-led-info { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_button_function: pmx-button-function { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_power_auto_switch: pmx-power-auto-switch { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_function_red: pmx-led-function_red { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - }; - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - spi@10600 { - status = "okay"; - - m25p40@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p40", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x60000>; - label = "uboot"; - read-only; - }; - - partition@60000 { - reg = <0x60000 0x10000>; - label = "dtb"; - read-only; - }; - - partition@70000 { - reg = <0x70000 0x10000>; - label = "uboot_env"; - }; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_function &pmx_power_switch - &pmx_power_auto_switch>; - pinctrl-names = "default"; - - option { - label = "Function Button"; - linux,code = <KEY_OPTION>; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - reserved { - label = "Power-on Switch"; - linux,code = <KEY_RESERVED>; - linux,input-type = <5>; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - power { - label = "Power-auto Switch"; - linux,code = <KEY_ESC>; - linux,input-type = <5>; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue>; - pinctrl-names = "default"; - - func_blue { - label = "lsxl:blue:func"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - alarm { - label = "lsxl:red:alarm"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - - info { - label = "lsxl:amber:info"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - power { - label = "lsxl:blue:power"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - func_red { - label = "lsxl:red:func"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; - pinctrl-names = "default"; - gpios = <&gpio0 19 GPIO_ACTIVE_LOW - &gpio0 18 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = <0 3 - 1500 2 - 3250 1 - 5000 0>; - alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - - restart_poweroff { - compatible = "restart-poweroff"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_hdd &pmx_usb_vbus>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 11 0>; - }; - hdd_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "HDD Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 10 0>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/dts/kirkwood-net2big.dts b/arch/arm/dts/kirkwood-net2big.dts deleted file mode 100644 index 3e3ac289e5b..00000000000 --- a/arch/arm/dts/kirkwood-net2big.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for LaCie 2Big Network v2 - * - * Copyright (C) 2014 - * - * Andrew Lunn <andrew@lunn.ch> - * - * Based on netxbig_v2-setup.c, - * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com> - * -*/ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-netxbig.dtsi" - -/ { - model = "LaCie 2Big Network v2"; - compatible = "lacie,net2big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - fan { - compatible = "gpio-fan"; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; -}; - -®ulators { - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; -}; - -&i2c0 { - g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; - }; -}; diff --git a/arch/arm/dts/kirkwood-netxbig.dtsi b/arch/arm/dts/kirkwood-netxbig.dtsi deleted file mode 100644 index b5737026e24..00000000000 --- a/arch/arm/dts/kirkwood-netxbig.dtsi +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree common file for LaCie 2Big and 5Big Network v2 - * - * Copyright (C) 2014 - * - * Andrew Lunn <andrew@lunn.ch> - * - * Based on netxbig_v2-setup.c, - * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com> - * -*/ - -#include <dt-bindings/leds/leds-netxbig.h> -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - }; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - /* - * esc and power represent a three position rocker - * switch. Thus the conventional KEY_POWER does not fit - */ - exc { - label = "Back power switch (on|auto)"; - linux,code = <KEY_ESC>; - linux,input-type = <5>; - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - power { - label = "Back power switch (auto|off)"; - linux,code = <KEY_1>; - linux,input-type = <5>; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - option { - label = "Function button"; - linux,code = <KEY_OPTION>; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - }; - - regulators: regulators { - status = "okay"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd0power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; - }; - }; - - netxbig_gpio_ext: netxbig-gpio-ext { - compatible = "lacie,netxbig-gpio-ext"; - - addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH - &gpio1 16 GPIO_ACTIVE_HIGH - &gpio1 17 GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH - &gpio1 13 GPIO_ACTIVE_HIGH - &gpio1 14 GPIO_ACTIVE_HIGH>; - enable-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - - netxbig-leds { - compatible = "lacie,netxbig-leds"; - - gpio-ext = <&netxbig_gpio_ext>; - - timers = <NETXBIG_LED_TIMER1 500 500 - NETXBIG_LED_TIMER2 500 1000>; - - blue-power { - label = "netxbig:blue:power"; - mode-addr = <0>; - mode-val = <NETXBIG_LED_OFF 0 - NETXBIG_LED_ON 1 - NETXBIG_LED_TIMER1 3 - NETXBIG_LED_TIMER2 7>; - bright-addr = <1>; - max-brightness = <7>; - }; - red-power { - label = "netxbig:red:power"; - mode-addr = <0>; - mode-val = <NETXBIG_LED_OFF 0 - NETXBIG_LED_ON 2 - NETXBIG_LED_TIMER1 4>; - bright-addr = <1>; - max-brightness = <7>; - }; - blue-sata0 { - label = "netxbig:blue:sata0"; - mode-addr = <3>; - mode-val = <NETXBIG_LED_OFF 0 - NETXBIG_LED_ON 7 - NETXBIG_LED_SATA 1 - NETXBIG_LED_TIMER1 3>; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata0 { - label = "netxbig:red:sata0"; - mode-addr = <3>; - mode-val = <NETXBIG_LED_OFF 0 - NETXBIG_LED_ON 2 - NETXBIG_LED_TIMER1 4>; - bright-addr = <2>; - max-brightness = <7>; - }; - blue-sata1 { - label = "netxbig:blue:sata1"; - mode-addr = <4>; - mode-val = <NETXBIG_LED_OFF 0 - NETXBIG_LED_ON 7 - NETXBIG_LED_SATA 1 - NETXBIG_LED_TIMER1 3>; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata1 { - label = "netxbig:red:sata1"; - mode-addr = <4>; - mode-val = <NETXBIG_LED_OFF 0 - NETXBIG_LED_ON 2 - NETXBIG_LED_TIMER1 4>; - bright-addr = <2>; - max-brightness = <7>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <8>; - }; - - ethphy1: ethernet-phy@1 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - - pmx_button_function: pmx-button-function { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_button_power_off: pmx-button-power-off { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - pmx_button_power_on: pmx-button-power-on { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; -}; - -&i2c0 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x50>; - }; -}; diff --git a/arch/arm/dts/kirkwood-ns2-common.dtsi b/arch/arm/dts/kirkwood-ns2-common.dtsi deleted file mode 100644 index 51530ea8662..00000000000 --- a/arch/arm/dts/kirkwood-ns2-common.dtsi +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_ns2_sata0: pmx-ns2-sata0 { - marvell,pins = "mpp21"; - marvell,function = "sata0"; - }; - pmx_ns2_sata1: pmx-ns2-sata1 { - marvell,pins = "mpp20"; - marvell,function = "sata1"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - }; - }; - - i2c@11000 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x50>; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - power { - label = "Power push button"; - linux,code = <KEY_POWER>; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-fail { - label = "ns2:red:fail"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@X { - /* overwrite reg property in board file */ - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-ns2.dts b/arch/arm/dts/kirkwood-ns2.dts deleted file mode 100644 index 7b67083e1ec..00000000000 --- a/arch/arm/dts/kirkwood-ns2.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include <dt-bindings/leds/leds-ns2.h> -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Network Space v2"; - compatible = "lacie,netspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = <NS_V2_LED_OFF 1 0 - NS_V2_LED_ON 0 1 - NS_V2_LED_ON 1 1 - NS_V2_LED_SATA 0 0>; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/arch/arm/dts/kirkwood-ns2lite.dts b/arch/arm/dts/kirkwood-ns2lite.dts deleted file mode 100644 index b0cb5907ed6..00000000000 --- a/arch/arm/dts/kirkwood-ns2lite.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Network Space Lite v2"; - compatible = "lacie,netspace_lite_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue-sata { - label = "ns2:blue:sata"; - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - linux,default-trigger = "disk-activity"; - }; - }; -}; - -ðphy0 { reg = <0>; }; diff --git a/arch/arm/dts/kirkwood-ns2max.dts b/arch/arm/dts/kirkwood-ns2max.dts deleted file mode 100644 index c0a087e7740..00000000000 --- a/arch/arm/dts/kirkwood-ns2max.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include <dt-bindings/leds/leds-ns2.h> -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Network Space Max v2"; - compatible = "lacie,netspace_max_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0 &pmx_ns2_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW - &gpio0 7 GPIO_ACTIVE_LOW - &gpio1 1 GPIO_ACTIVE_LOW - &gpio0 23 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = - < 0 0 - 1500 15 - 1700 14 - 1800 13 - 2100 12 - 3100 11 - 3300 10 - 4300 9 - 5500 8>; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = <NS_V2_LED_OFF 1 0 - NS_V2_LED_ON 0 1 - NS_V2_LED_ON 1 1 - NS_V2_LED_SATA 0 0>; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/arch/arm/dts/kirkwood-ns2mini.dts b/arch/arm/dts/kirkwood-ns2mini.dts deleted file mode 100644 index 5b9fa14b642..00000000000 --- a/arch/arm/dts/kirkwood-ns2mini.dts +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include <dt-bindings/leds/leds-ns2.h> -#include "kirkwood-ns2-common.dtsi" - -/ { - /* This machine is embedded in the first LaCie CloudBox product. */ - model = "LaCie Network Space Mini v2"; - compatible = "lacie,netspace_mini_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW - &gpio0 7 GPIO_ACTIVE_LOW - &gpio1 1 GPIO_ACTIVE_LOW - &gpio0 23 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = - < 0 0 - 3000 15 - 3180 14 - 4140 13 - 4570 12 - 6760 11 - 7140 10 - 7980 9 - 9200 8>; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = <NS_V2_LED_OFF 1 0 - NS_V2_LED_ON 0 1 - NS_V2_LED_ON 1 1 - NS_V2_LED_SATA 0 0>; - }; - }; -}; - -ðphy0 { reg = <0>; }; diff --git a/arch/arm/dts/kirkwood-nsa310s.dts b/arch/arm/dts/kirkwood-nsa310s.dts deleted file mode 100644 index 09ee76c2a2e..00000000000 --- a/arch/arm/dts/kirkwood-nsa310s.dts +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree file for the Zyxel NSA 310S NAS box. - * - * Copyright (c) 2015-2021, Tony Dinh <mibodhi@gmail.com> - * - * Based on - * Copyright (c) 2014, Adam Baker <linux@baker-net.org.uk> - * Based upon the board setup file created by Peter Schildmann - */ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Zyxel NSA310S"; - compatible = "zyxel,nsa320s", "marvell,kirkwood-88f6702", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - pmx_sata0: pmx-sata0 { - marvell,pins ; - marvell,function = "sata0"; - }; - - pmx_sata1: pmx-sata1 { - marvell,pins ; - marvell,function = "sata1"; - }; - - pmx_usb_power: pmx-usb-power { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_pwr_off: pmx-pwr-off { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - pmx_btn_reset: pmx-btn-reset { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - pmx_btn_copy: pmx-btn-copy { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - - pmx_btn_power: pmx-btn-power { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - - pmx_led_hdd2_green: pmx-led-hdd2-green { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - pmx_led_hdd2_red: pmx-led-hdd2-red { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_led_usb_green: pmx-led-usb-green { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_led_copy_green: pmx-led-copy-green { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_led_copy_red: pmx-led-copy-red { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - pmx_led_sys_green: pmx-led-sys-green { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_led_sys_orange: pmx-led-sys-orange { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_green: pmx-led-hdd1-green { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_red: pmx-led-hdd1-red { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_pwr_sata1: pmx-pwr-sata1 { - marvell,pins = "mpp33"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "ok"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - rtc@10300 { - status = "disabled"; - }; - - i2c@11000 { - status = "okay"; - ht1382: rtc@68 { - compatible = "htk,ht1382"; - reg = <0x68>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pmx_usb_power &pmx_pwr_sata1>; - - usb0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; - }; - - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_pwr_off>; - pinctrl-names = "default"; - gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; - pinctrl-names = "default"; - - button@1 { - label = "Power Button"; - linux,code = <KEY_POWER>; - gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - }; - button@2 { - label = "Copy Button"; - linux,code = <KEY_COPY>; - gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - button@3 { - label = "Reset Button"; - linux,code = <KEY_RESTART>; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red - &pmx_led_usb_green - &pmx_led_sys_green &pmx_led_sys_orange - &pmx_led_copy_green &pmx_led_copy_red - &pmx_led_hdd1_green &pmx_led_hdd1_red>; - pinctrl-names = "default"; - - green-sys { - label = "nsa310s:green:sys"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - orange-sys { - label = "nsa310s:orange:sys"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - green-hdd1 { - label = "nsa310s:green:hdd1"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - }; - red-hdd1 { - label = "nsa310s:red:hdd1"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - green-hdd2 { - label = "nsa310s:green:hdd2"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - red-hdd2 { - label = "nsa310s:red:hdd2"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - green-usb { - label = "nsa310s:green:usb"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - green-copy { - label = "nsa310s:green:copy"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "ide-disk"; - }; - red-copy { - label = "nsa310s:red:copy"; - gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x0100000>; - }; - partition@100000 { - label = "stock_uboot_env"; - reg = <0x0100000 0x0080000>; - }; - partition@180000 { - label = "key_store"; - reg = <0x0180000 0x0080000>; - }; - partition@200000 { - label = "info"; - reg = <0x0200000 0x0080000>; - }; - partition@280000 { - label = "etc"; - reg = <0x0280000 0x0a00000>; - }; - partition@c80000 { - label = "kernel_1"; - reg = <0x0c80000 0x0a00000>; - }; - partition@1680000 { - label = "rootfs1"; - reg = <0x1680000 0x2fc0000>; - }; - partition@4640000 { - label = "kernel_2"; - reg = <0x4640000 0x0a00000>; - }; - partition@5040000 { - label = "rootfs2"; - reg = <0x5040000 0x2fc0000>; - }; -}; - -&mdio { - status = "okay"; - ethphy0: ethernet-phy@1 { - compatible = "marvell,88e1510"; - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii"; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/dts/kirkwood-nsa325-u-boot.dtsi b/arch/arm/dts/kirkwood-nsa325-u-boot.dtsi new file mode 100644 index 00000000000..dec27b2a87a --- /dev/null +++ b/arch/arm/dts/kirkwood-nsa325-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&nand { + partition@0 { + /delete-property/ read-only; + }; +}; diff --git a/arch/arm/dts/kirkwood-nsa325.dts b/arch/arm/dts/kirkwood-nsa325.dts deleted file mode 100644 index efc57cfa41e..00000000000 --- a/arch/arm/dts/kirkwood-nsa325.dts +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Device tree file for the Zyxel NSA 325 NAS box. - * - * Copyright (c) 2015, Hans Ulli Kroll <ulli.kroll@googlemail.com> - * - * - * Based upon the board setup file created by Peter Schildmann - */ - -/dts-v1/; - -#include "kirkwood-nsa3x0-common.dtsi" - -/ { - model = "ZyXEL NSA325"; - compatible = "zyxel,nsa325", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - pmx_led_hdd2_green: pmx-led-hdd2-green { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_led_hdd2_red: pmx-led-hdd2-red { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_mcu_data: pmx-mcu-data { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_led_usb_green: pmx-led-usb-green { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_mcu_clk: pmx-mcu-clk { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_mcu_act: pmx-mcu-act { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_led_sys_green: pmx-led-sys-green { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_led_sys_orange: pmx-led-sys-orange { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_green: pmx-led-hdd1-green { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_red: pmx-led-hdd1-red { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_htp: pmx-htp { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - /* - * Buzzer needs to be switched at around 1kHz so is - * not compatible with the gpio-beeper driver. - */ - pmx_buzzer: pmx-buzzer { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_vid_b1: pmx-vid-b1 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_power_resume_data: pmx-power-resume-data { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - pmx_power_resume_clk: pmx-power-resume-clk { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - - pmx_pwr_sata1: pmx-pwr-sata1 { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - - /* This board uses the pcf8563 RTC instead of the SoC RTC */ - rtc@10300 { - status = "disabled"; - }; - - i2c@11000 { - status = "okay"; - - pcf8563: pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_pwr_sata1>; - pinctrl-names = "default"; - - usb0_power: regulator@1 { - enable-active-high; - }; - - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red - &pmx_led_usb_green - &pmx_led_sys_green &pmx_led_sys_orange - &pmx_led_copy_green &pmx_led_copy_red - &pmx_led_hdd1_green &pmx_led_hdd1_red>; - pinctrl-names = "default"; - - green-sys { - label = "nsa325:green:sys"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - orange-sys { - label = "nsa325:orange:sys"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - green-hdd1 { - label = "nsa325:green:hdd1"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - red-hdd1 { - label = "nsa325:red:hdd1"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - green-hdd2 { - label = "nsa325:green:hdd2"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - red-hdd2 { - label = "nsa325:red:hdd2"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - green-usb { - label = "nsa325:green:usb"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - green-copy { - label = "nsa325:green:copy"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - red-copy { - label = "nsa325:red:copy"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - - /* The following pins are currently not assigned to a driver, - some of them should be configured as inputs. - pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act - &pmx_htp &pmx_vid_b1 - &pmx_power_resume_data &pmx_power_resume_clk>; */ - }; - -}; - -&mdio { - status = "okay"; - ethphy0: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/dts/kirkwood-nsa3x0-common.dtsi b/arch/arm/dts/kirkwood-nsa3x0-common.dtsi deleted file mode 100644 index a21c50d44a4..00000000000 --- a/arch/arm/dts/kirkwood-nsa3x0-common.dtsi +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "ZyXEL NSA310"; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pmx_usb_power: pmx-usb-power { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_pwr_off: pmx-pwr-off { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - pmx_btn_reset: pmx-btn-reset { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_btn_copy: pmx-btn-copy { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_btn_power: pmx-btn-power { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - - pmx_led_copy_green: pmx-led-copy-green { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_led_copy_red: pmx-led-copy-red { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_pwr_off>; - pinctrl-names = "default"; - gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; - pinctrl-names = "default"; - - power { - label = "Power Button"; - linux,code = <KEY_POWER>; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - copy { - label = "Copy Button"; - linux,code = <KEY_COPY>; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset Button"; - linux,code = <KEY_RESTART>; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - }; - - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power>; - pinctrl-names = "default"; - - usb0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x0100000>; - }; - partition@100000 { - label = "uboot_env"; - reg = <0x0100000 0x0080000>; - }; - partition@180000 { - label = "key_store"; - reg = <0x0180000 0x0080000>; - }; - partition@200000 { - label = "info"; - reg = <0x0200000 0x0080000>; - }; - partition@280000 { - label = "etc"; - reg = <0x0280000 0x0a00000>; - }; - partition@c80000 { - label = "kernel_1"; - reg = <0x0c80000 0x0a00000>; - }; - partition@1680000 { - label = "rootfs1"; - reg = <0x1680000 0x2fc0000>; - }; - partition@4640000 { - label = "kernel_2"; - reg = <0x4640000 0x0a00000>; - }; - partition@5040000 { - label = "rootfs2"; - reg = <0x5040000 0x2fc0000>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/dts/kirkwood-openrd-base.dts b/arch/arm/dts/kirkwood-openrd-base.dts deleted file mode 100644 index 094191ece3d..00000000000 --- a/arch/arm/dts/kirkwood-openrd-base.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD Base Board Description - * - * Andrew Lunn <andrew@lunn.ch> - * - * This file contains the definitions that are specific to OpenRD - * base variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Base"; - compatible = "marvell,openrd-base", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - serial@12100 { - status = "okay"; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-openrd-client.dts b/arch/arm/dts/kirkwood-openrd-client.dts deleted file mode 100644 index 74dc23daf64..00000000000 --- a/arch/arm/dts/kirkwood-openrd-client.dts +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD Client Board Description - * - * Andrew Lunn <andrew@lunn.ch> - * - * This file contains the definitions that are specific to OpenRD - * client variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Client"; - compatible = "marvell,openrd-client", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - audio-controller@a0000 { - status = "okay"; - }; - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - cs42l51: cs42l51@4a { - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - #sound-dai-cells = <0>; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&audio0 0>; - }; - - simple-audio-card,codec { - sound-dai = <&cs42l51>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; - ethphy1: ethernet-phy@24 { - reg = <24>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/dts/kirkwood-openrd-ultimate.dts b/arch/arm/dts/kirkwood-openrd-ultimate.dts deleted file mode 100644 index 888e13320c1..00000000000 --- a/arch/arm/dts/kirkwood-openrd-ultimate.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD Ultimate Board Description - * - * Andrew Lunn <andrew@lunn.ch> - * - * This file contains the definitions that are specific to OpenRD - * ultimate variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Ultimate"; - compatible = "marvell,openrd-ultimate", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - cs42l51: cs42l51@4a { - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - }; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/dts/kirkwood-openrd.dtsi b/arch/arm/dts/kirkwood-openrd.dtsi deleted file mode 100644 index 47f03c69c55..00000000000 --- a/arch/arm/dts/kirkwood-openrd.dtsi +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD (Base|Client|Ultimate) Board Description - * - * Andrew Lunn <andrew@lunn.ch> - * - * This file contains the definitions that are common between the three - * variants of the Marvell Kirkwood Development Board. - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>; - pinctrl-names = "default"; - - pmx_select28: pmx-select-rs232-rs485 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_select34: pmx-select-uart-sd { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "okay"; - - }; - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - mvsdio@90000 { - status = "okay"; - cd-gpios = <&gpio0 29 9>; - }; - gpio@10100 { - p28 { - gpio-hog; - gpios = <28 GPIO_ACTIVE_HIGH>; - /* - * SelRS232or485 selects between RS-232 or RS-485 - * mode for the second UART. - * - * Low: RS-232 - * High: RS-485 - * - * To use the second UART, you need to change also - * the SelUARTorSD. - */ - output-low; - line-name = "SelRS232or485"; - }; - }; - gpio@10140 { - p2 { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - /* - * SelUARTorSD selects between the second UART - * (serial@12100) and SD (mvsdio@90000). - * - * Low: UART - * High: SD - * - * When changing this line make sure the newly - * selected device node is enabled and the - * previously selected device node is disabled. - */ - output-high; /* Select SD by default */ - line-name = "SelUARTorSD"; - }; - }; - }; -}; - -&nand { - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@600000 { - label = "root"; - reg = <0x0600000 0x1FA00000>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/dts/kirkwood-pogo_e02.dts b/arch/arm/dts/kirkwood-pogo_e02.dts deleted file mode 100644 index f9e95e55f36..00000000000 --- a/arch/arm/dts/kirkwood-pogo_e02.dts +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-pogo_e02.dts - Device tree file for Pogoplug E02 - * - * Copyright (C) 2015 Christoph Junghans <ottxor@gentoo.org> - * - * based on information of dts files from - * Arch Linux ARM by Oleg Rakhmanov <moonman.ca@gmail.com> - * OpenWrt by Felix Kaechele <heffer@fedoraproject.org> - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Cloud Engines Pogoplug E02"; - compatible = "cloudengines,pogoe02", "marvell,kirkwood-88f6281", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-leds { - compatible = "gpio-leds"; - - health { - label = "pogo_e02:green:health"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - fault { - label = "pogo_e02:orange:fault"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pinctrl { - pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange - &pmx_led_green >; - pinctrl-names = "default"; - - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_green: pmx-led-green { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - pmx_led_orange: pmx-led-orange { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&nand { - chip-delay = <40>; - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "pogoplug"; - reg = <0x0500000 0x2000000>; - }; - - partition@2500000 { - label = "root"; - reg = <0x02500000 0x5b00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-pogoplug-series-4.dts b/arch/arm/dts/kirkwood-pogoplug-series-4.dts deleted file mode 100644 index 5aa4669ae25..00000000000 --- a/arch/arm/dts/kirkwood-pogoplug-series-4.dts +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4 - * inspired by the board files made by Kevin Mihelich for ArchLinux, - * and their DTS file. - * - * Copyright (C) 2015 Linus Walleij <linus.walleij@linaro.org> - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6192.dtsi" -#include <dt-bindings/input/linux-event-codes.h> - -/ { - model = "Cloud Engines PogoPlug Series 4"; - compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - chosen { - stdout-path = "uart0:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_eject>; - pinctrl-names = "default"; - - eject { - debounce-interval = <50>; - wakeup-source; - linux,code = <KEY_EJECTCD>; - label = "Eject Button"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_green &pmx_led_red>; - pinctrl-names = "default"; - - health { - label = "pogoplugv4:green:health"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - fault { - label = "pogoplugv4:red:fault"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pinctrl { - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp21"; - marvell,function = "sata0"; - }; - - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp20"; - marvell,function = "sata1"; - }; - - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - pmx_sdio_wp: pmx-sdio-wp { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_button_eject: pmx-button-eject { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_green: pmx-led-green { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_led_red: pmx-led-red { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; -}; - -&uart0 { - status = "okay"; -}; - -/* - * This PCIE controller has a USB 3.0 XHCI controller at 1,0 - */ -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&sata { - status = "okay"; - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - nr-ports = <1>; -}; - -&sdio { - status = "okay"; - pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; - pinctrl-names = "default"; - cd-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; -}; - -&nand { - /* 128 MiB of NAND flash */ - chip-delay = <40>; - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x200000>; - read-only; - }; - - partition@200000 { - label = "uImage"; - reg = <0x00200000 0x300000>; - }; - - partition@500000 { - label = "uImage2"; - reg = <0x00500000 0x300000>; - }; - - partition@800000 { - label = "failsafe"; - reg = <0x00800000 0x800000>; - }; - - partition@1000000 { - label = "root"; - reg = <0x01000000 0x7000000>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/dts/kirkwood-sheevaplug-common.dtsi deleted file mode 100644 index 0a698d3b739..00000000000 --- a/arch/arm/dts/kirkwood-sheevaplug-common.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs - * - * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com> - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_led_red: pmx-led-red { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_blue: pmx-led-blue { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_sdio_wp: pmx-sdio-wp { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 0>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "root"; - reg = <0x0500000 0x1fb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-sheevaplug.dts b/arch/arm/dts/kirkwood-sheevaplug.dts deleted file mode 100644 index c73cc904e5c..00000000000 --- a/arch/arm/dts/kirkwood-sheevaplug.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-sheevaplug.dts - Device tree file for Sheevaplug - * - * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com> - */ - -/dts-v1/; - -#include "kirkwood-sheevaplug-common.dtsi" - -/ { - model = "Globalscale Technologies SheevaPlug"; - compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_blue &pmx_led_red>; - pinctrl-names = "default"; - - health { - label = "sheevaplug:blue:health"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - misc { - label = "sheevaplug:red:misc"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/arch/arm/dts/kirkwood-synology.dtsi b/arch/arm/dts/kirkwood-synology.dtsi deleted file mode 100644 index c97ed29a0a0..00000000000 --- a/arch/arm/dts/kirkwood-synology.dtsi +++ /dev/null @@ -1,855 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Nodes for Marvell 628x Synology devices - * - * Andrew Lunn <andrew@lunn.ch> - * Ben Peddell <klightspeed@killerwolves.net> - * - */ - -/ { - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_alarmled_12: pmx-alarmled-12 { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_15: pmx-fanctrl-15 { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_16: pmx-fanctrl-16 { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_17: pmx-fanctrl-17 { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_18: pmx-fanalarm-18 { - marvell,pins = "mpp18"; - marvell,function = "gpo"; - }; - - pmx_hddled_20: pmx-hddled-20 { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - - pmx_hddled_21: pmx-hddled-21 { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_hddled_22: pmx-hddled-22 { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_hddled_23: pmx-hddled-23 { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - pmx_hddled_24: pmx-hddled-24 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - pmx_hddled_25: pmx-hddled-25 { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - - pmx_hddled_26: pmx-hddled-26 { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - - pmx_hddled_27: pmx-hddled-27 { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - pmx_hddled_28: pmx-hddled-28 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_hdd1_pwr_29: pmx-hdd1-pwr-29 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_hdd1_pwr_30: pmx-hdd-pwr-30 { - marvell,pins = "mpp30"; - marvell,function = "gpio"; - }; - - pmx_hdd2_pwr_31: pmx-hdd2-pwr-31 { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_32: pmx-fanctrl-32 { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_33: pmx-fanctrl-33 { - marvell,pins = "mpp33"; - marvell,function = "gpo"; - }; - - pmx_fanctrl_34: pmx-fanctrl-34 { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_35: pmx-fanalarm-35 { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - - pmx_hddled_36: pmx-hddled-36 { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_hddled_37: pmx-hddled-37 { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_hddled_38: pmx-hddled-38 { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_hddled_39: pmx-hddled-39 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_hddled_40: pmx-hddled-40 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - pmx_hddled_41: pmx-hddled-41 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_hddled_42: pmx-hddled-42 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_hddled_43: pmx-hddled-43 { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - pmx_hddled_44: pmx-hddled-44 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_hddled_45: pmx-hddled-45 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_hdd3_pwr_44: pmx-hdd3-pwr-44 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_hdd4_pwr_45: pmx-hdd4-pwr-45 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_44: pmx-fanalarm-44 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_45: pmx-fanalarm-45 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - }; - - rtc@10300 { - status = "disabled"; - }; - - spi@10600 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x00000000 0x00080000>; - label = "RedBoot"; - }; - - partition@80000 { - reg = <0x00080000 0x00200000>; - label = "zImage"; - }; - - partition@280000 { - reg = <0x00280000 0x00140000>; - label = "rd.gz"; - }; - - partition@3c0000 { - reg = <0x003c0000 0x00010000>; - label = "vendor"; - }; - - partition@3d0000 { - reg = <0x003d0000 0x00020000>; - label = "RedBoot config"; - }; - - partition@3f0000 { - reg = <0x003f0000 0x00010000>; - label = "FIS directory"; - }; - }; - }; - - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - rs5c372: rs5c372@32 { - status = "disabled"; - compatible = "ricoh,rs5c372"; - reg = <0x32>; - }; - - s35390a: s35390a@30 { - status = "disabled"; - compatible = "sii,s35390a"; - reg = <0x30>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - serial@12100 { - status = "okay"; - }; - - poweroff@12100 { - compatible = "synology,power-off"; - reg = <0x12100 0x100>; - clocks = <&gate_clk 7>; - }; - - sata@80000 { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio-fan-150-32-35 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 - &pmx_fanalarm_35>; - pinctrl-names = "default"; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH - &gpio1 1 GPIO_ACTIVE_HIGH - &gpio1 2 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2200 1 - 2500 2 - 3000 4 - 3300 3 - 3700 5 - 3800 6 - 4200 7 >; - }; - - gpio-fan-150-15-18 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_18>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2200 1 - 2500 2 - 3000 4 - 3300 3 - 3700 5 - 3800 6 - 4200 7 >; - }; - - gpio-fan-100-32-35 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 - &pmx_fanalarm_35>; - pinctrl-names = "default"; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH - &gpio1 1 GPIO_ACTIVE_HIGH - &gpio1 2 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-fan-100-15-18 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_18>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-fan-100-15-35-1 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_35>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-fan-100-15-35-3 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_35 &pmx_fanalarm_44 &pmx_fanalarm_45>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH - &gpio1 12 GPIO_ACTIVE_HIGH - &gpio1 13 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-leds-alarm-12 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_alarmled_12>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:alarm"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-20 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_20 &pmx_hddled_21 &pmx_hddled_22 - &pmx_hddled_23 &pmx_hddled_24 &pmx_hddled_25 - &pmx_hddled_26 &pmx_hddled_27>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - - hdd3-green { - label = "synology:green:hdd3"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - hdd3-amber { - label = "synology:amber:hdd3"; - gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - hdd4-green { - label = "synology:green:hdd4"; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - }; - - hdd4-amber { - label = "synology:amber:hdd4"; - gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-21-1 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-21-2 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-36 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_36 &pmx_hddled_37 &pmx_hddled_38 - &pmx_hddled_39 &pmx_hddled_40 &pmx_hddled_41 - &pmx_hddled_42 &pmx_hddled_43 &pmx_hddled_44 - &pmx_hddled_45>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - hdd3-green { - label = "synology:green:hdd3"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - }; - - hdd3-amber { - label = "synology:amber:hdd3"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - hdd4-green { - label = "synology:green:hdd4"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - - hdd4-amber { - label = "synology:amber:hdd4"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - - hdd5-green { - label = "synology:green:hdd5"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - }; - - hdd5-amber { - label = "synology:amber:hdd5"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-38 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - }; - - regulators-hdd-29 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_29 &pmx_hdd2_pwr_31>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-30-1 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_30>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-30-2 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-30-4 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34 - &pmx_hdd3_pwr_44 &pmx_hdd4_pwr_45>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "hdd3power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "hdd4power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-31 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd2_pwr_31>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-34 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd2_pwr_34 &pmx_hdd3_pwr_44 - &pmx_hdd4_pwr_45>; - pinctrl-names = "default"; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "hdd3power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "hdd4power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - device_type = "ethernet-phy"; - reg = <8>; - }; - - ethphy1: ethernet-phy@1 { - device_type = "ethernet-phy"; - reg = <9>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "disabled"; - - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/dts/kirkwood.dtsi b/arch/arm/dts/kirkwood.dtsi deleted file mode 100644 index 81c7eda2c44..00000000000 --- a/arch/arm/dts/kirkwood.dtsi +++ /dev/null @@ -1,393 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/include/ "skeleton.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/gpio.h> - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - compatible = "marvell,kirkwood"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,feroceon"; - reg = <0>; - clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; - clock-names = "cpu_clk", "ddrclk", "powersave"; - }; - }; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - i2c0 = &i2c0; - }; - - mbus@f1000000 { - compatible = "marvell,kirkwood-mbus", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - /* If a board file needs to change this ranges it must replace it completely */ - ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */ - MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */ - MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */ - >; - controller = <&mbusc>; - pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ - pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ - - nand: nand@12f { - #address-cells = <1>; - #size-cells = <1>; - cle = <0>; - ale = <1>; - bank-width = <1>; - compatible = "marvell,orion-nand"; - reg = <MBUS_ID(0x01, 0x2f) 0 0x400>; - chip-delay = <25>; - /* set partition map and/or chip-delay in board dts */ - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - status = "disabled"; - }; - - crypto_sram: sa-sram@301 { - compatible = "mmio-sram"; - reg = <MBUS_ID(0x03, 0x01) 0x0 0x800>; - clocks = <&gate_clk 17>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - - ocp@f1000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0xf1000000 0x0100000>; - #address-cells = <1>; - #size-cells = <1>; - - pinctrl: pin-controller@10000 { - /* set compatible property in SoC file */ - reg = <0x10000 0x20>; - - pmx_ge1: pmx-ge1 { - marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", - "mpp24", "mpp25", "mpp26", "mpp27", - "mpp30", "mpp31", "mpp32", "mpp33"; - marvell,function = "ge1"; - }; - - pmx_nand: pmx-nand { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp18", "mpp19"; - marvell,function = "nand"; - }; - - /* - * Default SPI0 pinctrl setting with CSn on mpp0, - * overwrite marvell,pins on board level if required. - */ - pmx_spi: pmx-spi { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; - marvell,function = "spi"; - }; - - pmx_twsi0: pmx-twsi0 { - marvell,pins = "mpp8", "mpp9"; - marvell,function = "twsi0"; - }; - - /* - * Default UART pinctrl setting without RTS/CTS, - * overwrite marvell,pins on board level if required. - */ - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11"; - marvell,function = "uart0"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14"; - marvell,function = "uart1"; - }; - }; - - core_clk: core-clocks@10030 { - compatible = "marvell,kirkwood-core-clock"; - reg = <0x10030 0x4>; - #clock-cells = <1>; - }; - - spi0: spi@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <23>; - reg = <0x10600 0x28>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; - status = "disabled"; - }; - - gpio0: gpio@10100 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x10100 0x40>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <35>, <36>, <37>, <38>; - clocks = <&gate_clk 7>; - }; - - gpio1: gpio@10140 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x10140 0x40>; - ngpios = <18>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <39>, <40>, <41>; - clocks = <&gate_clk 7>; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <29>; - clock-frequency = <100000>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_twsi0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <33>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <34>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x80>, <0x1500 0x20>; - }; - - sysc: system-controller@20000 { - compatible = "marvell,orion-system-controller"; - reg = <0x20000 0x120>; - }; - - bridge_intc: bridge-interrupt-ctrl@20110 { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <1>; - marvell,#interrupts = <6>; - }; - - gate_clk: clock-gating-control@2011c { - compatible = "marvell,kirkwood-gating-clock"; - reg = <0x2011c 0x4>; - clocks = <&core_clk 0>; - #clock-cells = <1>; - }; - - l2: l2-cache@20128 { - compatible = "marvell,kirkwood-cache"; - reg = <0x20128 0x4>; - }; - - intc: main-interrupt-ctrl@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x10>, <0x20210 0x10>; - }; - - timer: timer@20300 { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; - - wdt: watchdog-timer@20300 { - compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>, <0x20108 0x4>; - interrupt-parent = <&bridge_intc>; - interrupts = <3>; - clocks = <&gate_clk 7>; - status = "okay"; - }; - - cesa: crypto@30000 { - compatible = "marvell,kirkwood-crypto"; - reg = <0x30000 0x10000>; - reg-names = "regs"; - interrupts = <22>; - clocks = <&gate_clk 17>; - marvell,crypto-srams = <&crypto_sram>; - marvell,crypto-sram-size = <0x800>; - status = "okay"; - }; - - usb0: ehci@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <19>; - clocks = <&gate_clk 3>; - status = "okay"; - }; - - dma0: xor@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60A00 0x100>; - status = "okay"; - clocks = <&gate_clk 8>; - - xor00 { - interrupts = <5>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <6>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - dma1: xor@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60B00 0x100>; - status = "okay"; - clocks = <&gate_clk 16>; - - xor00 { - interrupts = <7>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <8>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - eth0: ethernet-controller@72000 { - compatible = "marvell,kirkwood-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x4000>; - clocks = <&gate_clk 0>; - marvell,tx-checksum-limit = <1600>; - status = "disabled"; - - eth0port: ethernet0-port@0 { - compatible = "marvell,kirkwood-eth-port"; - reg = <0>; - interrupts = <11>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - /* set phy-handle property in board file */ - }; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <46>; - clocks = <&gate_clk 0>; - status = "disabled"; - - /* add phy nodes in board file */ - }; - - eth1: ethernet-controller@76000 { - compatible = "marvell,kirkwood-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76000 0x4000>; - clocks = <&gate_clk 19>; - marvell,tx-checksum-limit = <1600>; - pinctrl-0 = <&pmx_ge1>; - pinctrl-names = "default"; - status = "disabled"; - - eth1port: ethernet1-port@0 { - compatible = "marvell,kirkwood-eth-port"; - reg = <0>; - interrupts = <15>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - /* set phy-handle property in board file */ - }; - }; - - sata_phy0: sata-phy@82000 { - compatible = "marvell,mvebu-sata-phy"; - reg = <0x82000 0x0334>; - clocks = <&gate_clk 14>; - clock-names = "sata"; - #phy-cells = <0>; - status = "ok"; - }; - - sata_phy1: sata-phy@84000 { - compatible = "marvell,mvebu-sata-phy"; - reg = <0x84000 0x0334>; - clocks = <&gate_clk 15>; - clock-names = "sata"; - #phy-cells = <0>; - status = "ok"; - }; - - audio0: audio-controller@a0000 { - compatible = "marvell,kirkwood-audio"; - #sound-dai-cells = <0>; - reg = <0xa0000 0x2210>; - interrupts = <24>; - clocks = <&gate_clk 9>; - clock-names = "internal"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/meson-axg-jethome-jethub-j100.dts b/arch/arm/dts/meson-axg-jethome-jethub-j100.dts deleted file mode 100644 index 5783732dc6f..00000000000 --- a/arch/arm/dts/meson-axg-jethome-jethub-j100.dts +++ /dev/null @@ -1,361 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Vyacheslav Bocharov <adeep@lexina.in> - * Copyright (c) 2020 JetHome - * Author: Aleksandr Kazantsev <ak@tvip.ru> - * Author: Alexey Shevelkin <ash@tvip.ru> - * Author: Vyacheslav Bocharov <adeep@lexina.in> - */ - -/dts-v1/; - -#include "meson-axg.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - compatible = "jethome,jethub-j100", "amlogic,a113d", "amlogic,meson-axg"; - model = "JetHome JetHub J100"; - aliases { - serial0 = &uart_AO; /* Console */ - serial1 = &uart_AO_B; /* External UART (Wireless Module) */ - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* 1024MB RAM */ - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - reserved-memory { - linux,cma { - size = <0x0 0x400000>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_5v>; - regulator-always-on; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - usb_pwr: regulator-usb_pwr { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - regulator-always-on; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */ - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&scpi_sensors 0>; - trips { - cpu_passive: cpu-passive { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - cpu_hot: cpu-hot { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "hot"; - }; - - cpu_critical: cpu-critical { - temperature = <100000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - }; - - cpu_cooling_maps: cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - onewire { - compatible = "w1-gpio"; - gpios = <&gpio GPIOA_14 GPIO_ACTIVE_HIGH>; - #gpio-cells = <1>; - }; -}; - -&efuse { - sn: sn@32 { - reg = <0x32 0x20>; - }; - - eth_mac: eth_mac@0 { - reg = <0x0 0x6>; - }; - - bt_mac: bt_mac@6 { - reg = <0x6 0x6>; - }; - - wifi_mac: wifi_mac@c { - reg = <0xc 0x6>; - }; - - bid: bid@12 { - reg = <0x12 0x20>; - }; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rmii_x_pins>; - pinctrl-names = "default"; - phy-handle = <ð_phy0>; - phy-mode = "rmii"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - /* ICPlus IP101A/G Ethernet PHY (vendor_id=0x0243, model_id=0x0c54) */ - eth_phy0: ethernet-phy@0 { - /* compatible = "ethernet-phy-id0243.0c54";*/ - max-speed = <100>; - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <10000>; - reset-gpios = <&gpio GPIOZ_5 GPIO_ACTIVE_LOW>; - }; - }; -}; - -/* Internal I2C bus (on CPU module) */ -&i2c1 { - status = "okay"; - pinctrl-0 = <&i2c1_z_pins>; - pinctrl-names = "default"; - - /* RTC */ - pcf8563: pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - status = "okay"; - }; -}; - -/* Peripheral I2C bus (on motherboard) */ -&i2c_AO { - status = "okay"; - pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>; - pinctrl-names = "default"; -}; - -&pwm_ab { - status = "okay"; - pinctrl-0 = <&pwm_a_x20_pins>; - pinctrl-names = "default"; -}; - -/* wifi module */ -&sd_emmc_b { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr104; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* emmc storage */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* UART Bluetooth */ -&uart_B { - status = "okay"; - pinctrl-0 = <&uart_b_z_pins>, <&uart_b_z_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>; - }; -}; - -/* UART Console */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -/* UART Wireless module */ -&uart_AO_B { - status = "okay"; - pinctrl-0 = <&uart_ao_b_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - phy-supply = <&usb_pwr>; -}; - -&spicc1 { - status = "okay"; - pinctrl-0 = <&spi1_x_pins>, <&spi1_ss0_x_pins>; - pinctrl-names = "default"; -}; - -&gpio { - gpio-line-names = - "", "", "", "", "", // 0 - 4 - "", "", "", "", "", // 5 - 9 - "UserButton", "", "", "", "", // 10 - 14 - "", "", "", "", "", // 15 - 19 - "", "", "", "", "", // 20 - 24 - "", "LedRed", "LedGreen", "Output3", "Output2", // 25 - 29 - "Output1", "", "", "", "", // 30 - 34 - "", "ZigBeeBOOT", "", "", "", // 35 - 39 - "", "ZigBeeRESET", "", "Input4", "Input3", // 40 - 44 - "Input2", "Input1", "", "", "", // 45 - 49 - "", "", "", "", "", // 50 - 54 - "", "", "", "", "", // 55 - 59 - "", "", "", "", "", // 60 - 64 - "", "", "", "", "", // 65 - 69 - "", "", "", "", "", // 70 - 74 - "", "", "", "", "", // 75 - 79 - "", "", "", "", "", // 80 - 84 - "", ""; // 85-86 -}; - -&cpu0 { - #cooling-cells = <2>; -}; - -&cpu1 { - #cooling-cells = <2>; -}; - -&cpu2 { - #cooling-cells = <2>; -}; - -&cpu3 { - #cooling-cells = <2>; -}; diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts deleted file mode 100644 index 359589d1dfa..00000000000 --- a/arch/arm/dts/meson-axg-s400.dts +++ /dev/null @@ -1,602 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - */ - -/dts-v1/; - -#include "meson-axg.dtsi" -#include <dt-bindings/input/input.h> - -/ { - compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg"; - model = "Amlogic Meson AXG S400 Development Board"; - - adc_keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-next { - label = "Next"; - linux,code = <KEY_NEXT>; - press-threshold-microvolt = <1116000>; /* 62% */ - }; - - button-prev { - label = "Previous"; - linux,code = <KEY_PREVIOUS>; - press-threshold-microvolt = <900000>; /* 50% */ - }; - - button-wifi { - label = "Wifi"; - linux,code = <KEY_WLAN>; - press-threshold-microvolt = <684000>; /* 38% */ - }; - - button-up { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - press-threshold-microvolt = <468000>; /* 26% */ - }; - - button-down { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - press-threshold-microvolt = <252000>; /* 14% */ - }; - - button-voice { - label = "Voice"; - linux,code = <KEY_VOICECOMMAND>; - press-threshold-microvolt = <0>; /* 0% */ - }; - }; - - aliases { - serial0 = &uart_AO; - serial1 = &uart_A; - }; - - linein: audio-codec-0 { - #sound-dai-cells = <0>; - compatible = "everest,es7241"; - VDDA-supply = <&vcc_3v3>; - VDDP-supply = <&vcc_3v3>; - VDDD-supply = <&vcc_3v3>; - status = "okay"; - sound-name-prefix = "Linein"; - }; - - lineout: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "everest,es7154"; - VDD-supply = <&vcc_3v3>; - PVDD-supply = <&vcc_5v>; - status = "okay"; - sound-name-prefix = "Lineout"; - }; - - spdif_dit: audio-codec-2 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - status = "okay"; - sound-name-prefix = "DIT"; - }; - - dmics: audio-codec-3 { - #sound-dai-cells = <0>; - compatible = "dmic-codec"; - num-channels = <7>; - wakeup-delay-ms = <50>; - status = "okay"; - sound-name-prefix = "MIC"; - }; - - spdif_dir: audio-codec-4 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dir"; - status = "okay"; - sound-name-prefix = "DIR"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&main_12v>; - - gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - usb_pwr: regulator-usb_pwr { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - speaker-leds { - compatible = "gpio-leds"; - - aled1 { - label = "speaker:aled1"; - gpios = <&gpio_speaker 7 0>; - }; - - aled2 { - label = "speaker:aled2"; - gpios = <&gpio_speaker 6 0>; - }; - - aled3 { - label = "speaker:aled3"; - gpios = <&gpio_speaker 5 0>; - }; - - aled4 { - label = "speaker:aled4"; - gpios = <&gpio_speaker 4 0>; - }; - - aled5 { - label = "speaker:aled5"; - gpios = <&gpio_speaker 3 0>; - }; - - aled6 { - label = "speaker:aled6"; - gpios = <&gpio_speaker 2 0>; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "AXG-S400"; - audio-aux-devs = <&tdmin_a>, <&tdmin_b>, <&tdmin_c>, - <&tdmin_lb>, <&tdmout_c>; - audio-widgets = "Line", "Lineout", - "Line", "Linein", - "Speaker", "Speaker1 Left", - "Speaker", "Speaker1 Right"; - audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2", - "SPDIFOUT IN 0", "FRDDR_A OUT 3", - "TDMOUT_C IN 1", "FRDDR_B OUT 2", - "SPDIFOUT IN 1", "FRDDR_B OUT 3", - "TDMOUT_C IN 2", "FRDDR_C OUT 2", - "SPDIFOUT IN 2", "FRDDR_C OUT 3", - "TDM_C Playback", "TDMOUT_C OUT", - "TDMIN_A IN 2", "TDM_C Capture", - "TDMIN_A IN 5", "TDM_C Loopback", - "TDMIN_B IN 2", "TDM_C Capture", - "TDMIN_B IN 5", "TDM_C Loopback", - "TDMIN_C IN 2", "TDM_C Capture", - "TDMIN_C IN 5", "TDM_C Loopback", - "TDMIN_LB IN 2", "TDM_C Loopback", - "TDMIN_LB IN 5", "TDM_C Capture", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT", - "TODDR_A IN 2", "TDMIN_C OUT", - "TODDR_B IN 2", "TDMIN_C OUT", - "TODDR_C IN 2", "TDMIN_C OUT", - "TODDR_A IN 3", "SPDIFIN Capture", - "TODDR_B IN 3", "SPDIFIN Capture", - "TODDR_C IN 3", "SPDIFIN Capture", - "TODDR_A IN 4", "PDM Capture", - "TODDR_B IN 4", "PDM Capture", - "TODDR_C IN 4", "PDM Capture", - "TODDR_A IN 6", "TDMIN_LB OUT", - "TODDR_B IN 6", "TDMIN_LB OUT", - "TODDR_C IN 6", "TDMIN_LB OUT", - "Lineout", "Lineout AOUTL", - "Lineout", "Lineout AOUTR", - "Speaker1 Left", "SPK1 OUT_A", - "Speaker1 Left", "SPK1 OUT_B", - "Speaker1 Right", "SPK1 OUT_C", - "Speaker1 Right", "SPK1 OUT_D", - "Linein AINL", "Linein", - "Linein AINR", "Linein"; - assigned-clocks = <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <589824000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - dai-link-6 { - sound-dai = <&tdmif_c>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-rx-mask-1 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&lineout>; - }; - - codec-1 { - sound-dai = <&speaker_amp1>; - }; - - codec-2 { - sound-dai = <&linein>; - }; - - }; - - dai-link-7 { - sound-dai = <&spdifout>; - - codec { - sound-dai = <&spdif_dit>; - }; - }; - - dai-link-8 { - sound-dai = <&spdifin>; - - codec { - sound-dai = <&spdif_dir>; - }; - }; - - dai-link-9 { - sound-dai = <&pdm>; - - codec { - sound-dai = <&dmics>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */ - }; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_y_pins>; - pinctrl-names = "default"; - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - interrupt-parent = <&gpio_intc>; - interrupts = <98 IRQ_TYPE_LEVEL_LOW>; - eee-broken-1000t; - }; - }; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&i2c1 { - status = "okay"; - pinctrl-0 = <&i2c1_z_pins>; - pinctrl-names = "default"; - - speaker_amp1: audio-codec@1b { - compatible = "ti,tas5707"; - reg = <0x1b>; - reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - AVDD-supply = <&vcc_3v3>; - DVDD-supply = <&vcc_3v3>; - PVDD_A-supply = <&main_12v>; - PVDD_B-supply = <&main_12v>; - PVDD_C-supply = <&main_12v>; - PVDD_D-supply = <&main_12v>; - sound-name-prefix = "SPK1"; - }; -}; - -&i2c_AO { - status = "okay"; - pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>; - pinctrl-names = "default"; - - gpio_speaker: gpio-controller@1f { - compatible = "nxp,pca9557"; - reg = <0x1f>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <&vddao_3v3>; - }; -}; - -&pdm { - pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>, - <&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pcieA { - reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pcieB { - reset-gpios = <&gpio GPIOZ_10 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&pwm_ab { - status = "okay"; - pinctrl-0 = <&pwm_a_x20_pins>; - pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* wifi module */ -&sd_emmc_b { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr104; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* emmc storage */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&spdifin { - pinctrl-0 = <&spdif_in_a19_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&spdifout { - pinctrl-0 = <&spdif_out_a20_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tdmif_a { - pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>, - <&tdma_din0_pins>, <&tdma_dout0_x15_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tdmif_b { - pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>, - <&tdmb_din3_pins>, <&mclk_b_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tdmif_c { - pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>, - <&tdmc_din1_pins>, <&tdmc_dout2_pins>, - <&mclk_c_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmin_c { - status = "okay"; -}; - -&tdmin_lb { - status = "okay"; -}; - -&tdmout_c { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "otg"; - vbus-supply = <&usb_pwr>; -}; diff --git a/arch/arm/dts/meson-axg.dtsi b/arch/arm/dts/meson-axg.dtsi deleted file mode 100644 index 3f5254eeb47..00000000000 --- a/arch/arm/dts/meson-axg.dtsi +++ /dev/null @@ -1,1957 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - */ - -#include <dt-bindings/clock/axg-aoclkc.h> -#include <dt-bindings/clock/axg-audio-clkc.h> -#include <dt-bindings/clock/axg-clkc.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/gpio/meson-axg-gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> -#include <dt-bindings/reset/amlogic,meson-axg-reset.h> -#include <dt-bindings/power/meson-axg-power.h> - -/ { - compatible = "amlogic,meson-axg"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - tdmif_a: audio-controller-0 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_A"; - clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, - <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_b: audio-controller-1 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_B"; - clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, - <&clkc_audio AUD_CLKID_MST_B_SCLK>, - <&clkc_audio AUD_CLKID_MST_B_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_c: audio-controller-2 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_C"; - clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, - <&clkc_audio AUD_CLKID_MST_C_SCLK>, - <&clkc_audio AUD_CLKID_MST_C_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - l2: l2-cache0 { - compatible = "cache"; - }; - }; - - sm: secure-monitor { - compatible = "amlogic,meson-gxbb-sm"; - }; - - efuse: efuse { - compatible = "amlogic,meson-gxbb-efuse"; - clocks = <&clkc CLKID_EFUSE>; - #address-cells = <1>; - #size-cells = <1>; - read-only; - secure-monitor = <&sm>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 16 MiB reserved for Hardware ROM Firmware */ - hwrom_reserved: hwrom@0 { - reg = <0x0 0x0 0x0 0x1000000>; - no-map; - }; - - /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@5000000 { - reg = <0x0 0x05000000 0x0 0x300000>; - no-map; - }; - }; - - scpi { - compatible = "arm,scpi-pre-1.0"; - mboxes = <&mailbox 1 &mailbox 2>; - shmem = <&cpu_scp_lpri &cpu_scp_hpri>; - - scpi_clocks: clocks { - compatible = "arm,scpi-clocks"; - - scpi_dvfs: clock-controller { - compatible = "arm,scpi-dvfs-clocks"; - #clock-cells = <1>; - clock-indices = <0>; - clock-output-names = "vcpu"; - }; - }; - - scpi_sensors: sensors { - compatible = "amlogic,meson-gxbb-scpi-sensors"; - #thermal-sensor-cells = <1>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - pcieA: pcie@f9800000 { - compatible = "amlogic,axg-pcie", "snps,dw-pcie"; - reg = <0x0 0xf9800000 0x0 0x400000>, - <0x0 0xff646000 0x0 0x2000>, - <0x0 0xf9f00000 0x0 0x100000>; - reg-names = "elbi", "cfg", "config"; - interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; - bus-range = <0x0 0xff>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>; - - clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>; - clock-names = "general", "pclk", "port"; - resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>; - reset-names = "port", "apb"; - num-lanes = <1>; - phys = <&pcie_phy>; - phy-names = "pcie"; - status = "disabled"; - }; - - pcieB: pcie@fa000000 { - compatible = "amlogic,axg-pcie", "snps,dw-pcie"; - reg = <0x0 0xfa000000 0x0 0x400000>, - <0x0 0xff648000 0x0 0x2000>, - <0x0 0xfa400000 0x0 0x100000>; - reg-names = "elbi", "cfg", "config"; - interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; - bus-range = <0x0 0xff>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>; - - clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>; - clock-names = "general", "pclk", "port"; - resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>; - reset-names = "port", "apb"; - num-lanes = <1>; - phys = <&pcie_phy>; - phy-names = "pcie"; - status = "disabled"; - }; - - usb: usb@ffe09080 { - compatible = "amlogic,meson-axg-usb-ctrl"; - reg = <0x0 0xffe09080 0x0 0x20>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "usb_ctrl", "ddr"; - resets = <&reset RESET_USB_OTG>; - - dr_mode = "otg"; - - phys = <&usb2_phy1>; - phy-names = "usb2-phy1"; - - dwc2: usb@ff400000 { - compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; - reg = <0x0 0xff400000 0x0 0x40000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLKID_USB1>; - clock-names = "otg"; - phys = <&usb2_phy1>; - dr_mode = "peripheral"; - g-rx-fifo-size = <192>; - g-np-tx-fifo-size = <128>; - g-tx-fifo-size = <128 128 16 16 16>; - }; - - dwc3: usb@ff500000 { - compatible = "snps,dwc3"; - reg = <0x0 0xff500000 0x0 0x100000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - }; - }; - - ethmac: ethernet@ff3f0000 { - compatible = "amlogic,meson-axg-dwmac", - "snps,dwmac-3.70a", - "snps,dwmac"; - reg = <0x0 0xff3f0000 0x0 0x10000>, - <0x0 0xff634540 0x0 0x8>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "stmmaceth", "clkin0", "clkin1", - "timing-adjustment"; - rx-fifo-depth = <4096>; - tx-fifo-depth = <2048>; - power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>; - status = "disabled"; - }; - - pcie_phy: phy@ff644000 { - compatible = "amlogic,axg-pcie-phy"; - reg = <0x0 0xff644000 0x0 0x1c>; - resets = <&reset RESET_PCIE_PHY>; - phys = <&mipi_pcie_analog_dphy>; - phy-names = "analog"; - #phy-cells = <0>; - }; - - pdm: audio-controller@ff632000 { - compatible = "amlogic,axg-pdm"; - reg = <0x0 0xff632000 0x0 0x34>; - #sound-dai-cells = <0>; - sound-name-prefix = "PDM"; - clocks = <&clkc_audio AUD_CLKID_PDM>, - <&clkc_audio AUD_CLKID_PDM_DCLK>, - <&clkc_audio AUD_CLKID_PDM_SYSCLK>; - clock-names = "pclk", "dclk", "sysclk"; - status = "disabled"; - }; - - periphs: bus@ff634000 { - compatible = "simple-bus"; - reg = <0x0 0xff634000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; - - hwrng: rng@18 { - compatible = "amlogic,meson-rng"; - reg = <0x0 0x18 0x0 0x4>; - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; - }; - - pinctrl_periphs: pinctrl@480 { - compatible = "amlogic,meson-axg-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@480 { - reg = <0x0 0x00480 0x0 0x40>, - <0x0 0x004e8 0x0 0x14>, - <0x0 0x00520 0x0 0x14>, - <0x0 0x00430 0x0 0x3c>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_periphs 0 0 86>; - }; - - i2c0_pins: i2c0 { - mux { - groups = "i2c0_sck", - "i2c0_sda"; - function = "i2c0"; - bias-disable; - }; - }; - - i2c1_x_pins: i2c1_x { - mux { - groups = "i2c1_sck_x", - "i2c1_sda_x"; - function = "i2c1"; - bias-disable; - }; - }; - - i2c1_z_pins: i2c1_z { - mux { - groups = "i2c1_sck_z", - "i2c1_sda_z"; - function = "i2c1"; - bias-disable; - }; - }; - - i2c2_a_pins: i2c2_a { - mux { - groups = "i2c2_sck_a", - "i2c2_sda_a"; - function = "i2c2"; - bias-disable; - }; - }; - - i2c2_x_pins: i2c2_x { - mux { - groups = "i2c2_sck_x", - "i2c2_sda_x"; - function = "i2c2"; - bias-disable; - }; - }; - - i2c3_a6_pins: i2c3_a6 { - mux { - groups = "i2c3_sda_a6", - "i2c3_sck_a7"; - function = "i2c3"; - bias-disable; - }; - }; - - i2c3_a12_pins: i2c3_a12 { - mux { - groups = "i2c3_sda_a12", - "i2c3_sck_a13"; - function = "i2c3"; - bias-disable; - }; - }; - - i2c3_a19_pins: i2c3_a19 { - mux { - groups = "i2c3_sda_a19", - "i2c3_sck_a20"; - function = "i2c3"; - bias-disable; - }; - }; - - emmc_pins: emmc { - mux-0 { - groups = "emmc_nand_d0", - "emmc_nand_d1", - "emmc_nand_d2", - "emmc_nand_d3", - "emmc_nand_d4", - "emmc_nand_d5", - "emmc_nand_d6", - "emmc_nand_d7", - "emmc_cmd"; - function = "emmc"; - bias-pull-up; - }; - - mux-1 { - groups = "emmc_clk"; - function = "emmc"; - bias-disable; - }; - }; - - emmc_ds_pins: emmc_ds { - mux { - groups = "emmc_ds"; - function = "emmc"; - bias-pull-down; - }; - }; - - emmc_clk_gate_pins: emmc_clk_gate { - mux { - groups = "BOOT_8"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - eth_rgmii_x_pins: eth-x-rgmii { - mux { - groups = "eth_mdio_x", - "eth_mdc_x", - "eth_rgmii_rx_clk_x", - "eth_rx_dv_x", - "eth_rxd0_x", - "eth_rxd1_x", - "eth_rxd2_rgmii", - "eth_rxd3_rgmii", - "eth_rgmii_tx_clk", - "eth_txen_x", - "eth_txd0_x", - "eth_txd1_x", - "eth_txd2_rgmii", - "eth_txd3_rgmii"; - function = "eth"; - bias-disable; - }; - }; - - eth_rgmii_y_pins: eth-y-rgmii { - mux { - groups = "eth_mdio_y", - "eth_mdc_y", - "eth_rgmii_rx_clk_y", - "eth_rx_dv_y", - "eth_rxd0_y", - "eth_rxd1_y", - "eth_rxd2_rgmii", - "eth_rxd3_rgmii", - "eth_rgmii_tx_clk", - "eth_txen_y", - "eth_txd0_y", - "eth_txd1_y", - "eth_txd2_rgmii", - "eth_txd3_rgmii"; - function = "eth"; - bias-disable; - }; - }; - - eth_rmii_x_pins: eth-x-rmii { - mux { - groups = "eth_mdio_x", - "eth_mdc_x", - "eth_rgmii_rx_clk_x", - "eth_rx_dv_x", - "eth_rxd0_x", - "eth_rxd1_x", - "eth_txen_x", - "eth_txd0_x", - "eth_txd1_x"; - function = "eth"; - bias-disable; - }; - }; - - eth_rmii_y_pins: eth-y-rmii { - mux { - groups = "eth_mdio_y", - "eth_mdc_y", - "eth_rgmii_rx_clk_y", - "eth_rx_dv_y", - "eth_rxd0_y", - "eth_rxd1_y", - "eth_txen_y", - "eth_txd0_y", - "eth_txd1_y"; - function = "eth"; - bias-disable; - }; - }; - - mclk_b_pins: mclk_b { - mux { - groups = "mclk_b"; - function = "mclk_b"; - bias-disable; - }; - }; - - mclk_c_pins: mclk_c { - mux { - groups = "mclk_c"; - function = "mclk_c"; - bias-disable; - }; - }; - - pdm_dclk_a14_pins: pdm_dclk_a14 { - mux { - groups = "pdm_dclk_a14"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_dclk_a19_pins: pdm_dclk_a19 { - mux { - groups = "pdm_dclk_a19"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_pins: pdm_din0 { - mux { - groups = "pdm_din0"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_pins: pdm_din1 { - mux { - groups = "pdm_din1"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_pins: pdm_din2 { - mux { - groups = "pdm_din2"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_pins: pdm_din3 { - mux { - groups = "pdm_din3"; - function = "pdm"; - bias-disable; - }; - }; - - pwm_a_a_pins: pwm_a_a { - mux { - groups = "pwm_a_a"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_a_x18_pins: pwm_a_x18 { - mux { - groups = "pwm_a_x18"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_a_x20_pins: pwm_a_x20 { - mux { - groups = "pwm_a_x20"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_a_z_pins: pwm_a_z { - mux { - groups = "pwm_a_z"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_b_a_pins: pwm_b_a { - mux { - groups = "pwm_b_a"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_b_x_pins: pwm_b_x { - mux { - groups = "pwm_b_x"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_b_z_pins: pwm_b_z { - mux { - groups = "pwm_b_z"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_c_a_pins: pwm_c_a { - mux { - groups = "pwm_c_a"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x10_pins: pwm_c_x10 { - mux { - groups = "pwm_c_x10"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x17_pins: pwm_c_x17 { - mux { - groups = "pwm_c_x17"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_d_x11_pins: pwm_d_x11 { - mux { - groups = "pwm_d_x11"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_d_x16_pins: pwm_d_x16 { - mux { - groups = "pwm_d_x16"; - function = "pwm_d"; - bias-disable; - }; - }; - - sdio_pins: sdio { - mux-0 { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_cmd"; - function = "sdio"; - bias-pull-up; - }; - - mux-1 { - groups = "sdio_clk"; - function = "sdio"; - bias-disable; - }; - }; - - sdio_clk_gate_pins: sdio_clk_gate { - mux { - groups = "GPIOX_4"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - spdif_in_z_pins: spdif_in_z { - mux { - groups = "spdif_in_z"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a1_pins: spdif_in_a1 { - mux { - groups = "spdif_in_a1"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a7_pins: spdif_in_a7 { - mux { - groups = "spdif_in_a7"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a19_pins: spdif_in_a19 { - mux { - groups = "spdif_in_a19"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a20_pins: spdif_in_a20 { - mux { - groups = "spdif_in_a20"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_out_a1_pins: spdif_out_a1 { - mux { - groups = "spdif_out_a1"; - function = "spdif_out"; - bias-disable; - }; - }; - - spdif_out_a11_pins: spdif_out_a11 { - mux { - groups = "spdif_out_a11"; - function = "spdif_out"; - bias-disable; - }; - }; - - spdif_out_a19_pins: spdif_out_a19 { - mux { - groups = "spdif_out_a19"; - function = "spdif_out"; - bias-disable; - }; - }; - - spdif_out_a20_pins: spdif_out_a20 { - mux { - groups = "spdif_out_a20"; - function = "spdif_out"; - bias-disable; - }; - }; - - spdif_out_z_pins: spdif_out_z { - mux { - groups = "spdif_out_z"; - function = "spdif_out"; - bias-disable; - }; - }; - - spi0_pins: spi0 { - mux { - groups = "spi0_miso", - "spi0_mosi", - "spi0_clk"; - function = "spi0"; - bias-disable; - }; - }; - - spi0_ss0_pins: spi0_ss0 { - mux { - groups = "spi0_ss0"; - function = "spi0"; - bias-disable; - }; - }; - - spi0_ss1_pins: spi0_ss1 { - mux { - groups = "spi0_ss1"; - function = "spi0"; - bias-disable; - }; - }; - - spi0_ss2_pins: spi0_ss2 { - mux { - groups = "spi0_ss2"; - function = "spi0"; - bias-disable; - }; - }; - - spi1_a_pins: spi1_a { - mux { - groups = "spi1_miso_a", - "spi1_mosi_a", - "spi1_clk_a"; - function = "spi1"; - bias-disable; - }; - }; - - spi1_ss0_a_pins: spi1_ss0_a { - mux { - groups = "spi1_ss0_a"; - function = "spi1"; - bias-disable; - }; - }; - - spi1_ss1_pins: spi1_ss1 { - mux { - groups = "spi1_ss1"; - function = "spi1"; - bias-disable; - }; - }; - - spi1_x_pins: spi1_x { - mux { - groups = "spi1_miso_x", - "spi1_mosi_x", - "spi1_clk_x"; - function = "spi1"; - bias-disable; - }; - }; - - spi1_ss0_x_pins: spi1_ss0_x { - mux { - groups = "spi1_ss0_x"; - function = "spi1"; - bias-disable; - }; - }; - - tdma_din0_pins: tdma_din0 { - mux { - groups = "tdma_din0"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_dout0_x14_pins: tdma_dout0_x14 { - mux { - groups = "tdma_dout0_x14"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_dout0_x15_pins: tdma_dout0_x15 { - mux { - groups = "tdma_dout0_x15"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_dout1_pins: tdma_dout1 { - mux { - groups = "tdma_dout1"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_din1_pins: tdma_din1 { - mux { - groups = "tdma_din1"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_fs_pins: tdma_fs { - mux { - groups = "tdma_fs"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_fs_slv_pins: tdma_fs_slv { - mux { - groups = "tdma_fs_slv"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_sclk_pins: tdma_sclk { - mux { - groups = "tdma_sclk"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_sclk_slv_pins: tdma_sclk_slv { - mux { - groups = "tdma_sclk_slv"; - function = "tdma"; - bias-disable; - }; - }; - - tdmb_din0_pins: tdmb_din0 { - mux { - groups = "tdmb_din0"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_din1_pins: tdmb_din1 { - mux { - groups = "tdmb_din1"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_din2_pins: tdmb_din2 { - mux { - groups = "tdmb_din2"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_din3_pins: tdmb_din3 { - mux { - groups = "tdmb_din3"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_dout0_pins: tdmb_dout0 { - mux { - groups = "tdmb_dout0"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_dout1_pins: tdmb_dout1 { - mux { - groups = "tdmb_dout1"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_dout2_pins: tdmb_dout2 { - mux { - groups = "tdmb_dout2"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_dout3_pins: tdmb_dout3 { - mux { - groups = "tdmb_dout3"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_fs_pins: tdmb_fs { - mux { - groups = "tdmb_fs"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_fs_slv_pins: tdmb_fs_slv { - mux { - groups = "tdmb_fs_slv"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_sclk_pins: tdmb_sclk { - mux { - groups = "tdmb_sclk"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_sclk_slv_pins: tdmb_sclk_slv { - mux { - groups = "tdmb_sclk_slv"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmc_fs_pins: tdmc_fs { - mux { - groups = "tdmc_fs"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_fs_slv_pins: tdmc_fs_slv { - mux { - groups = "tdmc_fs_slv"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_sclk_pins: tdmc_sclk { - mux { - groups = "tdmc_sclk"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_sclk_slv_pins: tdmc_sclk_slv { - mux { - groups = "tdmc_sclk_slv"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_din0_pins: tdmc_din0 { - mux { - groups = "tdmc_din0"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_din1_pins: tdmc_din1 { - mux { - groups = "tdmc_din1"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_din2_pins: tdmc_din2 { - mux { - groups = "tdmc_din2"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_din3_pins: tdmc_din3 { - mux { - groups = "tdmc_din3"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_dout0_pins: tdmc_dout0 { - mux { - groups = "tdmc_dout0"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_dout1_pins: tdmc_dout1 { - mux { - groups = "tdmc_dout1"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_dout2_pins: tdmc_dout2 { - mux { - groups = "tdmc_dout2"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_dout3_pins: tdmc_dout3 { - mux { - groups = "tdmc_dout3"; - function = "tdmc"; - bias-disable; - }; - }; - - uart_a_pins: uart_a { - mux { - groups = "uart_tx_a", - "uart_rx_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a_cts_rts_pins: uart_a_cts_rts { - mux { - groups = "uart_cts_a", - "uart_rts_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_b_x_pins: uart_b_x { - mux { - groups = "uart_tx_b_x", - "uart_rx_b_x"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_x_cts_rts_pins: uart_b_x_cts_rts { - mux { - groups = "uart_cts_b_x", - "uart_rts_b_x"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_z_pins: uart_b_z { - mux { - groups = "uart_tx_b_z", - "uart_rx_b_z"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_z_cts_rts_pins: uart_b_z_cts_rts { - mux { - groups = "uart_cts_b_z", - "uart_rts_b_z"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_ao_b_z_pins: uart_ao_b_z { - mux { - groups = "uart_ao_tx_b_z", - "uart_ao_rx_b_z"; - function = "uart_ao_b_z"; - bias-disable; - }; - }; - - uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { - mux { - groups = "uart_ao_cts_b_z", - "uart_ao_rts_b_z"; - function = "uart_ao_b_z"; - bias-disable; - }; - }; - }; - }; - - hiubus: bus@ff63c000 { - compatible = "simple-bus"; - reg = <0x0 0xff63c000 0x0 0x1c00>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; - - sysctrl: system-controller@0 { - compatible = "amlogic,meson-axg-hhi-sysctrl", - "simple-mfd", "syscon"; - reg = <0 0 0 0x400>; - - clkc: clock-controller { - compatible = "amlogic,axg-clkc"; - #clock-cells = <1>; - clocks = <&xtal>; - clock-names = "xtal"; - }; - - pwrc: power-controller { - compatible = "amlogic,meson-axg-pwrc"; - #power-domain-cells = <1>; - amlogic,ao-sysctrl = <&sysctrl_AO>; - resets = <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_VCBUS>, - <&reset RESET_VENCL>, - <&reset RESET_VID_LOCK>; - reset-names = "viu", "venc", "vcbus", - "vencl", "vid_lock"; - clocks = <&clkc CLKID_VPU>, - <&clkc CLKID_VAPB>; - clock-names = "vpu", "vapb"; - /* - * VPU clocking is provided by two identical clock paths - * VPU_0 and VPU_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - * Same for VAPB but with a final gate after the glitch free mux. - */ - assigned-clocks = <&clkc CLKID_VPU_0_SEL>, - <&clkc CLKID_VPU_0>, - <&clkc CLKID_VPU>, /* Glitch free mux */ - <&clkc CLKID_VAPB_0_SEL>, - <&clkc CLKID_VAPB_0>, - <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>, - <0>, /* Do Nothing */ - <&clkc CLKID_VPU_0>, - <&clkc CLKID_FCLK_DIV4>, - <0>, /* Do Nothing */ - <&clkc CLKID_VAPB_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <250000000>, - <0>, /* Do Nothing */ - <0>, /* Do Nothing */ - <250000000>, - <0>; /* Do Nothing */ - }; - - mipi_pcie_analog_dphy: phy { - compatible = "amlogic,axg-mipi-pcie-analog-phy"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - mailbox: mailbox@ff63c404 { - compatible = "amlogic,meson-gxbb-mhu"; - reg = <0 0xff63c404 0 0x4c>; - interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; - #mbox-cells = <1>; - }; - - mipi_dphy: phy@ff640000 { - compatible = "amlogic,axg-mipi-dphy"; - reg = <0x0 0xff640000 0x0 0x100>; - clocks = <&clkc CLKID_MIPI_DSI_PHY>; - clock-names = "pclk"; - resets = <&reset RESET_MIPI_PHY>; - reset-names = "phy"; - phys = <&mipi_pcie_analog_dphy>; - phy-names = "analog"; - #phy-cells = <0>; - status = "disabled"; - }; - - audio: bus@ff642000 { - compatible = "simple-bus"; - reg = <0x0 0xff642000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; - - clkc_audio: clock-controller@0 { - compatible = "amlogic,axg-audio-clkc"; - reg = <0x0 0x0 0x0 0xb4>; - #clock-cells = <1>; - - clocks = <&clkc CLKID_AUDIO>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL3>, - <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_FCLK_DIV3>, - <&clkc CLKID_FCLK_DIV4>, - <&clkc CLKID_GP0_PLL>; - clock-names = "pclk", - "mst_in0", - "mst_in1", - "mst_in2", - "mst_in3", - "mst_in4", - "mst_in5", - "mst_in6", - "mst_in7"; - - resets = <&reset RESET_AUDIO>; - }; - - toddr_a: audio-controller@100 { - compatible = "amlogic,axg-toddr"; - reg = <0x0 0x100 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_A"; - interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_A>; - resets = <&arb AXG_ARB_TODDR_A>; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - toddr_b: audio-controller@140 { - compatible = "amlogic,axg-toddr"; - reg = <0x0 0x140 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_B"; - interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_B>; - resets = <&arb AXG_ARB_TODDR_B>; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - toddr_c: audio-controller@180 { - compatible = "amlogic,axg-toddr"; - reg = <0x0 0x180 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_C"; - interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_C>; - resets = <&arb AXG_ARB_TODDR_C>; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_a: audio-controller@1c0 { - compatible = "amlogic,axg-frddr"; - reg = <0x0 0x1c0 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_A"; - interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; - resets = <&arb AXG_ARB_FRDDR_A>; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - frddr_b: audio-controller@200 { - compatible = "amlogic,axg-frddr"; - reg = <0x0 0x200 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_B"; - interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; - resets = <&arb AXG_ARB_FRDDR_B>; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_c: audio-controller@240 { - compatible = "amlogic,axg-frddr"; - reg = <0x0 0x240 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_C"; - interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; - resets = <&arb AXG_ARB_FRDDR_C>; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - arb: reset-controller@280 { - compatible = "amlogic,meson-axg-audio-arb"; - reg = <0x0 0x280 0x0 0x4>; - #reset-cells = <1>; - clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; - }; - - tdmin_a: audio-controller@300 { - compatible = "amlogic,axg-tdmin"; - reg = <0x0 0x300 0x0 0x40>; - sound-name-prefix = "TDMIN_A"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_b: audio-controller@340 { - compatible = "amlogic,axg-tdmin"; - reg = <0x0 0x340 0x0 0x40>; - sound-name-prefix = "TDMIN_B"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_c: audio-controller@380 { - compatible = "amlogic,axg-tdmin"; - reg = <0x0 0x380 0x0 0x40>; - sound-name-prefix = "TDMIN_C"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_lb: audio-controller@3c0 { - compatible = "amlogic,axg-tdmin"; - reg = <0x0 0x3c0 0x0 0x40>; - sound-name-prefix = "TDMIN_LB"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - spdifin: audio-controller@400 { - compatible = "amlogic,axg-spdifin"; - reg = <0x0 0x400 0x0 0x30>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFIN"; - interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, - <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; - clock-names = "pclk", "refclk"; - status = "disabled"; - }; - - spdifout: audio-controller@480 { - compatible = "amlogic,axg-spdifout"; - reg = <0x0 0x480 0x0 0x50>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFOUT"; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, - <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; - clock-names = "pclk", "mclk"; - status = "disabled"; - }; - - tdmout_a: audio-controller@500 { - compatible = "amlogic,axg-tdmout"; - reg = <0x0 0x500 0x0 0x40>; - sound-name-prefix = "TDMOUT_A"; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_b: audio-controller@540 { - compatible = "amlogic,axg-tdmout"; - reg = <0x0 0x540 0x0 0x40>; - sound-name-prefix = "TDMOUT_B"; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_c: audio-controller@580 { - compatible = "amlogic,axg-tdmout"; - reg = <0x0 0x580 0x0 0x40>; - sound-name-prefix = "TDMOUT_C"; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - }; - - aobus: bus@ff800000 { - compatible = "simple-bus"; - reg = <0x0 0xff800000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; - - sysctrl_AO: sys-ctrl@0 { - compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; - reg = <0x0 0x0 0x0 0x100>; - - clkc_AO: clock-controller { - compatible = "amlogic,meson-axg-aoclkc"; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; - }; - }; - - pinctrl_aobus: pinctrl@14 { - compatible = "amlogic,meson-axg-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x00014 0x0 0x8>, - <0x0 0x0002c 0x0 0x4>, - <0x0 0x00024 0x0 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 0 15>; - }; - - i2c_ao_sck_4_pins: i2c_ao_sck_4 { - mux { - groups = "i2c_ao_sck_4"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sck_8_pins: i2c_ao_sck_8 { - mux { - groups = "i2c_ao_sck_8"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sck_10_pins: i2c_ao_sck_10 { - mux { - groups = "i2c_ao_sck_10"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sda_5_pins: i2c_ao_sda_5 { - mux { - groups = "i2c_ao_sda_5"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sda_9_pins: i2c_ao_sda_9 { - mux { - groups = "i2c_ao_sda_9"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sda_11_pins: i2c_ao_sda_11 { - mux { - groups = "i2c_ao_sda_11"; - function = "i2c_ao"; - bias-disable; - }; - }; - - remote_input_ao_pins: remote_input_ao { - mux { - groups = "remote_input_ao"; - function = "remote_input_ao"; - bias-disable; - }; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_ao_tx_a", - "uart_ao_rx_a"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { - mux { - groups = "uart_ao_cts_a", - "uart_ao_rts_a"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - uart_ao_b_pins: uart_ao_b { - mux { - groups = "uart_ao_tx_b", - "uart_ao_rx_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { - mux { - groups = "uart_ao_cts_b", - "uart_ao_rts_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - }; - - sec_AO: ao-secure@140 { - compatible = "amlogic,meson-gx-ao-secure", "syscon"; - reg = <0x0 0x140 0x0 0x140>; - amlogic,has-chip-id; - }; - - pwm_AO_cd: pwm@2000 { - compatible = "amlogic,meson-axg-ao-pwm"; - reg = <0x0 0x02000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart_AO: serial@3000 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; - reg = <0x0 0x3000 0x0 0x18>; - interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_AO_B: serial@4000 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; - reg = <0x0 0x4000 0x0 0x18>; - interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - i2c_AO: i2c@5000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x05000 0x0 0x20>; - interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_AO_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm_AO_ab: pwm@7000 { - compatible = "amlogic,meson-axg-ao-pwm"; - reg = <0x0 0x07000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - ir: ir@8000 { - compatible = "amlogic,meson-gxbb-ir"; - reg = <0x0 0x8000 0x0 0x20>; - interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - - saradc: adc@9000 { - compatible = "amlogic,meson-axg-saradc", - "amlogic,meson-saradc"; - reg = <0x0 0x9000 0x0 0x38>; - #io-channel-cells = <1>; - interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, - <&clkc_AO CLKID_AO_SAR_ADC>, - <&clkc_AO CLKID_AO_SAR_ADC_CLK>, - <&clkc_AO CLKID_AO_SAR_ADC_SEL>; - clock-names = "clkin", "core", "adc_clk", "adc_sel"; - status = "disabled"; - }; - }; - - ge2d: ge2d@ff940000 { - compatible = "amlogic,axg-ge2d"; - reg = <0x0 0xff940000 0x0 0x10000>; - interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_VAPB>; - resets = <&reset RESET_GE2D>; - }; - - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - reg = <0x0 0xffc01000 0 0x1000>, - <0x0 0xffc02000 0 0x2000>, - <0x0 0xffc04000 0 0x2000>, - <0x0 0xffc06000 0 0x2000>; - interrupt-controller; - interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - - cbus: bus@ffd00000 { - compatible = "simple-bus"; - reg = <0x0 0xffd00000 0x0 0x25000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; - - reset: reset-controller@1004 { - compatible = "amlogic,meson-axg-reset"; - reg = <0x0 0x01004 0x0 0x9c>; - #reset-cells = <1>; - }; - - gpio_intc: interrupt-controller@f080 { - compatible = "amlogic,meson-axg-gpio-intc", - "amlogic,meson-gpio-intc"; - reg = <0x0 0xf080 0x0 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; - }; - - watchdog@f0d0 { - compatible = "amlogic,meson-gxbb-wdt"; - reg = <0x0 0xf0d0 0x0 0x10>; - clocks = <&xtal>; - }; - - pwm_ab: pwm@1b000 { - compatible = "amlogic,meson-axg-ee-pwm"; - reg = <0x0 0x1b000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@1a000 { - compatible = "amlogic,meson-axg-ee-pwm"; - reg = <0x0 0x1a000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - spicc0: spi@13000 { - compatible = "amlogic,meson-axg-spicc"; - reg = <0x0 0x13000 0x0 0x3c>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLKID_SPICC0>; - clock-names = "core"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spicc1: spi@15000 { - compatible = "amlogic,meson-axg-spicc"; - reg = <0x0 0x15000 0x0 0x3c>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLKID_SPICC1>; - clock-names = "core"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - clk_msr: clock-measure@18000 { - compatible = "amlogic,meson-axg-clk-measure"; - reg = <0x0 0x18000 0x0 0x10>; - }; - - i2c3: i2c@1c000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x1c000 0x0 0x20>; - interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@1d000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x1d000 0x0 0x20>; - interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@1e000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x1e000 0x0 0x20>; - interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@1f000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x1f000 0x0 0x20>; - interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart_B: serial@23000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x23000 0x0 0x18>; - interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - }; - - uart_A: serial@24000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x24000 0x0 0x18>; - interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - fifo-size = <128>; - }; - }; - - apb: bus@ffe00000 { - compatible = "simple-bus"; - reg = <0x0 0xffe00000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; - - sd_emmc_b: sd@5000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0x5000 0x0 0x800>; - interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_B>; - }; - - sd_emmc_c: mmc@7000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0x7000 0x0 0x800>; - interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_C>; - }; - - usb2_phy1: phy@9020 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x9020 0x0 0x20>; - clocks = <&clkc CLKID_USB>; - clock-names = "phy"; - resets = <&reset RESET_USB_OTG>; - reset-names = "phy"; - }; - }; - - sram: sram@fffc0000 { - compatible = "mmio-sram"; - reg = <0x0 0xfffc0000 0x0 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xfffc0000 0x20000>; - - cpu_scp_lpri: scp-sram@13000 { - compatible = "amlogic,meson-axg-scp-shmem"; - reg = <0x13000 0x400>; - }; - - cpu_scp_hpri: scp-sram@13400 { - compatible = "amlogic,meson-axg-scp-shmem"; - reg = <0x13400 0x400>; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; -}; diff --git a/arch/arm/dts/meson-g12-common.dtsi b/arch/arm/dts/meson-g12-common.dtsi deleted file mode 100644 index 9dbd50820b1..00000000000 --- a/arch/arm/dts/meson-g12-common.dtsi +++ /dev/null @@ -1,2493 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - */ - -#include <dt-bindings/phy/phy.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/clock/g12a-clkc.h> -#include <dt-bindings/clock/g12a-aoclkc.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - mmc0 = &sd_emmc_b; /* SD card */ - mmc1 = &sd_emmc_c; /* eMMC */ - mmc2 = &sd_emmc_a; /* SDIO */ - }; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - simplefb_cvbs: framebuffer-cvbs { - compatible = "amlogic,simple-framebuffer", - "simple-framebuffer"; - amlogic,pipeline = "vpu-cvbs"; - clocks = <&clkc CLKID_HDMI>, - <&clkc CLKID_HTX_PCLK>, - <&clkc CLKID_VPU_INTR>; - status = "disabled"; - }; - - simplefb_hdmi: framebuffer-hdmi { - compatible = "amlogic,simple-framebuffer", - "simple-framebuffer"; - amlogic,pipeline = "vpu-hdmi"; - clocks = <&clkc CLKID_HDMI>, - <&clkc CLKID_HTX_PCLK>, - <&clkc CLKID_VPU_INTR>; - status = "disabled"; - }; - }; - - efuse: efuse { - compatible = "amlogic,meson-gxbb-efuse"; - clocks = <&clkc CLKID_EFUSE>; - #address-cells = <1>; - #size-cells = <1>; - read-only; - secure-monitor = <&sm>; - }; - - gpu_opp_table: opp-table-gpu { - compatible = "operating-points-v2"; - - opp-124999998 { - opp-hz = /bits/ 64 <124999998>; - opp-microvolt = <800000>; - }; - opp-249999996 { - opp-hz = /bits/ 64 <249999996>; - opp-microvolt = <800000>; - }; - opp-285714281 { - opp-hz = /bits/ 64 <285714281>; - opp-microvolt = <800000>; - }; - opp-399999994 { - opp-hz = /bits/ 64 <399999994>; - opp-microvolt = <800000>; - }; - opp-499999992 { - opp-hz = /bits/ 64 <499999992>; - opp-microvolt = <800000>; - }; - opp-666666656 { - opp-hz = /bits/ 64 <666666656>; - opp-microvolt = <800000>; - }; - opp-799999987 { - opp-hz = /bits/ 64 <799999987>; - opp-microvolt = <800000>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@5000000 { - reg = <0x0 0x05000000 0x0 0x300000>; - no-map; - }; - - /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ - secmon_reserved_bl32: secmon@5300000 { - reg = <0x0 0x05300000 0x0 0x2000000>; - no-map; - }; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x0 0x10000000>; - alignment = <0x0 0x400000>; - linux,cma-default; - }; - }; - - sm: secure-monitor { - compatible = "amlogic,meson-gxbb-sm"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - pcie: pcie@fc000000 { - compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; - reg = <0x0 0xfc000000 0x0 0x400000>, - <0x0 0xff648000 0x0 0x2000>, - <0x0 0xfc400000 0x0 0x200000>; - reg-names = "elbi", "cfg", "config"; - interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; - bus-range = <0x0 0xff>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>, - <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; - - clocks = <&clkc CLKID_PCIE_PHY - &clkc CLKID_PCIE_COMB - &clkc CLKID_PCIE_PLL>; - clock-names = "general", - "pclk", - "port"; - resets = <&reset RESET_PCIE_CTRL_A>, - <&reset RESET_PCIE_APB>; - reset-names = "port", - "apb"; - num-lanes = <1>; - phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; - phy-names = "pcie"; - status = "disabled"; - }; - - ethmac: ethernet@ff3f0000 { - compatible = "amlogic,meson-g12a-dwmac", - "snps,dwmac-3.70a", - "snps,dwmac"; - reg = <0x0 0xff3f0000 0x0 0x10000>, - <0x0 0xff634540 0x0 0x8>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "stmmaceth", "clkin0", "clkin1", - "timing-adjustment"; - rx-fifo-depth = <4096>; - tx-fifo-depth = <2048>; - status = "disabled"; - - mdio0: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; - }; - - apb: bus@ff600000 { - compatible = "simple-bus"; - reg = <0x0 0xff600000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; - - hdmi_tx: hdmi-tx@0 { - compatible = "amlogic,meson-g12a-dw-hdmi"; - reg = <0x0 0x0 0x0 0x10000>; - interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; - resets = <&reset RESET_HDMITX_CAPB3>, - <&reset RESET_HDMITX_PHY>, - <&reset RESET_HDMITX>; - reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; - clocks = <&clkc CLKID_HDMI>, - <&clkc CLKID_HTX_PCLK>, - <&clkc CLKID_VPU_INTR>; - clock-names = "isfr", "iahb", "venci"; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <0>; - status = "disabled"; - - /* VPU VENC Input */ - hdmi_tx_venc_port: port@0 { - reg = <0>; - - hdmi_tx_in: endpoint { - remote-endpoint = <&hdmi_tx_out>; - }; - }; - - /* TMDS Output */ - hdmi_tx_tmds_port: port@1 { - reg = <1>; - }; - }; - - apb_efuse: bus@30000 { - compatible = "simple-bus"; - reg = <0x0 0x30000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; - - hwrng: rng@218 { - compatible = "amlogic,meson-rng"; - reg = <0x0 0x218 0x0 0x4>; - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; - }; - }; - - acodec: audio-controller@32000 { - compatible = "amlogic,t9015"; - reg = <0x0 0x32000 0x0 0x14>; - #sound-dai-cells = <0>; - sound-name-prefix = "ACODEC"; - clocks = <&clkc CLKID_AUDIO_CODEC>; - clock-names = "pclk"; - resets = <&reset RESET_AUDIO_CODEC>; - status = "disabled"; - }; - - periphs: bus@34400 { - compatible = "simple-bus"; - reg = <0x0 0x34400 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; - - periphs_pinctrl: pinctrl@40 { - compatible = "amlogic,meson-g12a-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@40 { - reg = <0x0 0x40 0x0 0x4c>, - <0x0 0xe8 0x0 0x18>, - <0x0 0x120 0x0 0x18>, - <0x0 0x2c0 0x0 0x40>, - <0x0 0x340 0x0 0x1c>; - reg-names = "gpio", - "pull", - "pull-enable", - "mux", - "ds"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&periphs_pinctrl 0 0 86>; - }; - - cec_ao_a_h_pins: cec_ao_a_h { - mux { - groups = "cec_ao_a_h"; - function = "cec_ao_a_h"; - bias-disable; - }; - }; - - cec_ao_b_h_pins: cec_ao_b_h { - mux { - groups = "cec_ao_b_h"; - function = "cec_ao_b_h"; - bias-disable; - }; - }; - - emmc_ctrl_pins: emmc-ctrl { - mux-0 { - groups = "emmc_cmd"; - function = "emmc"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - - mux-1 { - groups = "emmc_clk"; - function = "emmc"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - emmc_data_4b_pins: emmc-data-4b { - mux-0 { - groups = "emmc_nand_d0", - "emmc_nand_d1", - "emmc_nand_d2", - "emmc_nand_d3"; - function = "emmc"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - }; - - emmc_data_8b_pins: emmc-data-8b { - mux-0 { - groups = "emmc_nand_d0", - "emmc_nand_d1", - "emmc_nand_d2", - "emmc_nand_d3", - "emmc_nand_d4", - "emmc_nand_d5", - "emmc_nand_d6", - "emmc_nand_d7"; - function = "emmc"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - }; - - emmc_ds_pins: emmc-ds { - mux { - groups = "emmc_nand_ds"; - function = "emmc"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - emmc_clk_gate_pins: emmc_clk_gate { - mux { - groups = "BOOT_8"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - hdmitx_ddc_pins: hdmitx_ddc { - mux { - groups = "hdmitx_sda", - "hdmitx_sck"; - function = "hdmitx"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - hdmitx_hpd_pins: hdmitx_hpd { - mux { - groups = "hdmitx_hpd_in"; - function = "hdmitx"; - bias-disable; - }; - }; - - - i2c0_sda_c_pins: i2c0-sda-c { - mux { - groups = "i2c0_sda_c"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - - }; - }; - - i2c0_sck_c_pins: i2c0-sck-c { - mux { - groups = "i2c0_sck_c"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sda_z0_pins: i2c0-sda-z0 { - mux { - groups = "i2c0_sda_z0"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sck_z1_pins: i2c0-sck-z1 { - mux { - groups = "i2c0_sck_z1"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sda_z7_pins: i2c0-sda-z7 { - mux { - groups = "i2c0_sda_z7"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sda_z8_pins: i2c0-sda-z8 { - mux { - groups = "i2c0_sda_z8"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sda_x_pins: i2c1-sda-x { - mux { - groups = "i2c1_sda_x"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sck_x_pins: i2c1-sck-x { - mux { - groups = "i2c1_sck_x"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sda_h2_pins: i2c1-sda-h2 { - mux { - groups = "i2c1_sda_h2"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sck_h3_pins: i2c1-sck-h3 { - mux { - groups = "i2c1_sck_h3"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sda_h6_pins: i2c1-sda-h6 { - mux { - groups = "i2c1_sda_h6"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sck_h7_pins: i2c1-sck-h7 { - mux { - groups = "i2c1_sck_h7"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sda_x_pins: i2c2-sda-x { - mux { - groups = "i2c2_sda_x"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sck_x_pins: i2c2-sck-x { - mux { - groups = "i2c2_sck_x"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sda_z_pins: i2c2-sda-z { - mux { - groups = "i2c2_sda_z"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sck_z_pins: i2c2-sck-z { - mux { - groups = "i2c2_sck_z"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sda_h_pins: i2c3-sda-h { - mux { - groups = "i2c3_sda_h"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sck_h_pins: i2c3-sck-h { - mux { - groups = "i2c3_sck_h"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sda_a_pins: i2c3-sda-a { - mux { - groups = "i2c3_sda_a"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sck_a_pins: i2c3-sck-a { - mux { - groups = "i2c3_sck_a"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk0_a_pins: mclk0-a { - mux { - groups = "mclk0_a"; - function = "mclk0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk1_a_pins: mclk1-a { - mux { - groups = "mclk1_a"; - function = "mclk1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk1_x_pins: mclk1-x { - mux { - groups = "mclk1_x"; - function = "mclk1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk1_z_pins: mclk1-z { - mux { - groups = "mclk1_z"; - function = "mclk1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - nor_pins: nor { - mux { - groups = "nor_d", - "nor_q", - "nor_c", - "nor_cs"; - function = "nor"; - bias-disable; - }; - }; - - pdm_din0_a_pins: pdm-din0-a { - mux { - groups = "pdm_din0_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_c_pins: pdm-din0-c { - mux { - groups = "pdm_din0_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_x_pins: pdm-din0-x { - mux { - groups = "pdm_din0_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_z_pins: pdm-din0-z { - mux { - groups = "pdm_din0_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_a_pins: pdm-din1-a { - mux { - groups = "pdm_din1_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_c_pins: pdm-din1-c { - mux { - groups = "pdm_din1_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_x_pins: pdm-din1-x { - mux { - groups = "pdm_din1_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_z_pins: pdm-din1-z { - mux { - groups = "pdm_din1_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_a_pins: pdm-din2-a { - mux { - groups = "pdm_din2_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_c_pins: pdm-din2-c { - mux { - groups = "pdm_din2_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_x_pins: pdm-din2-x { - mux { - groups = "pdm_din2_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_z_pins: pdm-din2-z { - mux { - groups = "pdm_din2_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_a_pins: pdm-din3-a { - mux { - groups = "pdm_din3_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_c_pins: pdm-din3-c { - mux { - groups = "pdm_din3_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_x_pins: pdm-din3-x { - mux { - groups = "pdm_din3_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_z_pins: pdm-din3-z { - mux { - groups = "pdm_din3_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_dclk_a_pins: pdm-dclk-a { - mux { - groups = "pdm_dclk_a"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pdm_dclk_c_pins: pdm-dclk-c { - mux { - groups = "pdm_dclk_c"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pdm_dclk_x_pins: pdm-dclk-x { - mux { - groups = "pdm_dclk_x"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pdm_dclk_z_pins: pdm-dclk-z { - mux { - groups = "pdm_dclk_z"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pwm_a_pins: pwm-a { - mux { - groups = "pwm_a"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_b_x7_pins: pwm-b-x7 { - mux { - groups = "pwm_b_x7"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_b_x19_pins: pwm-b-x19 { - mux { - groups = "pwm_b_x19"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_c_c_pins: pwm-c-c { - mux { - groups = "pwm_c_c"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x5_pins: pwm-c-x5 { - mux { - groups = "pwm_c_x5"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x8_pins: pwm-c-x8 { - mux { - groups = "pwm_c_x8"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_d_x3_pins: pwm-d-x3 { - mux { - groups = "pwm_d_x3"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_d_x6_pins: pwm-d-x6 { - mux { - groups = "pwm_d_x6"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_e_pins: pwm-e { - mux { - groups = "pwm_e"; - function = "pwm_e"; - bias-disable; - }; - }; - - pwm_f_z_pins: pwm-f-z { - mux { - groups = "pwm_f_z"; - function = "pwm_f"; - bias-disable; - }; - }; - - pwm_f_a_pins: pwm-f-a { - mux { - groups = "pwm_f_a"; - function = "pwm_f"; - bias-disable; - }; - }; - - pwm_f_x_pins: pwm-f-x { - mux { - groups = "pwm_f_x"; - function = "pwm_f"; - bias-disable; - }; - }; - - pwm_f_h_pins: pwm-f-h { - mux { - groups = "pwm_f_h"; - function = "pwm_f"; - bias-disable; - }; - }; - - sdcard_c_pins: sdcard_c { - mux-0 { - groups = "sdcard_d0_c", - "sdcard_d1_c", - "sdcard_d2_c", - "sdcard_d3_c", - "sdcard_cmd_c"; - function = "sdcard"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - - mux-1 { - groups = "sdcard_clk_c"; - function = "sdcard"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - sdcard_clk_gate_c_pins: sdcard_clk_gate_c { - mux { - groups = "GPIOC_4"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - sdcard_z_pins: sdcard_z { - mux-0 { - groups = "sdcard_d0_z", - "sdcard_d1_z", - "sdcard_d2_z", - "sdcard_d3_z", - "sdcard_cmd_z"; - function = "sdcard"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - - mux-1 { - groups = "sdcard_clk_z"; - function = "sdcard"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - sdcard_clk_gate_z_pins: sdcard_clk_gate_z { - mux { - groups = "GPIOZ_6"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - sdio_pins: sdio { - mux { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_clk", - "sdio_cmd"; - function = "sdio"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - sdio_clk_gate_pins: sdio_clk_gate { - mux { - groups = "GPIOX_4"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - spdif_in_a10_pins: spdif-in-a10 { - mux { - groups = "spdif_in_a10"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a12_pins: spdif-in-a12 { - mux { - groups = "spdif_in_a12"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_h_pins: spdif-in-h { - mux { - groups = "spdif_in_h"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_out_h_pins: spdif-out-h { - mux { - groups = "spdif_out_h"; - function = "spdif_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - spdif_out_a11_pins: spdif-out-a11 { - mux { - groups = "spdif_out_a11"; - function = "spdif_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - spdif_out_a13_pins: spdif-out-a13 { - mux { - groups = "spdif_out_a13"; - function = "spdif_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - spicc0_x_pins: spicc0-x { - mux { - groups = "spi0_mosi_x", - "spi0_miso_x", - "spi0_clk_x"; - function = "spi0"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - spicc0_ss0_x_pins: spicc0-ss0-x { - mux { - groups = "spi0_ss0_x"; - function = "spi0"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - spicc0_c_pins: spicc0-c { - mux { - groups = "spi0_mosi_c", - "spi0_miso_c", - "spi0_ss0_c", - "spi0_clk_c"; - function = "spi0"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - spicc1_pins: spicc1 { - mux { - groups = "spi1_mosi", - "spi1_miso", - "spi1_clk"; - function = "spi1"; - drive-strength-microamp = <4000>; - }; - }; - - spicc1_ss0_pins: spicc1-ss0 { - mux { - groups = "spi1_ss0"; - function = "spi1"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - tdm_a_din0_pins: tdm-a-din0 { - mux { - groups = "tdm_a_din0"; - function = "tdm_a"; - bias-disable; - }; - }; - - - tdm_a_din1_pins: tdm-a-din1 { - mux { - groups = "tdm_a_din1"; - function = "tdm_a"; - bias-disable; - }; - }; - - tdm_a_dout0_pins: tdm-a-dout0 { - mux { - groups = "tdm_a_dout0"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_dout1_pins: tdm-a-dout1 { - mux { - groups = "tdm_a_dout1"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_fs_pins: tdm-a-fs { - mux { - groups = "tdm_a_fs"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_sclk_pins: tdm-a-sclk { - mux { - groups = "tdm_a_sclk"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_slv_fs_pins: tdm-a-slv-fs { - mux { - groups = "tdm_a_slv_fs"; - function = "tdm_a"; - bias-disable; - }; - }; - - - tdm_a_slv_sclk_pins: tdm-a-slv-sclk { - mux { - groups = "tdm_a_slv_sclk"; - function = "tdm_a"; - bias-disable; - }; - }; - - tdm_b_din0_pins: tdm-b-din0 { - mux { - groups = "tdm_b_din0"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din1_pins: tdm-b-din1 { - mux { - groups = "tdm_b_din1"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din2_pins: tdm-b-din2 { - mux { - groups = "tdm_b_din2"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din3_a_pins: tdm-b-din3-a { - mux { - groups = "tdm_b_din3_a"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din3_h_pins: tdm-b-din3-h { - mux { - groups = "tdm_b_din3_h"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_dout0_pins: tdm-b-dout0 { - mux { - groups = "tdm_b_dout0"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout1_pins: tdm-b-dout1 { - mux { - groups = "tdm_b_dout1"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout2_pins: tdm-b-dout2 { - mux { - groups = "tdm_b_dout2"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout3_a_pins: tdm-b-dout3-a { - mux { - groups = "tdm_b_dout3_a"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout3_h_pins: tdm-b-dout3-h { - mux { - groups = "tdm_b_dout3_h"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_fs_pins: tdm-b-fs { - mux { - groups = "tdm_b_fs"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_sclk_pins: tdm-b-sclk { - mux { - groups = "tdm_b_sclk"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_slv_fs_pins: tdm-b-slv-fs { - mux { - groups = "tdm_b_slv_fs"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_slv_sclk_pins: tdm-b-slv-sclk { - mux { - groups = "tdm_b_slv_sclk"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_c_din0_a_pins: tdm-c-din0-a { - mux { - groups = "tdm_c_din0_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din0_z_pins: tdm-c-din0-z { - mux { - groups = "tdm_c_din0_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din1_a_pins: tdm-c-din1-a { - mux { - groups = "tdm_c_din1_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din1_z_pins: tdm-c-din1-z { - mux { - groups = "tdm_c_din1_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din2_a_pins: tdm-c-din2-a { - mux { - groups = "tdm_c_din2_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - eth_leds_pins: eth-leds { - mux { - groups = "eth_link_led", - "eth_act_led"; - function = "eth"; - bias-disable; - }; - }; - - eth_pins: eth { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_rgmii_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_txen", - "eth_txd0", - "eth_txd1"; - function = "eth"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - eth_rgmii_pins: eth-rgmii { - mux { - groups = "eth_rxd2_rgmii", - "eth_rxd3_rgmii", - "eth_rgmii_tx_clk", - "eth_txd2_rgmii", - "eth_txd3_rgmii"; - function = "eth"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - tdm_c_din2_z_pins: tdm-c-din2-z { - mux { - groups = "tdm_c_din2_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din3_a_pins: tdm-c-din3-a { - mux { - groups = "tdm_c_din3_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din3_z_pins: tdm-c-din3-z { - mux { - groups = "tdm_c_din3_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_dout0_a_pins: tdm-c-dout0-a { - mux { - groups = "tdm_c_dout0_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout0_z_pins: tdm-c-dout0-z { - mux { - groups = "tdm_c_dout0_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout1_a_pins: tdm-c-dout1-a { - mux { - groups = "tdm_c_dout1_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout1_z_pins: tdm-c-dout1-z { - mux { - groups = "tdm_c_dout1_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout2_a_pins: tdm-c-dout2-a { - mux { - groups = "tdm_c_dout2_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout2_z_pins: tdm-c-dout2-z { - mux { - groups = "tdm_c_dout2_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout3_a_pins: tdm-c-dout3-a { - mux { - groups = "tdm_c_dout3_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout3_z_pins: tdm-c-dout3-z { - mux { - groups = "tdm_c_dout3_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_fs_a_pins: tdm-c-fs-a { - mux { - groups = "tdm_c_fs_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_fs_z_pins: tdm-c-fs-z { - mux { - groups = "tdm_c_fs_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_sclk_a_pins: tdm-c-sclk-a { - mux { - groups = "tdm_c_sclk_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_sclk_z_pins: tdm-c-sclk-z { - mux { - groups = "tdm_c_sclk_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { - mux { - groups = "tdm_c_slv_fs_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { - mux { - groups = "tdm_c_slv_fs_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { - mux { - groups = "tdm_c_slv_sclk_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { - mux { - groups = "tdm_c_slv_sclk_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - uart_a_pins: uart-a { - mux { - groups = "uart_a_tx", - "uart_a_rx"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a_cts_rts_pins: uart-a-cts-rts { - mux { - groups = "uart_a_cts", - "uart_a_rts"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_b_pins: uart-b { - mux { - groups = "uart_b_tx", - "uart_b_rx"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_c_pins: uart-c { - mux { - groups = "uart_c_tx", - "uart_c_rx"; - function = "uart_c"; - bias-disable; - }; - }; - - uart_c_cts_rts_pins: uart-c-cts-rts { - mux { - groups = "uart_c_cts", - "uart_c_rts"; - function = "uart_c"; - bias-disable; - }; - }; - }; - }; - - cpu_temp: temperature-sensor@34800 { - compatible = "amlogic,g12a-cpu-thermal", - "amlogic,g12a-thermal"; - reg = <0x0 0x34800 0x0 0x50>; - interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_TS>; - #thermal-sensor-cells = <0>; - amlogic,ao-secure = <&sec_AO>; - }; - - ddr_temp: temperature-sensor@34c00 { - compatible = "amlogic,g12a-ddr-thermal", - "amlogic,g12a-thermal"; - reg = <0x0 0x34c00 0x0 0x50>; - interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_TS>; - #thermal-sensor-cells = <0>; - amlogic,ao-secure = <&sec_AO>; - }; - - usb2_phy0: phy@36000 { - compatible = "amlogic,g12a-usb2-phy"; - reg = <0x0 0x36000 0x0 0x2000>; - clocks = <&xtal>; - clock-names = "xtal"; - resets = <&reset RESET_USB_PHY20>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - dmc: bus@38000 { - compatible = "simple-bus"; - reg = <0x0 0x38000 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; - - canvas: video-lut@48 { - compatible = "amlogic,canvas"; - reg = <0x0 0x48 0x0 0x14>; - }; - }; - - usb2_phy1: phy@3a000 { - compatible = "amlogic,g12a-usb2-phy"; - reg = <0x0 0x3a000 0x0 0x2000>; - clocks = <&xtal>; - clock-names = "xtal"; - resets = <&reset RESET_USB_PHY21>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - hiu: bus@3c000 { - compatible = "simple-bus"; - reg = <0x0 0x3c000 0x0 0x1400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; - - hhi: system-controller@0 { - compatible = "amlogic,meson-gx-hhi-sysctrl", - "simple-mfd", "syscon"; - reg = <0 0 0 0x400>; - - clkc: clock-controller { - compatible = "amlogic,g12a-clkc"; - #clock-cells = <1>; - clocks = <&xtal>; - clock-names = "xtal"; - }; - - pwrc: power-controller { - compatible = "amlogic,meson-g12a-pwrc"; - #power-domain-cells = <1>; - amlogic,ao-sysctrl = <&rti>; - resets = <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_VCBUS>, - <&reset RESET_BT656>, - <&reset RESET_RDMA>, - <&reset RESET_VENCI>, - <&reset RESET_VENCP>, - <&reset RESET_VDAC>, - <&reset RESET_VDI6>, - <&reset RESET_VENCL>, - <&reset RESET_VID_LOCK>; - reset-names = "viu", "venc", "vcbus", "bt656", - "rdma", "venci", "vencp", "vdac", - "vdi6", "vencl", "vid_lock"; - clocks = <&clkc CLKID_VPU>, - <&clkc CLKID_VAPB>; - clock-names = "vpu", "vapb"; - /* - * VPU clocking is provided by two identical clock paths - * VPU_0 and VPU_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - * Same for VAPB but with a final gate after the glitch free mux. - */ - assigned-clocks = <&clkc CLKID_VPU_0_SEL>, - <&clkc CLKID_VPU_0>, - <&clkc CLKID_VPU>, /* Glitch free mux */ - <&clkc CLKID_VAPB_0_SEL>, - <&clkc CLKID_VAPB_0>, - <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_VPU_0>, - <&clkc CLKID_FCLK_DIV4>, - <0>, /* Do Nothing */ - <&clkc CLKID_VAPB_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>, /* Do Nothing */ - <0>, /* Do Nothing */ - <250000000>, - <0>; /* Do Nothing */ - }; - }; - }; - - usb3_pcie_phy: phy@46000 { - compatible = "amlogic,g12a-usb3-pcie-phy"; - reg = <0x0 0x46000 0x0 0x2000>; - clocks = <&clkc CLKID_PCIE_PLL>; - clock-names = "ref_clk"; - resets = <&reset RESET_PCIE_PHY>; - reset-names = "phy"; - assigned-clocks = <&clkc CLKID_PCIE_PLL>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - }; - - eth_phy: mdio-multiplexer@4c000 { - compatible = "amlogic,g12a-mdio-mux"; - reg = <0x0 0x4c000 0x0 0xa4>; - clocks = <&clkc CLKID_ETH_PHY>, - <&xtal>, - <&clkc CLKID_MPLL_50M>; - clock-names = "pclk", "clkin0", "clkin1"; - mdio-parent-bus = <&mdio0>; - #address-cells = <1>; - #size-cells = <0>; - - ext_mdio: mdio@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - int_mdio: mdio@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - internal_ephy: ethernet_phy@8 { - compatible = "ethernet-phy-id0180.3301", - "ethernet-phy-ieee802.3-c22"; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <8>; - max-speed = <100>; - }; - }; - }; - }; - - pmu: pmu@ff638000 { - reg = <0x0 0xff638000 0x0 0x100>, - <0x0 0xff638c00 0x0 0x100>; - interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; - }; - - aobus: bus@ff800000 { - compatible = "simple-bus"; - reg = <0x0 0xff800000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; - - rti: sys-ctrl@0 { - compatible = "amlogic,meson-gx-ao-sysctrl", - "simple-mfd", "syscon"; - reg = <0x0 0x0 0x0 0x100>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; - - clkc_AO: clock-controller { - compatible = "amlogic,meson-g12a-aoclkc"; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; - }; - - ao_pinctrl: pinctrl@14 { - compatible = "amlogic,meson-g12a-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x14 0x0 0x8>, - <0x0 0x1c 0x0 0x8>, - <0x0 0x24 0x0 0x14>; - reg-names = "mux", - "ds", - "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&ao_pinctrl 0 0 15>; - }; - - i2c_ao_sck_pins: i2c_ao_sck_pins { - mux { - groups = "i2c_ao_sck"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c_ao_sda_pins: i2c_ao_sda { - mux { - groups = "i2c_ao_sda"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c_ao_sck_e_pins: i2c_ao_sck_e { - mux { - groups = "i2c_ao_sck_e"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c_ao_sda_e_pins: i2c_ao_sda_e { - mux { - groups = "i2c_ao_sda_e"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk0_ao_pins: mclk0-ao { - mux { - groups = "mclk0_ao"; - function = "mclk0_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_din0_pins: tdm-ao-b-din0 { - mux { - groups = "tdm_ao_b_din0"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - spdif_ao_out_pins: spdif-ao-out { - mux { - groups = "spdif_ao_out"; - function = "spdif_ao_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - tdm_ao_b_din1_pins: tdm-ao-b-din1 { - mux { - groups = "tdm_ao_b_din1"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - tdm_ao_b_din2_pins: tdm-ao-b-din2 { - mux { - groups = "tdm_ao_b_din2"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { - mux { - groups = "tdm_ao_b_dout0"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { - mux { - groups = "tdm_ao_b_dout1"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { - mux { - groups = "tdm_ao_b_dout2"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_fs_pins: tdm-ao-b-fs { - mux { - groups = "tdm_ao_b_fs"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_sclk_pins: tdm-ao-b-sclk { - mux { - groups = "tdm_ao_b_sclk"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { - mux { - groups = "tdm_ao_b_slv_fs"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { - mux { - groups = "tdm_ao_b_slv_sclk"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - uart_ao_a_pins: uart-a-ao { - mux { - groups = "uart_ao_a_tx", - "uart_ao_a_rx"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { - mux { - groups = "uart_ao_a_cts", - "uart_ao_a_rts"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - uart_ao_b_2_3_pins: uart-ao-b-2-3 { - mux { - groups = "uart_ao_b_tx_2", - "uart_ao_b_rx_3"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_8_9_pins: uart-ao-b-8-9 { - mux { - groups = "uart_ao_b_tx_8", - "uart_ao_b_rx_9"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_cts_rts_pins: uart-ao-b-cts-rts { - mux { - groups = "uart_ao_b_cts", - "uart_ao_b_rts"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - pwm_a_e_pins: pwm-a-e { - mux { - groups = "pwm_a_e"; - function = "pwm_a_e"; - bias-disable; - }; - }; - - pwm_ao_a_pins: pwm-ao-a { - mux { - groups = "pwm_ao_a"; - function = "pwm_ao_a"; - bias-disable; - }; - }; - - pwm_ao_b_pins: pwm-ao-b { - mux { - groups = "pwm_ao_b"; - function = "pwm_ao_b"; - bias-disable; - }; - }; - - pwm_ao_c_4_pins: pwm-ao-c-4 { - mux { - groups = "pwm_ao_c_4"; - function = "pwm_ao_c"; - bias-disable; - }; - }; - - pwm_ao_c_6_pins: pwm-ao-c-6 { - mux { - groups = "pwm_ao_c_6"; - function = "pwm_ao_c"; - bias-disable; - }; - }; - - pwm_ao_d_5_pins: pwm-ao-d-5 { - mux { - groups = "pwm_ao_d_5"; - function = "pwm_ao_d"; - bias-disable; - }; - }; - - pwm_ao_d_10_pins: pwm-ao-d-10 { - mux { - groups = "pwm_ao_d_10"; - function = "pwm_ao_d"; - bias-disable; - }; - }; - - pwm_ao_d_e_pins: pwm-ao-d-e { - mux { - groups = "pwm_ao_d_e"; - function = "pwm_ao_d"; - }; - }; - - remote_input_ao_pins: remote-input-ao { - mux { - groups = "remote_ao_input"; - function = "remote_ao_input"; - bias-disable; - }; - }; - }; - }; - - vrtc: rtc@a8 { - compatible = "amlogic,meson-vrtc"; - reg = <0x0 0x000a8 0x0 0x4>; - }; - - cec_AO: cec@100 { - compatible = "amlogic,meson-gx-ao-cec"; - reg = <0x0 0x00100 0x0 0x14>; - interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_AO CLKID_AO_CEC>; - clock-names = "core"; - status = "disabled"; - }; - - sec_AO: ao-secure@140 { - compatible = "amlogic,meson-gx-ao-secure", "syscon"; - reg = <0x0 0x140 0x0 0x140>; - amlogic,has-chip-id; - }; - - cecb_AO: cec@280 { - compatible = "amlogic,meson-g12a-ao-cec"; - reg = <0x0 0x00280 0x0 0x1c>; - interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; - clock-names = "oscin"; - status = "disabled"; - }; - - pwm_AO_cd: pwm@2000 { - compatible = "amlogic,meson-g12a-ao-pwm-cd"; - reg = <0x0 0x2000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart_AO: serial@3000 { - compatible = "amlogic,meson-gx-uart", - "amlogic,meson-ao-uart"; - reg = <0x0 0x3000 0x0 0x18>; - interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_AO_B: serial@4000 { - compatible = "amlogic,meson-gx-uart", - "amlogic,meson-ao-uart"; - reg = <0x0 0x4000 0x0 0x18>; - interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - i2c_AO: i2c@5000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x05000 0x0 0x20>; - interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - pwm_AO_ab: pwm@7000 { - compatible = "amlogic,meson-g12a-ao-pwm-ab"; - reg = <0x0 0x7000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - ir: ir@8000 { - compatible = "amlogic,meson-gxbb-ir"; - reg = <0x0 0x8000 0x0 0x20>; - interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - - saradc: adc@9000 { - compatible = "amlogic,meson-g12a-saradc", - "amlogic,meson-saradc"; - reg = <0x0 0x9000 0x0 0x48>; - #io-channel-cells = <1>; - interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, - <&clkc_AO CLKID_AO_SAR_ADC>, - <&clkc_AO CLKID_AO_SAR_ADC_CLK>, - <&clkc_AO CLKID_AO_SAR_ADC_SEL>; - clock-names = "clkin", "core", "adc_clk", "adc_sel"; - status = "disabled"; - }; - }; - - vdec: video-decoder@ff620000 { - compatible = "amlogic,g12a-vdec"; - reg = <0x0 0xff620000 0x0 0x10000>, - <0x0 0xffd0e180 0x0 0xe4>; - reg-names = "dos", "esparser"; - interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "vdec", "esparser"; - - amlogic,ao-sysctrl = <&rti>; - amlogic,canvas = <&canvas>; - - clocks = <&clkc CLKID_PARSER>, - <&clkc CLKID_DOS>, - <&clkc CLKID_VDEC_1>, - <&clkc CLKID_VDEC_HEVC>, - <&clkc CLKID_VDEC_HEVCF>; - clock-names = "dos_parser", "dos", "vdec_1", - "vdec_hevc", "vdec_hevcf"; - resets = <&reset RESET_PARSER>; - reset-names = "esparser"; - }; - - vpu: vpu@ff900000 { - compatible = "amlogic,meson-g12a-vpu"; - reg = <0x0 0xff900000 0x0 0x100000>, - <0x0 0xff63c000 0x0 0x1000>; - reg-names = "vpu", "hhi"; - interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - amlogic,canvas = <&canvas>; - - /* CVBS VDAC output port */ - cvbs_vdac_port: port@0 { - reg = <0>; - }; - - /* HDMI-TX output port */ - hdmi_tx_port: port@1 { - reg = <1>; - - hdmi_tx_out: endpoint { - remote-endpoint = <&hdmi_tx_in>; - }; - }; - }; - - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - reg = <0x0 0xffc01000 0 0x1000>, - <0x0 0xffc02000 0 0x2000>, - <0x0 0xffc04000 0 0x2000>, - <0x0 0xffc06000 0 0x2000>; - interrupt-controller; - interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - - cbus: bus@ffd00000 { - compatible = "simple-bus"; - reg = <0x0 0xffd00000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; - - reset: reset-controller@1004 { - compatible = "amlogic,meson-axg-reset"; - reg = <0x0 0x1004 0x0 0x9c>; - #reset-cells = <1>; - }; - - gpio_intc: interrupt-controller@f080 { - compatible = "amlogic,meson-g12a-gpio-intc", - "amlogic,meson-gpio-intc"; - reg = <0x0 0xf080 0x0 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; - }; - - watchdog: watchdog@f0d0 { - compatible = "amlogic,meson-gxbb-wdt"; - reg = <0x0 0xf0d0 0x0 0x10>; - clocks = <&xtal>; - }; - - spicc0: spi@13000 { - compatible = "amlogic,meson-g12a-spicc"; - reg = <0x0 0x13000 0x0 0x44>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLKID_SPICC0>, - <&clkc CLKID_SPICC0_SCLK>; - clock-names = "core", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spicc1: spi@15000 { - compatible = "amlogic,meson-g12a-spicc"; - reg = <0x0 0x15000 0x0 0x44>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLKID_SPICC1>, - <&clkc CLKID_SPICC1_SCLK>; - clock-names = "core", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spifc: spi@14000 { - compatible = "amlogic,meson-gxbb-spifc"; - status = "disabled"; - reg = <0x0 0x14000 0x0 0x80>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_CLK81>; - }; - - pwm_ef: pwm@19000 { - compatible = "amlogic,meson-g12a-ee-pwm"; - reg = <0x0 0x19000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@1a000 { - compatible = "amlogic,meson-g12a-ee-pwm"; - reg = <0x0 0x1a000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_ab: pwm@1b000 { - compatible = "amlogic,meson-g12a-ee-pwm"; - reg = <0x0 0x1b000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - i2c3: i2c@1c000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1c000 0x0 0x20>; - interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - i2c2: i2c@1d000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1d000 0x0 0x20>; - interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - i2c1: i2c@1e000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1e000 0x0 0x20>; - interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - i2c0: i2c@1f000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1f000 0x0 0x20>; - interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - clk_msr: clock-measure@18000 { - compatible = "amlogic,meson-g12a-clk-measure"; - reg = <0x0 0x18000 0x0 0x10>; - }; - - uart_C: serial@22000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x22000 0x0 0x18>; - interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_B: serial@23000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x23000 0x0 0x18>; - interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_A: serial@24000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x24000 0x0 0x18>; - interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - fifo-size = <128>; - }; - }; - - sd_emmc_a: sd@ffe03000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe03000 0x0 0x800>; - interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_A>, - <&clkc CLKID_SD_EMMC_A_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_A>; - }; - - sd_emmc_b: sd@ffe05000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe05000 0x0 0x800>; - interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_B>; - }; - - sd_emmc_c: mmc@ffe07000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe07000 0x0 0x800>; - interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_C>; - }; - - usb: usb@ffe09000 { - status = "disabled"; - compatible = "amlogic,meson-g12a-usb-ctrl"; - reg = <0x0 0xffe09000 0x0 0xa0>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc CLKID_USB>; - resets = <&reset RESET_USB>; - - dr_mode = "otg"; - - phys = <&usb2_phy0>, <&usb2_phy1>, - <&usb3_pcie_phy PHY_TYPE_USB3>; - phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; - - dwc2: usb@ff400000 { - compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; - reg = <0x0 0xff400000 0x0 0x40000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "otg"; - phys = <&usb2_phy1>; - phy-names = "usb2-phy"; - dr_mode = "peripheral"; - g-rx-fifo-size = <192>; - g-np-tx-fifo-size = <128>; - g-tx-fifo-size = <128 128 16 16 16>; - }; - - dwc3: usb@ff500000 { - compatible = "snps,dwc3"; - reg = <0x0 0xff500000 0x0 0x100000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - snps,dis_u2_susphy_quirk; - snps,quirk-frame-length-adjustment = <0x20>; - snps,parkmode-disable-ss-quirk; - }; - }; - - mali: gpu@ffe40000 { - compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; - reg = <0x0 0xffe40000 0x0 0x40000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&clkc CLKID_MALI>; - resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; - operating-points-v2 = <&gpu_opp_table>; - #cooling-cells = <2>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&cpu_temp>; - - trips { - cpu_passive: cpu-passive { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - cpu_hot: cpu-hot { - temperature = <95000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "hot"; - }; - - cpu_critical: cpu-critical { - temperature = <110000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - }; - - ddr_thermal: ddr-thermal { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&ddr_temp>; - - trips { - ddr_passive: ddr-passive { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - ddr_critical: ddr-critical { - temperature = <110000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map { - trip = <&ddr_passive>; - cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; - arm,no-tick-in-suspend; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; - -}; diff --git a/arch/arm/dts/meson-g12.dtsi b/arch/arm/dts/meson-g12.dtsi deleted file mode 100644 index 6a1f4dcf648..00000000000 --- a/arch/arm/dts/meson-g12.dtsi +++ /dev/null @@ -1,385 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -#include "meson-g12-common.dtsi" -#include <dt-bindings/clock/axg-audio-clkc.h> -#include <dt-bindings/power/meson-g12a-power.h> -#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> -#include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h> - -/ { - tdmif_a: audio-controller-0 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_A"; - clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, - <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_b: audio-controller-1 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_B"; - clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, - <&clkc_audio AUD_CLKID_MST_B_SCLK>, - <&clkc_audio AUD_CLKID_MST_B_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_c: audio-controller-2 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_C"; - clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, - <&clkc_audio AUD_CLKID_MST_C_SCLK>, - <&clkc_audio AUD_CLKID_MST_C_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; -}; - -&apb { - pdm: audio-controller@40000 { - compatible = "amlogic,g12a-pdm", - "amlogic,axg-pdm"; - reg = <0x0 0x40000 0x0 0x34>; - #sound-dai-cells = <0>; - sound-name-prefix = "PDM"; - clocks = <&clkc_audio AUD_CLKID_PDM>, - <&clkc_audio AUD_CLKID_PDM_DCLK>, - <&clkc_audio AUD_CLKID_PDM_SYSCLK>; - clock-names = "pclk", "dclk", "sysclk"; - resets = <&clkc_audio AUD_RESET_PDM>; - status = "disabled"; - }; - - audio: bus@42000 { - compatible = "simple-bus"; - reg = <0x0 0x42000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; - - clkc_audio: clock-controller@0 { - status = "disabled"; - compatible = "amlogic,g12a-audio-clkc"; - reg = <0x0 0x0 0x0 0xb4>; - #clock-cells = <1>; - #reset-cells = <1>; - - clocks = <&clkc CLKID_AUDIO>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL3>, - <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_FCLK_DIV3>, - <&clkc CLKID_FCLK_DIV4>, - <&clkc CLKID_GP0_PLL>; - clock-names = "pclk", - "mst_in0", - "mst_in1", - "mst_in2", - "mst_in3", - "mst_in4", - "mst_in5", - "mst_in6", - "mst_in7"; - - resets = <&reset RESET_AUDIO>; - }; - - toddr_a: audio-controller@100 { - compatible = "amlogic,g12a-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x100 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_A"; - interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_A>; - resets = <&arb AXG_ARB_TODDR_A>, - <&clkc_audio AUD_RESET_TODDR_A>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - toddr_b: audio-controller@140 { - compatible = "amlogic,g12a-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x140 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_B"; - interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_B>; - resets = <&arb AXG_ARB_TODDR_B>, - <&clkc_audio AUD_RESET_TODDR_B>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - toddr_c: audio-controller@180 { - compatible = "amlogic,g12a-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x180 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_C"; - interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_C>; - resets = <&arb AXG_ARB_TODDR_C>, - <&clkc_audio AUD_RESET_TODDR_C>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_a: audio-controller@1c0 { - compatible = "amlogic,g12a-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x1c0 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_A"; - interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; - resets = <&arb AXG_ARB_FRDDR_A>, - <&clkc_audio AUD_RESET_FRDDR_A>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - frddr_b: audio-controller@200 { - compatible = "amlogic,g12a-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x200 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_B"; - interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; - resets = <&arb AXG_ARB_FRDDR_B>, - <&clkc_audio AUD_RESET_FRDDR_B>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_c: audio-controller@240 { - compatible = "amlogic,g12a-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x240 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_C"; - interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; - resets = <&arb AXG_ARB_FRDDR_C>, - <&clkc_audio AUD_RESET_FRDDR_C>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - arb: reset-controller@280 { - status = "disabled"; - compatible = "amlogic,meson-axg-audio-arb"; - reg = <0x0 0x280 0x0 0x4>; - #reset-cells = <1>; - clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; - }; - - tdmin_a: audio-controller@300 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x300 0x0 0x40>; - sound-name-prefix = "TDMIN_A"; - resets = <&clkc_audio AUD_RESET_TDMIN_A>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_b: audio-controller@340 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x340 0x0 0x40>; - sound-name-prefix = "TDMIN_B"; - resets = <&clkc_audio AUD_RESET_TDMIN_B>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_c: audio-controller@380 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x380 0x0 0x40>; - sound-name-prefix = "TDMIN_C"; - resets = <&clkc_audio AUD_RESET_TDMIN_C>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_lb: audio-controller@3c0 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x3c0 0x0 0x40>; - sound-name-prefix = "TDMIN_LB"; - resets = <&clkc_audio AUD_RESET_TDMIN_LB>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - spdifin: audio-controller@400 { - compatible = "amlogic,g12a-spdifin", - "amlogic,axg-spdifin"; - reg = <0x0 0x400 0x0 0x30>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFIN"; - interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, - <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; - clock-names = "pclk", "refclk"; - resets = <&clkc_audio AUD_RESET_SPDIFIN>; - status = "disabled"; - }; - - spdifout: audio-controller@480 { - compatible = "amlogic,g12a-spdifout", - "amlogic,axg-spdifout"; - reg = <0x0 0x480 0x0 0x50>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFOUT"; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, - <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; - clock-names = "pclk", "mclk"; - resets = <&clkc_audio AUD_RESET_SPDIFOUT>; - status = "disabled"; - }; - - tdmout_a: audio-controller@500 { - compatible = "amlogic,g12a-tdmout"; - reg = <0x0 0x500 0x0 0x40>; - sound-name-prefix = "TDMOUT_A"; - resets = <&clkc_audio AUD_RESET_TDMOUT_A>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_b: audio-controller@540 { - compatible = "amlogic,g12a-tdmout"; - reg = <0x0 0x540 0x0 0x40>; - sound-name-prefix = "TDMOUT_B"; - resets = <&clkc_audio AUD_RESET_TDMOUT_B>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_c: audio-controller@580 { - compatible = "amlogic,g12a-tdmout"; - reg = <0x0 0x580 0x0 0x40>; - sound-name-prefix = "TDMOUT_C"; - resets = <&clkc_audio AUD_RESET_TDMOUT_C>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - spdifout_b: audio-controller@680 { - compatible = "amlogic,g12a-spdifout", - "amlogic,axg-spdifout"; - reg = <0x0 0x680 0x0 0x50>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFOUT_B"; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, - <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; - clock-names = "pclk", "mclk"; - resets = <&clkc_audio AUD_RESET_SPDIFOUT_B>; - status = "disabled"; - }; - - toacodec: audio-controller@740 { - compatible = "amlogic,g12a-toacodec"; - reg = <0x0 0x740 0x0 0x4>; - #sound-dai-cells = <1>; - sound-name-prefix = "TOACODEC"; - resets = <&clkc_audio AUD_RESET_TOACODEC>; - status = "disabled"; - }; - - tohdmitx: audio-controller@744 { - compatible = "amlogic,g12a-tohdmitx"; - reg = <0x0 0x744 0x0 0x4>; - #sound-dai-cells = <1>; - sound-name-prefix = "TOHDMITX"; - resets = <&clkc_audio AUD_RESET_TOHDMITX>; - status = "disabled"; - }; - }; -}; - -ðmac { - power-domains = <&pwrc PWRC_G12A_ETH_ID>; -}; - -&vpu { - power-domains = <&pwrc PWRC_G12A_VPU_ID>; -}; - -&sd_emmc_a { - amlogic,dram-access-quirk; -}; - -&simplefb_cvbs { - power-domains = <&pwrc PWRC_G12A_VPU_ID>; -}; - -&simplefb_hdmi { - power-domains = <&pwrc PWRC_G12A_VPU_ID>; -}; - diff --git a/arch/arm/dts/meson-g12a-radxa-zero.dts b/arch/arm/dts/meson-g12a-radxa-zero.dts deleted file mode 100644 index e3bb6df42ff..00000000000 --- a/arch/arm/dts/meson-g12a-radxa-zero.dts +++ /dev/null @@ -1,405 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 BayLibre SAS. All rights reserved. - */ - -/dts-v1/; - -#include "meson-g12a.dtsi" -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "radxa,zero", "amlogic,g12a"; - model = "Radxa Zero"; - - aliases { - serial0 = &uart_AO; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - cvbs-connector { - status = "disabled"; - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - hdmi_pw: regulator-hdmi_pw { - compatible = "regulator-fixed"; - regulator-name = "HDMI_PW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vddcpu: regulator-vddcpu { - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&ao_5v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "RADXA-ZERO"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_pw>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "disabled"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddao_1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr50; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm/dts/meson-g12a-sei510.dts b/arch/arm/dts/meson-g12a-sei510.dts deleted file mode 100644 index 81269ccc249..00000000000 --- a/arch/arm/dts/meson-g12a-sei510.dts +++ /dev/null @@ -1,566 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre SAS. All rights reserved. - */ - -/dts-v1/; - -#include "meson-g12a.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "seirobotics,sei510", "amlogic,g12a"; - model = "SEI Robotics SEI510"; - - adc_keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-onoff { - label = "On/Off"; - linux,code = <KEY_POWER>; - press-threshold-microvolt = <1700000>; - }; - }; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - mono_dac: audio-codec-0 { - compatible = "maxim,max98357a"; - #sound-dai-cells = <0>; - sound-name-prefix = "U16"; - sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>; - }; - - dmics: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "dmic-codec"; - num-channels = <2>; - wakeup-delay-ms = <50>; - status = "okay"; - sound-name-prefix = "MIC"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - emmc_1v8: regulator-emmc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - vddao_3v3_t: regultor-vddao_3v3_t { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3_T"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vddcpu: regulator-vddcpu { - /* - * SY8120B1ABC DC/DC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&dc_in>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddio_ao1v8: regulator-vddio_ao1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - reserved-memory { - /* TEE Reserved Memory */ - bl32_reserved: bl32@5000000 { - reg = <0x0 0x05300000 0x0 0x2000000>; - no-map; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "SEI510"; - audio-aux-devs = <&tdmout_a>, <&tdmout_b>, - <&tdmin_a>, <&tdmin_b>; - audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", - "TDMOUT_A IN 1", "FRDDR_B OUT 0", - "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT", - "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TODDR_A IN 4", "PDM Capture", - "TODDR_B IN 4", "PDM Capture", - "TODDR_C IN 4", "PDM Capture", - "TDMIN_A IN 0", "TDM_A Capture", - "TDMIN_A IN 3", "TDM_A Loopback", - "TDMIN_B IN 0", "TDM_A Capture", - "TDMIN_B IN 3", "TDM_A Loopback", - "TDMIN_A IN 1", "TDM_B Capture", - "TDMIN_A IN 4", "TDM_B Loopback", - "TDMIN_B IN 1", "TDM_B Capture", - "TDMIN_B IN 4", "TDM_B Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* internal speaker interface */ - dai-link-6 { - sound-dai = <&tdmif_a>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&mono_dac>; - }; - - codec-1 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; - }; - }; - - /* 8ch hdmi interface */ - dai-link-7 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* internal digital mics */ - dai-link-8 { - sound-dai = <&pdm>; - - codec { - sound-dai = <&dmics>; - }; - }; - - /* hdmi glue */ - dai-link-9 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - phy-handle = <&internal_ephy>; - phy-mode = "rmii"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&pdm { - pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_din1_z_pins>, - <&pdm_din2_z_pins>, <&pdm_din3_z_pins>, - <&pdm_dclk_z_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr50; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_ao1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&emmc_1v8>; -}; - -&tdmif_a { - pinctrl-0 = <&tdm_a_dout0_pins>, <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>; - pinctrl-names = "default"; - status = "okay"; - - assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD0>, - <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD0>; - assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - assigned-clock-rates = <0>, <0>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmout_a { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - vbat-supply = <&vddao_3v3>; - vddio-supply = <&vddio_ao1v8>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts deleted file mode 100644 index a26bfe72550..00000000000 --- a/arch/arm/dts/meson-g12a-u200.dts +++ /dev/null @@ -1,308 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - */ - -/dts-v1/; - -#include "meson-g12a.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> - -/ { - compatible = "amlogic,u200", "amlogic,g12a"; - model = "Amlogic Meson G12A U200 Development Board"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - usb_pwr_en: regulator-usb_pwr_en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&main_12v>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - vddcpu: regulator-vddcpu { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - phy-handle = <&internal_ephy>; - phy-mode = "rmii"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -/* i2c Touch */ -&i2c0 { - status = "okay"; - pinctrl-0 = <&i2c0_sda_z0_pins>, <&i2c0_sck_z1_pins>; - pinctrl-names = "default"; -}; - -/* i2c CM */ -&i2c2 { - status = "okay"; - pinctrl-0 = <&i2c2_sda_z_pins>, <&i2c2_sck_z_pins>; - pinctrl-names = "default"; -}; - -/* i2c Audio */ -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_pwr_en>; -}; - -&usb2_phy0 { - phy-supply = <&vcc_5v>; -}; - -&usb2_phy1 { - phy-supply = <&vcc_5v>; -}; diff --git a/arch/arm/dts/meson-g12a.dtsi b/arch/arm/dts/meson-g12a.dtsi deleted file mode 100644 index 7677764eeee..00000000000 --- a/arch/arm/dts/meson-g12a.dtsi +++ /dev/null @@ -1,140 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - */ - -#include "meson-g12.dtsi" - -/ { - compatible = "amlogic,g12a"; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - }; - }; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <666666666>; - opp-microvolt = <731000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <731000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <731000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <761000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <791000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <831000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <861000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <981000>; - }; - }; -}; - -&cpu_thermal { - cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&pmu { - compatible = "amlogic,g12a-ddr-pmu"; -}; diff --git a/arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts b/arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts deleted file mode 100644 index 31365316b2e..00000000000 --- a/arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-g12b-a311d.dtsi" -#include "meson-g12b-bananapi.dtsi" - -/ { - compatible = "bananapi,bpi-m2s", "amlogic,a311d", "amlogic,g12b"; - model = "BananaPi M2S"; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c3; - }; -}; - -/* Camera (CSI) bus */ -&i2c1 { - status = "okay"; - pinctrl-0 = <&i2c1_sda_h6_pins>, <&i2c1_sck_h7_pins>; - pinctrl-names = "default"; -}; - -/* Display (DSI) bus */ -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; -}; diff --git a/arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts b/arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts deleted file mode 100644 index 124a8090108..00000000000 --- a/arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-g12b-a311d.dtsi" -#include "meson-khadas-vim3.dtsi" -#include "meson-g12b-khadas-vim3.dtsi" - -/ { - compatible = "khadas,vim3", "amlogic,a311d", "amlogic,g12b"; -}; - -/* - * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential - * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between - * an USB3.0 Type A connector and a M.2 Key M slot. - * The PHY driving these differential lines is shared between - * the USB3.0 controller and the PCIe Controller, thus only - * a single controller can use it. - * If the MCU is configured to mux the PCIe/USB3.0 differential lines - * to the M.2 Key M slot, uncomment the following block to disable - * USB3.0 from the USB Complex and enable the PCIe controller. - * The End User is not expected to uncomment the following except for - * testing purposes, but instead rely on the firmware/bootloader to - * update these nodes accordingly if PCIe mode is selected by the MCU. - */ -/* -&pcie { - status = "okay"; -}; - -&usb { - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; -}; - */ diff --git a/arch/arm/dts/meson-g12b-a311d.dtsi b/arch/arm/dts/meson-g12b-a311d.dtsi deleted file mode 100644 index d61f43052a3..00000000000 --- a/arch/arm/dts/meson-g12b-a311d.dtsi +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include "meson-g12b.dtsi" - -/ { - cpu_opp_table_0: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <731000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <761000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <781000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <811000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <861000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <901000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <951000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1001000>; - }; - }; - - cpub_opp_table_1: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <731000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <731000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <751000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <771000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <771000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <781000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <791000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <831000>; - }; - - opp-1908000000 { - opp-hz = /bits/ 64 <1908000000>; - opp-microvolt = <861000>; - }; - - opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <911000>; - }; - - opp-2108000000 { - opp-hz = /bits/ 64 <2108000000>; - opp-microvolt = <951000>; - }; - - opp-2208000000 { - opp-hz = /bits/ 64 <2208000000>; - opp-microvolt = <1011000>; - }; - }; -}; diff --git a/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts b/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts deleted file mode 100644 index 1b0c3881c6a..00000000000 --- a/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts +++ /dev/null @@ -1,165 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org> - */ - -/dts-v1/; - -#include "meson-g12b-bananapi-cm4.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "bananapi,bpi-cm4io", "bananapi,bpi-cm4", "amlogic,a311d", "amlogic,g12b"; - model = "BananaPi BPI-CM4IO Baseboard with BPI-CM4 Module"; - - aliases { - ethernet0 = ðmac; - i2c0 = &i2c1; - i2c1 = &i2c3; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 2>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Function"; - linux,code = <KEY_FN>; - press-threshold-microvolt = <10000>; - }; - }; - - hdmi_connector: hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-green { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "BPI-CM4IO"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&cecb_AO { - status = "okay"; -}; - -ðmac { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -/* CSI port */ -&i2c1 { - status = "okay"; -}; - -/* DSI port for touchscreen */ -&i2c3 { - status = "okay"; -}; - -/* miniPCIe port with USB + SIM slot */ -&pcie { - status = "okay"; -}; - -&sd_emmc_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -/* Peripheral Only USB-C port */ -&usb { - dr_mode = "peripheral"; - - status = "okay"; -}; diff --git a/arch/arm/dts/meson-g12b-bananapi-cm4.dtsi b/arch/arm/dts/meson-g12b-bananapi-cm4.dtsi deleted file mode 100644 index 97e522921b0..00000000000 --- a/arch/arm/dts/meson-g12b-bananapi-cm4.dtsi +++ /dev/null @@ -1,388 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org> - */ - -#include "meson-g12b-a311d.dtsi" -#include <dt-bindings/gpio/meson-g12a-gpio.h> - -/ { - aliases { - serial0 = &uart_AO; - rtc1 = &vrtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOAO_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - emmc_1v8: regulator-emmc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - dc_in: regulator-dc-in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vddio_c: regulator-vddio-c { - compatible = "regulator-gpio"; - regulator-name = "VDDIO_C"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - enable-gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>; - enable-active-high; - regulator-always-on; - - gpios = <&gpio_ao GPIOAO_9 GPIO_OPEN_DRAIN>; - gpios-states = <1>; - - states = <1800000 0>, - <3300000 1>; - }; - - vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - vddcpu_a: regulator-vddcpu-a { - /* - * MP8756GD DC/DC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <680000>; - regulator-max-microvolt = <1040000>; - - pwm-supply = <&dc_in>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * SY8120B1ABC DC/DC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <680000>; - regulator-max-microvolt = <1040000>; - - pwm-supply = <&dc_in>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -/* Ethernet to be enabled in baseboard DT */ -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - phy-mode = "rgmii-txid"; - phy-handle = <&external_phy>; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -/* HDMI to be enabled in baseboard DT */ -&hdmi_tx { - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&dc_in>; -}; - -/* "Camera" I2C bus */ -&i2c1 { - pinctrl-0 = <&i2c1_sda_h6_pins>, <&i2c1_sck_h7_pins>; - pinctrl-names = "default"; -}; - -/* Main I2C bus */ -&i2c2 { - pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>; - pinctrl-names = "default"; -}; - -/* "ID" I2C bus */ -&i2c3 { - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; -}; - -&pcie { - reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - - status = "okay"; -}; - -&pwm_ef { - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - - status = "okay"; -}; - -&saradc { - vref-supply = <&vddao_1v8>; - - status = "okay"; -}; - -/* on-module SDIO WiFi */ -&sd_emmc_a { - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - sd-uhs-sdr104; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; - - status = "okay"; - - rtl8822cs: wifi@1 { - reg = <1>; - }; -}; - -/* SD card to be enabled in baseboard DT */ -&sd_emmc_b { - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_c>; -}; - -/* on-module eMMC */ -&sd_emmc_c { - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_1v8>; - - status = "okay"; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -/* on-module UART BT */ -&uart_A { - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - status = "okay"; - - bluetooth { - compatible = "realtek,rtl8822cs-bt"; - enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; - device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart_AO { - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usb { - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; -}; diff --git a/arch/arm/dts/meson-g12b-bananapi.dtsi b/arch/arm/dts/meson-g12b-bananapi.dtsi deleted file mode 100644 index 83709787eb9..00000000000 --- a/arch/arm/dts/meson-g12b-bananapi.dtsi +++ /dev/null @@ -1,521 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com> - */ - -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - rtc1 = &vrtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 4 GiB */ - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 2>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "RST"; - linux,code = <KEY_POWER>; - press-threshold-microvolt = <10000>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - fan0: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - cooling-min-state = <0>; - cooling-max-state = <3>; - cooling-levels = <0 120 170 220>; - pwms = <&pwm_cd 1 40000 0>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - dc_in: regulator-dc-in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc-5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - }; - - vcc_1v8: regulator-vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - }; - - vddcpu_a: regulator-vddcpu-a { - compatible = "pwm-regulator"; - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - pwm-supply = <&dc_in>; - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - compatible = "pwm-regulator"; - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - pwm-supply = <&vsys_3v3>; - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - regulator-boot-on; - regulator-always-on; - }; - - vsys_3v3: regulator-vsys-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VSYS_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - emmc_1v8: regulator-emmc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - usb_pwr: regulator-usb-pwr { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "BPI-M2S"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -/* Main i2c bus */ -&i2c2 { - status = "okay"; - pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>; - pinctrl-names = "default"; -}; - -&pcie { - status = "okay"; - reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>; -}; - -&pwm_ab { - status = "okay"; - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&pwm_cd { - status = "okay"; - pinctrl-0 = <&pwm_d_x6_pins>; - pinctrl-names = "default"; - pwm-gpios = <&gpio GPIOAO_10 GPIO_ACTIVE_HIGH>; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddao_1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - /* enable if WiFi/BT board connected */ - status = "disabled"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - sd-uhs-sdr104; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vsys_3v3>; - vqmmc-supply = <&vddao_1v8>; - - rtl8822cs: wifi@1 { - reg = <1>; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vsys_3v3>; - vqmmc-supply = <&vsys_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&emmc_1v8>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - /* enable if WiFi/BT board connected */ - status = "disabled"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "realtek,rtl8822cs-bt"; - enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; - device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb2_phy0 { - phy-supply = <&dc_in>; -}; - -&usb2_phy1 { - phy-supply = <&usb_pwr>; -}; - -&usb3_pcie_phy { - phy-supply = <&usb_pwr>; -}; - -&usb { - status = "okay"; - dr_mode = "peripheral"; - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; -}; diff --git a/arch/arm/dts/meson-g12b-gsking-x.dts b/arch/arm/dts/meson-g12b-gsking-x.dts deleted file mode 100644 index 6c7bfacbad7..00000000000 --- a/arch/arm/dts/meson-g12b-gsking-x.dts +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-g12b-w400.dtsi" -#include <dt-bindings/leds/common.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "azw,gsking-x", "amlogic,s922x", "amlogic,g12b"; - model = "Beelink GS-King X"; - - aliases { - rtc0 = &rtc; - rtc1 = &vrtc; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "GSKING-X"; - audio-aux-devs = <&tdmout_a>; - audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 1", - "TDMOUT_A IN 1", "FRDDR_B OUT 1", - "TDMOUT_A IN 2", "FRDDR_C OUT 1", - "TDM_A Playback", "TDMOUT_A OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_a>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; - }; - }; - - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - wakeup-source; - }; -}; - -&tdmif_a { - status = "okay"; -}; - -&tdmout_a { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; diff --git a/arch/arm/dts/meson-g12b-gtking-pro.dts b/arch/arm/dts/meson-g12b-gtking-pro.dts deleted file mode 100644 index 707daf92787..00000000000 --- a/arch/arm/dts/meson-g12b-gtking-pro.dts +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-g12b-w400.dtsi" -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b"; - model = "Beelink GT-King Pro"; - - aliases { - rtc0 = &rtc; - rtc1 = &vrtc; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-white { - label = "power:white"; - gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "GTKING-PRO"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - wakeup-source; - }; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; diff --git a/arch/arm/dts/meson-g12b-gtking.dts b/arch/arm/dts/meson-g12b-gtking.dts deleted file mode 100644 index 5d96c144905..00000000000 --- a/arch/arm/dts/meson-g12b-gtking.dts +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-g12b-w400.dtsi" -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b"; - model = "Beelink GT-King"; - - aliases { - rtc0 = &rtc; - rtc1 = &vrtc; - }; - - spdif_dit: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - status = "okay"; - sound-name-prefix = "DIT"; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "GTKING"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "SPDIFOUT IN 0", "FRDDR_A OUT 3", - "SPDIFOUT IN 1", "FRDDR_B OUT 3", - "SPDIFOUT IN 2", "FRDDR_C OUT 3"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* spdif hdmi or toslink interface */ - dai-link-4 { - sound-dai = <&spdifout>; - - codec-0 { - sound-dai = <&spdif_dit>; - }; - - codec-1 { - sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>; - }; - }; - - /* spdif hdmi interface */ - dai-link-5 { - sound-dai = <&spdifout_b>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-6 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - wakeup-source; - }; -}; - -&spdifout { - pinctrl-0 = <&spdif_out_h_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&spdifout_b { - status = "okay"; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; diff --git a/arch/arm/dts/meson-g12b-khadas-vim3.dtsi b/arch/arm/dts/meson-g12b-khadas-vim3.dtsi deleted file mode 100644 index f42cf4b8af2..00000000000 --- a/arch/arm/dts/meson-g12b-khadas-vim3.dtsi +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com> - */ - -/ { - model = "Khadas VIM3"; - - vddcpu_a: regulator-vddcpu-a { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - vin-supply = <&dc_in>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * Silergy SY8030DEC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - vin-supply = <&vsys_3v3>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - diff --git a/arch/arm/dts/meson-g12b-odroid-go-ultra.dts b/arch/arm/dts/meson-g12b-odroid-go-ultra.dts deleted file mode 100644 index 1e40709610c..00000000000 --- a/arch/arm/dts/meson-g12b-odroid-go-ultra.dts +++ /dev/null @@ -1,722 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Neil Armstrong <neil.armstrong@linaro.org> - */ - -/dts-v1/; - -#include "meson-g12b-s922x.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/sound/meson-g12a-toacodec.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "hardkernel,odroid-go-ultra", "amlogic,s922x", "amlogic,g12b"; - model = "Hardkernel ODROID-GO-Ultra"; - - aliases { - serial0 = &uart_AO; - rtc0 = &vrtc; - }; - - adc-joystick-left { - compatible = "adc-joystick"; - io-channels = <&saradc 2>, <&saradc 3>; - poll-interval = <10>; - #address-cells = <1>; - #size-cells = <0>; - - axis@0 { - reg = <0>; - linux,code = <ABS_Y>; - abs-range = <3150 950>; - abs-fuzz = <32>; - abs-flat = <64>; - }; - axis@1 { - reg = <1>; - linux,code = <ABS_X>; - abs-range = <700 2900>; - abs-fuzz = <32>; - abs-flat = <64>; - }; - }; - - adc-joystick-right { - compatible = "adc-joystick"; - io-channels = <&saradc 0>, <&saradc 1>; - poll-interval = <10>; - #address-cells = <1>; - #size-cells = <0>; - - axis@0 { - reg = <0>; - linux,code = <ABS_RY>; - abs-range = <3150 950>; - abs-fuzz = <32>; - abs-flat = <64>; - }; - axis@1 { - reg = <1>; - linux,code = <ABS_RX>; - abs-range = <800 3000>; - abs-fuzz = <32>; - abs-flat = <64>; - }; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - codec_clk: codec-clk { - compatible = "fixed-clock"; - clock-frequency = <12288000>; - clock-output-names = "codec_clk"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys-polled"; - poll-interval = <10>; - pinctrl-0 = <&keypad_gpio_pins>; - pinctrl-names = "default"; - - volume-up-button { - label = "VOLUME-UP"; - linux,code = <KEY_VOLUMEUP>; - gpios = <&gpio GPIOX_8 GPIO_ACTIVE_LOW>; - }; - volume-down-button { - label = "VOLUME-DOWN"; - linux,code = <KEY_VOLUMEDOWN>; - gpios = <&gpio GPIOX_9 GPIO_ACTIVE_LOW>; - }; - dpad-up-button { - label = "DPAD-UP"; - linux,code = <BTN_DPAD_UP>; - gpios = <&gpio GPIOX_0 GPIO_ACTIVE_LOW>; - }; - dpad-down-button { - label = "DPAD-DOWN"; - linux,code = <BTN_DPAD_DOWN>; - gpios = <&gpio GPIOX_1 GPIO_ACTIVE_LOW>; - }; - dpad-left-button { - label = "DPAD-LEFT"; - linux,code = <BTN_DPAD_LEFT>; - gpios = <&gpio GPIOX_2 GPIO_ACTIVE_LOW>; - }; - dpad-right-button { - label = "DPAD-RIGHT"; - linux,code = <BTN_DPAD_RIGHT>; - gpios = <&gpio GPIOX_3 GPIO_ACTIVE_LOW>; - }; - a-button { - label = "A"; - linux,code = <BTN_EAST>; - gpios = <&gpio GPIOX_4 GPIO_ACTIVE_LOW>; - }; - b-button { - label = "B"; - linux,code = <BTN_SOUTH>; - gpios = <&gpio GPIOX_5 GPIO_ACTIVE_LOW>; - }; - y-button { - label = "Y"; - linux,code = <BTN_WEST>; - gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - }; - x-button { - label = "X"; - linux,code = <BTN_NORTH>; - gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; - }; - f1-button { - label = "F1"; - linux,code = <BTN_TRIGGER_HAPPY1>; - gpios = <&gpio GPIOX_17 GPIO_ACTIVE_LOW>; - }; - f2-button { - label = "F2"; - linux,code = <BTN_TRIGGER_HAPPY2>; - gpios = <&gpio GPIOX_10 GPIO_ACTIVE_LOW>; - }; - f3-button { - label = "F3"; - linux,code = <BTN_TRIGGER_HAPPY3>; - gpios = <&gpio GPIOX_11 GPIO_ACTIVE_LOW>; - }; - f4-button { - label = "F4"; - linux,code = <BTN_TRIGGER_HAPPY4>; - gpios = <&gpio GPIOX_12 GPIO_ACTIVE_LOW>; - }; - f5-button { - label = "F5"; - linux,code = <BTN_TRIGGER_HAPPY5>; - gpios = <&gpio GPIOX_13 GPIO_ACTIVE_LOW>; - }; - f6-button { - label = "F6"; - linux,code = <BTN_TRIGGER_HAPPY6>; - gpios = <&gpio GPIOX_16 GPIO_ACTIVE_LOW>; - }; - top-left-button { - label = "TOP Left"; - linux,code = <BTN_TL>; - gpios = <&gpio GPIOX_14 GPIO_ACTIVE_LOW>; - }; - top-left2-button { - label = "TOP Left 2"; - linux,code = <BTN_TL2>; - gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>; - }; - top-right-button { - label = "TOP Right"; - linux,code = <BTN_TR>; - gpios = <&gpio GPIOX_15 GPIO_ACTIVE_LOW>; - }; - top-right2-button { - label = "TOP Right 2"; - linux,code = <BTN_TR2>; - gpios = <&gpio GPIOX_18 GPIO_ACTIVE_LOW>; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - color = <LED_COLOR_ID_BLUE>; - gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - vdd_sys: regulator-vdd-sys { - compatible = "regulator-fixed"; - regulator-name = "VDD_SYS"; - regulator-min-microvolt = <3800000>; - regulator-max-microvolt = <3800000>; - regulator-always-on; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "Odroid GO Ultra"; - audio-widgets = "Microphone", "Mic Jack", - "Headphone", "Headphones", - "Speaker", "Internal Speakers"; - audio-aux-devs = <&tdmout_b>, <&tdmin_b>, <&speaker_amp>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TDMIN_B IN 1", "TDM_B Capture", - "TDMIN_B IN 4", "TDM_B Loopback", - "TODDR_A IN 1", "TDMIN_B OUT", - "MICL", "Mic Jack", - "Headphones", "HPOL", - "Headphones", "HPOR", - "Speaker Amplifier INL", "HPOL", - "Speaker Amplifier INR", "HPOR", - "Internal Speakers", "Speaker Amplifier OUTL", - "Internal Speakers", "Speaker Amplifier OUTR"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&toddr_a>; - }; - - dai-link-2 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&rk817>; - }; - }; - }; - - speaker_amp: speaker-amplifier { - compatible = "simple-audio-amplifier"; - sound-name-prefix = "Speaker Amplifier"; - VCC-supply = <&hp_5v>; - }; -}; - -&arb { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -/* RK817 only supports 12.5mV steps, round up the values */ -&cpu_opp_table_0 { - opp-1000000000 { - opp-microvolt = <737500>; - }; - opp-1200000000 { - opp-microvolt = <737500>; - }; - opp-1398000000 { - opp-microvolt = <762500>; - }; - opp-1512000000 { - opp-microvolt = <800000>; - }; - opp-1608000000 { - opp-microvolt = <837500>; - }; - opp-1704000000 { - opp-microvolt = <862500>; - }; - opp-1896000000 { - opp-microvolt = <987500>; - }; - opp-1992000000 { - opp-microvolt = <1012500>; - }; -}; - -/* RK818 only supports 12.5mV steps, round up the values */ -&cpub_opp_table_1 { - opp-1000000000 { - opp-microvolt = <775000>; - }; - opp-1200000000 { - opp-microvolt = <775000>; - }; - opp-1398000000 { - opp-microvolt = <800000>; - }; - opp-1512000000 { - opp-microvolt = <825000>; - }; - opp-1608000000 { - opp-microvolt = <862500>; - }; - opp-1704000000 { - opp-microvolt = <900000>; - }; - opp-1800000000 { - opp-microvolt = <987500>; - }; - opp-1908000000 { - opp-microvolt = <1025000>; - }; -}; - -&i2c_AO { - status = "okay"; - pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>; - pinctrl-names = "default"; - - rk818: pmic@1c { - compatible = "rockchip,rk818"; - reg = <0x1c>; - interrupt-parent = <&gpio_intc>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_7 */ - - vcc1-supply = <&vdd_sys>; - vcc2-supply = <&vdd_sys>; - vcc3-supply = <&vdd_sys>; - vcc4-supply = <&vdd_sys>; - vcc6-supply = <&vdd_sys>; - vcc7-supply = <&vcc_2v3>; - vcc8-supply = <&vcc_2v3>; - vcc9-supply = <&vddao_3v3>; - boost-supply = <&vdd_sys>; - switch-supply = <&vdd_sys>; - - regulators { - vddcpu_a: DCDC_REG1 { - regulator-name = "vddcpu_a"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <775000>; - regulator-max-microvolt = <1025000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <775000>; - }; - }; - - vdd_ee: DCDC_REG2 { - regulator-name = "vdd_ee"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1250000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <875000>; - }; - }; - - vddq_1v1: DCDC_REG3 { - regulator-name = "vddq_1v1"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vddao_3v3: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vddao_3v3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - hp_5v: DCDC_BOOST { - regulator-always-on; - regulator-boot-on; - regulator-name = "hp_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vddio_ao1v8: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vddio_ao1v8"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vddq_1v8: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vddq_1v8"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vddio_c: LDO_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vddio_c"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_sd: SWITCH_REG { - regulator-name = "vcc_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - OTG_SWITCH { - regulator-name = "otg_switch"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; - - rk817: pmic@20 { - compatible = "rockchip,rk817"; - reg = <0x20>; - interrupt-parent = <&gpio_intc>; - - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_5 */ - - vcc1-supply = <&vdd_sys>; - vcc2-supply = <&vdd_sys>; - vcc3-supply = <&vdd_sys>; - vcc4-supply = <&vdd_sys>; - vcc5-supply = <&vdd_sys>; - vcc6-supply = <&vdd_sys>; - vcc7-supply = <&vdd_sys>; - vcc8-supply = <&vdd_sys>; - vcc9-supply = <&rk817_boost>; - - #sound-dai-cells = <0>; - clocks = <&codec_clk>; - clock-names = "mclk"; - - #clock-cells = <1>; - - regulators { - vddcpu_b: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <737500>; - regulator-max-microvolt = <1012500>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-name = "vddcpu_b"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_2v3: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2300000>; - regulator-max-microvolt = <2400000>; - regulator-initial-mode = <0x2>; - regulator-name = "vcc_2v3"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vdd_codec"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_lcd: LDO_REG8 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_lcd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk817_boost: BOOST { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5400000>; - regulator-name = "rk817_boost"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - usb_host: OTG_SWITCH { - regulator-name = "usb_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&clkc_audio { - status = "okay"; -}; - -ð_phy { - status = "disabled"; -}; - -&frddr_a { - status = "okay"; -}; - -&periphs_pinctrl { - keypad_gpio_pins: keypad-gpio { - mux { - groups = "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", - "GPIOX_4", "GPIOX_5", "GPIOX_6", "GPIOX_7", - "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11", - "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15", - "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19"; - function = "gpio_periphs"; - bias-pull-up; - output-disable; - }; - }; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao1v8>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vddio_c>; - -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vddio_ao1v8>; -}; - - -&tdmif_b { - pinctrl-0 = <&tdm_b_dout0_pins>, <&tdm_b_fs_pins>, <&tdm_b_sclk_pins>, <&tdm_b_din1_pins>; - pinctrl-names = "default"; - status = "okay"; - - assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD1>, - <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD1>; - assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_B_SCLK>, - <&clkc_audio AUD_CLKID_MST_B_LRCLK>; - assigned-clock-rates = <0>, <0>; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "peripheral"; -}; - -&usb2_phy0 { - status = "okay"; -}; - -&usb2_phy1 { - status = "okay"; - phy-supply = <&usb_host>; -}; diff --git a/arch/arm/dts/meson-g12b-odroid-n2-plus.dts b/arch/arm/dts/meson-g12b-odroid-n2-plus.dts deleted file mode 100644 index ce1198ad34e..00000000000 --- a/arch/arm/dts/meson-g12b-odroid-n2-plus.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/dts-v1/; - -/* The Amlogic S922X Rev. C supports the same OPPs as the A311D variant */ -#include "meson-g12b-a311d.dtsi" -#include "meson-g12b-odroid-n2.dtsi" - -/ { - compatible = "hardkernel,odroid-n2-plus", "amlogic,s922x", "amlogic,g12b"; - model = "Hardkernel ODROID-N2Plus"; -}; - -&vddcpu_a { - regulator-min-microvolt = <680000>; - regulator-max-microvolt = <1040000>; - - pwms = <&pwm_ab 0 1500 0>; -}; - -&vddcpu_b { - regulator-min-microvolt = <680000>; - regulator-max-microvolt = <1040000>; - - pwms = <&pwm_AO_cd 1 1500 0>; -}; - diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts deleted file mode 100644 index a198a91259e..00000000000 --- a/arch/arm/dts/meson-g12b-odroid-n2.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/dts-v1/; - -#include "meson-g12b-s922x.dtsi" -#include "meson-g12b-odroid-n2.dtsi" - -/ { - compatible = "hardkernel,odroid-n2", "amlogic,s922x", "amlogic,g12b"; - model = "Hardkernel ODROID-N2"; -}; diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dtsi b/arch/arm/dts/meson-g12b-odroid-n2.dtsi deleted file mode 100644 index 24d0442dffb..00000000000 --- a/arch/arm/dts/meson-g12b-odroid-n2.dtsi +++ /dev/null @@ -1,303 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include "meson-g12b-odroid.dtsi" - -/ { - aliases { - rtc0 = &rtc; - }; - - dio2133: audio-amplifier-0 { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - VCC-supply = <&vcc_5v>; - sound-name-prefix = "U19"; - status = "okay"; - }; - - hub_5v: regulator-hub_5v { - compatible = "regulator-fixed"; - regulator-name = "HUB_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the Hub CHIPENABLE, LOW sets low power state */ - gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "ODROID-N2"; - audio-widgets = "Line", "Lineout"; - audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>, - <&tdmin_b>, <&tdmin_c>, <&tdmin_lb>, - <&dio2133>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TDMOUT_C IN 0", "FRDDR_A OUT 2", - "TDMOUT_C IN 1", "FRDDR_B OUT 2", - "TDMOUT_C IN 2", "FRDDR_C OUT 2", - "TDM_C Playback", "TDMOUT_C OUT", - "TDMIN_A IN 4", "TDM_B Loopback", - "TDMIN_B IN 4", "TDM_B Loopback", - "TDMIN_C IN 4", "TDM_B Loopback", - "TDMIN_LB IN 1", "TDM_B Loopback", - "TDMIN_A IN 5", "TDM_C Loopback", - "TDMIN_B IN 5", "TDM_C Loopback", - "TDMIN_C IN 5", "TDM_C Loopback", - "TDMIN_LB IN 2", "TDM_C Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT", - "TODDR_A IN 2", "TDMIN_C OUT", - "TODDR_B IN 2", "TDMIN_C OUT", - "TODDR_C IN 2", "TDMIN_C OUT", - "TODDR_A IN 6", "TDMIN_LB OUT", - "TODDR_B IN 6", "TDMIN_LB OUT", - "TODDR_C IN 6", "TDMIN_LB OUT", - "U19 INL", "ACODEC LOLP", - "U19 INR", "ACODEC LORP", - "Lineout", "U19 OUTL", - "Lineout", "U19 OUTR"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-6 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - - codec-1 { - sound-dai = <&toacodec TOACODEC_IN_B>; - }; - }; - - /* i2s jack output interface */ - dai-link-7 { - sound-dai = <&tdmif_c>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>; - }; - - codec-1 { - sound-dai = <&toacodec TOACODEC_IN_C>; - }; - }; - - /* hdmi glue */ - dai-link-8 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - - /* acodec glue */ - dai-link-9 { - sound-dai = <&toacodec TOACODEC_OUT>; - - codec { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddao_1v8>; - status = "okay"; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&gpio { - gpio-line-names = - /* GPIOZ */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* GPIOH */ - "", "", "", "", "", "", "", "", - "", - /* BOOT */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* GPIOC */ - "", "", "", "", "", "", "", "", - /* GPIOA */ - "PIN_44", /* GPIOA_0 */ - "PIN_46", /* GPIOA_1 */ - "PIN_45", /* GPIOA_2 */ - "PIN_47", /* GPIOA_3 */ - "PIN_26", /* GPIOA_4 */ - "", "", "", "", "", "", - "PIN_42", /* GPIOA_11 */ - "PIN_32", /* GPIOA_12 */ - "PIN_7", /* GPIOA_13 */ - "PIN_27", /* GPIOA_14 */ - "PIN_28", /* GPIOA_15 */ - /* GPIOX */ - "PIN_16", /* GPIOX_0 */ - "PIN_18", /* GPIOX_1 */ - "PIN_22", /* GPIOX_2 */ - "PIN_11", /* GPIOX_3 */ - "PIN_13", /* GPIOX_4 */ - "PIN_33", /* GPIOX_5 */ - "PIN_35", /* GPIOX_6 */ - "PIN_15", /* GPIOX_7 */ - "PIN_19", /* GPIOX_8 */ - "PIN_21", /* GPIOX_9 */ - "PIN_24", /* GPIOX_10 */ - "PIN_23", /* GPIOX_11 */ - "PIN_8", /* GPIOX_12 */ - "PIN_10", /* GPIOX_13 */ - "PIN_29", /* GPIOX_14 */ - "PIN_31", /* GPIOX_15 */ - "PIN_12", /* GPIOX_16 */ - "PIN_3", /* GPIOX_17 */ - "PIN_5", /* GPIOX_18 */ - "PIN_36"; /* GPIOX_19 */ - /* - * WARNING: The USB Hub on the Odroid-N2 needs a reset signal - * to be turned high in order to be detected by the USB Controller - * This signal should be handled by a USB specific power sequence - * in order to reset the Hub when USB bus is powered down. - */ - hog-0 { - gpio-hog; - gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - wakeup-source; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-odroid"; -}; - -/* - * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins - * and eMMC Data 4 to 7 pins. - * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0, - * and change bus-width to 4 then spifc can be enabled. - * The SW1 slide should also be set to the correct position. - */ -&spifc { - status = "disabled"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - mx25u64: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25u6435f", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - }; -}; - -&toacodec { - status = "okay"; -}; - -&usb { - vbus-supply = <&usb_pwr_en>; -}; - -&usb2_phy1 { - /* Enable the hub which is connected to this port */ - phy-supply = <&hub_5v>; -}; diff --git a/arch/arm/dts/meson-g12b-odroid-n2l.dts b/arch/arm/dts/meson-g12b-odroid-n2l.dts deleted file mode 100644 index 70919f40d59..00000000000 --- a/arch/arm/dts/meson-g12b-odroid-n2l.dts +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Dongjin Kim <tobetter@gmail.com> - */ - -/dts-v1/; - -/* The Amlogic S922X Rev. C supports the same OPPs as the A311D variant */ -#include "meson-g12b-a311d.dtsi" -#include "meson-g12b-odroid.dtsi" - -/ { - compatible = "hardkernel,odroid-n2l", "amlogic,s922x", "amlogic,g12b"; - model = "Hardkernel ODROID-N2L"; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "ODROID-N2L"; - audio-aux-devs = <&tdmout_b>, <&tdmin_a>, <&tdmin_b>, - <&tdmin_c>, <&tdmin_lb>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TDMIN_A IN 4", "TDM_B Loopback", - "TDMIN_B IN 4", "TDM_B Loopback", - "TDMIN_C IN 4", "TDM_B Loopback", - "TDMIN_LB IN 1", "TDM_B Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT", - "TODDR_A IN 2", "TDMIN_C OUT", - "TODDR_B IN 2", "TDMIN_C OUT", - "TODDR_C IN 2", "TDMIN_C OUT", - "TODDR_A IN 6", "TDMIN_LB OUT", - "TODDR_B IN 6", "TDMIN_LB OUT", - "TODDR_C IN 6", "TDMIN_LB OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-6 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-7 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -ð_phy { - status = "disabled"; -}; - -&vddcpu_a { - regulator-min-microvolt = <680000>; - regulator-max-microvolt = <1040000>; - - pwms = <&pwm_ab 0 1500 0>; -}; - -&vddcpu_b { - regulator-min-microvolt = <680000>; - regulator-max-microvolt = <1040000>; - - pwms = <&pwm_AO_cd 1 1500 0>; -}; - -&usb2_phy0 { - phy-supply = <&usb_pwr_en>; -}; - -&usb2_phy1 { - phy-supply = <&usb_pwr_en>; -}; diff --git a/arch/arm/dts/meson-g12b-odroid.dtsi b/arch/arm/dts/meson-g12b-odroid.dtsi deleted file mode 100644 index 9e12a34b284..00000000000 --- a/arch/arm/dts/meson-g12b-odroid.dtsi +++ /dev/null @@ -1,445 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/sound/meson-g12a-toacodec.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - rtc1 = &vrtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - fan: gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_HIGH>; - /* Using Dummy Speed */ - gpio-fan,speed-map = <0 0>, <1 1>; - #cooling-cells = <2>; - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - label = "n2:blue"; - gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - tflash_vdd: regulator-tflash_vdd { - compatible = "regulator-fixed"; - - regulator-name = "TFLASH_VDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - tf_io: gpio-regulator-tf_io { - compatible = "regulator-gpio"; - - regulator-name = "TF_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - usb_pwr_en: regulator-usb_pwr_en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the microUSB port power enable */ - gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&main_12v>; - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddcpu_a: regulator-vddcpu-a { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - pwm-supply = <&main_12v>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * Silergy SY8120B1ABC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - pwm-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu_thermal { - trips { - cpu_active: cpu-active { - temperature = <60000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; - }; - - cooling-maps { - map { - trip = <&cpu_active>; - cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&ddr_thermal { - trips { - ddr_active: ddr-active { - temperature = <60000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; - }; - - cooling-maps { - map { - trip = <&ddr_active>; - cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddao_1v8>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&tflash_vdd>; - vqmmc-supply = <&tf_io>; - -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmif_c { - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmin_c { - status = "okay"; -}; - -&tdmin_lb { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tdmout_c { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; -}; - -&usb2_phy0 { - phy-supply = <&vcc_5v>; -}; diff --git a/arch/arm/dts/meson-g12b-radxa-zero2.dts b/arch/arm/dts/meson-g12b-radxa-zero2.dts deleted file mode 100644 index 890f5bfebb0..00000000000 --- a/arch/arm/dts/meson-g12b-radxa-zero2.dts +++ /dev/null @@ -1,489 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com> - * Copyright (c) 2022 Radxa Limited - * Author: Yuntian Zhang <yt@radxa.com> - */ - -/dts-v1/; - -#include "meson-g12b-a311d.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "radxa,zero2", "amlogic,a311d", "amlogic,g12b"; - model = "Radxa Zero2"; - - aliases { - serial0 = &uart_AO; - serial2 = &uart_A; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - power-button { - label = "power"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-green { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio GPIOA_12 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - ao_5v: regulator-ao-5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vcc_1v8: regulator-vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vddcpu_a: regulator-vddcpu-a { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1022000>; - - pwm-supply = <&ao_5v>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * Silergy SY8120B1ABC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1022000>; - - pwm-supply = <&ao_5v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "RADXA-ZERO2"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; - - wifi32k: clock-0 { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&gpio { - gpio-line-names = - /* GPIOZ */ - "PIN_27", "PIN_28", "PIN_7", "PIN_11", "PIN_13", "PIN_15", "PIN_18", "PIN_40", - "", "", "", "", "", "", "", "", - /* GPIOH */ - "", "", "", "", "PIN_19", "PIN_21", "PIN_24", "PIN_23", - "", - /* BOOT */ - "", "", "", "", "", "", "", "", - "", "", "", "", "EMMC_PWRSEQ", "", "", "", - /* GPIOC */ - "", "", "", "", "", "", "SD_CD", "PIN_36", - /* GPIOA */ - "PIN_32", "PIN_12", "PIN_35", "", "", "PIN_38", "", "", - "", "", "", "", "LED_GREEN", "PIN_31", "PIN_3", "PIN_5", - /* GPIOX */ - "", "", "", "", "", "", "SDIO_PWRSEQ", "", - "", "", "", "", "", "", "", "", - "", "BT_SHUTDOWN", "", ""; -}; - -&gpio_ao { - gpio-line-names = - /* GPIOAO */ - "PIN_8", "PIN_10", "", "BTN_POWER", "", "", "", "PIN_29", - "PIN_33", "PIN_37", "FAN", "", - /* GPIOE */ - "", "", ""; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&ao_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "disabled"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_ef { - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_ab { - pinctrl-0 = <&pwm_ao_a_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddao_1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; -}; diff --git a/arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts b/arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts deleted file mode 100644 index 7f66f263a2c..00000000000 --- a/arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-g12b-s922x.dtsi" -#include "meson-g12b-bananapi.dtsi" - -/ { - compatible = "bananapi,bpi-m2s", "amlogic,s922x", "amlogic,g12b"; - model = "BananaPi M2S"; -}; diff --git a/arch/arm/dts/meson-g12b-s922x.dtsi b/arch/arm/dts/meson-g12b-s922x.dtsi deleted file mode 100644 index 1e5d0ee5d54..00000000000 --- a/arch/arm/dts/meson-g12b-s922x.dtsi +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include "meson-g12b.dtsi" - -/ { - cpu_opp_table_0: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <731000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <731000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <731000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <761000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <791000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <831000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <861000>; - }; - - opp-1896000000 { - opp-hz = /bits/ 64 <1896000000>; - opp-microvolt = <981000>; - }; - - opp-1992000000 { - opp-hz = /bits/ 64 <1992000000>; - opp-microvolt = <1001000>; - }; - }; - - cpub_opp_table_1: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <751000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <751000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <751000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <751000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <771000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <771000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <791000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <821000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <861000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <891000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <981000>; - }; - - opp-1908000000 { - opp-hz = /bits/ 64 <1908000000>; - opp-microvolt = <1022000>; - }; - }; -}; diff --git a/arch/arm/dts/meson-g12b-w400.dtsi b/arch/arm/dts/meson-g12b-w400.dtsi deleted file mode 100644 index feb08850474..00000000000 --- a/arch/arm/dts/meson-g12b-w400.dtsi +++ /dev/null @@ -1,425 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-g12b.dtsi" -#include "meson-g12b-s922x.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&main_12v>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddcpu_a: regulator-vddcpu-a { - /* - * MP1653 Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * MP1652 Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - usb1_pow: regulator-usb1-pow { - compatible = "regulator-fixed"; - regulator-name = "USB1_POW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* connected to SY6280A Power Switch */ - gpio = <&gpio GPIOA_8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_pwr_en: regulator-usb-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to USB3 Type-A Port power enable */ - gpio = <&gpio GPIOAO_7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&pwm_ef { - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - non-removable; - disable-wp; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <100000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; - vbus-supply = <&usb_pwr_en>; -}; - -&usb2_phy0 { - phy-supply = <&usb1_pow>; -}; - -&usb2_phy1 { - phy-supply = <&usb1_pow>; -}; diff --git a/arch/arm/dts/meson-g12b.dtsi b/arch/arm/dts/meson-g12b.dtsi deleted file mode 100644 index 75ff00fb2e4..00000000000 --- a/arch/arm/dts/meson-g12b.dtsi +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include "meson-g12.dtsi" - -/ { - compatible = "amlogic,g12b"; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu100>; - }; - - core1 { - cpu = <&cpu101>; - }; - - core2 { - cpu = <&cpu102>; - }; - - core3 { - cpu = <&cpu103>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <592>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - capacity-dmips-mhz = <592>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu100: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0 0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu101: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0 0x101>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu102: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0 0x102>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu103: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0 0x103>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - }; - }; -}; - -&clkc { - compatible = "amlogic,g12b-clkc"; -}; - -&cpu_thermal { - cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&mali { - dma-coherent; -}; - -&pmu { - compatible = "amlogic,g12b-ddr-pmu"; -}; diff --git a/arch/arm/dts/meson-gx-libretech-pc.dtsi b/arch/arm/dts/meson-gx-libretech-pc.dtsi deleted file mode 100644 index 4e84ab87cc7..00000000000 --- a/arch/arm/dts/meson-gx-libretech-pc.dtsi +++ /dev/null @@ -1,447 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 BayLibre SAS. - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -/* Libretech Amlogic GX PC form factor - AKA: Tartiflette */ - -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/sound/meson-aiu.h> - -/ { - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-update { - label = "update"; - linux,code = <KEY_VENDOR>; - press-threshold-microvolt = <1300000>; - }; - }; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - spi0 = &spifc; - }; - - dio2133: analog-amplifier { - compatible = "simple-audio-amplifier"; - sound-name-prefix = "AU2"; - VCC-supply = <&vcc5v>; - enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - status = "disabled"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - - led-green { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_DISK_ACTIVITY; - gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - }; - - led-blue { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - panic-indicator; - }; - }; - - vcc_card: regulator-vcc_card { - compatible = "regulator-fixed"; - regulator-name = "VCC_CARD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddio_ao3v3>; - - gpio = <&gpio GPIODV_4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc5v: regulator-vcc5v { - compatible = "regulator-fixed"; - regulator-name = "VCC5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&ao_5v>; - - gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vddio_ao3v3: regulator-vddio_ao3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddio_ao3v3>; - regulator-always-on; - }; - - vddio_card: regulator-vddio-card { - compatible = "regulator-gpio"; - regulator-name = "VDDIO_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio GPIODV_5 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - - regulator-settling-time-up-us = <200>; - regulator-settling-time-down-us = <50000>; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "LIBRETECH-PC"; - audio-aux-devs = <&dio2133>; - audio-widgets = "Speaker", "7J4-14 LEFT", - "Speaker", "7J4-11 RIGHT"; - audio-routing = "AU2 INL", "ACODEC LOLN", - "AU2 INR", "ACODEC LORN", - "7J4-14 LEFT", "AU2 OUTL", - "7J4-11 RIGHT", "AU2 OUTR"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - - codec-1 { - sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - - dai-link-3 { - sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; - - codec-0 { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddio_ao18>; - status = "okay"; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; - status = "okay"; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_phy_irq_pins>; - pinctrl-names = "default"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - reg = <0>; - max-speed = <1000>; - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <25 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&pinctrl_periphs { - /* - * Make sure the reset pin of the usb HUB is driven high to take - * it out of reset. - */ - usb1_rst_pins: usb1_rst_irq { - mux { - groups = "GPIODV_3"; - function = "gpio_periphs"; - bias-disable; - output-high; - }; - }; - - /* Make sure the phy irq pin is properly configured as input */ - eth_phy_irq_pins: eth_phy_irq { - mux { - groups = "GPIOZ_15"; - function = "gpio_periphs"; - bias-disable; - output-disable; - }; - }; -}; - -&hdmi_tx { - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc5v>; - status = "okay"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c_C { - pinctrl-0 = <&i2c_c_dv18_pins>; - pinctrl-names = "default"; - status = "okay"; - - rtc: rtc@51 { - reg = <0x51>; - compatible = "nxp,pcf8563"; - #clock-cells = <0>; - clock-output-names = "rtc_clkout"; - }; -}; - -&pwm_AO_ab { - pinctrl-0 = <&pwm_ao_a_3_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_b_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_ef { - pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; - status = "okay"; -}; - -&saradc { - vref-supply = <&vddio_ao18>; - status = "okay"; -}; - -/* SD card */ -&sd_emmc_b { - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - max-frequency = <200000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vcc_card>; - vqmmc-supply = <&vddio_card>; - - status = "okay"; -}; - -/* eMMC */ -&sd_emmc_c { - pinctrl-0 = <&emmc_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddio_ao3v3>; - vqmmc-supply = <&vddio_boot>; - - status = "okay"; -}; - -&spifc { - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - status = "okay"; - - gd25lq128: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <12000000>; - }; -}; - -&uart_AO { - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb1_rst_pins>; - pinctrl-names = "default"; - phy-supply = <&vcc5v>; -}; - -&usb2_phy1 { - phy-supply = <&vcc5v>; -}; diff --git a/arch/arm/dts/meson-gx-mali450.dtsi b/arch/arm/dts/meson-gx-mali450.dtsi deleted file mode 100644 index f9771b51c85..00000000000 --- a/arch/arm/dts/meson-gx-mali450.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 BayLibre SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/ { - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-125000000 { - opp-hz = /bits/ 64 <125000000>; - opp-microvolt = <950000>; - }; - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <950000>; - }; - opp-285714285 { - opp-hz = /bits/ 64 <285714285>; - opp-microvolt = <950000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <950000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <950000>; - }; - opp-666666666 { - opp-hz = /bits/ 64 <666666666>; - opp-microvolt = <950000>; - }; - opp-744000000 { - opp-hz = /bits/ 64 <744000000>; - opp-microvolt = <950000>; - }; - }; -}; - -&apb { - mali: gpu@c0000 { - compatible = "arm,mali-450"; - reg = <0x0 0xc0000 0x0 0x40000>; - interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gp", "gpmmu", "pp", "pmu", - "pp0", "ppmmu0", "pp1", "ppmmu1", - "pp2", "ppmmu2"; - operating-points-v2 = <&gpu_opp_table>; - }; -}; diff --git a/arch/arm/dts/meson-gx-p23x-q20x.dtsi b/arch/arm/dts/meson-gx-p23x-q20x.dtsi deleted file mode 100644 index dafc841f7c1..00000000000 --- a/arch/arm/dts/meson-gx-p23x-q20x.dtsi +++ /dev/null @@ -1,324 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -/* Common DTSI for same Amlogic Q200/Q201 and P230/P231 boards using either - * the pin-compatible S912 (GXM) or S905D (GXL) SoCs. - */ - -#include <dt-bindings/sound/meson-aiu.h> - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - dio2133: analog-amplifier { - compatible = "simple-audio-amplifier"; - sound-name-prefix = "AU2"; - VCC-supply = <&hdmi_5v>; - enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - }; - - spdif_dit: audio-codec-0 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - status = "okay"; - sound-name-prefix = "DIT"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - hdmi_5v: regulator-hdmi-5v { - compatible = "regulator-fixed"; - - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "P230-Q200"; - audio-aux-devs = <&dio2133>; - audio-widgets = "Line", "Lineout"; - audio-routing = "AU2 INL", "ACODEC LOLP", - "AU2 INR", "ACODEC LORP", - "AU2 INL", "ACODEC LOLN", - "AU2 INR", "ACODEC LORN", - "Lineout", "AU2 OUTL", - "Lineout", "AU2 OUTR"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - - codec-1 { - sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; - }; - }; - - dai-link-3 { - sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; - - codec-0 { - sound-dai = <&spdif_dit>; - }; - }; - - dai-link-4 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - - dai-link-5 { - sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; - - codec-0 { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddio_ao18>; - status = "okay"; -}; - -&aiu { - status = "okay"; - pinctrl-0 = <&spdif_out_h_pins>; - pinctrl-names = "default"; - -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "otg"; -}; diff --git a/arch/arm/dts/meson-gx.dtsi b/arch/arm/dts/meson-gx.dtsi deleted file mode 100644 index 11f89bfecb5..00000000000 --- a/arch/arm/dts/meson-gx.dtsi +++ /dev/null @@ -1,675 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - * - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/power/meson-gxbb-power.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - mmc0 = &sd_emmc_b; /* SD card */ - mmc1 = &sd_emmc_c; /* eMMC */ - mmc2 = &sd_emmc_a; /* SDIO */ - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 16 MiB reserved for Hardware ROM Firmware */ - hwrom_reserved: hwrom@0 { - reg = <0x0 0x0 0x0 0x1000000>; - no-map; - }; - - /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@10000000 { - reg = <0x0 0x10000000 0x0 0x200000>; - no-map; - }; - - /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved_alt: secmon@5000000 { - reg = <0x0 0x05000000 0x0 0x300000>; - no-map; - }; - - /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ - secmon_reserved_bl32: secmon@5300000 { - reg = <0x0 0x05300000 0x0 0x2000000>; - no-map; - }; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x0 0x10000000>; - alignment = <0x0 0x400000>; - linux,cma-default; - }; - }; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - simplefb_cvbs: framebuffer-cvbs { - compatible = "amlogic,simple-framebuffer", - "simple-framebuffer"; - amlogic,pipeline = "vpu-cvbs"; - power-domains = <&pwrc PWRC_GXBB_VPU_ID>; - status = "disabled"; - }; - - simplefb_hdmi: framebuffer-hdmi { - compatible = "amlogic,simple-framebuffer", - "simple-framebuffer"; - amlogic,pipeline = "vpu-hdmi"; - power-domains = <&pwrc PWRC_GXBB_VPU_ID>; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - #cooling-cells = <2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - thermal-sensors = <&scpi_sensors 0>; - - trips { - cpu_passive: cpu-passive { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - cpu_hot: cpu-hot { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "hot"; - }; - - cpu_critical: cpu-critical { - temperature = <110000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cpu_cooling_maps: cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; - - firmware { - sm: secure-monitor { - compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; - }; - }; - - efuse: efuse { - compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; - #address-cells = <1>; - #size-cells = <1>; - read-only; - secure-monitor = <&sm>; - - sn: sn@14 { - reg = <0x14 0x10>; - }; - - eth_mac: eth-mac@34 { - reg = <0x34 0x10>; - }; - - bid: bid@46 { - reg = <0x46 0x30>; - }; - }; - - scpi { - compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; - mboxes = <&mailbox 1 &mailbox 2>; - shmem = <&cpu_scp_lpri &cpu_scp_hpri>; - - scpi_clocks: clocks { - compatible = "arm,scpi-clocks"; - - scpi_dvfs: clocks-0 { - compatible = "arm,scpi-dvfs-clocks"; - #clock-cells = <1>; - clock-indices = <0>; - clock-output-names = "vcpu"; - }; - }; - - scpi_sensors: sensors { - compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; - #thermal-sensor-cells = <1>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - cbus: bus@c1100000 { - compatible = "simple-bus"; - reg = <0x0 0xc1100000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; - - gpio_intc: interrupt-controller@9880 { - compatible = "amlogic,meson-gpio-intc"; - reg = <0x0 0x9880 0x0 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; - status = "disabled"; - }; - - reset: reset-controller@4404 { - compatible = "amlogic,meson-gxbb-reset"; - reg = <0x0 0x04404 0x0 0x9c>; - #reset-cells = <1>; - }; - - aiu: audio-controller@5400 { - compatible = "amlogic,aiu"; - #sound-dai-cells = <2>; - sound-name-prefix = "AIU"; - reg = <0x0 0x5400 0x0 0x2ac>; - interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "i2s", "spdif"; - status = "disabled"; - }; - - uart_A: serial@84c0 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x84c0 0x0 0x18>; - interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - fifo-size = <128>; - }; - - uart_B: serial@84dc { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x84dc 0x0 0x18>; - interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - - i2c_A: i2c@8500 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x08500 0x0 0x20>; - interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm_ab: pwm@8550 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x08550 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@8650 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x08650 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - saradc: adc@8680 { - compatible = "amlogic,meson-saradc"; - reg = <0x0 0x8680 0x0 0x34>; - #io-channel-cells = <1>; - interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - - pwm_ef: pwm@86c0 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x086c0 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart_C: serial@8700 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x8700 0x0 0x18>; - interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - - clock-measure@8758 { - compatible = "amlogic,meson-gx-clk-measure"; - reg = <0x0 0x8758 0x0 0x10>; - }; - - i2c_B: i2c@87c0 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x087c0 0x0 0x20>; - interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c_C: i2c@87e0 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x087e0 0x0 0x20>; - interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spicc: spi@8d80 { - compatible = "amlogic,meson-gx-spicc"; - reg = <0x0 0x08d80 0x0 0x80>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spifc: spi@8c80 { - compatible = "amlogic,meson-gxbb-spifc"; - reg = <0x0 0x08c80 0x0 0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - watchdog@98d0 { - compatible = "amlogic,meson-gxbb-wdt"; - reg = <0x0 0x098d0 0x0 0x10>; - clocks = <&xtal>; - }; - }; - - gic: interrupt-controller@c4301000 { - compatible = "arm,gic-400"; - reg = <0x0 0xc4301000 0 0x1000>, - <0x0 0xc4302000 0 0x2000>, - <0x0 0xc4304000 0 0x2000>, - <0x0 0xc4306000 0 0x2000>; - interrupt-controller; - interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - - sram: sram@c8000000 { - compatible = "mmio-sram"; - reg = <0x0 0xc8000000 0x0 0x14000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xc8000000 0x14000>; - - cpu_scp_lpri: scp-sram@0 { - compatible = "amlogic,meson-gxbb-scp-shmem"; - reg = <0x13000 0x400>; - }; - - cpu_scp_hpri: scp-sram@200 { - compatible = "amlogic,meson-gxbb-scp-shmem"; - reg = <0x13400 0x400>; - }; - }; - - aobus: bus@c8100000 { - compatible = "simple-bus"; - reg = <0x0 0xc8100000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; - - sysctrl_AO: sys-ctrl@0 { - compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; - reg = <0x0 0x0 0x0 0x100>; - - clkc_AO: clock-controller { - compatible = "amlogic,meson-gx-aoclkc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - }; - - cec_AO: cec@100 { - compatible = "amlogic,meson-gx-ao-cec"; - reg = <0x0 0x00100 0x0 0x14>; - interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - - sec_AO: ao-secure@140 { - compatible = "amlogic,meson-gx-ao-secure", "syscon"; - reg = <0x0 0x140 0x0 0x140>; - amlogic,has-chip-id; - }; - - uart_AO: serial@4c0 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; - reg = <0x0 0x004c0 0x0 0x18>; - interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - - uart_AO_B: serial@4e0 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; - reg = <0x0 0x004e0 0x0 0x18>; - interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - - i2c_AO: i2c@500 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x500 0x0 0x20>; - interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm_AO_ab: pwm@550 { - compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; - reg = <0x0 0x00550 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - ir: ir@580 { - compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; - reg = <0x0 0x00580 0x0 0x40>; - interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - }; - - vdec: video-codec@c8820000 { - compatible = "amlogic,gx-vdec"; - reg = <0x0 0xc8820000 0x0 0x10000>, - <0x0 0xc110a580 0x0 0xe4>; - reg-names = "dos", "esparser"; - - interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "vdec", "esparser"; - - amlogic,ao-sysctrl = <&sysctrl_AO>; - amlogic,canvas = <&canvas>; - }; - - periphs: bus@c8834000 { - compatible = "simple-bus"; - reg = <0x0 0xc8834000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; - - hwrng: rng@0 { - compatible = "amlogic,meson-rng"; - reg = <0x0 0x0 0x0 0x4>; - }; - }; - - dmcbus: bus@c8838000 { - compatible = "simple-bus"; - reg = <0x0 0xc8838000 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>; - - canvas: video-lut@48 { - compatible = "amlogic,canvas"; - reg = <0x0 0x48 0x0 0x14>; - }; - }; - - hiubus: bus@c883c000 { - compatible = "simple-bus"; - reg = <0x0 0xc883c000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; - - sysctrl: system-controller@0 { - compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"; - reg = <0 0 0 0x400>; - - pwrc: power-controller { - compatible = "amlogic,meson-gxbb-pwrc"; - #power-domain-cells = <1>; - amlogic,ao-sysctrl = <&sysctrl_AO>; - }; - }; - - mailbox: mailbox@404 { - compatible = "amlogic,meson-gxbb-mhu"; - reg = <0 0x404 0 0x4c>; - interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; - #mbox-cells = <1>; - }; - }; - - ethmac: ethernet@c9410000 { - compatible = "amlogic,meson-gxbb-dwmac", - "snps,dwmac-3.70a", - "snps,dwmac"; - reg = <0x0 0xc9410000 0x0 0x10000>, - <0x0 0xc8834540 0x0 0x4>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - rx-fifo-depth = <4096>; - tx-fifo-depth = <2048>; - power-domains = <&pwrc PWRC_GXBB_ETHERNET_MEM_ID>; - status = "disabled"; - }; - - apb: apb@d0000000 { - compatible = "simple-bus"; - reg = <0x0 0xd0000000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; - - sd_emmc_a: mmc@70000 { - compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x70000 0x0 0x800>; - interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - sd_emmc_b: mmc@72000 { - compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x72000 0x0 0x800>; - interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - sd_emmc_c: mmc@74000 { - compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x74000 0x0 0x800>; - interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - }; - - vpu: vpu@d0100000 { - compatible = "amlogic,meson-gx-vpu"; - reg = <0x0 0xd0100000 0x0 0x100000>, - <0x0 0xc883c000 0x0 0x1000>; - reg-names = "vpu", "hhi"; - interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - amlogic,canvas = <&canvas>; - - /* CVBS VDAC output port */ - cvbs_vdac_port: port@0 { - reg = <0>; - }; - - /* HDMI-TX output port */ - hdmi_tx_port: port@1 { - reg = <1>; - - hdmi_tx_out: endpoint { - remote-endpoint = <&hdmi_tx_in>; - }; - }; - }; - - hdmi_tx: hdmi-tx@c883a000 { - compatible = "amlogic,meson-gx-dw-hdmi"; - reg = <0x0 0xc883a000 0x0 0x1c>; - interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <0>; - sound-name-prefix = "HDMITX"; - status = "disabled"; - - /* VPU VENC Input */ - hdmi_tx_venc_port: port@0 { - reg = <0>; - - hdmi_tx_in: endpoint { - remote-endpoint = <&hdmi_tx_out>; - }; - }; - - /* TMDS Output */ - hdmi_tx_tmds_port: port@1 { - reg = <1>; - }; - }; - }; -}; diff --git a/arch/arm/dts/meson-gxbb-kii-pro.dts b/arch/arm/dts/meson-gxbb-kii-pro.dts deleted file mode 100644 index e238f1f1012..00000000000 --- a/arch/arm/dts/meson-gxbb-kii-pro.dts +++ /dev/null @@ -1,140 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Mohammad Rasim <mohammad.rasim96@gmail.com> - */ - -/dts-v1/; - -#include "meson-gxbb-p20x.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/sound/meson-aiu.h> - -/ { - compatible = "videostrong,kii-pro", "amlogic,meson-gxbb"; - model = "Videostrong KII Pro"; - - spdif_dit: audio-codec-0 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - status = "okay"; - sound-name-prefix = "DIT"; - }; - - leds { - compatible = "gpio-leds"; - led { - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; - color = <LED_COLOR_ID_RED>; - function = LED_FUNCTION_STATUS; - default-state = "off"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <20>; - - button-reset { - label = "reset"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "KII-PRO"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - }; - - dai-link-3 { - sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; - - codec-0 { - sound-dai = <&spdif_dit>; - }; - }; - - dai-link-4 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&aiu { - status = "okay"; - pinctrl-0 = <&spdif_out_y_pins>; - pinctrl-names = "default"; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rmii"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* IC Plus IP101GR (0x02430c54) */ - reg = <0>; - reset-assert-us = <10000>; - reset-deassert-us = <10000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ir { - linux,rc-map-name = "rc-videostrong-kii-pro"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm4335a0"; - shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts b/arch/arm/dts/meson-gxbb-nanopi-k2.dts deleted file mode 100644 index 7d94160f580..00000000000 --- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts +++ /dev/null @@ -1,426 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Andreas Färber - */ - -/dts-v1/; - -#include "meson-gxbb.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/sound/meson-aiu.h> - -/ { - compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb"; - model = "FriendlyARM NanoPi K2"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-stat { - label = "nanopi-k2:blue:stat"; - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; - default-state = "on"; - panic-indicator; - }; - }; - - vdd_5v: regulator-vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "VDD_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vddio_ao18: regulator-vddio-ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddio_ao3v3: regulator-vddio-ao3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_tf: regulator-vddio-tf { - compatible = "regulator-gpio"; - - regulator-name = "VDDIO_TF"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - - regulator-settling-time-up-us = <100>; - regulator-settling-time-down-us = <5000>; - }; - - wifi_32k: wifi-32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi_32k>; - clock-names = "ext_clock"; - }; - - vcc1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - /* CVBS is available on CON1 pin 36, disabled by default */ - cvbs-connector { - compatible = "composite-video-connector"; - status = "disabled"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "NANOPI-K2"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <2>; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&gpio_ao { - gpio-line-names = "UART TX", "UART RX", "Power Control", "Power Key In", - "VCCK En", "CON1 Header Pin31", - "I2S Header Pin6", "IR In", "I2S Header Pin7", - "I2S Header Pin3", "I2S Header Pin4", - "I2S Header Pin5", "HDMI CEC", "SYS LED", - /* GPIO_TEST_N */ - ""; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", - "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", - "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En", - "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3", - "Eth PHY nRESET", "Eth PHY Intc", - /* Bank GPIOH */ - "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", - "CON1 Header Pin33", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4", - "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk", - "eMMC Reset", "eMMC CMD", - "", "", "", "", "eMMC DS", - "", "", - /* Bank CARD */ - "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", - "SDCard D3", "SDCard D2", "SDCard Det", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", - "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", - "VDDEE Regulator", "VCCK Regulator", - /* Bank GPIOY */ - "CON1 Header Pin7", "CON1 Header Pin11", - "CON1 Header Pin13", "CON1 Header Pin15", - "CON1 Header Pin18", "CON1 Header Pin19", - "CON1 Header Pin22", "CON1 Header Pin21", - "CON1 Header Pin24", "CON1 Header Pin23", - "CON1 Header Pin26", "CON1 Header Pin29", - "CON1 Header Pin32", "CON1 Header Pin8", - "CON1 Header Pin10", "CON1 Header Pin16", - "CON1 Header Pin12", - /* Bank GPIOX */ - "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2", - "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD", - "WIFI Power Enable", "WIFI WAKE HOST", - "Bluetooth PCM DOUT", "Bluetooth PCM DIN", - "Bluetooth PCM SYNC", "Bluetooth PCM CLK", - "Bluetooth UART TX", "Bluetooth UART RX", - "Bluetooth UART CTS", "Bluetooth UART RTS", - "", "", "", "WIFI 32K", "Bluetooth Enable", - "Bluetooth WAKE HOST", "", - /* Bank GPIOCLK */ - "", "CON1 Header Pin35", "", ""; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>, <&sdio_irq_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddio_ao3v3>; - vqmmc-supply = <&vddio_ao18>; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - }; -}; - -/* SD */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddio_ao3v3>; - vqmmc-supply = <&vddio_tf>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "disabled"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - disable-wp; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc3v3>; - vqmmc-supply = <&vcc1v8>; -}; - -/* DBG_UART */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -/* Bluetooth on AP6212 */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&wifi_32k>; - clock-names = "lpo"; - vbat-supply = <&vddio_ao3v3>; - vddio-supply = <&vddio_ao18>; - host-wakeup-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; - }; -}; - -/* 40-pin CON1 */ -&uart_C { - status = "disabled"; - pinctrl-0 = <&uart_c_pins>; - pinctrl-names = "default"; -}; - -&usb0_phy { - status = "okay"; - phy-supply = <&vdd_5v>; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts deleted file mode 100644 index 01356437a07..00000000000 --- a/arch/arm/dts/meson-gxbb-odroidc2.dts +++ /dev/null @@ -1,414 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Kevin Hilman <khilman@kernel.org> - */ - -/dts-v1/; - -#include "meson-gxbb.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/sound/meson-aiu.h> - -/ { - compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb"; - model = "Hardkernel ODROID-C2"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - usb_otg_pwr: regulator-usb-pwrs { - compatible = "regulator-fixed"; - - regulator-name = "USB_OTG_PWR"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - /* - * signal name from schematics: PWREN - */ - gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * signal name from schematics: USB_POWER - */ - vin-supply = <&p5v0>; - }; - - leds { - compatible = "gpio-leds"; - led-blue { - label = "c2:blue:alive"; - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - p5v0: regulator-p5v0 { - compatible = "regulator-fixed"; - - regulator-name = "P5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - hdmi_p5v0: regulator-hdmi_p5v0 { - compatible = "regulator-fixed"; - regulator-name = "HDMI_P5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - /* AP2331SA-7 */ - vin-supply = <&p5v0>; - }; - - tflash_vdd: regulator-tflash_vdd { - compatible = "regulator-fixed"; - - regulator-name = "TFLASH_VDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - /* - * signal name from schematics: TFLASH_VDD_EN - */ - gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* U16 RT9179GB */ - vin-supply = <&vddio_ao3v3>; - }; - - tf_io: gpio-regulator-tf_io { - compatible = "regulator-gpio"; - - regulator-name = "TF_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - /* - * signal name from schematics: TF_3V3N_1V8_EN - */ - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - /* U12/U13 RT9179GB */ - vin-supply = <&vddio_ao3v3>; - }; - - vcc1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - /* U18 RT9179GB */ - vin-supply = <&vddio_ao3v3>; - }; - - vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao1v8: regulator-vddio-ao1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - /* U17 RT9179GB */ - vin-supply = <&p5v0>; - }; - - vddio_ao3v3: regulator-vddio-ao3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - /* U11 MP2161GJ-C499 */ - vin-supply = <&p5v0>; - }; - - ddr3_1v5: regulator-ddr3_1v5 { - compatible = "regulator-fixed"; - regulator-name = "DDR3_1V5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - /* U15 MP2161GJ-C499 */ - vin-supply = <&p5v0>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "ODROID-C2"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <2>; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_p5v0>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-odroid"; -}; - -&gpio_ao { - gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En", - "USB HUB nRESET", "USB OTG Power En", - "J7 Header Pin2", "IR In", "J7 Header Pin4", - "J7 Header Pin6", "J7 Header Pin5", "J7 Header Pin7", - "HDMI CEC", "SYS LED", - /* GPIO_TEST_N */ - ""; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", - "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", - "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En", - "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3", - "Eth PHY nRESET", "Eth PHY Intc", - /* Bank GPIOH */ - "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", "", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4", - "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk", - "eMMC Reset", "eMMC CMD", - "", "", "", "", "", "", "", - /* Bank CARD */ - "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", - "SDCard D3", "SDCard D2", "SDCard Det", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", - "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", - "PWM D", "PWM B", - /* Bank GPIOY */ - "Revision Bit0", "Revision Bit1", "", - "J2 Header Pin35", "", "", "", "J2 Header Pin36", - "J2 Header Pin31", "", "", "", "TF VDD En", - "J2 Header Pin32", "J2 Header Pin26", "", "", - /* Bank GPIOX */ - "J2 Header Pin29", "J2 Header Pin24", - "J2 Header Pin23", "J2 Header Pin22", - "J2 Header Pin21", "J2 Header Pin18", - "J2 Header Pin33", "J2 Header Pin19", - "J2 Header Pin16", "J2 Header Pin15", - "J2 Header Pin12", "J2 Header Pin13", - "J2 Header Pin8", "J2 Header Pin10", - "", "", "", "", "", - "J2 Header Pin11", "", "J2 Header Pin7", "", - /* Bank GPIOCLK */ - "", "", "", ""; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc1v8>; -}; - -&scpi_clocks { - status = "disabled"; -}; - -/* SD */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&tflash_vdd>; - vqmmc-supply = <&tf_io>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - disable-wp; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc3v3>; - vqmmc-supply = <&vcc1v8>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0_phy { - status = "disabled"; - phy-supply = <&usb_otg_pwr>; -}; - -&usb1_phy { - status = "okay"; - phy-supply = <&usb_otg_pwr>; -}; - -&usb0 { - status = "disabled"; -}; - -&usb1 { - dr_mode = "host"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - hub@1 { - /* Genesys Logic GL852G USB 2.0 hub */ - compatible = "usb5e3,610"; - reg = <1>; - vdd-supply = <&p5v0>; - reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; - }; -}; diff --git a/arch/arm/dts/meson-gxbb-p200.dts b/arch/arm/dts/meson-gxbb-p200.dts deleted file mode 100644 index 3c93d1898b4..00000000000 --- a/arch/arm/dts/meson-gxbb-p200.dts +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Kevin Hilman <khilman@kernel.org> - */ - -/dts-v1/; - -#include "meson-gxbb-p20x.dtsi" -#include <dt-bindings/input/input.h> - -/ { - compatible = "amlogic,p200", "amlogic,meson-gxbb"; - model = "Amlogic Meson GXBB P200 Development Board"; - - avdd18_usb_adc: regulator-avdd18_usb_adc { - compatible = "regulator-fixed"; - regulator-name = "AVDD18_USB_ADC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - adc_keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-home { - label = "Home"; - linux,code = <KEY_HOME>; - press-threshold-microvolt = <900000>; /* 50% */ - }; - - button-esc { - label = "Esc"; - linux,code = <KEY_ESC>; - press-threshold-microvolt = <684000>; /* 38% */ - }; - - button-up { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - press-threshold-microvolt = <468000>; /* 26% */ - }; - - button-down { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - press-threshold-microvolt = <252000>; /* 14% */ - }; - - button-menu { - label = "Menu"; - linux,code = <KEY_MENU>; - press-threshold-microvolt = <0>; /* 0% */ - }; - }; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <2>; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@3 { - /* Micrel KSZ9031 (0x00221620) */ - reg = <3>; - - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&i2c_B { - status = "okay"; - pinctrl-0 = <&i2c_b_pins>; - pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&avdd18_usb_adc>; -}; diff --git a/arch/arm/dts/meson-gxbb-p201.dts b/arch/arm/dts/meson-gxbb-p201.dts deleted file mode 100644 index 150a82f3b2d..00000000000 --- a/arch/arm/dts/meson-gxbb-p201.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Kevin Hilman <khilman@kernel.org> - */ - -/dts-v1/; - -#include "meson-gxbb-p20x.dtsi" - -/ { - compatible = "amlogic,p201", "amlogic,meson-gxbb"; - model = "Amlogic Meson GXBB P201 Development Board"; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rmii_pins>; - pinctrl-names = "default"; - phy-mode = "rmii"; - - snps,reset-gpio = <&gpio GPIOZ_14 0>; - snps,reset-delays-us = <0>, <10000>, <1000000>; - snps,reset-active-low; -}; diff --git a/arch/arm/dts/meson-gxbb-p20x.dtsi b/arch/arm/dts/meson-gxbb-p20x.dtsi deleted file mode 100644 index e803a466fe4..00000000000 --- a/arch/arm/dts/meson-gxbb-p20x.dtsi +++ /dev/null @@ -1,250 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Kevin Hilman <khilman@kernel.org> - */ - -#include "meson-gxbb.dtsi" - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - usb_pwr: regulator-usb-pwrs { - compatible = "regulator-fixed"; - - regulator-name = "USB_PWR"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - /* signal name in schematic: USB_PWR_EN */ - gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddio_card: gpio-regulator { - compatible = "regulator-gpio"; - - regulator-name = "VDDIO_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - - /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ - states = <1800000 0>, - <3300000 1>; - - regulator-settling-time-up-us = <10000>; - regulator-settling-time-down-us = <150000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - cvbs_connector: cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_card>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0_phy { - status = "okay"; - phy-supply = <&usb_pwr>; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm/dts/meson-gxbb-wetek-hub.dts b/arch/arm/dts/meson-gxbb-wetek-hub.dts deleted file mode 100644 index 58733017eda..00000000000 --- a/arch/arm/dts/meson-gxbb-wetek-hub.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 BayLibre, Inc. - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/dts-v1/; - -#include "meson-gxbb-wetek.dtsi" -#include <dt-bindings/sound/meson-aiu.h> - -/ { - compatible = "wetek,hub", "amlogic,meson-gxbb"; - model = "WeTek Hub"; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "WETEK-HUB"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&aiu { - status = "okay"; -}; - -&ir { - linux,rc-map-name = "rc-wetek-hub"; -}; diff --git a/arch/arm/dts/meson-gxbb-wetek-play2.dts b/arch/arm/dts/meson-gxbb-wetek-play2.dts deleted file mode 100644 index 505ffcd8eb7..00000000000 --- a/arch/arm/dts/meson-gxbb-wetek-play2.dts +++ /dev/null @@ -1,119 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 BayLibre, Inc. - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/dts-v1/; - -#include "meson-gxbb-wetek.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/sound/meson-aiu.h> - -/ { - compatible = "wetek,play2", "amlogic,meson-gxbb"; - model = "WeTek Play 2"; - - spdif_dit: audio-codec-0 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - status = "okay"; - sound-name-prefix = "DIT"; - }; - - leds { - led-wifi { - label = "wetek-play:wifi-status"; - gpios = <&gpio GPIODV_26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-ethernet { - label = "wetek-play:ethernet-status"; - gpios = <&gpio GPIODV_27 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - button { - label = "reset"; - linux,code = <KEY_RESTART>; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; - }; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "WETEK-PLAY2"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - }; - - dai-link-3 { - sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; - - codec-0 { - sound-dai = <&spdif_dit>; - }; - }; - - dai-link-4 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&aiu { - status = "okay"; - pinctrl-0 = <&spdif_out_y_pins>; - pinctrl-names = "default"; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&ir { - linux,rc-map-name = "rc-wetek-play2"; -}; diff --git a/arch/arm/dts/meson-gxbb-wetek.dtsi b/arch/arm/dts/meson-gxbb-wetek.dtsi deleted file mode 100644 index 94dafb95530..00000000000 --- a/arch/arm/dts/meson-gxbb-wetek.dtsi +++ /dev/null @@ -1,292 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Kevin Hilman <khilman@kernel.org> - */ - -#include "meson-gxbb.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-power { - /* red in suspend or power-off */ - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_POWER; - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; - default-state = "on"; - panic-indicator; - }; - }; - - usb_pwr: regulator-usb-pwrs { - compatible = "regulator-fixed"; - - regulator-name = "USB_PWR"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <2>; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vddio_ao18>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vcc_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* This is connected to the Bluetooth module: */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; - }; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0_phy { - status = "okay"; - phy-supply = <&usb_pwr>; -}; - -&usb0 { - status = "okay"; -}; diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi deleted file mode 100644 index 12ef6e81c8b..00000000000 --- a/arch/arm/dts/meson-gxbb.dtsi +++ /dev/null @@ -1,870 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -#include "meson-gx.dtsi" -#include "meson-gx-mali450.dtsi" -#include <dt-bindings/gpio/meson-gxbb-gpio.h> -#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> -#include <dt-bindings/clock/gxbb-clkc.h> -#include <dt-bindings/clock/gxbb-aoclkc.h> -#include <dt-bindings/reset/gxbb-aoclkc.h> - -/ { - compatible = "amlogic,meson-gxbb"; - - soc { - usb0_phy: phy@c0000000 { - compatible = "amlogic,meson-gxbb-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0xc0000000 0x0 0x20>; - resets = <&reset RESET_USB_OTG>; - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; - clock-names = "usb_general", "usb"; - status = "disabled"; - }; - - usb1_phy: phy@c0000020 { - compatible = "amlogic,meson-gxbb-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0xc0000020 0x0 0x20>; - resets = <&reset RESET_USB_OTG>; - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; - clock-names = "usb_general", "usb"; - status = "disabled"; - }; - - usb0: usb@c9000000 { - compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; - reg = <0x0 0xc9000000 0x0 0x40000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; - clock-names = "otg"; - phys = <&usb0_phy>; - phy-names = "usb2-phy"; - dr_mode = "host"; - status = "disabled"; - }; - - usb1: usb@c9100000 { - compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; - reg = <0x0 0xc9100000 0x0 0x40000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "otg"; - phys = <&usb1_phy>; - phy-names = "usb2-phy"; - dr_mode = "host"; - status = "disabled"; - }; - }; -}; - -&aiu { - compatible = "amlogic,aiu-gxbb", "amlogic,aiu"; - clocks = <&clkc CLKID_AIU_GLUE>, - <&clkc CLKID_I2S_OUT>, - <&clkc CLKID_AOCLK_GATE>, - <&clkc CLKID_CTS_AMCLK>, - <&clkc CLKID_MIXER_IFACE>, - <&clkc CLKID_IEC958>, - <&clkc CLKID_IEC958_GATE>, - <&clkc CLKID_CTS_MCLK_I958>, - <&clkc CLKID_CTS_I958>; - clock-names = "pclk", - "i2s_pclk", - "i2s_aoclk", - "i2s_mclk", - "i2s_mixer", - "spdif_pclk", - "spdif_aoclk", - "spdif_mclk", - "spdif_mclk_sel"; - resets = <&reset RESET_AIU>; -}; - -&aobus { - pinctrl_aobus: pinctrl@14 { - compatible = "amlogic,meson-gxbb-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x00014 0x0 0x8>, - <0x0 0x0002c 0x0 0x4>, - <0x0 0x00024 0x0 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 0 14>; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { - mux { - groups = "uart_cts_ao_a", - "uart_rts_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - uart_ao_b_pins: uart_ao_b { - mux { - groups = "uart_tx_ao_b", "uart_rx_ao_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { - mux { - groups = "uart_cts_ao_b", - "uart_rts_ao_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - remote_input_ao_pins: remote_input_ao { - mux { - groups = "remote_input_ao"; - function = "remote_input_ao"; - bias-disable; - }; - }; - - i2c_ao_pins: i2c_ao { - mux { - groups = "i2c_sck_ao", - "i2c_sda_ao"; - function = "i2c_ao"; - bias-disable; - }; - }; - - pwm_ao_a_3_pins: pwm_ao_a_3 { - mux { - groups = "pwm_ao_a_3"; - function = "pwm_ao_a_3"; - bias-disable; - }; - }; - - pwm_ao_a_6_pins: pwm_ao_a_6 { - mux { - groups = "pwm_ao_a_6"; - function = "pwm_ao_a_6"; - bias-disable; - }; - }; - - pwm_ao_a_12_pins: pwm_ao_a_12 { - mux { - groups = "pwm_ao_a_12"; - function = "pwm_ao_a_12"; - bias-disable; - }; - }; - - pwm_ao_b_pins: pwm_ao_b { - mux { - groups = "pwm_ao_b"; - function = "pwm_ao_b"; - bias-disable; - }; - }; - - i2s_am_clk_pins: i2s_am_clk { - mux { - groups = "i2s_am_clk"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_ao_clk_pins: i2s_out_ao_clk { - mux { - groups = "i2s_out_ao_clk"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_lr_clk_pins: i2s_out_lr_clk { - mux { - groups = "i2s_out_lr_clk"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_ch01_ao_pins: i2s_out_ch01_ao { - mux { - groups = "i2s_out_ch01_ao"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_ch23_ao_pins: i2s_out_ch23_ao { - mux { - groups = "i2s_out_ch23_ao"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_ch45_ao_pins: i2s_out_ch45_ao { - mux { - groups = "i2s_out_ch45_ao"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - spdif_out_ao_6_pins: spdif_out_ao_6 { - mux { - groups = "spdif_out_ao_6"; - function = "spdif_out_ao"; - }; - }; - - spdif_out_ao_13_pins: spdif_out_ao_13 { - mux { - groups = "spdif_out_ao_13"; - function = "spdif_out_ao"; - bias-disable; - }; - }; - - ao_cec_pins: ao_cec { - mux { - groups = "ao_cec"; - function = "cec_ao"; - bias-disable; - }; - }; - - ee_cec_pins: ee_cec { - mux { - groups = "ee_cec"; - function = "cec_ao"; - bias-disable; - }; - }; - }; -}; - -&cbus { - spifc: spi@8c80 { - compatible = "amlogic,meson-gxbb-spifc"; - reg = <0x0 0x08c80 0x0 0x80>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_SPI>; - status = "disabled"; - }; -}; - -&cec_AO { - clocks = <&clkc_AO CLKID_AO_CEC_32K>; - clock-names = "core"; -}; - -&clkc_AO { - compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; -}; - -&efuse { - clocks = <&clkc CLKID_EFUSE>; -}; - -ðmac { - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; -}; - -&gpio_intc { - compatible = "amlogic,meson-gxbb-gpio-intc", - "amlogic,meson-gpio-intc"; - status = "okay"; -}; - -&hdmi_tx { - compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; - resets = <&reset RESET_HDMITX_CAPB3>, - <&reset RESET_HDMI_SYSTEM_RESET>, - <&reset RESET_HDMI_TX>; - reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, - <&clkc CLKID_GCLK_VENCI_INT0>; - clock-names = "isfr", "iahb", "venci"; -}; - -&sysctrl { - clkc: clock-controller { - compatible = "amlogic,gxbb-clkc"; - #clock-cells = <1>; - clocks = <&xtal>; - clock-names = "xtal"; - }; -}; - -&hwrng { - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; -}; - -&i2c_A { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_AO { - clocks = <&clkc CLKID_AO_I2C>; -}; - -&i2c_B { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_C { - clocks = <&clkc CLKID_I2C>; -}; - -&mali { - compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; - - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; - - assigned-clocks = <&clkc CLKID_GP0_PLL>; - assigned-clock-rates = <744000000>; -}; - -&periphs { - pinctrl_periphs: pinctrl@4b0 { - compatible = "amlogic,meson-gxbb-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@4b0 { - reg = <0x0 0x004b0 0x0 0x28>, - <0x0 0x004e8 0x0 0x14>, - <0x0 0x00520 0x0 0x14>, - <0x0 0x00430 0x0 0x40>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_periphs 0 0 119>; - }; - - emmc_pins: emmc { - mux-0 { - groups = "emmc_nand_d07", - "emmc_cmd"; - function = "emmc"; - bias-pull-up; - }; - - mux-1 { - groups = "emmc_clk"; - function = "emmc"; - bias-disable; - }; - }; - - emmc_ds_pins: emmc-ds { - mux { - groups = "emmc_ds"; - function = "emmc"; - bias-pull-down; - }; - }; - - emmc_clk_gate_pins: emmc_clk_gate { - mux { - groups = "BOOT_8"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - nor_pins: nor { - mux { - groups = "nor_d", - "nor_q", - "nor_c", - "nor_cs"; - function = "nor"; - bias-disable; - }; - }; - - spi_pins: spi-pins { - mux { - groups = "spi_miso", - "spi_mosi", - "spi_sclk"; - function = "spi"; - bias-disable; - }; - }; - - spi_idle_high_pins: spi-idle-high-pins { - mux { - groups = "spi_sclk"; - bias-pull-up; - }; - }; - - spi_idle_low_pins: spi-idle-low-pins { - mux { - groups = "spi_sclk"; - bias-pull-down; - }; - }; - - spi_ss0_pins: spi-ss0 { - mux { - groups = "spi_ss0"; - function = "spi"; - bias-disable; - }; - }; - - sdcard_pins: sdcard { - mux-0 { - groups = "sdcard_d0", - "sdcard_d1", - "sdcard_d2", - "sdcard_d3", - "sdcard_cmd"; - function = "sdcard"; - bias-pull-up; - }; - - mux-1 { - groups = "sdcard_clk"; - function = "sdcard"; - bias-disable; - }; - }; - - sdcard_clk_gate_pins: sdcard_clk_gate { - mux { - groups = "CARD_2"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - sdio_pins: sdio { - mux-0 { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_cmd"; - function = "sdio"; - bias-pull-up; - }; - - mux-1 { - groups = "sdio_clk"; - function = "sdio"; - bias-disable; - }; - }; - - sdio_clk_gate_pins: sdio_clk_gate { - mux { - groups = "GPIOX_4"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - sdio_irq_pins: sdio_irq { - mux { - groups = "sdio_irq"; - function = "sdio"; - bias-disable; - }; - }; - - uart_a_pins: uart_a { - mux { - groups = "uart_tx_a", - "uart_rx_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a_cts_rts_pins: uart_a_cts_rts { - mux { - groups = "uart_cts_a", - "uart_rts_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_b_pins: uart_b { - mux { - groups = "uart_tx_b", - "uart_rx_b"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_cts_rts_pins: uart_b_cts_rts { - mux { - groups = "uart_cts_b", - "uart_rts_b"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_c_pins: uart_c { - mux { - groups = "uart_tx_c", - "uart_rx_c"; - function = "uart_c"; - bias-disable; - }; - }; - - uart_c_cts_rts_pins: uart_c_cts_rts { - mux { - groups = "uart_cts_c", - "uart_rts_c"; - function = "uart_c"; - bias-disable; - }; - }; - - i2c_a_pins: i2c_a { - mux { - groups = "i2c_sck_a", - "i2c_sda_a"; - function = "i2c_a"; - bias-disable; - }; - }; - - i2c_b_pins: i2c_b { - mux { - groups = "i2c_sck_b", - "i2c_sda_b"; - function = "i2c_b"; - bias-disable; - }; - }; - - i2c_c_pins: i2c_c { - mux { - groups = "i2c_sck_c", - "i2c_sda_c"; - function = "i2c_c"; - bias-disable; - }; - }; - - eth_rgmii_pins: eth-rgmii { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_clk_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_rxd2", - "eth_rxd3", - "eth_rgmii_tx_clk", - "eth_tx_en", - "eth_txd0", - "eth_txd1", - "eth_txd2", - "eth_txd3"; - function = "eth"; - bias-disable; - }; - }; - - eth_rmii_pins: eth-rmii { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_clk_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_tx_en", - "eth_txd0", - "eth_txd1"; - function = "eth"; - bias-disable; - }; - }; - - pwm_a_x_pins: pwm_a_x { - mux { - groups = "pwm_a_x"; - function = "pwm_a_x"; - bias-disable; - }; - }; - - pwm_a_y_pins: pwm_a_y { - mux { - groups = "pwm_a_y"; - function = "pwm_a_y"; - bias-disable; - }; - }; - - pwm_b_pins: pwm_b { - mux { - groups = "pwm_b"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_d_pins: pwm_d { - mux { - groups = "pwm_d"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_e_pins: pwm_e { - mux { - groups = "pwm_e"; - function = "pwm_e"; - bias-disable; - }; - }; - - pwm_f_x_pins: pwm_f_x { - mux { - groups = "pwm_f_x"; - function = "pwm_f_x"; - bias-disable; - }; - }; - - pwm_f_y_pins: pwm_f_y { - mux { - groups = "pwm_f_y"; - function = "pwm_f_y"; - bias-disable; - }; - }; - - hdmi_hpd_pins: hdmi_hpd { - mux { - groups = "hdmi_hpd"; - function = "hdmi_hpd"; - bias-disable; - }; - }; - - hdmi_i2c_pins: hdmi_i2c { - mux { - groups = "hdmi_sda", "hdmi_scl"; - function = "hdmi_i2c"; - bias-disable; - }; - }; - - i2sout_ch23_y_pins: i2sout_ch23_y { - mux { - groups = "i2sout_ch23_y"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2sout_ch45_y_pins: i2sout_ch45_y { - mux { - groups = "i2sout_ch45_y"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2sout_ch67_y_pins: i2sout_ch67_y { - mux { - groups = "i2sout_ch67_y"; - function = "i2s_out"; - bias-disable; - }; - }; - - spdif_out_y_pins: spdif_out_y { - mux { - groups = "spdif_out_y"; - function = "spdif_out"; - bias-disable; - }; - }; - }; -}; - -&pwrc { - resets = <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_VCBUS>, - <&reset RESET_BT656>, - <&reset RESET_DVIN_RESET>, - <&reset RESET_RDMA>, - <&reset RESET_VENCI>, - <&reset RESET_VENCP>, - <&reset RESET_VDAC>, - <&reset RESET_VDI6>, - <&reset RESET_VENCL>, - <&reset RESET_VID_LOCK>; - reset-names = "viu", "venc", "vcbus", "bt656", - "dvin", "rdma", "venci", "vencp", - "vdac", "vdi6", "vencl", "vid_lock"; - clocks = <&clkc CLKID_VPU>, - <&clkc CLKID_VAPB>; - clock-names = "vpu", "vapb"; - /* - * VPU clocking is provided by two identical clock paths - * VPU_0 and VPU_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - * Same for VAPB but with a final gate after the glitch free mux. - */ - assigned-clocks = <&clkc CLKID_VPU_0_SEL>, - <&clkc CLKID_VPU_0>, - <&clkc CLKID_VPU>, /* Glitch free mux */ - <&clkc CLKID_VAPB_0_SEL>, - <&clkc CLKID_VAPB_0>, - <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_VPU_0>, - <&clkc CLKID_FCLK_DIV4>, - <0>, /* Do Nothing */ - <&clkc CLKID_VAPB_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>, /* Do Nothing */ - <0>, /* Do Nothing */ - <250000000>, - <0>; /* Do Nothing */ -}; - -&saradc { - compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc"; - clocks = <&xtal>, - <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SAR_ADC_CLK>, - <&clkc CLKID_SAR_ADC_SEL>; - clock-names = "clkin", "core", "adc_clk", "adc_sel"; -}; - -&sd_emmc_a { - clocks = <&clkc CLKID_SD_EMMC_A>, - <&clkc CLKID_SD_EMMC_A_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_A>; -}; - -&sd_emmc_b { - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_B>; -}; - -&sd_emmc_c { - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_C>; -}; - -&simplefb_hdmi { - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, - <&clkc CLKID_GCLK_VENCI_INT0>; -}; - -&spicc { - clocks = <&clkc CLKID_SPICC>; - clock-names = "core"; - resets = <&reset RESET_PERIPHS_SPICC>; - num-cs = <1>; -}; - -&spifc { - clocks = <&clkc CLKID_SPI>; -}; - -&uart_A { - clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_AO { - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_AO_B { - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_B { - clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_C { - clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&vpu { - compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu"; - power-domains = <&pwrc PWRC_GXBB_VPU_ID>; -}; - -&vdec { - compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec"; - clocks = <&clkc CLKID_DOS_PARSER>, - <&clkc CLKID_DOS>, - <&clkc CLKID_VDEC_1>, - <&clkc CLKID_VDEC_HEVC>; - clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc"; - resets = <&reset RESET_PARSER>; - reset-names = "esparser"; -}; diff --git a/arch/arm/dts/meson-gxl-mali.dtsi b/arch/arm/dts/meson-gxl-mali.dtsi deleted file mode 100644 index 478e755cc87..00000000000 --- a/arch/arm/dts/meson-gxl-mali.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 BayLibre SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include "meson-gx-mali450.dtsi" - -&mali { - compatible = "amlogic,meson-gxl-mali", "arm,mali-450"; - - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; - - assigned-clocks = <&clkc CLKID_GP0_PLL>; - assigned-clock-rates = <744000000>; -}; diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts deleted file mode 100644 index 213a0705ebd..00000000000 --- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -/dts-v1/; - -#include <dt-bindings/input/input.h> -#include <dt-bindings/sound/meson-aiu.h> - -#include "meson-gxl-s805x.dtsi" - -/ { - compatible = "libretech,aml-s805x-ac", "amlogic,s805x", - "amlogic,meson-gxl"; - model = "Libre Computer AML-S805X-AC"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - spi0 = &spifc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - /* - * The pads are present but no connector is soldered on - * 2J2, so keep this off by default. - */ - status = "disabled"; - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - dc_5v: regulator-dc_5v { - compatible = "regulator-fixed"; - regulator-name = "DC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x20000000>; - }; - - vcck: regulator-vcck { - compatible = "regulator-fixed"; - regulator-name = "VCCK"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_5v>; - - /* - * This is controlled by GPIOAO_9 we reserve this but - * claiming it as done below reset the board anyway - * Need to investigate this - * - * gpio = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - * enable-active-high; - */ - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_5v>; - regulator-always-on; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "LIBRETECH-AC"; - audio-widgets = "Speaker", "9J5-3 LEFT", - "Speaker", "9J5-2 RIGHT"; - audio-routing = "9J5-3 LEFT", "ACODEC LOLN", - "9J5-2 RIGHT", "ACODEC LORN"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - - codec-1 { - sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - - dai-link-3 { - sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; - - codec-0 { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddio_ao18>; - status = "okay"; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; -}; - -&internal_phy { - pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&gpio_ao { - gpio-line-names = "UART TX", - "UART RX", - "7J1 Header Pin31", - "", "", "", "", - "IR In", - "HDMI CEC", - "5V VCCK Regulator", - /* GPIO_TEST_N */ - ""; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "", "", "", "", "", "", "", - "", "", "", "", "", "", "", - "Eth Link LED", "Eth Activity LED", - /* Bank GPIOH */ - "HDMI HPD", "HDMI SDA", "HDMI SCL", - "", "7J1 Header Pin13", - "7J1 Header Pin15", - "7J1 Header Pin7", - "7J1 Header Pin12", - "7J1 Header Pin16", - "7J1 Header Pin18", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", - "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", - "eMMC Clk", "eMMC Reset", "eMMC CMD", - "SPI NOR MOSI", "SPI NOR MISO", "SPI NOR Clk", - "", "SPI NOR Chip Select", - /* Bank CARD */ - "", "", "", "", "", "", "", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", - "7J1 Header Pin27", "7J1 Header Pin28", "", - "7J1 Header Pin29", - "VCCK Regulator", "VDDEE Regulator", - /* Bank GPIOX */ - "7J1 Header Pin22", "7J1 Header Pin26", - "7J1 Header Pin36", "7J1 Header Pin38", - "7J1 Header Pin40", "7J1 Header Pin37", - "7J1 Header Pin33", "7J1 Header Pin35", - "7J1 Header Pin19", "7J1 Header Pin21", - "7J1 Header Pin24", "7J1 Header Pin23", - "7J1 Header Pin8", "7J1 Header Pin10", - "", "", "7J1 Header Pin32", "", "", - /* Bank GPIOCLK */ - "", ""; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&spifc { - status = "okay"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - w25q32: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <3000000>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm/dts/meson-gxl-s805x.dtsi b/arch/arm/dts/meson-gxl-s805x.dtsi deleted file mode 100644 index 29975849822..00000000000 --- a/arch/arm/dts/meson-gxl-s805x.dtsi +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 BayLibre SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include "meson-gxl-s905x.dtsi" - -/ { - compatible = "amlogic,s805x", "amlogic,meson-gxl"; -}; - -/* The S805X Package doesn't seem to handle the 744MHz OPP correctly */ -&gpu_opp_table { - opp-744000000 { - status = "disabled"; - }; -}; - -&mali { - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-rates; -}; diff --git a/arch/arm/dts/meson-gxl-s905d-libretech-pc.dts b/arch/arm/dts/meson-gxl-s905d-libretech-pc.dts deleted file mode 100644 index 100a1cfeea1..00000000000 --- a/arch/arm/dts/meson-gxl-s905d-libretech-pc.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 BayLibre SAS. All rights reserved. - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -/dts-v1/; - -#include "meson-gxl-s905d.dtsi" -#include "meson-gx-libretech-pc.dtsi" - -/ { - compatible = "libretech,aml-s905d-pc", "amlogic,s905d", - "amlogic,meson-gxl"; - model = "Libre Computer AML-S905D-PC"; -}; diff --git a/arch/arm/dts/meson-gxl-s905d.dtsi b/arch/arm/dts/meson-gxl-s905d.dtsi deleted file mode 100644 index 43321919547..00000000000 --- a/arch/arm/dts/meson-gxl-s905d.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -#include "meson-gxl.dtsi" -#include "meson-gxl-mali.dtsi" - -/ { - compatible = "amlogic,s905d", "amlogic,meson-gxl"; -}; diff --git a/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts b/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts deleted file mode 100644 index a18d6d241a5..00000000000 --- a/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts +++ /dev/null @@ -1,247 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Vyacheslav Bocharov <adeep@lexina.in> - * Copyright (c) 2020 JetHome - * Author: Aleksandr Kazantsev <ak@tvip.ru> - * Author: Alexey Shevelkin <ash@tvip.ru> - * Author: Vyacheslav Bocharov <adeep@lexina.in> - */ - -/dts-v1/; - -#include "meson-gxl.dtsi" - -/ { - compatible = "jethome,jethub-j80", "amlogic,s905w", "amlogic,meson-gxl"; - model = "JetHome JetHub J80"; - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - reserved-memory { - linux,cma { - size = <0x0 0x1000000>; - }; - }; - - aliases { - serial0 = &uart_AO; /* Console */ - serial1 = &uart_A; /* Bluetooth */ - serial2 = &uart_AO_B; /* Wireless module 1 */ - serial3 = &uart_C; /* Wireless module 2 */ - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; -}; - -&efuse { - bt_mac: bt-mac@6 { - reg = <0x6 0x6>; - }; - - wifi_mac: wifi-mac@c { - reg = <0xc 0x6>; - }; -}; - -&sn { - reg = <0x32 0x20>; -}; - -ð_mac { - reg = <0x0 0x6>; -}; - -&bid { - reg = <0x12 0x20>; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* Console UART */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -/* S905W only has access to its internal PHY */ -ðmac { - status = "okay"; - phy-mode = "rmii"; - phy-handle = <&internal_phy>; -}; - -&internal_phy { - status = "okay"; - pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; - pinctrl-names = "default"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "realtek,rtl8822cs-bt"; - enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - host-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart_C { - status = "okay"; - pinctrl-0 = <&uart_c_pins>; - pinctrl-names = "default"; -}; - -&uart_AO_B { - status = "okay"; - pinctrl-0 = <&uart_ao_b_pins>, <&uart_ao_b_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; -}; - -&i2c_B { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_b_pins>; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - status = "okay"; - }; -}; diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts deleted file mode 100644 index 02f81839d4e..00000000000 --- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. - */ - -/dts-v1/; - -#include "meson-gxl-s905x-p212.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/sound/meson-aiu.h> - -/ { - compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl"; - model = "Khadas VIM"; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Function"; - linux,code = <KEY_FN>; - press-threshold-microvolt = <10000>; - }; - }; - - aliases { - serial2 = &uart_AO_B; - ethernet0 = ðmac; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; - - led-controller { - compatible = "pwm-leds"; - - led-1 { - label = "vim:red:power"; - pwms = <&pwm_AO_ab 1 7812500 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "KHADAS-VIM"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; -}; - -&i2c_B { - status = "okay"; - pinctrl-0 = <&i2c_b_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - status = "okay"; - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - }; -}; - -&ir { - linux,rc-map-name = "rc-khadas"; -}; - -&gpio_ao { - gpio-line-names = "UART TX", - "UART RX", - "Power Key In", - "J9 Header Pin35", - "J9 Header Pin16", - "J9 Header Pin15", - "J9 Header Pin33", - "IR In", - "HDMI CEC", - "SYS LED", - /* GPIO_TEST_N */ - ""; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "", "", "", "", "", "", "", - "", "", "", "", "", "", "", - "Power OFF", - "VCCK Enable", - /* Bank GPIOH */ - "HDMI HPD", "HDMI SDA", "HDMI SCL", - "HDMI_5V_EN", "SPDIF", - "J9 Header Pin37", - "J9 Header Pin30", - "J9 Header Pin29", - "J9 Header Pin32", - "J9 Header Pin31", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", - "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", - "eMMC Clk", "eMMC Reset", "eMMC CMD", - "", "BOOT_MODE", "", "", "eMMC Data Strobe", - /* Bank CARD */ - "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", - "SDCard D3", "SDCard D2", "SDCard Det", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", - "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", - "VCCK Regulator", "VDDEE Regulator", - /* Bank GPIOX */ - "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2", - "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD", - "WIFI Power Enable", "WIFI WAKE HOST", - "Bluetooth PCM DOUT", "Bluetooth PCM DIN", - "Bluetooth PCM SYNC", "Bluetooth PCM CLK", - "Bluetooth UART TX", "Bluetooth UART RX", - "Bluetooth UART CTS", "Bluetooth UART RTS", - "WIFI 32K", "Bluetooth Enable", - "Bluetooth WAKE HOST", - /* Bank GPIOCLK */ - "", "J9 Header Pin39"; -}; - -&pwm_AO_ab { - status = "okay"; - pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; - pinctrl-names = "default"; - clocks = <&xtal> , <&xtal>; - clock-names = "clkin0", "clkin1" ; -}; - -&pwm_ef { - pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; -}; - -&sd_emmc_a { - max-frequency = <100000000>; -}; - -/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */ -&uart_AO { - status = "okay"; -}; - -/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */ -&uart_AO_B { - status = "okay"; - pinctrl-0 = <&uart_ao_b_pins>; - pinctrl-names = "default"; -}; - -&usb { - dr_mode = "peripheral"; -}; diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts deleted file mode 100644 index 6c4e68e0e62..00000000000 --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts +++ /dev/null @@ -1,313 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 BayLibre, SAS. - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -/dts-v1/; - -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/sound/meson-aiu.h> - -#include "meson-gxl-s905x.dtsi" - -/ { - compatible = "libretech,aml-s905x-cc-v2", "amlogic,s905x", - "amlogic,meson-gxl"; - model = "Libre Computer AML-S905X-CC V2"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - spi0 = &spifc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - panic-indicator; - }; - - led-green { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_DISK_ACTIVITY; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vcck: regulator-vcck { - compatible = "regulator-fixed"; - regulator-name = "VCCK"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vcc_card: regulator-vcc_card { - compatible = "regulator-fixed"; - regulator-name = "VCC_CARD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddio_ao3v3>; - - gpio = <&gpio GPIOCLK_1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc5v: regulator-vcc5v { - compatible = "regulator-fixed"; - regulator-name = "VCC5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&ao_5v>; - - gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>; - }; - - vddio_ao3v3: regulator-vddio_ao3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vddio_card: regulator-vddio-card { - compatible = "regulator-gpio"; - regulator-name = "VDDIO_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - - regulator-settling-time-up-us = <200>; - regulator-settling-time-down-us = <50000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddio_ao3v3>; - regulator-always-on; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC 1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddio_ao3v3>; - regulator-always-on; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "LIBRETECH-CC-V2"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -ðmac { - status = "okay"; -}; - -&internal_phy { - pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - hdmi-supply = <&vcc5v>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* SD card */ -&sd_emmc_b { - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vcc_card>; - vqmmc-supply = <&vddio_card>; - - status = "okay"; -}; - -/* eMMC */ -&sd_emmc_c { - pinctrl-0 = <&emmc_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddio_ao3v3>; - vqmmc-supply = <&vcc_1v8>; - - status = "okay"; -}; - -&spifc { - status = "okay"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - nor_4u1: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <3000000>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; - -&usb2_phy0 { - phy-supply = <&vcc5v>; -}; - -&usb2_phy1 { - phy-supply = <&vcc5v>; -}; diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts deleted file mode 100644 index 82bfabfbd39..00000000000 --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts +++ /dev/null @@ -1,356 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -/dts-v1/; - -#include <dt-bindings/input/input.h> -#include <dt-bindings/sound/meson-aiu.h> - -#include "meson-gxl-s905x.dtsi" - -/ { - compatible = "libretech,aml-s905x-cc", "amlogic,s905x", - "amlogic,meson-gxl"; - model = "Libre Computer AML-S905X-CC"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - dio2133: analog-amplifier { - compatible = "simple-audio-amplifier"; - sound-name-prefix = "AU2"; - VCC-supply = <&hdmi_5v>; - enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-system { - label = "librecomputer:system-status"; - gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - default-state = "on"; - panic-indicator; - }; - - led-blue { - label = "librecomputer:blue"; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - hdmi_5v: regulator-hdmi-5v { - compatible = "regulator-fixed"; - - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_card: regulator-vcc-card { - compatible = "regulator-gpio"; - - regulator-name = "VCC_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - - regulator-settling-time-up-us = <200>; - regulator-settling-time-down-us = <50000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - /* This is provided by LDOs on the eMMC daugther card */ - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "LIBRETECH-CC"; - audio-aux-devs = <&dio2133>; - audio-widgets = "Line", "Lineout"; - audio-routing = "AU2 INL", "ACODEC LOLN", - "AU2 INR", "ACODEC LORN", - "Lineout", "AU2 OUTL", - "Lineout", "AU2 OUTR"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - - codec-1 { - sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - - dai-link-3 { - sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; - - codec-0 { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddio_ao18>; - status = "okay"; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; -}; - -&internal_phy { - pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&gpio_ao { - gpio-line-names = "UART TX", - "UART RX", - "Blue LED", - "SDCard Voltage Switch", - "7J1 Header Pin5", - "7J1 Header Pin3", - "7J1 Header Pin12", - "IR In", - "9J3 Switch HDMI CEC/7J1 Header Pin11", - "7J1 Header Pin13", - /* GPIO_TEST_N */ - "7J1 Header Pin15"; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "", "", "", "", "", "", "", - "", "", "", "", "", "", "", - "Eth Link LED", "Eth Activity LED", - /* Bank GPIOH */ - "HDMI HPD", "HDMI SDA", "HDMI SCL", - "HDMI_5V_EN", "9J1 Header Pin2", - "Analog Audio Mute", - "2J3 Header Pin6", - "2J3 Header Pin5", - "2J3 Header Pin4", - "2J3 Header Pin3", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", - "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", - "eMMC Clk", "eMMC Reset", "eMMC CMD", - "ALT BOOT MODE", "", "", "", "eMMC Data Strobe", - /* Bank CARD */ - "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", - "SDCard D3", "SDCard D2", "SDCard Det", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", - "Green LED", "VCCK Enable", - "7J1 Header Pin27", "7J1 Header Pin28", - "VCCK Regulator", "VDDEE Regulator", - /* Bank GPIOX */ - "7J1 Header Pin22", "7J1 Header Pin26", - "7J1 Header Pin36", "7J1 Header Pin38", - "7J1 Header Pin40", "7J1 Header Pin37", - "7J1 Header Pin33", "7J1 Header Pin35", - "7J1 Header Pin19", "7J1 Header Pin21", - "7J1 Header Pin24", "7J1 Header Pin23", - "7J1 Header Pin8", "7J1 Header Pin10", - "7J1 Header Pin16", "7J1 Header Pin18", - "7J1 Header Pin32", "7J1 Header Pin29", - "7J1 Header Pin31", - /* Bank GPIOCLK */ - "7J1 Header Pin7", ""; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_card>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; - -&usb2_phy0 { - /* - * even though the schematics don't show it: - * HDMI_5V is also used as supply for the USB VBUS. - */ - phy-supply = <&hdmi_5v>; -}; diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dts b/arch/arm/dts/meson-gxl-s905x-p212.dts deleted file mode 100644 index 9b4ea6a4939..00000000000 --- a/arch/arm/dts/meson-gxl-s905x-p212.dts +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -/dts-v1/; - -#include "meson-gxl-s905x-p212.dtsi" -#include <dt-bindings/sound/meson-aiu.h> - -/ { - compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl"; - model = "Amlogic Meson GXL (S905X) P212 Development Board"; - - dio2133: analog-amplifier { - compatible = "simple-audio-amplifier"; - sound-name-prefix = "AU2"; - VCC-supply = <&hdmi_5v>; - enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "S905X-P212"; - audio-aux-devs = <&dio2133>; - audio-widgets = "Line", "Lineout"; - audio-routing = "AU2 INL", "ACODEC LOLN", - "AU2 INR", "ACODEC LORN", - "Lineout", "AU2 OUTL", - "Lineout", "AU2 OUTR"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - - codec-1 { - sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - - dai-link-3 { - sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; - - codec-0 { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddio_ao18>; - status = "okay"; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; -}; diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi deleted file mode 100644 index a150cc0e18f..00000000000 --- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi +++ /dev/null @@ -1,213 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. - * Based on meson-gx-p23x-q20x.dtsi: - * - Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - * - Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/* Common DTSI for devices which are based on the P212 reference board. */ - -#include "meson-gxl-s905x.dtsi" - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - hdmi_5v: regulator-hdmi-5v { - compatible = "regulator-fixed"; - - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; -}; - -ðmac { - status = "okay"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* This is connected to the Bluetooth module: */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; - -&usb2_phy0 { - /* - * HDMI_5V is also used as supply for the USB VBUS. - */ - phy-supply = <&hdmi_5v>; -}; diff --git a/arch/arm/dts/meson-gxl-s905x.dtsi b/arch/arm/dts/meson-gxl-s905x.dtsi deleted file mode 100644 index 40c19f69e9d..00000000000 --- a/arch/arm/dts/meson-gxl-s905x.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -#include "meson-gxl.dtsi" -#include "meson-gxl-mali.dtsi" - -/ { - compatible = "amlogic,s905x", "amlogic,meson-gxl"; -}; - -/* S905X only has access to its internal PHY */ -ðmac { - phy-mode = "rmii"; - phy-handle = <&internal_phy>; -}; diff --git a/arch/arm/dts/meson-gxl.dtsi b/arch/arm/dts/meson-gxl.dtsi deleted file mode 100644 index 17bcfa4702e..00000000000 --- a/arch/arm/dts/meson-gxl.dtsi +++ /dev/null @@ -1,940 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -#include "meson-gx.dtsi" -#include <dt-bindings/clock/gxbb-clkc.h> -#include <dt-bindings/clock/gxbb-aoclkc.h> -#include <dt-bindings/gpio/meson-gxl-gpio.h> -#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> - -/ { - compatible = "amlogic,meson-gxl"; - - soc { - usb: usb@d0078080 { - compatible = "amlogic,meson-gxl-usb-ctrl"; - reg = <0x0 0xd0078080 0x0 0x20>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "usb_ctrl", "ddr"; - resets = <&reset RESET_USB_OTG>; - - dr_mode = "otg"; - - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; - - dwc2: usb@c9100000 { - compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; - reg = <0x0 0xc9100000 0x0 0x40000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLKID_USB1>; - clock-names = "otg"; - phys = <&usb2_phy1>; - dr_mode = "peripheral"; - g-rx-fifo-size = <192>; - g-np-tx-fifo-size = <128>; - g-tx-fifo-size = <128 128 16 16 16>; - }; - - dwc3: usb@c9000000 { - compatible = "snps,dwc3"; - reg = <0x0 0xc9000000 0x0 0x100000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - }; - }; - - acodec: audio-controller@c8832000 { - compatible = "amlogic,t9015"; - reg = <0x0 0xc8832000 0x0 0x14>; - #sound-dai-cells = <0>; - sound-name-prefix = "ACODEC"; - clocks = <&clkc CLKID_ACODEC>; - clock-names = "pclk"; - resets = <&reset RESET_ACODEC>; - status = "disabled"; - }; - - crypto: crypto@c883e000 { - compatible = "amlogic,gxl-crypto"; - reg = <0x0 0xc883e000 0x0 0x36>; - interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_BLKMV>; - clock-names = "blkmv"; - status = "okay"; - }; - }; -}; - -&aiu { - compatible = "amlogic,aiu-gxl", "amlogic,aiu"; - clocks = <&clkc CLKID_AIU_GLUE>, - <&clkc CLKID_I2S_OUT>, - <&clkc CLKID_AOCLK_GATE>, - <&clkc CLKID_CTS_AMCLK>, - <&clkc CLKID_MIXER_IFACE>, - <&clkc CLKID_IEC958>, - <&clkc CLKID_IEC958_GATE>, - <&clkc CLKID_CTS_MCLK_I958>, - <&clkc CLKID_CTS_I958>; - clock-names = "pclk", - "i2s_pclk", - "i2s_aoclk", - "i2s_mclk", - "i2s_mixer", - "spdif_pclk", - "spdif_aoclk", - "spdif_mclk", - "spdif_mclk_sel"; - resets = <&reset RESET_AIU>; -}; - -&apb { - usb2_phy0: phy@78000 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x78000 0x0 0x20>; - clocks = <&clkc CLKID_USB>; - clock-names = "phy"; - resets = <&reset RESET_USB_OTG>; - reset-names = "phy"; - status = "okay"; - }; - - usb2_phy1: phy@78020 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x78020 0x0 0x20>; - clocks = <&clkc CLKID_USB>; - clock-names = "phy"; - resets = <&reset RESET_USB_OTG>; - reset-names = "phy"; - status = "okay"; - }; -}; - -&efuse { - clocks = <&clkc CLKID_EFUSE>; -}; - -ðmac { - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; - - mdio0: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; -}; - -&aobus { - pinctrl_aobus: pinctrl@14 { - compatible = "amlogic,meson-gxl-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x00014 0x0 0x8>, - <0x0 0x0002c 0x0 0x4>, - <0x0 0x00024 0x0 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 0 14>; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { - mux { - groups = "uart_cts_ao_a", - "uart_rts_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - uart_ao_b_pins: uart_ao_b { - mux { - groups = "uart_tx_ao_b", "uart_rx_ao_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_0_1_pins: uart_ao_b_0_1 { - mux { - groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { - mux { - groups = "uart_cts_ao_b", - "uart_rts_ao_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - remote_input_ao_pins: remote_input_ao { - mux { - groups = "remote_input_ao"; - function = "remote_input_ao"; - bias-disable; - }; - }; - - i2c_ao_pins: i2c_ao { - mux { - groups = "i2c_sck_ao", - "i2c_sda_ao"; - function = "i2c_ao"; - bias-disable; - }; - }; - - pwm_ao_a_3_pins: pwm_ao_a_3 { - mux { - groups = "pwm_ao_a_3"; - function = "pwm_ao_a"; - bias-disable; - }; - }; - - pwm_ao_a_8_pins: pwm_ao_a_8 { - mux { - groups = "pwm_ao_a_8"; - function = "pwm_ao_a"; - bias-disable; - }; - }; - - pwm_ao_b_pins: pwm_ao_b { - mux { - groups = "pwm_ao_b"; - function = "pwm_ao_b"; - bias-disable; - }; - }; - - pwm_ao_b_6_pins: pwm_ao_b_6 { - mux { - groups = "pwm_ao_b_6"; - function = "pwm_ao_b"; - bias-disable; - }; - }; - - i2s_out_ch23_ao_pins: i2s_out_ch23_ao { - mux { - groups = "i2s_out_ch23_ao"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_ch45_ao_pins: i2s_out_ch45_ao { - mux { - groups = "i2s_out_ch45_ao"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - spdif_out_ao_6_pins: spdif_out_ao_6 { - mux { - groups = "spdif_out_ao_6"; - function = "spdif_out_ao"; - bias-disable; - }; - }; - - spdif_out_ao_9_pins: spdif_out_ao_9 { - mux { - groups = "spdif_out_ao_9"; - function = "spdif_out_ao"; - bias-disable; - }; - }; - - ao_cec_pins: ao_cec { - mux { - groups = "ao_cec"; - function = "cec_ao"; - bias-disable; - }; - }; - - ee_cec_pins: ee_cec { - mux { - groups = "ee_cec"; - function = "cec_ao"; - bias-disable; - }; - }; - }; -}; - -&cec_AO { - clocks = <&clkc_AO CLKID_AO_CEC_32K>; - clock-names = "core"; -}; - -&clkc_AO { - compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc"; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; -}; - -&gpio_intc { - compatible = "amlogic,meson-gxl-gpio-intc", - "amlogic,meson-gpio-intc"; - status = "okay"; -}; - -&hdmi_tx { - compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; - resets = <&reset RESET_HDMITX_CAPB3>, - <&reset RESET_HDMI_SYSTEM_RESET>, - <&reset RESET_HDMI_TX>; - reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, - <&clkc CLKID_GCLK_VENCI_INT0>; - clock-names = "isfr", "iahb", "venci"; -}; - -&sysctrl { - clkc: clock-controller { - compatible = "amlogic,gxl-clkc"; - #clock-cells = <1>; - clocks = <&xtal>; - clock-names = "xtal"; - }; -}; - -&hwrng { - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; -}; - -&i2c_A { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_AO { - clocks = <&clkc CLKID_AO_I2C>; -}; - -&i2c_B { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_C { - clocks = <&clkc CLKID_I2C>; -}; - -&periphs { - pinctrl_periphs: pinctrl@4b0 { - compatible = "amlogic,meson-gxl-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@4b0 { - reg = <0x0 0x004b0 0x0 0x28>, - <0x0 0x004e8 0x0 0x14>, - <0x0 0x00520 0x0 0x14>, - <0x0 0x00430 0x0 0x40>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_periphs 0 0 100>; - }; - - emmc_pins: emmc { - mux-0 { - groups = "emmc_nand_d07", - "emmc_cmd"; - function = "emmc"; - bias-pull-up; - }; - - mux-1 { - groups = "emmc_clk"; - function = "emmc"; - bias-disable; - }; - }; - - emmc_ds_pins: emmc-ds { - mux { - groups = "emmc_ds"; - function = "emmc"; - bias-pull-down; - }; - }; - - emmc_clk_gate_pins: emmc_clk_gate { - mux { - groups = "BOOT_8"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - nor_pins: nor { - mux { - groups = "nor_d", - "nor_q", - "nor_c", - "nor_cs"; - function = "nor"; - bias-disable; - }; - }; - - spi_pins: spi-pins { - mux { - groups = "spi_miso", - "spi_mosi", - "spi_sclk"; - function = "spi"; - bias-disable; - }; - }; - - spi_idle_high_pins: spi-idle-high-pins { - mux { - groups = "spi_sclk"; - bias-pull-up; - }; - }; - - spi_idle_low_pins: spi-idle-low-pins { - mux { - groups = "spi_sclk"; - bias-pull-down; - }; - }; - - spi_ss0_pins: spi-ss0 { - mux { - groups = "spi_ss0"; - function = "spi"; - bias-disable; - }; - }; - - sdcard_pins: sdcard { - mux-0 { - groups = "sdcard_d0", - "sdcard_d1", - "sdcard_d2", - "sdcard_d3", - "sdcard_cmd"; - function = "sdcard"; - bias-pull-up; - }; - - mux-1 { - groups = "sdcard_clk"; - function = "sdcard"; - bias-disable; - }; - }; - - sdcard_clk_gate_pins: sdcard_clk_gate { - mux { - groups = "CARD_2"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - sdio_pins: sdio { - mux-0 { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_cmd"; - function = "sdio"; - bias-pull-up; - }; - - mux-1 { - groups = "sdio_clk"; - function = "sdio"; - bias-disable; - }; - }; - - sdio_clk_gate_pins: sdio_clk_gate { - mux { - groups = "GPIOX_4"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - sdio_irq_pins: sdio_irq { - mux { - groups = "sdio_irq"; - function = "sdio"; - bias-disable; - }; - }; - - uart_a_pins: uart_a { - mux { - groups = "uart_tx_a", - "uart_rx_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a_cts_rts_pins: uart_a_cts_rts { - mux { - groups = "uart_cts_a", - "uart_rts_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_b_pins: uart_b { - mux { - groups = "uart_tx_b", - "uart_rx_b"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_cts_rts_pins: uart_b_cts_rts { - mux { - groups = "uart_cts_b", - "uart_rts_b"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_c_pins: uart_c { - mux { - groups = "uart_tx_c", - "uart_rx_c"; - function = "uart_c"; - bias-disable; - }; - }; - - uart_c_cts_rts_pins: uart_c_cts_rts { - mux { - groups = "uart_cts_c", - "uart_rts_c"; - function = "uart_c"; - bias-disable; - }; - }; - - i2c_a_pins: i2c_a { - mux { - groups = "i2c_sck_a", - "i2c_sda_a"; - function = "i2c_a"; - bias-disable; - }; - }; - - i2c_b_pins: i2c_b { - mux { - groups = "i2c_sck_b", - "i2c_sda_b"; - function = "i2c_b"; - bias-disable; - }; - }; - - i2c_c_pins: i2c_c { - mux { - groups = "i2c_sck_c", - "i2c_sda_c"; - function = "i2c_c"; - bias-disable; - }; - }; - - i2c_c_dv18_pins: i2c_c_dv18 { - mux { - groups = "i2c_sck_c_dv19", - "i2c_sda_c_dv18"; - function = "i2c_c"; - bias-disable; - }; - }; - - eth_pins: eth_c { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_clk_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_rxd2", - "eth_rxd3", - "eth_rgmii_tx_clk", - "eth_tx_en", - "eth_txd0", - "eth_txd1", - "eth_txd2", - "eth_txd3"; - function = "eth"; - bias-disable; - }; - }; - - eth_link_led_pins: eth_link_led { - mux { - groups = "eth_link_led"; - function = "eth_led"; - bias-disable; - }; - }; - - eth_act_led_pins: eth_act_led { - mux { - groups = "eth_act_led"; - function = "eth_led"; - }; - }; - - pwm_a_pins: pwm_a { - mux { - groups = "pwm_a"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_b_pins: pwm_b { - mux { - groups = "pwm_b"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_c_pins: pwm_c { - mux { - groups = "pwm_c"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_d_pins: pwm_d { - mux { - groups = "pwm_d"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_e_pins: pwm_e { - mux { - groups = "pwm_e"; - function = "pwm_e"; - bias-disable; - }; - }; - - pwm_f_clk_pins: pwm_f_clk { - mux { - groups = "pwm_f_clk"; - function = "pwm_f"; - bias-disable; - }; - }; - - pwm_f_x_pins: pwm_f_x { - mux { - groups = "pwm_f_x"; - function = "pwm_f"; - bias-disable; - }; - }; - - hdmi_hpd_pins: hdmi_hpd { - mux { - groups = "hdmi_hpd"; - function = "hdmi_hpd"; - bias-disable; - }; - }; - - hdmi_i2c_pins: hdmi_i2c { - mux { - groups = "hdmi_sda", "hdmi_scl"; - function = "hdmi_i2c"; - bias-disable; - }; - }; - - i2s_am_clk_pins: i2s_am_clk { - mux { - groups = "i2s_am_clk"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2s_out_ao_clk_pins: i2s_out_ao_clk { - mux { - groups = "i2s_out_ao_clk"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2s_out_lr_clk_pins: i2s_out_lr_clk { - mux { - groups = "i2s_out_lr_clk"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2s_out_ch01_pins: i2s_out_ch01 { - mux { - groups = "i2s_out_ch01"; - function = "i2s_out"; - bias-disable; - }; - }; - i2sout_ch23_z_pins: i2sout_ch23_z { - mux { - groups = "i2sout_ch23_z"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2sout_ch45_z_pins: i2sout_ch45_z { - mux { - groups = "i2sout_ch45_z"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2sout_ch67_z_pins: i2sout_ch67_z { - mux { - groups = "i2sout_ch67_z"; - function = "i2s_out"; - bias-disable; - }; - }; - - spdif_out_h_pins: spdif_out_ao_h { - mux { - groups = "spdif_out_h"; - function = "spdif_out"; - bias-disable; - }; - }; - }; - - eth_phy_mux: mdio@558 { - reg = <0x0 0x558 0x0 0xc>; - compatible = "amlogic,gxl-mdio-mux"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "ref"; - mdio-parent-bus = <&mdio0>; - - external_mdio: mdio@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - internal_mdio: mdio@1 { - reg = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - - internal_phy: ethernet-phy@8 { - compatible = "ethernet-phy-id0181.4400"; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <8>; - max-speed = <100>; - }; - }; - }; -}; - -&pwrc { - resets = <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_VCBUS>, - <&reset RESET_BT656>, - <&reset RESET_DVIN_RESET>, - <&reset RESET_RDMA>, - <&reset RESET_VENCI>, - <&reset RESET_VENCP>, - <&reset RESET_VDAC>, - <&reset RESET_VDI6>, - <&reset RESET_VENCL>, - <&reset RESET_VID_LOCK>; - reset-names = "viu", "venc", "vcbus", "bt656", - "dvin", "rdma", "venci", "vencp", - "vdac", "vdi6", "vencl", "vid_lock"; - clocks = <&clkc CLKID_VPU>, - <&clkc CLKID_VAPB>; - clock-names = "vpu", "vapb"; - /* - * VPU clocking is provided by two identical clock paths - * VPU_0 and VPU_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - * Same for VAPB but with a final gate after the glitch free mux. - */ - assigned-clocks = <&clkc CLKID_VPU_0_SEL>, - <&clkc CLKID_VPU_0>, - <&clkc CLKID_VPU>, /* Glitch free mux */ - <&clkc CLKID_VAPB_0_SEL>, - <&clkc CLKID_VAPB_0>, - <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_VPU_0>, - <&clkc CLKID_FCLK_DIV4>, - <0>, /* Do Nothing */ - <&clkc CLKID_VAPB_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>, /* Do Nothing */ - <0>, /* Do Nothing */ - <250000000>, - <0>; /* Do Nothing */ -}; - -&saradc { - compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; - clocks = <&xtal>, - <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SAR_ADC_CLK>, - <&clkc CLKID_SAR_ADC_SEL>; - clock-names = "clkin", "core", "adc_clk", "adc_sel"; -}; - -&sd_emmc_a { - clocks = <&clkc CLKID_SD_EMMC_A>, - <&clkc CLKID_SD_EMMC_A_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_A>; -}; - -&sd_emmc_b { - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_B>; -}; - -&sd_emmc_c { - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_C>; -}; - -&simplefb_hdmi { - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, - <&clkc CLKID_GCLK_VENCI_INT0>; -}; - -&spicc { - clocks = <&clkc CLKID_SPICC>; - clock-names = "core"; - resets = <&reset RESET_PERIPHS_SPICC>; - num-cs = <1>; -}; - -&spifc { - clocks = <&clkc CLKID_SPI>; -}; - -&uart_A { - clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_AO { - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_AO_B { - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_B { - clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_C { - clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&vpu { - compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu"; - power-domains = <&pwrc PWRC_GXBB_VPU_ID>; -}; - -&vdec { - compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec"; - clocks = <&clkc CLKID_DOS_PARSER>, - <&clkc CLKID_DOS>, - <&clkc CLKID_VDEC_1>, - <&clkc CLKID_VDEC_HEVC>; - clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc"; - resets = <&reset RESET_PARSER>; - reset-names = "esparser"; -}; diff --git a/arch/arm/dts/meson-gxm-gt1-ultimate.dts b/arch/arm/dts/meson-gxm-gt1-ultimate.dts deleted file mode 100644 index 2c267884cc1..00000000000 --- a/arch/arm/dts/meson-gxm-gt1-ultimate.dts +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" -#include "meson-gx-p23x-q20x.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> - -/ { - compatible = "azw,gt1-ultimate", "amlogic,s912", "amlogic,meson-gxm"; - model = "Beelink GT1 Ultimate"; - - leds { - compatible = "gpio-leds"; - - led-white { - color = <LED_COLOR_ID_WHITE>; - function = LED_FUNCTION_POWER; - gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - panic-indicator; - }; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "update"; - linux,code = <KEY_VENDOR>; - press-threshold-microvolt = <10000>; - }; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>; - pinctrl-names = "default"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; - phy-mode = "rgmii"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <25 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&ir { - linux,rc-map-name = "rc-beelink-gs1"; -}; - -&sd_emmc_a { - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts deleted file mode 100644 index 74897a15489..00000000000 --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts +++ /dev/null @@ -1,424 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. - * Copyright (c) 2017 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/sound/meson-aiu.h> - -/ { - compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm"; - model = "Khadas VIM2"; - - aliases { - serial0 = &uart_AO; - serial2 = &uart_AO_B; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Function"; - linux,code = <KEY_FN>; - press-threshold-microvolt = <10000>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - gpio_fan: gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH - &gpio GPIODV_15 GPIO_ACTIVE_HIGH>; - /* Dummy RPM values since fan is optional */ - gpio-fan,speed-map = - <0 0>, - <1 1>, - <2 2>, - <3 3>; - #cooling-cells = <2>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - led-controller { - compatible = "pwm-leds"; - - led-1 { - label = "vim:red:power"; - pwms = <&pwm_AO_ab 1 7812500 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - hdmi_5v: regulator-hdmi-5v { - compatible = "regulator-fixed"; - - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "KHADAS-VIM2"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cpu_cooling_maps { - map0 { - cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>; - }; - - map1 { - cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>, - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>; - pinctrl-names = "default"; - - /* Select external PHY by default */ - phy-handle = <&external_phy>; - - amlogic,tx-delay-ns = <2>; - - /* External PHY is in RGMII */ - phy-mode = "rgmii"; - - status = "okay"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <25 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; -}; - -&i2c_B { - status = "okay"; - pinctrl-0 = <&i2c_b_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - status = "okay"; - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-khadas"; -}; - -&pwm_AO_ab { - status = "okay"; - pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* - * EMMC_DS pin is shared between SPI NOR CS and eMMC Data Strobe - * Remove emmc_ds_pins from sd_emmc_c pinctrl-0 then spifc can be enabled - */ -&spifc { - status = "disabled"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - w25q32: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q16", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - }; -}; - -/* This one is connected to the Bluetooth module */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */ -&uart_AO_B { - status = "okay"; - pinctrl-0 = <&uart_ao_b_pins>; - pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -&usb { - status = "okay"; - dr_mode = "peripheral"; -}; diff --git a/arch/arm/dts/meson-gxm-s912-libretech-pc.dts b/arch/arm/dts/meson-gxm-s912-libretech-pc.dts deleted file mode 100644 index 444c249863c..00000000000 --- a/arch/arm/dts/meson-gxm-s912-libretech-pc.dts +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 BayLibre SAS. All rights reserved. - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" -#include "meson-gx-libretech-pc.dtsi" - -/ { - compatible = "libretech,aml-s912-pc", "amlogic,s912", - "amlogic,meson-gxm"; - model = "Libre Computer AML-S912-PC"; - - typec2_vbus: regulator-typec2_vbus { - compatible = "regulator-fixed"; - regulator-name = "TYPEC2_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v>; - - gpio = <&gpio GPIODV_1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&pinctrl_periphs { - /* - * Make sure the irq pin of the TYPE C controller is not driven - * by the SoC. - */ - fusb302_irq_pins: fusb302_irq { - mux { - groups = "GPIODV_0"; - function = "gpio_periphs"; - bias-pull-up; - output-disable; - }; - }; -}; - -&i2c_C { - fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - - pinctrl-0 = <&fusb302_irq_pins>; - pinctrl-names = "default"; - interrupt-parent = <&gpio_intc>; - interrupts = <59 IRQ_TYPE_LEVEL_LOW>; - - vbus-supply = <&typec2_vbus>; - - status = "okay"; - }; -}; - -&usb2_phy2 { - phy-supply = <&typec2_vbus>; -}; diff --git a/arch/arm/dts/meson-gxm-wetek-core2.dts b/arch/arm/dts/meson-gxm-wetek-core2.dts deleted file mode 100644 index f8c40340b9c..00000000000 --- a/arch/arm/dts/meson-gxm-wetek-core2.dts +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" -#include "meson-gx-p23x-q20x.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> - -/ { - compatible = "wetek,core2", "amlogic,s912", "amlogic,meson-gxm"; - model = "WeTek Core 2"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 3 GiB */ - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-update { - label = "update"; - linux,code = <KEY_VENDOR>; - press-threshold-microvolt = <10000>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - button-power { - label = "power"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -/* Disabled as Realtek RTL8152 USB provides Ethernet */ -ðmac { - status = "disabled"; -}; - -&internal_phy { - status = "disabled"; -}; - -&ir { - linux,rc-map-name = "rc-wetek-play2"; -}; - -/* This is connected to the Bluetooth module: */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; diff --git a/arch/arm/dts/meson-gxm.dtsi b/arch/arm/dts/meson-gxm.dtsi deleted file mode 100644 index 411cc312fc6..00000000000 --- a/arch/arm/dts/meson-gxm.dtsi +++ /dev/null @@ -1,216 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -#include "meson-gxl.dtsi" - -/ { - compatible = "amlogic,meson-gxm"; - - cpus { - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - }; - - cpu0: cpu@0 { - capacity-dmips-mhz = <1024>; - }; - - cpu1: cpu@1 { - capacity-dmips-mhz = <1024>; - }; - - cpu2: cpu@2 { - capacity-dmips-mhz = <1024>; - }; - - cpu3: cpu@3 { - capacity-dmips-mhz = <1024>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 1>; - #cooling-cells = <2>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x101>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 1>; - #cooling-cells = <2>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x102>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 1>; - #cooling-cells = <2>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x103>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 1>; - #cooling-cells = <2>; - }; - }; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-125000000 { - opp-hz = /bits/ 64 <125000000>; - opp-microvolt = <950000>; - }; - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <950000>; - }; - opp-285714285 { - opp-hz = /bits/ 64 <285714285>; - opp-microvolt = <950000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <950000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <950000>; - }; - opp-666666666 { - opp-hz = /bits/ 64 <666666666>; - opp-microvolt = <950000>; - }; - }; -}; - -&apb { - usb2_phy2: phy@78040 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x78040 0x0 0x20>; - clocks = <&clkc CLKID_USB>; - clock-names = "phy"; - resets = <&reset RESET_USB_OTG>; - reset-names = "phy"; - status = "okay"; - }; - - mali: gpu@c0000 { - compatible = "amlogic,meson-gxm-mali", "arm,mali-t820"; - reg = <0x0 0xc0000 0x0 0x40000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&clkc CLKID_MALI>; - resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>; - operating-points-v2 = <&gpu_opp_table>; - }; -}; - -&clkc_AO { - compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc"; -}; - -&cpu_cooling_maps { - map0 { - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; -}; - -&saradc { - compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc"; -}; - -&scpi_dvfs { - clock-indices = <0 1>; - clock-output-names = "vbig", "vlittle"; -}; - -&vpu { - compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu"; -}; - -&hdmi_tx { - compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; -}; - -&usb { - compatible = "amlogic,meson-gxm-usb-ctrl"; - - phy-names = "usb2-phy0", "usb2-phy1", "usb2-phy2"; - phys = <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>; -}; - -&vdec { - compatible = "amlogic,gxm-vdec", "amlogic,gx-vdec"; -}; diff --git a/arch/arm/dts/meson-khadas-vim3.dtsi b/arch/arm/dts/meson-khadas-vim3.dtsi deleted file mode 100644 index 3cf4ecb6d52..00000000000 --- a/arch/arm/dts/meson-khadas-vim3.dtsi +++ /dev/null @@ -1,534 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com> - */ - -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - rtc0 = &rtc; - rtc1 = &vrtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 2>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Function"; - linux,code = <KEY_FN>; - press-threshold-microvolt = <10000>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-white { - color = <LED_COLOR_ID_WHITE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-red { - color = <LED_COLOR_ID_RED>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_expander 5 GPIO_ACTIVE_HIGH>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - }; - - emmc_1v8: regulator-emmc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vsys_3v3: regulator-vsys_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VSYS_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - usb_pwr: regulator-usb_pwr { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - - sound { - compatible = "amlogic,axg-sound-card"; - model = "KHADAS-VIM3"; - audio-aux-devs = <&tdmin_a>, <&tdmout_a>; - audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", - "TDMOUT_A IN 1", "FRDDR_B OUT 0", - "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT", - "TDMIN_A IN 0", "TDM_A Capture", - "TDMIN_A IN 3", "TDM_A Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-6 { - sound-dai = <&tdmif_a>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; - }; - }; - - /* hdmi glue */ - dai-link-7 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cpu_thermal { - trips { - cpu_active: cpu-active { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; - }; - - cooling-maps { - map { - trip = <&cpu_active>; - cooling-device = <&khadas_mcu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c_AO { - status = "okay"; - pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>; - pinctrl-names = "default"; - - khadas_mcu: system-controller@18 { - compatible = "khadas,mcu"; - reg = <0x18>; - #cooling-cells = <2>; - }; - - gpio_expander: gpio-controller@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - vcc-supply = <&vcc_3v3>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-khadas"; -}; - -&pcie { - reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddao_1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vsys_3v3>; - vqmmc-supply = <&vddao_1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vsys_3v3>; - vqmmc-supply = <&vsys_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&emmc_1v8>; -}; - -/* - * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR CS - * and eMMC Data 4 to 7 pins. - * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0, - * and change bus-width to 4 then spifc can be enabled. - */ -&spifc { - status = "disabled"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - w25q128: spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q128fw", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - }; -}; - -&tdmif_a { - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmout_a { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb2_phy0 { - phy-supply = <&dc_in>; -}; - -&usb2_phy1 { - phy-supply = <&usb_pwr>; -}; - -&usb3_pcie_phy { - phy-supply = <&usb_pwr>; -}; - -&usb { - status = "okay"; - dr_mode = "peripheral"; -}; diff --git a/arch/arm/dts/meson-sm1-bananapi-m2-pro.dts b/arch/arm/dts/meson-sm1-bananapi-m2-pro.dts deleted file mode 100644 index 586034316ec..00000000000 --- a/arch/arm/dts/meson-sm1-bananapi-m2-pro.dts +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 BayLibre SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/dts-v1/; - -#include "meson-sm1-bananapi.dtsi" -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "bananapi,bpi-m2-pro", "amlogic,sm1"; - model = "Banana Pi BPI-M2-PRO"; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "BPI-M2-PRO"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&clkc_audio { - status = "okay"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; diff --git a/arch/arm/dts/meson-sm1-bananapi-m5.dts b/arch/arm/dts/meson-sm1-bananapi-m5.dts deleted file mode 100644 index f045bf85163..00000000000 --- a/arch/arm/dts/meson-sm1-bananapi-m5.dts +++ /dev/null @@ -1,221 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 BayLibre SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/dts-v1/; - -#include "meson-sm1-bananapi.dtsi" -#include <dt-bindings/sound/meson-g12a-toacodec.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "bananapi,bpi-m5", "amlogic,sm1"; - model = "Banana Pi BPI-M5"; - - /* TOFIX: handle CVBS_DET on SARADC channel 0 */ - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "BPI-M5"; - audio-widgets = "Line", "Lineout"; - audio-aux-devs = <&tdmout_b>, <&tdmout_c>, - <&tdmin_a>, <&tdmin_b>, <&tdmin_c>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TDMOUT_C IN 0", "FRDDR_A OUT 2", - "TDMOUT_C IN 1", "FRDDR_B OUT 2", - "TDMOUT_C IN 2", "FRDDR_C OUT 2", - "TDM_C Playback", "TDMOUT_C OUT", - "TDMIN_A IN 4", "TDM_B Loopback", - "TDMIN_B IN 4", "TDM_B Loopback", - "TDMIN_C IN 4", "TDM_B Loopback", - "TDMIN_A IN 5", "TDM_C Loopback", - "TDMIN_B IN 5", "TDM_C Loopback", - "TDMIN_C IN 5", "TDM_C Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT", - "TODDR_A IN 2", "TDMIN_C OUT", - "TODDR_B IN 2", "TDMIN_C OUT", - "TODDR_C IN 2", "TDMIN_C OUT", - "Lineout", "ACODEC LOLP", - "Lineout", "ACODEC LORP"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-6 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - - codec-1 { - sound-dai = <&toacodec TOACODEC_IN_B>; - }; - }; - - /* i2s jack output interface */ - dai-link-7 { - sound-dai = <&tdmif_c>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>; - }; - - codec-1 { - sound-dai = <&toacodec TOACODEC_IN_C>; - }; - }; - - /* hdmi glue */ - dai-link-8 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - - /* acodec glue */ - dai-link-9 { - sound-dai = <&toacodec TOACODEC_OUT>; - - codec { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddao_1v8>; - status = "okay"; -}; - - -&clkc_audio { - status = "okay"; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmif_c { - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmin_c { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tdmout_c { - status = "okay"; -}; - -&toacodec { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; diff --git a/arch/arm/dts/meson-sm1-bananapi.dtsi b/arch/arm/dts/meson-sm1-bananapi.dtsi deleted file mode 100644 index 17045ff81c6..00000000000 --- a/arch/arm/dts/meson-sm1-bananapi.dtsi +++ /dev/null @@ -1,435 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 BayLibre SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include "meson-sm1.dtsi" -#include <dt-bindings/leds/common.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> - -/ { - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 2>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-sw3 { - label = "SW3"; - linux,code = <BTN_3>; - press-threshold-microvolt = <1700000>; - }; - }; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key { - label = "SW1"; - linux,code = <BTN_1>; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <3 IRQ_TYPE_EDGE_BOTH>; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-green { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - - led-blue { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_1v8: regulator-emmc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vddio_c: regulator-vddio_c { - compatible = "regulator-gpio"; - regulator-name = "VDDIO_C"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - enable-gpios = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>; - enable-active-high; - regulator-always-on; - - gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>; - gpios-states = <1>; - - states = <1800000 0>, - <3300000 1>; - }; - - tflash_vdd: regulator-tflash_vdd { - compatible = "regulator-fixed"; - regulator-name = "TFLASH_VDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - regulator-always-on; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - vddcpu: regulator-vddcpu { - /* - * SY8120B1ABC DC/DC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - pwm-supply = <&dc_in>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - /* USB Hub Power Enable */ - vl_pwr_en: regulator-vl_pwr_en { - compatible = "regulator-fixed"; - regulator-name = "VL_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - - gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&arb { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii-txid"; - phy-handle = <&external_phy>; -}; - -&gpio { - gpio-line-names = - /* GPIOZ */ - "ETH_MDIO", /* GPIOZ_0 */ - "ETH_MDC", /* GPIOZ_1 */ - "ETH_RXCLK", /* GPIOZ_2 */ - "ETH_RX_DV", /* GPIOZ_3 */ - "ETH_RXD0", /* GPIOZ_4 */ - "ETH_RXD1", /* GPIOZ_5 */ - "ETH_RXD2", /* GPIOZ_6 */ - "ETH_RXD3", /* GPIOZ_7 */ - "ETH_TXCLK", /* GPIOZ_8 */ - "ETH_TXEN", /* GPIOZ_9 */ - "ETH_TXD0", /* GPIOZ_10 */ - "ETH_TXD1", /* GPIOZ_11 */ - "ETH_TXD2", /* GPIOZ_12 */ - "ETH_TXD3", /* GPIOZ_13 */ - "ETH_INTR", /* GPIOZ_14 */ - "ETH_NRST", /* GPIOZ_15 */ - /* GPIOH */ - "HDMI_SDA", /* GPIOH_0 */ - "HDMI_SCL", /* GPIOH_1 */ - "HDMI_HPD", /* GPIOH_2 */ - "HDMI_CEC", /* GPIOH_3 */ - "VL-RST_N", /* GPIOH_4 */ - "CON1-P36", /* GPIOH_5 */ - "VL-PWREN", /* GPIOH_6 */ - "WiFi_3V3_1V8", /* GPIOH_7 */ - "TFLASH_VDD_EN", /* GPIOH_8 */ - /* BOOT */ - "eMMC_D0", /* BOOT_0 */ - "eMMC_D1", /* BOOT_1 */ - "eMMC_D2", /* BOOT_2 */ - "eMMC_D3", /* BOOT_3 */ - "eMMC_D4", /* BOOT_4 */ - "eMMC_D5", /* BOOT_5 */ - "eMMC_D6", /* BOOT_6 */ - "eMMC_D7", /* BOOT_7 */ - "eMMC_CLK", /* BOOT_8 */ - "", - "eMMC_CMD", /* BOOT_10 */ - "", - "eMMC_RST#", /* BOOT_12 */ - "eMMC_DS", /* BOOT_13 */ - "", "", - /* GPIOC */ - "SD_D0_B", /* GPIOC_0 */ - "SD_D1_B", /* GPIOC_1 */ - "SD_D2_B", /* GPIOC_2 */ - "SD_D3_B", /* GPIOC_3 */ - "SD_CLK_B", /* GPIOC_4 */ - "SD_CMD_B", /* GPIOC_5 */ - "CARD_EN_DET", /* GPIOC_6 */ - "", - /* GPIOA */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", - "CON1-P27", /* GPIOA_14 */ - "CON1-P28", /* GPIOA_15 */ - /* GPIOX */ - "CON1-P16", /* GPIOX_0 */ - "CON1-P18", /* GPIOX_1 */ - "CON1-P22", /* GPIOX_2 */ - "CON1-P11", /* GPIOX_3 */ - "CON1-P13", /* GPIOX_4 */ - "CON1-P07", /* GPIOX_5 */ - "CON1-P33", /* GPIOX_6 */ - "CON1-P15", /* GPIOX_7 */ - "CON1-P19", /* GPIOX_8 */ - "CON1-P21", /* GPIOX_9 */ - "CON1-P24", /* GPIOX_10 */ - "CON1-P23", /* GPIOX_11 */ - "CON1-P08", /* GPIOX_12 */ - "CON1-P10", /* GPIOX_13 */ - "CON1-P29", /* GPIOX_14 */ - "CON1-P31", /* GPIOX_15 */ - "CON1-P26", /* GPIOX_16 */ - "CON1-P03", /* GPIOX_17 */ - "CON1-P05", /* GPIOX_18 */ - "CON1-P32"; /* GPIOX_19 */ - - /* - * WARNING: The USB Hub needs a reset signal to be turned high in - * order to be detected by the USB Controller. This signal should - * be handled by a USB specific power sequence to reset the Hub - * when the USB bus is powered down. - */ - usb-hub-hog { - gpio-hog; - gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&gpio_ao { - gpio-line-names = - /* GPIOAO */ - "DEBUG TX", /* GPIOAO_0 */ - "DEBUG RX", /* GPIOAO_1 */ - "SYS_LED2", /* GPIOAO_2 */ - "UPDATE_KEY", /* GPIOAO_3 */ - "CON1-P40", /* GPIOAO_4 */ - "IR_IN", /* GPIOAO_5 */ - "TF_3V3N_1V8_EN", /* GPIOAO_6 */ - "CON1-P35", /* GPIOAO_7 */ - "CON1-P12", /* GPIOAO_8 */ - "CON1-P37", /* GPIOAO_9 */ - "CON1-P38", /* GPIOAO_10 */ - "SYS_LED", /* GPIOAO_11 */ - /* GPIOE */ - "VDDEE_PWM", /* GPIOE_0 */ - "VDDCPU_PWM", /* GPIOE_1 */ - "TF_PWR_EN"; /* GPIOE_2 */ -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&dc_in>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddao_1v8>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - /* TOFIX: SD card is barely usable in SDR modes */ - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&tflash_vdd>; - vqmmc-supply = <&vddio_c>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&emmc_1v8>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; -}; - -&usb2_phy0 { - phy-supply = <&dc_in>; -}; - -&usb2_phy1 { - /* Enable the hub which is connected to this port */ - phy-supply = <&vl_pwr_en>; -}; diff --git a/arch/arm/dts/meson-sm1-khadas-vim3l.dts b/arch/arm/dts/meson-sm1-khadas-vim3l.dts deleted file mode 100644 index f2c09814359..00000000000 --- a/arch/arm/dts/meson-sm1-khadas-vim3l.dts +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/dts-v1/; - -#include "meson-sm1.dtsi" -#include "meson-khadas-vim3.dtsi" -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "khadas,vim3l", "amlogic,sm1"; - model = "Khadas VIM3L"; - - vddcpu: regulator-vddcpu { - /* - * Silergy SY8030DEC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - vin-supply = <&vsys_3v3>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - sound { - model = "G12B-KHADAS-VIM3L"; - audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", - "TDMOUT_A IN 1", "FRDDR_B OUT 0", - "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT", - "TDMIN_A IN 0", "TDM_A Capture", - "TDMIN_A IN 13", "TDM_A Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT"; - }; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -/* - * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential - * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between - * an USB3.0 Type A connector and a M.2 Key M slot. - * The PHY driving these differential lines is shared between - * the USB3.0 controller and the PCIe Controller, thus only - * a single controller can use it. - * If the MCU is configured to mux the PCIe/USB3.0 differential lines - * to the M.2 Key M slot, uncomment the following block to disable - * USB3.0 from the USB Complex and enable the PCIe controller. - * The End User is not expected to uncomment the following except for - * testing purposes, but instead rely on the firmware/bootloader to - * update these nodes accordingly if PCIe mode is selected by the MCU. - */ -/* -&pcie { - status = "okay"; -}; - -&usb { - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; -}; - */ - -&sd_emmc_a { - sd-uhs-sdr50; -}; diff --git a/arch/arm/dts/meson-sm1-odroid-c4.dts b/arch/arm/dts/meson-sm1-odroid-c4.dts deleted file mode 100644 index 8c30ce63686..00000000000 --- a/arch/arm/dts/meson-sm1-odroid-c4.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Dongjin Kim <tobetter@gmail.com> - */ - -/dts-v1/; - -#include "meson-sm1-odroid.dtsi" - -/ { - compatible = "hardkernel,odroid-c4", "amlogic,sm1"; - model = "Hardkernel ODROID-C4"; - - leds { - compatible = "gpio-leds"; - - led-blue { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - panic-indicator; - }; - }; - - sound { - model = "ODROID-C4"; - }; -}; - -&gpio { - /* - * WARNING: The USB Hub on the Odroid-C4 needs a reset signal - * to be turned high in order to be detected by the USB Controller - * This signal should be handled by a USB specific power sequence - * in order to reset the Hub when USB bus is powered down. - */ - hog-0 { - gpio-hog; - gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&ir { - linux,rc-map-name = "rc-odroid"; -}; diff --git a/arch/arm/dts/meson-sm1-odroid-hc4.dts b/arch/arm/dts/meson-sm1-odroid-hc4.dts deleted file mode 100644 index f3f953225bf..00000000000 --- a/arch/arm/dts/meson-sm1-odroid-hc4.dts +++ /dev/null @@ -1,140 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Dongjin Kim <tobetter@gmail.com> - */ - -/dts-v1/; - -#include "meson-sm1-odroid.dtsi" - -/ { - compatible = "hardkernel,odroid-hc4", "amlogic,sm1"; - model = "Hardkernel ODROID-HC4"; - - aliases { - rtc0 = &rtc; - rtc1 = &vrtc; - }; - - fan0: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - cooling-min-state = <0>; - cooling-max-state = <3>; - cooling-levels = <0 120 170 220>; - pwms = <&pwm_cd 1 40000 0>; - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - panic-indicator; - }; - - led-red { - color = <LED_COLOR_ID_RED>; - function = LED_FUNCTION_POWER; - gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - /* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */ - p12v_0: regulator-p12v_0 { - compatible = "regulator-fixed"; - regulator-name = "P12V_0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <&main_12v>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - regulator-always-on; - }; - - /* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */ - p12v_1: regulator-p12v_1 { - compatible = "regulator-fixed"; - regulator-name = "P12V_1"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <&main_12v>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - regulator-always-on; - }; - - sound { - model = "ODROID-HC4"; - }; -}; - -&cpu_thermal { - cooling-maps { - map { - trip = <&cpu_passive>; - cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&ir { - linux,rc-map-name = "rc-odroid"; -}; - -&i2c2 { - status = "okay"; - pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - status = "okay"; - compatible = "nxp,pcf8563"; - reg = <0x51>; - wakeup-source; - }; -}; - -&pcie { - status = "okay"; - reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; -}; - -&pwm_cd { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm_d_x6_pins>; -}; - -&sd_emmc_c { - status = "disabled"; -}; - -&spifc { - status = "okay"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - }; -}; - -&usb { - phys = <&usb2_phy1>; - phy-names = "usb2-phy1"; -}; - -&usb2_phy0 { - status = "disabled"; -}; diff --git a/arch/arm/dts/meson-sm1-odroid.dtsi b/arch/arm/dts/meson-sm1-odroid.dtsi deleted file mode 100644 index fd0ad85c165..00000000000 --- a/arch/arm/dts/meson-sm1-odroid.dtsi +++ /dev/null @@ -1,449 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Dongjin Kim <tobetter@gmail.com> - */ - -#include "meson-sm1.dtsi" -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - tflash_vdd: regulator-tflash_vdd { - compatible = "regulator-fixed"; - - regulator-name = "TFLASH_VDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>; - enable-active-high; - regulator-always-on; - }; - - tf_io: gpio-regulator-tf_io { - compatible = "regulator-gpio"; - - regulator-name = "TF_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_5v>; - - enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - - gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&main_12v>; - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddcpu: regulator-vddcpu { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - usb_pwr_en: regulator-usb_pwr_en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the microUSB port power enable */ - gpio = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&gpio { - gpio-line-names = - /* GPIOZ */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* GPIOH */ - "", "", "", "", "", - "PIN_36", /* GPIOH_5 */ - "PIN_26", /* GPIOH_6 */ - "PIN_32", /* GPIOH_7 */ - "", - /* BOOT */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* GPIOC */ - "", "", "", "", "", "", "", "", - /* GPIOA */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", - "PIN_27", /* GPIOA_14 */ - "PIN_28", /* GPIOA_15 */ - /* GPIOX */ - "PIN_16", /* GPIOX_0 */ - "PIN_18", /* GPIOX_1 */ - "PIN_22", /* GPIOX_2 */ - "PIN_11", /* GPIOX_3 */ - "PIN_13", /* GPIOX_4 */ - "PIN_7", /* GPIOX_5 */ - "PIN_33", /* GPIOX_6 */ - "PIN_15", /* GPIOX_7 */ - "PIN_19", /* GPIOX_8 */ - "PIN_21", /* GPIOX_9 */ - "PIN_24", /* GPIOX_10 */ - "PIN_23", /* GPIOX_11 */ - "PIN_8", /* GPIOX_12 */ - "PIN_10", /* GPIOX_13 */ - "PIN_29", /* GPIOX_14 */ - "PIN_31", /* GPIOX_15 */ - "PIN_12", /* GPIOX_16 */ - "PIN_3", /* GPIOX_17 */ - "PIN_5", /* GPIOX_18 */ - "PIN_35"; /* GPIOX_19 */ -}; - -&gpio_ao { - gpio-line-names = - /* GPIOAO */ - "", "", "", "", - "PIN_47", /* GPIOAO_4 */ - "", "", - "PIN_45", /* GPIOAO_7 */ - "PIN_46", /* GPIOAO_8 */ - "PIN_44", /* GPIOAO_9 */ - "PIN_42", /* GPIOAO_10 */ - "", - /* GPIOE */ - "", "", ""; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&saradc { - status = "okay"; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <200000000>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&tflash_vdd>; - vqmmc-supply = <&tf_io>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_pwr_en>; -}; - -&usb2_phy0 { - phy-supply = <&vcc_5v>; -}; - diff --git a/arch/arm/dts/meson-sm1-sei610.dts b/arch/arm/dts/meson-sm1-sei610.dts deleted file mode 100644 index 2194a778973..00000000000 --- a/arch/arm/dts/meson-sm1-sei610.dts +++ /dev/null @@ -1,616 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre SAS. All rights reserved. - */ - -/dts-v1/; - -#include "meson-sm1.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "seirobotics,sei610", "amlogic,sm1"; - model = "SEI Robotics SEI610"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - mono_dac: audio-codec-0 { - compatible = "maxim,max98357a"; - #sound-dai-cells = <0>; - sound-name-prefix = "U16"; - sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>; - }; - - dmics: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "dmic-codec"; - num-channels = <2>; - wakeup-delay-ms = <50>; - status = "okay"; - sound-name-prefix = "MIC"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key1 { - label = "A"; - linux,code = <BTN_0>; - gpios = <&gpio GPIOH_6 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <34 IRQ_TYPE_EDGE_BOTH>; - }; - - key2 { - label = "B"; - linux,code = <BTN_1>; - gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <35 IRQ_TYPE_EDGE_BOTH>; - }; - - key3 { - label = "C"; - linux,code = <BTN_2>; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <2 IRQ_TYPE_EDGE_BOTH>; - }; - - mic_mute { - label = "MicMute"; - linux,code = <SW_MUTE_DEVICE>; - linux,input-type = <EV_SW>; - gpios = <&gpio_ao GPIOE_2 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <99 IRQ_TYPE_EDGE_BOTH>; - }; - - power_key { - label = "PowerKey"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <3 IRQ_TYPE_EDGE_BOTH>; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - led-controller-1 { - compatible = "gpio-leds"; - - led-1 { - label = "sei610:blue:bt"; - gpios = <&gpio GPIOC_7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - default-state = "off"; - }; - }; - - led-controller-2 { - compatible = "pwm-leds"; - - led-2 { - label = "sei610:red:power"; - pwms = <&pwm_AO_ab 0 30518 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - active-low; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - emmc_1v8: regulator-emmc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - /* Used by Tuner, RGB Led & IR Emitter LED array */ - vddao_3v3_t: regulator-vddao_3v3_t { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3_T"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-low; - regulator-always-on; - }; - - vddcpu: regulator-vddcpu { - /* - * SY8120B1ABC DC/DC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - vin-supply = <&dc_in>; - - pwms = <&pwm_AO_cd 1 1500 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddio_ao1v8: regulator-vddio_ao1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - reserved-memory { - /* TEE Reserved Memory */ - bl32_reserved: bl32@5000000 { - reg = <0x0 0x05300000 0x0 0x2000000>; - no-map; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "SEI610"; - audio-aux-devs = <&tdmout_a>, <&tdmout_b>, - <&tdmin_a>, <&tdmin_b>; - audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", - "TDMOUT_A IN 1", "FRDDR_B OUT 0", - "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT", - "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TODDR_A IN 4", "PDM Capture", - "TODDR_B IN 4", "PDM Capture", - "TODDR_C IN 4", "PDM Capture", - "TDMIN_A IN 0", "TDM_A Capture", - "TDMIN_A IN 3", "TDM_A Loopback", - "TDMIN_B IN 0", "TDM_A Capture", - "TDMIN_B IN 3", "TDM_A Loopback", - "TDMIN_A IN 1", "TDM_B Capture", - "TDMIN_A IN 4", "TDM_B Loopback", - "TDMIN_B IN 1", "TDM_B Capture", - "TDMIN_B IN 4", "TDM_B Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* internal speaker interface */ - dai-link-6 { - sound-dai = <&tdmif_a>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&mono_dac>; - }; - - codec-1 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; - }; - }; - - /* 8ch hdmi interface */ - dai-link-7 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* internal digital mics */ - dai-link-8 { - sound-dai = <&pdm>; - - codec { - sound-dai = <&dmics>; - }; - }; - - /* hdmi glue */ - dai-link-9 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; -}; - -ðmac { - status = "okay"; - phy-handle = <&internal_ephy>; - phy-mode = "rmii"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pdm { - pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_dclk_z_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pwm_AO_ab { - status = "okay"; - pinctrl-0 = <&pwm_ao_a_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr50; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_ao1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&emmc_1v8>; -}; - -&tdmif_a { - pinctrl-0 = <&tdm_a_dout0_pins>, <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>; - pinctrl-names = "default"; - status = "okay"; - - assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD0>, - <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD0>; - assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - assigned-clock-rates = <0>, <0>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmout_a { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - interrupt-parent = <&gpio_intc>; - interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wakeup"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - vbat-supply = <&vddao_3v3>; - vddio-supply = <&vddio_ao1v8>; - }; -}; - -/* Exposed via the on-board USB to Serial FT232RL IC */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "otg"; -}; diff --git a/arch/arm/dts/meson-sm1.dtsi b/arch/arm/dts/meson-sm1.dtsi deleted file mode 100644 index 56ca0ba2241..00000000000 --- a/arch/arm/dts/meson-sm1.dtsi +++ /dev/null @@ -1,550 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include "meson-g12-common.dtsi" -#include <dt-bindings/clock/axg-audio-clkc.h> -#include <dt-bindings/power/meson-sm1-power.h> -#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> -#include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h> - -/ { - compatible = "amlogic,sm1"; - - tdmif_a: audio-controller-0 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_A"; - clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, - <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_b: audio-controller-1 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_B"; - clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, - <&clkc_audio AUD_CLKID_MST_B_SCLK>, - <&clkc_audio AUD_CLKID_MST_B_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_c: audio-controller-2 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_C"; - clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, - <&clkc_audio AUD_CLKID_MST_C_SCLK>, - <&clkc_audio AUD_CLKID_MST_C_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - }; - }; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <770000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <780000>; - }; - - opp-1404000000 { - opp-hz = /bits/ 64 <1404000000>; - opp-microvolt = <790000>; - }; - - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <800000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <810000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <850000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <900000>; - }; - - opp-1908000000 { - opp-hz = /bits/ 64 <1908000000>; - opp-microvolt = <950000>; - }; - }; -}; - -&apb { - audio: bus@60000 { - compatible = "simple-bus"; - reg = <0x0 0x60000 0x0 0x1000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x60000 0x0 0x1000>; - - clkc_audio: clock-controller@0 { - status = "disabled"; - compatible = "amlogic,sm1-audio-clkc"; - reg = <0x0 0x0 0x0 0xb4>; - #clock-cells = <1>; - #reset-cells = <1>; - - clocks = <&clkc CLKID_AUDIO>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL3>, - <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_FCLK_DIV3>, - <&clkc CLKID_FCLK_DIV4>, - <&clkc CLKID_FCLK_DIV5>; - clock-names = "pclk", - "mst_in0", - "mst_in1", - "mst_in2", - "mst_in3", - "mst_in4", - "mst_in5", - "mst_in6", - "mst_in7"; - - resets = <&reset RESET_AUDIO>; - }; - - toddr_a: audio-controller@100 { - compatible = "amlogic,sm1-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x100 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_A"; - interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_A>; - resets = <&arb AXG_ARB_TODDR_A>, - <&clkc_audio AUD_RESET_TODDR_A>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <8192>; - status = "disabled"; - }; - - toddr_b: audio-controller@140 { - compatible = "amlogic,sm1-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x140 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_B"; - interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_B>; - resets = <&arb AXG_ARB_TODDR_B>, - <&clkc_audio AUD_RESET_TODDR_B>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - toddr_c: audio-controller@180 { - compatible = "amlogic,sm1-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x180 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_C"; - interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_C>; - resets = <&arb AXG_ARB_TODDR_C>, - <&clkc_audio AUD_RESET_TODDR_C>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_a: audio-controller@1c0 { - compatible = "amlogic,sm1-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x1c0 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_A"; - interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; - resets = <&arb AXG_ARB_FRDDR_A>, - <&clkc_audio AUD_RESET_FRDDR_A>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - frddr_b: audio-controller@200 { - compatible = "amlogic,sm1-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x200 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_B"; - interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; - resets = <&arb AXG_ARB_FRDDR_B>, - <&clkc_audio AUD_RESET_FRDDR_B>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_c: audio-controller@240 { - compatible = "amlogic,sm1-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x240 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_C"; - interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; - resets = <&arb AXG_ARB_FRDDR_C>, - <&clkc_audio AUD_RESET_FRDDR_C>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - arb: reset-controller@280 { - status = "disabled"; - compatible = "amlogic,meson-sm1-audio-arb"; - reg = <0x0 0x280 0x0 0x4>; - #reset-cells = <1>; - clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; - }; - - tdmin_a: audio-controller@300 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x300 0x0 0x40>; - sound-name-prefix = "TDMIN_A"; - resets = <&clkc_audio AUD_RESET_TDMIN_A>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_b: audio-controller@340 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x340 0x0 0x40>; - sound-name-prefix = "TDMIN_B"; - resets = <&clkc_audio AUD_RESET_TDMIN_B>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_c: audio-controller@380 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x380 0x0 0x40>; - sound-name-prefix = "TDMIN_C"; - resets = <&clkc_audio AUD_RESET_TDMIN_C>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_lb: audio-controller@3c0 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x3c0 0x0 0x40>; - sound-name-prefix = "TDMIN_LB"; - resets = <&clkc_audio AUD_RESET_TDMIN_LB>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - spdifin: audio-controller@400 { - compatible = "amlogic,g12a-spdifin", - "amlogic,axg-spdifin"; - reg = <0x0 0x400 0x0 0x30>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFIN"; - interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, - <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; - clock-names = "pclk", "refclk"; - resets = <&clkc_audio AUD_RESET_SPDIFIN>; - status = "disabled"; - }; - - spdifout_a: audio-controller@480 { - compatible = "amlogic,g12a-spdifout", - "amlogic,axg-spdifout"; - reg = <0x0 0x480 0x0 0x50>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFOUT_A"; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, - <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; - clock-names = "pclk", "mclk"; - resets = <&clkc_audio AUD_RESET_SPDIFOUT>; - status = "disabled"; - }; - - tdmout_a: audio-controller@500 { - compatible = "amlogic,sm1-tdmout"; - reg = <0x0 0x500 0x0 0x40>; - sound-name-prefix = "TDMOUT_A"; - resets = <&clkc_audio AUD_RESET_TDMOUT_A>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_b: audio-controller@540 { - compatible = "amlogic,sm1-tdmout"; - reg = <0x0 0x540 0x0 0x40>; - sound-name-prefix = "TDMOUT_B"; - resets = <&clkc_audio AUD_RESET_TDMOUT_B>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_c: audio-controller@580 { - compatible = "amlogic,sm1-tdmout"; - reg = <0x0 0x580 0x0 0x40>; - sound-name-prefix = "TDMOUT_C"; - resets = <&clkc_audio AUD_RESET_TDMOUT_C>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - toacodec: audio-controller@740 { - compatible = "amlogic,sm1-toacodec", - "amlogic,g12a-toacodec"; - reg = <0x0 0x740 0x0 0x4>; - #sound-dai-cells = <1>; - sound-name-prefix = "TOACODEC"; - resets = <&clkc_audio AUD_RESET_TOACODEC>; - status = "disabled"; - }; - - tohdmitx: audio-controller@744 { - compatible = "amlogic,sm1-tohdmitx", - "amlogic,g12a-tohdmitx"; - reg = <0x0 0x744 0x0 0x4>; - #sound-dai-cells = <1>; - sound-name-prefix = "TOHDMITX"; - resets = <&clkc_audio AUD_RESET_TOHDMITX>; - status = "disabled"; - }; - - toddr_d: audio-controller@840 { - compatible = "amlogic,sm1-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x840 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_D"; - interrupts = <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_D>; - resets = <&arb AXG_ARB_TODDR_D>, - <&clkc_audio AUD_RESET_TODDR_D>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_d: audio-controller@880 { - compatible = "amlogic,sm1-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x880 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_D"; - interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_D>; - resets = <&arb AXG_ARB_FRDDR_D>, - <&clkc_audio AUD_RESET_FRDDR_D>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - }; - - pdm: audio-controller@61000 { - compatible = "amlogic,sm1-pdm", - "amlogic,axg-pdm"; - reg = <0x0 0x61000 0x0 0x34>; - #sound-dai-cells = <0>; - sound-name-prefix = "PDM"; - clocks = <&clkc_audio AUD_CLKID_PDM>, - <&clkc_audio AUD_CLKID_PDM_DCLK>, - <&clkc_audio AUD_CLKID_PDM_SYSCLK>; - clock-names = "pclk", "dclk", "sysclk"; - resets = <&clkc_audio AUD_RESET_PDM>; - status = "disabled"; - }; -}; - -&cecb_AO { - compatible = "amlogic,meson-sm1-ao-cec"; -}; - -&clk_msr { - compatible = "amlogic,meson-sm1-clk-measure"; -}; - - -&clkc { - compatible = "amlogic,sm1-clkc"; -}; - -&cpu_thermal { - cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -ðmac { - power-domains = <&pwrc PWRC_SM1_ETH_ID>; -}; - -&gpio_intc { - compatible = "amlogic,meson-sm1-gpio-intc", - "amlogic,meson-gpio-intc"; -}; - -&pcie { - power-domains = <&pwrc PWRC_SM1_PCIE_ID>; -}; - -&pmu { - compatible = "amlogic,sm1-ddr-pmu"; -}; - -&pwrc { - compatible = "amlogic,meson-sm1-pwrc"; -}; - -&simplefb_cvbs { - power-domains = <&pwrc PWRC_SM1_VPU_ID>; -}; - -&simplefb_hdmi { - power-domains = <&pwrc PWRC_SM1_VPU_ID>; -}; - -&vdec { - compatible = "amlogic,sm1-vdec"; -}; - -&vpu { - power-domains = <&pwrc PWRC_SM1_VPU_ID>; -}; - -&usb { - power-domains = <&pwrc PWRC_SM1_USB_ID>; -}; diff --git a/arch/arm/dts/msm8916-pm8916.dtsi b/arch/arm/dts/msm8916-pm8916.dtsi new file mode 100644 index 00000000000..b1a7eafbee3 --- /dev/null +++ b/arch/arm/dts/msm8916-pm8916.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * msm8916-pm8916.dtsi describes common properties (e.g. regulator connections) + * that apply to most devices that make use of the MSM8916 SoC and PM8916 PMIC. + * Many regulators have a fixed purpose in the original reference design and + * were rarely re-used for different purposes. Devices that deviate from the + * typical reference design should not make use of this include and instead add + * the necessary properties in the board-specific device tree. + */ + +#include "msm8916.dtsi" +#include "pm8916.dtsi" + +&camss { + vdda-supply = <&pm8916_l2>; +}; + +&mdss_dsi0 { + vdda-supply = <&pm8916_l2>; + vddio-supply = <&pm8916_l6>; +}; + +&mdss_dsi0_phy { + vddio-supply = <&pm8916_l6>; +}; + +&mpss { + pll-supply = <&pm8916_l7>; +}; + +&pm8916_codec { + vdd-cdc-io-supply = <&pm8916_l5>; + vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; + vdd-micbias-supply = <&pm8916_l13>; +}; + +&sdhc_1 { + vmmc-supply = <&pm8916_l8>; + vqmmc-supply = <&pm8916_l5>; +}; + +&sdhc_2 { + vmmc-supply = <&pm8916_l11>; + vqmmc-supply = <&pm8916_l12>; +}; + +&usb_hs_phy { + v1p8-supply = <&pm8916_l7>; + v3p3-supply = <&pm8916_l13>; +}; + +&wcnss { + vddpx-supply = <&pm8916_l7>; +}; + +&wcnss_iris { + vddxo-supply = <&pm8916_l7>; + vddrfa-supply = <&pm8916_s3>; + vddpa-supply = <&pm8916_l9>; + vdddig-supply = <&pm8916_l5>; +}; + +&rpm_requests { + pm8916_rpm_regulators: regulators { + compatible = "qcom,rpm-pm8916-regulators"; + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + /* pm8916_s1 is managed by rpmpd (MSM8916_VDDCX) */ + + pm8916_s3: s3 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; /* Needed for L2 */ + }; + + pm8916_s4: s4 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; + regulator-always-on; /* Needed for L5/L7 */ + }; + + /* + * Some of the regulators are unused or managed by another + * processor (e.g. the modem). We should still define nodes for + * them to ensure the vote from the application processor can be + * dropped in case the regulators are already on during boot. + * + * The labels for these nodes are omitted on purpose because + * boards should configure a proper voltage before using them. + */ + l1 {}; + + pm8916_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; /* Needed for LPDDR RAM */ + }; + + /* pm8916_l3 is managed by rpmpd (MSM8916_VDDMX) */ + + l4 {}; + + pm8916_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; /* Needed for most digital I/O */ + }; + + pm8916_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; /* Needed for CPU PLL */ + }; + + pm8916_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8916_l9: l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 {}; + + pm8916_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + pm8916_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8916_l13: l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 {}; + l15 {}; + l16 {}; + l17 {}; + l18 {}; + }; +}; diff --git a/arch/arm/dts/msm8916.dtsi b/arch/arm/dts/msm8916.dtsi new file mode 100644 index 00000000000..4f799b536a9 --- /dev/null +++ b/arch/arm/dts/msm8916.dtsi @@ -0,0 +1,2702 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. + */ + +#include <dt-bindings/arm/coresight-cti-dt.h> +#include <dt-bindings/clock/qcom,gcc-msm8916.h> +#include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/interconnect/qcom,msm8916.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/reset/qcom,gcc-msm8916.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0x80000000 0 0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz-apps@86000000 { + reg = <0x0 0x86000000 0x0 0x300000>; + no-map; + }; + + smem@86300000 { + compatible = "qcom,smem"; + reg = <0x0 0x86300000 0x0 0x100000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + }; + + hypervisor@86400000 { + reg = <0x0 0x86400000 0x0 0x100000>; + no-map; + }; + + tz@86500000 { + reg = <0x0 0x86500000 0x0 0x180000>; + no-map; + }; + + reserved@86680000 { + reg = <0x0 0x86680000 0x0 0x80000>; + no-map; + }; + + rmtfs@86700000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x86700000 0x0 0xe0000>; + no-map; + + qcom,client-id = <1>; + }; + + rfsa@867e0000 { + reg = <0x0 0x867e0000 0x0 0x20000>; + no-map; + }; + + mpss_mem: mpss@86800000 { + /* + * The memory region for the mpss firmware is generally + * relocatable and could be allocated dynamically. + * However, many firmware versions tend to fail when + * loaded to some special addresses, so it is hard to + * define reliable alloc-ranges. + * + * alignment = <0x0 0x400000>; + * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; + */ + reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */ + no-map; + status = "disabled"; + }; + + wcnss_mem: wcnss { + size = <0x0 0x600000>; + alignment = <0x0 0x100000>; + alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; + no-map; + status = "disabled"; + }; + + venus_mem: venus { + size = <0x0 0x500000>; + alignment = <0x0 0x100000>; + alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; + no-map; + status = "disabled"; + }; + + mba_mem: mba { + size = <0x0 0x100000>; + alignment = <0x0 0x100000>; + alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; + no-map; + status = "disabled"; + }; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + clocks = <&apcs>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + qcom,acc = <&cpu0_acc>; + qcom,saw = <&cpu0_saw>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + clocks = <&apcs>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,acc = <&cpu1_acc>; + qcom,saw = <&cpu1_saw>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + clocks = <&apcs>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + qcom,acc = <&cpu2_acc>; + qcom,saw = <&cpu2_saw>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + clocks = <&apcs>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,acc = <&cpu3_acc>; + qcom,saw = <&cpu3_saw>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "standalone-power-collapse"; + arm,psci-suspend-param = <0x40000002>; + entry-latency-us = <130>; + exit-latency-us = <150>; + min-residency-us = <2000>; + local-timer-stop; + }; + }; + + domain-idle-states { + + CLUSTER_RET: cluster-retention { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000012>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWRDN: cluster-gdhs { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000032>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + }; + + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + }; + opp-998400000 { + opp-hz = /bits/ 64 <998400000>; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-msm8916", "qcom,scm"; + clocks = <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", "bus", "iface"; + #reset-cells = <1>; + + qcom,dload-mode = <&tcsr 0x6100>; + }; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; + }; + }; + + rpm: remoteproc { + compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8916"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8916-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <1>; + }; + rpmpd_opp_svs_krait: opp2 { + opp-level = <2>; + }; + rpmpd_opp_svs_soc: opp3 { + opp-level = <3>; + }; + rpmpd_opp_nom: opp4 { + opp-level = <4>; + }; + rpmpd_opp_turbo: opp5 { + opp-level = <5>; + }; + rpmpd_opp_super_turbo: opp6 { + opp-level = <6>; + }; + }; + }; + }; + }; + }; + + smp2p-hexagon { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + hexagon_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + hexagon_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-wcnss { + compatible = "qcom,smp2p"; + qcom,smem = <451>, <431>; + + interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 18>; + + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-1 = <&apcs 8 13>; + qcom,ipc-3 = <&apcs 8 19>; + + apps_smsm: apps@0 { + reg = <0>; + + #qcom,smem-state-cells = <1>; + }; + + hexagon_smsm: hexagon@1 { + reg = <1>; + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@6 { + reg = <6>; + interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + rng@22000 { + compatible = "qcom,prng"; + reg = <0x00022000 0x200>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x004ab000 0x4>; + }; + + qfprom: qfprom@5c000 { + compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; + reg = <0x0005c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 7>; + }; + + tsens_s0_p1: s0-p1@d0 { + reg = <0xd0 0x2>; + bits = <7 5>; + }; + + tsens_s0_p2: s0-p2@d1 { + reg = <0xd1 0x2>; + bits = <4 5>; + }; + + tsens_s1_p1: s1-p1@d2 { + reg = <0xd2 0x1>; + bits = <1 5>; + }; + tsens_s1_p2: s1-p2@d2 { + reg = <0xd2 0x2>; + bits = <6 5>; + }; + tsens_s2_p1: s2-p1@d3 { + reg = <0xd3 0x1>; + bits = <3 5>; + }; + + tsens_s2_p2: s2-p2@d4 { + reg = <0xd4 0x1>; + bits = <0 5>; + }; + + // no tsens with hw_id 3 + + tsens_s4_p1: s4-p1@d4 { + reg = <0xd4 0x2>; + bits = <5 5>; + }; + + tsens_s4_p2: s4-p2@d5 { + reg = <0xd5 0x1>; + bits = <2 5>; + }; + + tsens_s5_p1: s5-p1@d5 { + reg = <0xd5 0x2>; + bits = <7 5>; + }; + + tsens_s5_p2: s5-p2@d6 { + reg = <0xd6 0x2>; + bits = <4 5>; + }; + + tsens_base2: base2@d7 { + reg = <0xd7 0x1>; + bits = <1 7>; + }; + + tsens_mode: mode@ef { + reg = <0xef 0x1>; + bits = <5 3>; + }; + }; + + rpm_msg_ram: sram@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x00060000 0x8000>; + }; + + sram@290000 { + compatible = "qcom,msm8916-rpm-stats"; + reg = <0x00290000 0x10000>; + }; + + bimc: interconnect@400000 { + compatible = "qcom,msm8916-bimc"; + reg = <0x00400000 0x62000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + + // no hw_id 3 + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2"; + #qcom,sensors = <5>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + #thermal-sensor-cells = <1>; + }; + + pcnoc: interconnect@500000 { + compatible = "qcom,msm8916-pcnoc"; + reg = <0x00500000 0x11000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + }; + + snoc: interconnect@580000 { + compatible = "qcom,msm8916-snoc"; + reg = <0x00580000 0x14000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + + stm: stm@802000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x00802000 0x1000>, + <0x09280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + status = "disabled"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + + /* System CTIs */ + /* CTI 0 - TMC connections */ + cti0: cti@810000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x00810000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + /* CTI 1 - TPIU connections */ + cti1: cti@811000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x00811000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + /* CTIs 2-11 - no information - not instantiated */ + + tpiu: tpiu@820000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x00820000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + status = "disabled"; + + in-ports { + port { + tpiu_in: endpoint { + remote-endpoint = <&replicator_out1>; + }; + }; + }; + }; + + funnel0: funnel@821000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x00821000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + status = "disabled"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * Not described input ports: + * 0 - connected to Resource and Power Manger CPU ETM + * 1 - not-connected + * 2 - connected to Modem CPU ETM + * 3 - not-connected + * 5 - not-connected + * 6 - connected trought funnel to Wireless CPU ETM + * 7 - connected to STM component + */ + + port@4 { + reg = <4>; + funnel0_in4: endpoint { + remote-endpoint = <&funnel1_out>; + }; + }; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + }; + + replicator: replicator@824000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x00824000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + status = "disabled"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = <&tpiu_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etf: etf@825000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x00825000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + status = "disabled"; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = <&funnel0_out>; + }; + }; + }; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = <&replicator_in>; + }; + }; + }; + }; + + etr: etr@826000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x00826000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + status = "disabled"; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = <&replicator_out0>; + }; + }; + }; + }; + + funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x00841000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + status = "disabled"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel1_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + port@1 { + reg = <1>; + funnel1_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + port@2 { + reg = <2>; + funnel1_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + port@3 { + reg = <3>; + funnel1_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = <&funnel0_in4>; + }; + }; + }; + }; + + debug0: debug@850000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x00850000 0x1000>; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&CPU0>; + status = "disabled"; + }; + + debug1: debug@852000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x00852000 0x1000>; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&CPU1>; + status = "disabled"; + }; + + debug2: debug@854000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x00854000 0x1000>; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&CPU2>; + status = "disabled"; + }; + + debug3: debug@856000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x00856000 0x1000>; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&CPU3>; + status = "disabled"; + }; + + /* Core CTIs; CTIs 12-15 */ + /* CTI - CPU-0 */ + cti12: cti@858000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x00858000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU0>; + arm,cs-dev-assoc = <&etm0>; + + status = "disabled"; + }; + + /* CTI - CPU-1 */ + cti13: cti@859000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x00859000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + arm,cs-dev-assoc = <&etm1>; + + status = "disabled"; + }; + + /* CTI - CPU-2 */ + cti14: cti@85a000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x0085a000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU2>; + arm,cs-dev-assoc = <&etm2>; + + status = "disabled"; + }; + + /* CTI - CPU-3 */ + cti15: cti@85b000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x0085b000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU3>; + arm,cs-dev-assoc = <&etm3>; + + status = "disabled"; + }; + + etm0: etm@85c000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0085c000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU0>; + + status = "disabled"; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&funnel1_in0>; + }; + }; + }; + }; + + etm1: etm@85d000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0085d000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU1>; + + status = "disabled"; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&funnel1_in1>; + }; + }; + }; + }; + + etm2: etm@85e000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0085e000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU2>; + + status = "disabled"; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&funnel1_in2>; + }; + }; + }; + }; + + etm3: etm@85f000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0085f000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU3>; + + status = "disabled"; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&funnel1_in3>; + }; + }; + }; + }; + + tlmm: pinctrl@1000000 { + compatible = "qcom,msm8916-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 122>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp_i2c1_default: blsp-i2c1-default-state { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c1_sleep: blsp-i2c1-sleep-state { + pins = "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c2_default: blsp-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c2_sleep: blsp-i2c2-sleep-state { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c3_default: blsp-i2c3-default-state { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c3_sleep: blsp-i2c3-sleep-state { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c4_default: blsp-i2c4-default-state { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c4_sleep: blsp-i2c4-sleep-state { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c5_default: blsp-i2c5-default-state { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c5_sleep: blsp-i2c5-sleep-state { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c6_default: blsp-i2c6-default-state { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c6_sleep: blsp-i2c6-sleep-state { + pins = "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_spi1_default: blsp-spi1-default-state { + spi-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi1_sleep: blsp-spi1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi2_default: blsp-spi2-default-state { + spi-pins { + pins = "gpio4", "gpio5", "gpio7"; + function = "blsp_spi2"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio6"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi2_sleep: blsp-spi2-sleep-state { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi3_default: blsp-spi3-default-state { + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "blsp_spi3"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio10"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi3_sleep: blsp-spi3-sleep-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi4_default: blsp-spi4-default-state { + spi-pins { + pins = "gpio12", "gpio13", "gpio15"; + function = "blsp_spi4"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio14"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi4_sleep: blsp-spi4-sleep-state { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi5_default: blsp-spi5-default-state { + spi-pins { + pins = "gpio16", "gpio17", "gpio19"; + function = "blsp_spi5"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi5_sleep: blsp-spi5-sleep-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi6_default: blsp-spi6-default-state { + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "blsp_spi6"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio22"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi6_sleep: blsp-spi6-sleep-state { + pins = "gpio20", "gpio21", "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_uart1_default: blsp-uart1-default-state { + /* TX, RX, CTS_N, RTS_N */ + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-disable; + }; + + blsp_uart1_sleep: blsp-uart1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_uart2_default: blsp-uart2-default-state { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + drive-strength = <16>; + bias-disable; + }; + + blsp_uart2_sleep: blsp-uart2-sleep-state { + pins = "gpio4", "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + camera_front_default: camera-front-default-state { + pwdn-pins { + pins = "gpio33"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + rst-pins { + pins = "gpio28"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + mclk1-pins { + pins = "gpio27"; + function = "cam_mclk1"; + drive-strength = <16>; + bias-disable; + }; + }; + + camera_rear_default: camera-rear-default-state { + pwdn-pins { + pins = "gpio34"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + rst-pins { + pins = "gpio35"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + mclk0-pins { + pins = "gpio26"; + function = "cam_mclk0"; + drive-strength = <16>; + bias-disable; + }; + }; + + cci0_default: cci0-default-state { + pins = "gpio29", "gpio30"; + function = "cci_i2c"; + drive-strength = <16>; + bias-disable; + }; + + cdc_dmic_default: cdc-dmic-default-state { + clk-pins { + pins = "gpio0"; + function = "dmic0_clk"; + drive-strength = <8>; + }; + data-pins { + pins = "gpio1"; + function = "dmic0_data"; + drive-strength = <8>; + }; + }; + + cdc_dmic_sleep: cdc-dmic-sleep-state { + clk-pins { + pins = "gpio0"; + function = "dmic0_clk"; + drive-strength = <2>; + bias-disable; + }; + data-pins { + pins = "gpio1"; + function = "dmic0_data"; + drive-strength = <2>; + bias-disable; + }; + }; + + cdc_pdm_default: cdc-pdm-default-state { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "cdc_pdm0"; + drive-strength = <8>; + bias-disable; + }; + + cdc_pdm_sleep: cdc-pdm-sleep-state { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "cdc_pdm0"; + drive-strength = <2>; + bias-pull-down; + }; + + pri_mi2s_default: mi2s-pri-default-state { + pins = "gpio113", "gpio114", "gpio115", "gpio116"; + function = "pri_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + pri_mi2s_sleep: mi2s-pri-sleep-state { + pins = "gpio113", "gpio114", "gpio115", "gpio116"; + function = "pri_mi2s"; + drive-strength = <2>; + bias-disable; + }; + + pri_mi2s_mclk_default: mi2s-pri-mclk-default-state { + pins = "gpio116"; + function = "pri_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state { + pins = "gpio116"; + function = "pri_mi2s"; + drive-strength = <2>; + bias-disable; + }; + + pri_mi2s_ws_default: mi2s-pri-ws-default-state { + pins = "gpio110"; + function = "pri_mi2s_ws"; + drive-strength = <8>; + bias-disable; + }; + + pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state { + pins = "gpio110"; + function = "pri_mi2s_ws"; + drive-strength = <2>; + bias-disable; + }; + + sec_mi2s_default: mi2s-sec-default-state { + pins = "gpio112", "gpio117", "gpio118", "gpio119"; + function = "sec_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + sec_mi2s_sleep: mi2s-sec-sleep-state { + pins = "gpio112", "gpio117", "gpio118", "gpio119"; + function = "sec_mi2s"; + drive-strength = <2>; + bias-disable; + }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + wcss_wlan_default: wcss-wlan-default-state { + pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; + function = "wcss_wlan"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-msm8916"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x01800000 0x80000>; + clocks = <&xo_board>, + <&sleep_clk>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "sleep_clk", + "dsi0pll", + "dsi0pllbyte", + "ext_mclk", + "ext_pri_i2s", + "ext_sec_i2s"; + }; + + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-msm8916", "syscon"; + reg = <0x01937000 0x30000>; + }; + + mdss: display-subsystem@1a00000 { + status = "disabled"; + compatible = "qcom,mdss"; + reg = <0x01a00000 0x1000>, + <0x01ac8000 0x3000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "vsync"; + + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mdss_mdp: display-controller@1a01000 { + compatible = "qcom,msm8916-mdp5", "qcom,mdp5"; + reg = <0x01a01000 0x89000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + iommus = <&apps_iommu 4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_mdp_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@1a98000 { + compatible = "qcom,msm8916-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x01a98000 0x25c>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + phys = <&mdss_dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdss_mdp_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@1a98300 { + compatible = "qcom,dsi-phy-28nm-lp"; + reg = <0x01a98300 0xd4>, + <0x01a98500 0x280>, + <0x01a98780 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&xo_board>; + clock-names = "iface", "ref"; + }; + }; + + camss: camss@1b0ac00 { + compatible = "qcom,msm8916-camss"; + reg = <0x01b0ac00 0x200>, + <0x01b00030 0x4>, + <0x01b0b000 0x200>, + <0x01b00038 0x4>, + <0x01b08000 0x100>, + <0x01b08400 0x100>, + <0x01b0a000 0x500>, + <0x01b00020 0x10>, + <0x01b10000 0x1000>; + reg-names = "csiphy0", + "csiphy0_clk_mux", + "csiphy1", + "csiphy1_clk_mux", + "csid0", + "csid1", + "ispif", + "csi_clk_mux", + "vfe0"; + interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csiphy0", + "csiphy1", + "csid0", + "csid1", + "ispif", + "vfe0"; + power-domains = <&gcc VFE_GDSC>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI0_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0_CLK>, + <&gcc GCC_CAMSS_CSI0PHY_CLK>, + <&gcc GCC_CAMSS_CSI0PIX_CLK>, + <&gcc GCC_CAMSS_CSI0RDI_CLK>, + <&gcc GCC_CAMSS_CSI1_AHB_CLK>, + <&gcc GCC_CAMSS_CSI1_CLK>, + <&gcc GCC_CAMSS_CSI1PHY_CLK>, + <&gcc GCC_CAMSS_CSI1PIX_CLK>, + <&gcc GCC_CAMSS_CSI1RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&gcc GCC_CAMSS_VFE_AHB_CLK>, + <&gcc GCC_CAMSS_VFE_AXI_CLK>; + clock-names = "top_ahb", + "ispif_ahb", + "csiphy0_timer", + "csiphy1_timer", + "csi0_ahb", + "csi0", + "csi0_phy", + "csi0_pix", + "csi0_rdi", + "csi1_ahb", + "csi1", + "csi1_phy", + "csi1_pix", + "csi1_rdi", + "ahb", + "vfe0", + "csi_vfe0", + "vfe_ahb", + "vfe_axi"; + iommus = <&apps_iommu 3>; + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + cci: cci@1b0c000 { + compatible = "qcom,msm8916-cci", "qcom,msm8226-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x01b0c000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb", "cci_ahb", + "cci", "camss_ahb"; + assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>; + assigned-clock-rates = <80000000>, <19200000>; + pinctrl-names = "default"; + pinctrl-0 = <&cci0_default>; + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gpu: gpu@1c00000 { + compatible = "qcom,adreno-306.0", "qcom,adreno"; + reg = <0x01c00000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + clock-names = + "core", + "iface", + "mem", + "mem_iface", + "alt_mem_iface", + "gfx3d"; + clocks = + <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_OXILI_GMEM_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GFX3D_CLK_SRC>; + power-domains = <&gcc OXILI_GDSC>; + operating-points-v2 = <&gpu_opp_table>; + iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + }; + }; + }; + + venus: video-codec@1d00000 { + compatible = "qcom,msm8916-venus"; + reg = <0x01d00000 0xff000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&gcc VENUS_GDSC>; + clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, + <&gcc GCC_VENUS0_AHB_CLK>, + <&gcc GCC_VENUS0_AXI_CLK>; + clock-names = "core", "iface", "bus"; + iommus = <&apps_iommu 5>; + memory-region = <&venus_mem>; + status = "disabled"; + + video-decoder { + compatible = "venus-decoder"; + }; + + video-encoder { + compatible = "venus-encoder"; + }; + }; + + apps_iommu: iommu@1ef0000 { + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x01e20000 0x20000>; + reg = <0x01ef0000 0x3000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <17>; + + /* VFE */ + iommu-ctx@3000 { + compatible = "qcom,msm-iommu-v1-sec"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* MDP_0 */ + iommu-ctx@4000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x4000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* VENUS_NS */ + iommu-ctx@5000 { + compatible = "qcom,msm-iommu-v1-sec"; + reg = <0x5000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpu_iommu: iommu@1f08000 { + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x01f08000 0x10000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <18>; + + /* GFX3D_USER */ + iommu-ctx@1000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* GFX3D_PRIV */ + iommu-ctx@2000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + spmi_bus: spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0200f000 0x001000>, + <0x02400000 0x400000>, + <0x02c00000 0x400000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + bam_dmux_dma: dma-controller@4044000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x04044000 0x19000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <0>; + + num-channels = <6>; + qcom,num-ees = <1>; + qcom,powered-remotely; + + status = "disabled"; + }; + + mpss: remoteproc@4080000 { + compatible = "qcom,msm8916-mss-pil"; + reg = <0x04080000 0x100>, + <0x04020000 0x040>; + + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + power-domains = <&rpmpd MSM8916_VDDCX>, + <&rpmpd MSM8916_VDDMX>; + power-domain-names = "cx", "mx"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&xo_board>; + clock-names = "iface", "bus", "mem", "xo"; + + qcom,smem-states = <&hexagon_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&scm 0>; + reset-names = "mss_restart"; + + qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; + + status = "disabled"; + + mba { + memory-region = <&mba_mem>; + }; + + mpss { + memory-region = <&mpss_mem>; + }; + + bam_dmux: bam-dmux { + compatible = "qcom,bam-dmux"; + + interrupt-parent = <&hexagon_smsm>; + interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pc", "pc-ack"; + + qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; + qcom,smem-state-names = "pc", "pc-ack"; + + dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; + dma-names = "tx", "rx"; + + status = "disabled"; + }; + + smd-edge { + interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; + + qcom,smd-edge = <0>; + qcom,ipc = <&apcs 8 12>; + qcom,remote-pid = <1>; + + label = "hexagon"; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,smd-channels = "fastrpcsmd-apps-dsp"; + label = "adsp"; + qcom,non-secure-domain; + + #address-cells = <1>; + #size-cells = <0>; + + cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + }; + }; + }; + }; + + sound: sound@7702000 { + status = "disabled"; + compatible = "qcom,apq8016-sbc-sndcard"; + reg = <0x07702000 0x4>, <0x07702004 0x4>; + reg-names = "mic-iomux", "spkr-iomux"; + }; + + lpass: audio-controller@7708000 { + status = "disabled"; + compatible = "qcom,apq8016-lpass-cpu"; + + /* + * Note: Unlike the name would suggest, the SEC_I2S_CLK + * is actually only used by Tertiary MI2S while + * Primary/Secondary MI2S both use the PRI_I2S_CLK. + */ + clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; + + clock-names = "ahbix-clk", + "mi2s-bit-clk0", + "mi2s-bit-clk1", + "mi2s-bit-clk2", + "mi2s-bit-clk3", + "pcnoc-mport-clk", + "pcnoc-sway-clk"; + #sound-dai-cells = <1>; + + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "lpass-irq-lpaif"; + reg = <0x07708000 0x10000>; + reg-names = "lpass-lpaif"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + lpass_codec: audio-codec@771c000 { + compatible = "qcom,msm8916-wcd-digital-codec"; + reg = <0x0771c000 0x400>; + clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, + <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "ahbix-clk", "mclk"; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + sdhc_1: mmc@7824900 { + compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x07824900 0x11c>, <0x07824000 0x800>; + reg-names = "hc", "core"; + + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + pinctrl-0 = <&sdc1_default>; + pinctrl-1 = <&sdc1_sleep>; + pinctrl-names = "default", "sleep"; + mmc-ddr-1_8v; + bus-width = <8>; + non-removable; + status = "disabled"; + }; + + sdhc_2: mmc@7864900 { + compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x07864900 0x11c>, <0x07864000 0x800>; + reg-names = "hc", "core"; + + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + pinctrl-0 = <&sdc2_default>; + pinctrl-1 = <&sdc2_sleep>; + pinctrl-names = "default", "sleep"; + bus-width = <4>; + status = "disabled"; + }; + + blsp_dma: dma-controller@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x23000>; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + blsp_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 0>, <&blsp_dma 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp_uart1_default>; + pinctrl-1 = <&blsp_uart1_sleep>; + status = "disabled"; + }; + + blsp_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 2>, <&blsp_dma 3>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + status = "disabled"; + }; + + blsp_i2c1: i2c@78b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b5000 0x500>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp_i2c1_default>; + pinctrl-1 = <&blsp_i2c1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi1: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b5000 0x500>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp_spi1_default>; + pinctrl-1 = <&blsp_spi1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c2: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b6000 0x500>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp_i2c2_default>; + pinctrl-1 = <&blsp_i2c2_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi2: spi@78b6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b6000 0x500>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp_spi2_default>; + pinctrl-1 = <&blsp_spi2_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c3: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b7000 0x500>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp_i2c3_default>; + pinctrl-1 = <&blsp_i2c3_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi3: spi@78b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b7000 0x500>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp_spi3_default>; + pinctrl-1 = <&blsp_spi3_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c4: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b8000 0x500>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp_i2c4_default>; + pinctrl-1 = <&blsp_i2c4_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi4: spi@78b8000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b8000 0x500>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp_spi4_default>; + pinctrl-1 = <&blsp_spi4_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c5: i2c@78b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b9000 0x500>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 12>, <&blsp_dma 13>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp_i2c5_default>; + pinctrl-1 = <&blsp_i2c5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi5: spi@78b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b9000 0x500>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 12>, <&blsp_dma 13>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp_spi5_default>; + pinctrl-1 = <&blsp_spi5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c6: i2c@78ba000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078ba000 0x500>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp_i2c6_default>; + pinctrl-1 = <&blsp_i2c6_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi6: spi@78ba000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078ba000 0x500>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp_spi6_default>; + pinctrl-1 = <&blsp_spi6_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usb: usb@78d9000 { + compatible = "qcom,ci-hdrc"; + reg = <0x078d9000 0x200>, + <0x078d9200 0x200>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names = "iface", "core"; + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <80000000>; + resets = <&gcc GCC_USB_HS_BCR>; + reset-names = "core"; + phy_type = "ulpi"; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + ahb-burst-config = <0>; + phy-names = "usb-phy"; + phys = <&usb_hs_phy>; + status = "disabled"; + #reset-cells = <1>; + + ulpi { + usb_hs_phy: phy { + compatible = "qcom,usb-hs-phy-msm8916", + "qcom,usb-hs-phy"; + #phy-cells = <0>; + clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "sleep"; + resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; + reset-names = "phy", "por"; + qcom,init-seq = /bits/ 8 <0x0 0x44>, + <0x1 0x6b>, + <0x2 0x24>, + <0x3 0x13>; + }; + }; + }; + + wcnss: remoteproc@a204000 { + compatible = "qcom,pronto-v2-pil", "qcom,pronto"; + reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; + reg-names = "ccu", "dxe", "pmu"; + + memory-region = <&wcnss_mem>; + + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + power-domains = <&rpmpd MSM8916_VDDCX>, + <&rpmpd MSM8916_VDDMX>; + power-domain-names = "cx", "mx"; + + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcss_wlan_default>; + + status = "disabled"; + + wcnss_iris: iris { + /* Separate chip, compatible is board-specific */ + clocks = <&rpmcc RPM_SMD_RF_CLK2>; + clock-names = "xo"; + }; + + smd-edge { + interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + + label = "pronto"; + + wcnss_ctrl: wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + qcom,mmio = <&wcnss>; + + wcnss_bt: bluetooth { + compatible = "qcom,wcnss-bt"; + }; + + wcnss_wifi: wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", "tx-rings-empty"; + }; + }; + }; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, + <0x0b001000 0x1000>, <0x0b004000 0x2000>; + interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + apcs: mailbox@b011000 { + compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; + reg = <0x0b011000 0x1000>; + #mbox-cells = <1>; + clocks = <&a53pll>, <&gcc GPLL0_VOTE>; + clock-names = "pll", "aux"; + #clock-cells = <0>; + }; + + a53pll: clock@b016000 { + compatible = "qcom,msm8916-a53pll"; + reg = <0x0b016000 0x40>; + #clock-cells = <0>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + timer@b020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0b020000 0x1000>; + clock-frequency = <19200000>; + + frame@b021000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b021000 0x1000>, + <0x0b022000 0x1000>; + }; + + frame@b023000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b023000 0x1000>; + status = "disabled"; + }; + + frame@b024000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b024000 0x1000>; + status = "disabled"; + }; + + frame@b025000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b025000 0x1000>; + status = "disabled"; + }; + + frame@b026000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b026000 0x1000>; + status = "disabled"; + }; + + frame@b027000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b027000 0x1000>; + status = "disabled"; + }; + + frame@b028000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b028000 0x1000>; + status = "disabled"; + }; + }; + + cpu0_acc: power-manager@b088000 { + compatible = "qcom,msm8916-acc"; + reg = <0x0b088000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu0_saw: power-manager@b089000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b089000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu1_acc: power-manager@b098000 { + compatible = "qcom,msm8916-acc"; + reg = <0x0b098000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu1_saw: power-manager@b099000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b099000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu2_acc: power-manager@b0a8000 { + compatible = "qcom,msm8916-acc"; + reg = <0x0b0a8000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu2_saw: power-manager@b0a9000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b0a9000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu3_acc: power-manager@b0b8000 { + compatible = "qcom,msm8916-acc"; + reg = <0x0b0b8000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu3_saw: power-manager@b0b9000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b0b9000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + }; + + thermal-zones { + cpu0-1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu0_1_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu0_1_crit: cpu-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_1_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2-3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 4>; + + trips { + cpu2_3_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu2_3_crit: cpu-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu2_3_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + + trips { + gpu_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit: gpu-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 1>; + + trips { + cam_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + modem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 0>; + + trips { + modem_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm/dts/msm8996.dtsi b/arch/arm/dts/msm8996.dtsi new file mode 100644 index 00000000000..6ba9da9e6a8 --- /dev/null +++ b/arch/arm/dts/msm8996.dtsi @@ -0,0 +1,3884 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,gcc-msm8996.h> +#include <dt-bindings/clock/qcom,mmcc-msm8996.h> +#include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/interconnect/qcom,msm8996.h> +#include <dt-bindings/interconnect/qcom,msm8996-cbf.h> +#include <dt-bindings/firmware/qcom,scm.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,apr.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + capacity-dmips-mhz = <1024>; + clocks = <&kryocc 0>; + interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + capacity-dmips-mhz = <1024>; + clocks = <&kryocc 0>; + interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + capacity-dmips-mhz = <1024>; + clocks = <&kryocc 1>; + interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; + operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + CPU3: cpu@101 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + capacity-dmips-mhz = <1024>; + clocks = <&kryocc 1>; + interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; + operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; + next-level-cache = <&L2_1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU2>; + }; + + core1 { + cpu = <&CPU3>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "standalone-power-collapse"; + arm,psci-suspend-param = <0x00000004>; + entry-latency-us = <130>; + exit-latency-us = <80>; + min-residency-us = <300>; + }; + }; + }; + + cluster0_opp: opp-table-cluster0 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + /* Nominal fmax for now */ + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; + }; + opp-422400000 { + opp-hz = /bits/ 64 <422400000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; + }; + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; + }; + opp-556800000 { + opp-hz = /bits/ 64 <556800000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; + }; + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <384000>; + }; + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <460800>; + }; + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <537600>; + }; + opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <672000>; + }; + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <672000>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <825600>; + }; + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <825600>; + }; + opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <902400>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-supported-hw = <0xd>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1056000>; + }; + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-supported-hw = <0x2>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1132800>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-supported-hw = <0xd>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1132800>; + }; + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + opp-supported-hw = <0x9>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1190400>; + }; + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-supported-hw = <0x04>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1305600>; + }; + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + opp-supported-hw = <0x9>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1382400>; + }; + }; + + cluster1_opp: opp-table-cluster1 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + /* Nominal fmax for now */ + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; + }; + opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; + }; + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; + }; + opp-556800000 { + opp-hz = /bits/ 64 <556800000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; + }; + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; + }; + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; + }; + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <384000>; + }; + opp-883200000 { + opp-hz = /bits/ 64 <883200000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <460800>; + }; + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <537600>; + }; + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <595200>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <672000>; + }; + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <672000>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <748800>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <825600>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <902400>; + }; + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <979200>; + }; + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1056000>; + }; + opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1190400>; + }; + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1228800>; + }; + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1305600>; + }; + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-supported-hw = <0xe>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1305600>; + }; + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1382400>; + }; + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-supported-hw = <0x4>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1305600>; + }; + opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1459200>; + }; + opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; + }; + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; + }; + opp-2150400000 { + opp-hz = /bits/ 64 <2150400000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-msm8996", "qcom,scm"; + qcom,dload-mode = <&tcsr_2 0x13000>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rpm: remoteproc { + compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8996"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8996-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp1: opp1 { + opp-level = <1>; + }; + + rpmpd_opp2: opp2 { + opp-level = <2>; + }; + + rpmpd_opp3: opp3 { + opp-level = <3>; + }; + + rpmpd_opp4: opp4 { + opp-level = <4>; + }; + + rpmpd_opp5: opp5 { + opp-level = <5>; + }; + + rpmpd_opp6: opp6 { + opp-level = <6>; + }; + }; + }; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@85800000 { + reg = <0x0 0x85800000 0x0 0x600000>; + no-map; + }; + + xbl_mem: memory@85e00000 { + reg = <0x0 0x85e00000 0x0 0x200000>; + no-map; + }; + + smem_mem: smem-mem@86000000 { + reg = <0x0 0x86000000 0x0 0x200000>; + no-map; + }; + + tz_mem: memory@86200000 { + reg = <0x0 0x86200000 0x0 0x2600000>; + no-map; + }; + + rmtfs_mem: rmtfs { + compatible = "qcom,rmtfs-mem"; + + size = <0x0 0x200000>; + alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + mpss_mem: mpss@88800000 { + reg = <0x0 0x88800000 0x0 0x6200000>; + no-map; + }; + + adsp_mem: adsp@8ea00000 { + reg = <0x0 0x8ea00000 0x0 0x1b00000>; + no-map; + }; + + slpi_mem: slpi@90500000 { + reg = <0x0 0x90500000 0x0 0xa00000>; + no-map; + }; + + gpu_mem: gpu@90f00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x90f00000 0x0 0x100000>; + no-map; + }; + + venus_mem: venus@91000000 { + reg = <0x0 0x91000000 0x0 0x500000>; + no-map; + }; + + mba_mem: mba@91500000 { + reg = <0x0 0x91500000 0x0 0x200000>; + no-map; + }; + + mdata_mem: mpss-metadata { + alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; + size = <0x0 0x4000>; + no-map; + }; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs_glb 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs_glb 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + mpss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + mpss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-slpi { + compatible = "qcom,smp2p"; + qcom,smem = <481>, <430>; + + interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs_glb 26>; + + qcom,local-pid = <0>; + qcom,remote-pid = <3>; + + slpi_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + slpi_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + pcie_phy: phy-wrapper@34000 { + compatible = "qcom,msm8996-qmp-pcie-phy"; + reg = <0x00034000 0x488>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00034000 0x4000>; + + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_CLK>; + clock-names = "aux", "cfg_ahb", "ref"; + + resets = <&gcc GCC_PCIE_PHY_BCR>, + <&gcc GCC_PCIE_PHY_COM_BCR>, + <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; + reset-names = "phy", "common", "cfg"; + + status = "disabled"; + + pciephy_0: phy@1000 { + reg = <0x1000 0x130>, + <0x1200 0x200>, + <0x1400 0x1dc>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "lane0"; + + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk_src"; + + #phy-cells = <0>; + }; + + pciephy_1: phy@2000 { + reg = <0x2000 0x130>, + <0x2200 0x200>, + <0x2400 0x1dc>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "pipe1"; + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "lane1"; + + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk_src"; + + #phy-cells = <0>; + }; + + pciephy_2: phy@3000 { + reg = <0x3000 0x130>, + <0x3200 0x200>, + <0x3400 0x1dc>; + + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; + clock-names = "pipe2"; + resets = <&gcc GCC_PCIE_2_PHY_BCR>; + reset-names = "lane2"; + + #clock-cells = <0>; + clock-output-names = "pcie_2_pipe_clk_src"; + + #phy-cells = <0>; + }; + }; + + rpm_msg_ram: sram@68000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x00068000 0x6000>; + }; + + qfprom@74000 { + compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; + reg = <0x00074000 0x8ff>; + #address-cells = <1>; + #size-cells = <1>; + + qusb2p_hstx_trim: hstx_trim@24e { + reg = <0x24e 0x2>; + bits = <5 4>; + }; + + qusb2s_hstx_trim: hstx_trim@24f { + reg = <0x24f 0x1>; + bits = <1 4>; + }; + + speedbin_efuse: speedbin@133 { + reg = <0x133 0x1>; + bits = <5 3>; + }; + }; + + rng: rng@83000 { + compatible = "qcom,prng-ee"; + reg = <0x00083000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + gcc: clock-controller@300000 { + compatible = "qcom,gcc-msm8996"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x00300000 0x90000>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_LN_BB_CLK>, + <&sleep_clk>, + <&pciephy_0>, + <&pciephy_1>, + <&pciephy_2>, + <&ssusb_phy_0>, + <&ufsphy_lane 0>, + <&ufsphy_lane 1>, + <&ufsphy_lane 2>; + clock-names = "cxo", + "cxo2", + "sleep_clk", + "pcie_0_pipe_clk_src", + "pcie_1_pipe_clk_src", + "pcie_2_pipe_clk_src", + "usb3_phy_pipe_clk_src", + "ufs_rx_symbol_0_clk_src", + "ufs_rx_symbol_1_clk_src", + "ufs_tx_symbol_0_clk_src"; + }; + + bimc: interconnect@408000 { + compatible = "qcom,msm8996-bimc"; + reg = <0x00408000 0x5a000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + + tsens0: thermal-sensor@4a9000 { + compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + #qcom,sensors = <13>; + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@4ad000 { + compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; + reg = <0x004ad000 0x1000>, /* TM */ + <0x004ac000 0x1000>; /* SROT */ + #qcom,sensors = <8>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + cryptobam: dma-controller@644000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x00644000 0x24000>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_CE1_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + }; + + crypto: crypto@67a000 { + compatible = "qcom,crypto-v5.4"; + reg = <0x0067a000 0x6000>; + clocks = <&gcc GCC_CE1_AHB_CLK>, + <&gcc GCC_CE1_AXI_CLK>, + <&gcc GCC_CE1_CLK>; + clock-names = "iface", "bus", "core"; + dmas = <&cryptobam 6>, <&cryptobam 7>; + dma-names = "rx", "tx"; + }; + + cnoc: interconnect@500000 { + compatible = "qcom,msm8996-cnoc"; + reg = <0x00500000 0x1000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + }; + + snoc: interconnect@524000 { + compatible = "qcom,msm8996-snoc"; + reg = <0x00524000 0x1c000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + + a0noc: interconnect@543000 { + compatible = "qcom,msm8996-a0noc"; + reg = <0x00543000 0x6000>; + #interconnect-cells = <1>; + clock-names = "aggre0_snoc_axi", + "aggre0_cnoc_ahb", + "aggre0_noc_mpu_cfg"; + clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, + <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, + <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; + power-domains = <&gcc AGGRE0_NOC_GDSC>; + }; + + a1noc: interconnect@562000 { + compatible = "qcom,msm8996-a1noc"; + reg = <0x00562000 0x5000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, + <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; + }; + + a2noc: interconnect@583000 { + compatible = "qcom,msm8996-a2noc"; + reg = <0x00583000 0x7000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi"; + clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, + <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, + <&gcc GCC_AGGRE2_UFS_AXI_CLK>, + <&gcc GCC_UFS_AXI_CLK>; + }; + + mnoc: interconnect@5a4000 { + compatible = "qcom,msm8996-mnoc"; + reg = <0x005a4000 0x1c000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a", "iface"; + clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, + <&rpmcc RPM_SMD_MMAXI_A_CLK>, + <&mmcc AHB_CLK_SRC>; + }; + + pnoc: interconnect@5c0000 { + compatible = "qcom,msm8996-pnoc"; + reg = <0x005c0000 0x3000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + }; + + tcsr_mutex: hwlock@740000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x00740000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr_1: syscon@760000 { + compatible = "qcom,tcsr-msm8996", "syscon"; + reg = <0x00760000 0x20000>; + }; + + tcsr_2: syscon@7a0000 { + compatible = "qcom,tcsr-msm8996", "syscon"; + reg = <0x007a0000 0x18000>; + }; + + mmcc: clock-controller@8c0000 { + compatible = "qcom,mmcc-msm8996"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x008c0000 0x40000>; + clocks = <&xo_board>, + <&gcc GPLL0>, + <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_hdmi_phy>; + clock-names = "xo", + "gpll0", + "gcc_mmss_noc_cfg_ahb_clk", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte", + "hdmipll"; + assigned-clocks = <&mmcc MMPLL9_PLL>, + <&mmcc MMPLL1_PLL>, + <&mmcc MMPLL3_PLL>, + <&mmcc MMPLL4_PLL>, + <&mmcc MMPLL5_PLL>; + assigned-clock-rates = <624000000>, + <810000000>, + <980000000>, + <960000000>, + <825000000>; + }; + + mdss: display-subsystem@900000 { + compatible = "qcom,mdss"; + + reg = <0x00900000 0x1000>, + <0x009b0000 0x1040>, + <0x009b8000 0x1040>; + reg-names = "mdss_phys", + "vbif_phys", + "vbif_nrt_phys"; + + power-domains = <&mmcc MDSS_GDSC>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>; + clock-names = "iface", "core"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + mdp: display-controller@901000 { + compatible = "qcom,msm8996-mdp5", "qcom,mdp5"; + reg = <0x00901000 0x90000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc SMMU_MDP_AXI_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "iommu", + "vsync"; + + iommus = <&mdp_smmu 0>; + + assigned-clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + assigned-clock-rates = <300000000>, + <19200000>; + + interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, + <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, + <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; + interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf3_out: endpoint { + remote-endpoint = <&mdss_hdmi_in>; + }; + }; + + port@1 { + reg = <1>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + mdp5_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@994000 { + compatible = "qcom,msm8996-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x00994000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "byte", + "iface", + "bus", + "core_mmss", + "pixel", + "core"; + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + phys = <&mdss_dsi0_phy>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@994400 { + compatible = "qcom,dsi-phy-14nm"; + reg = <0x00994400 0x100>, + <0x00994500 0x300>, + <0x00994800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + status = "disabled"; + }; + + mdss_dsi1: dsi@996000 { + compatible = "qcom,msm8996-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x00996000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_BYTE1_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>, + <&mmcc MDSS_PCLK1_CLK>, + <&mmcc MDSS_ESC1_CLK>; + clock-names = "mdp_core", + "byte", + "iface", + "bus", + "core_mmss", + "pixel", + "core"; + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + phys = <&mdss_dsi1_phy>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@996400 { + compatible = "qcom,dsi-phy-14nm"; + reg = <0x00996400 0x100>, + <0x00996500 0x300>, + <0x00996800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + status = "disabled"; + }; + + mdss_hdmi: hdmi-tx@9a0000 { + compatible = "qcom,hdmi-tx-8996"; + reg = <0x009a0000 0x50c>, + <0x00070000 0x6158>, + <0x009e0000 0xfff>; + reg-names = "core_physical", + "qfprom_physical", + "hdcp_physical"; + + interrupt-parent = <&mdss>; + interrupts = <8>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_HDMI_CLK>, + <&mmcc MDSS_HDMI_AHB_CLK>, + <&mmcc MDSS_EXTPCLK_CLK>; + clock-names = + "mdp_core", + "iface", + "core", + "alt_iface", + "extp"; + + phys = <&mdss_hdmi_phy>; + #sound-dai-cells = <1>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_hdmi_in: endpoint { + remote-endpoint = <&mdp5_intf3_out>; + }; + }; + }; + }; + + mdss_hdmi_phy: phy@9a0600 { + #phy-cells = <0>; + compatible = "qcom,hdmi-phy-8996"; + reg = <0x009a0600 0x1c4>, + <0x009a0a00 0x124>, + <0x009a0c00 0x124>, + <0x009a0e00 0x124>, + <0x009a1000 0x124>, + <0x009a1200 0x0c8>; + reg-names = "hdmi_pll", + "hdmi_tx_l0", + "hdmi_tx_l1", + "hdmi_tx_l2", + "hdmi_tx_l3", + "hdmi_phy"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&gcc GCC_HDMI_CLKREF_CLK>, + <&xo_board>; + clock-names = "iface", + "ref", + "xo"; + + #clock-cells = <0>; + + status = "disabled"; + }; + }; + + gpu: gpu@b00000 { + compatible = "qcom,adreno-530.2", "qcom,adreno"; + + reg = <0x00b00000 0x3f000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&mmcc GPU_GX_GFX3D_CLK>, + <&mmcc GPU_AHB_CLK>, + <&mmcc GPU_GX_RBBMTIMER_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_MMSS_BIMC_GFX_CLK>; + + clock-names = "core", + "iface", + "rbbmtimer", + "mem", + "mem_iface"; + + interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; + interconnect-names = "gfx-mem"; + + power-domains = <&mmcc GPU_GX_GDSC>; + iommus = <&adreno_smmu 0>; + + nvmem-cells = <&speedbin_efuse>; + nvmem-cell-names = "speed_bin"; + + operating-points-v2 = <&gpu_opp_table>; + + status = "disabled"; + + #cooling-cells = <2>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* + * 624Mhz is only available on speed bins 0 and 3. + * 560Mhz is only available on speed bins 0, 2 and 3. + * All the rest are available on all bins of the hardware. + */ + opp-624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-supported-hw = <0x09>; + }; + opp-560000000 { + opp-hz = /bits/ 64 <560000000>; + opp-supported-hw = <0x0d>; + }; + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + opp-supported-hw = <0xff>; + }; + opp-401800000 { + opp-hz = /bits/ 64 <401800000>; + opp-supported-hw = <0xff>; + }; + opp-315000000 { + opp-hz = /bits/ 64 <315000000>; + opp-supported-hw = <0xff>; + }; + opp-214000000 { + opp-hz = /bits/ 64 <214000000>; + opp-supported-hw = <0xff>; + }; + opp-133000000 { + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0xff>; + }; + }; + + zap-shader { + memory-region = <&gpu_mem>; + }; + }; + + tlmm: pinctrl@1010000 { + compatible = "qcom,msm8996-pinctrl"; + reg = <0x01010000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 150>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1_spi1_default: blsp1-spi1-default-state { + spi-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp1_spi1_sleep: blsp1-spi1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp2_uart2_2pins_default: blsp2-uart2-2pins-state { + pins = "gpio4", "gpio5"; + function = "blsp_uart8"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state { + pins = "gpio4", "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c2_default: blsp2-i2c2-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c8"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c6_default: blsp1-i2c6-state { + pins = "gpio27", "gpio28"; + function = "blsp_i2c6"; + drive-strength = <16>; + bias-disable; + }; + + blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { + pins = "gpio27", "gpio28"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_default: cci0-default-state { + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + drive-strength = <16>; + bias-disable; + }; + + camera0_state_on: + camera_rear_default: camera-rear-default-state { + camera0_mclk: mclk0-pins { + pins = "gpio13"; + function = "cam_mclk"; + drive-strength = <16>; + bias-disable; + }; + + camera0_rst: rst-pins { + pins = "gpio25"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + camera0_pwdn: pwdn-pins { + pins = "gpio26"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + }; + + cci1_default: cci1-default-state { + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + drive-strength = <16>; + bias-disable; + }; + + camera1_state_on: + camera_board_default: camera-board-default-state { + mclk1-pins { + pins = "gpio14"; + function = "cam_mclk"; + drive-strength = <16>; + bias-disable; + }; + + pwdn-pins { + pins = "gpio98"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + rst-pins { + pins = "gpio104"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + }; + + camera2_state_on: + camera_front_default: camera-front-default-state { + camera2_mclk: mclk2-pins { + pins = "gpio15"; + function = "cam_mclk"; + drive-strength = <16>; + bias-disable; + }; + + camera2_rst: rst-pins { + pins = "gpio23"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + pwdn-pins { + pins = "gpio133"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + }; + + pcie0_state_on: pcie0-state-on-state { + perst-pins { + pins = "gpio35"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio36"; + function = "pci_e0"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio37"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_state_off: pcie0-state-off-state { + perst-pins { + pins = "gpio35"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio36"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-pins { + pins = "gpio37"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2_default: blsp1-uart2-default-state { + pins = "gpio41", "gpio42", "gpio43", "gpio44"; + function = "blsp_uart2"; + drive-strength = <16>; + bias-disable; + }; + + blsp1_uart2_sleep: blsp1-uart2-sleep-state { + pins = "gpio41", "gpio42", "gpio43", "gpio44"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c3_default: blsp1-i2c3-default-state { + pins = "gpio47", "gpio48"; + function = "blsp_i2c3"; + drive-strength = <16>; + bias-disable; + }; + + blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { + pins = "gpio47", "gpio48"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_uart3_4pins_default: blsp2-uart3-4pins-state { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + function = "blsp_uart9"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + function = "blsp_uart9"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c3_default: blsp2-i2c3-state-state { + pins = "gpio51", "gpio52"; + function = "blsp_i2c9"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { + pins = "gpio51", "gpio52"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcd_intr_default: wcd-intr-default-state { + pins = "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp2_i2c1_default: blsp2-i2c1-state { + pins = "gpio55", "gpio56"; + function = "blsp_i2c7"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { + pins = "gpio55", "gpio56"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c5_default: blsp2-i2c5-state { + pins = "gpio60", "gpio61"; + function = "blsp_i2c11"; + drive-strength = <2>; + bias-disable; + }; + + /* Sleep state for BLSP2_I2C5 is missing.. */ + + cdc_reset_active: cdc-reset-active-state { + pins = "gpio64"; + function = "gpio"; + drive-strength = <16>; + bias-pull-down; + output-high; + }; + + cdc_reset_sleep: cdc-reset-sleep-state { + pins = "gpio64"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + blsp2_spi6_default: blsp2-spi6-default-state { + spi-pins { + pins = "gpio85", "gpio86", "gpio88"; + function = "blsp_spi12"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio87"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp2_spi6_sleep: blsp2-spi6-sleep-state { + pins = "gpio85", "gpio86", "gpio87", "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp2_i2c6_default: blsp2-i2c6-state { + pins = "gpio87", "gpio88"; + function = "blsp_i2c12"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { + pins = "gpio87", "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie1_state_on: pcie1-on-state { + perst-pins { + pins = "gpio130"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio131"; + function = "pci_e1"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio132"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie1_state_off: pcie1-off-state { + /* Perst is missing? */ + clkreq-pins { + pins = "gpio131"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-pins { + pins = "gpio132"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie2_state_on: pcie2-on-state { + perst-pins { + pins = "gpio114"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio115"; + function = "pci_e2"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio116"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie2_state_off: pcie2-off-state { + /* Perst is missing? */ + clkreq-pins { + pins = "gpio115"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-pins { + pins = "gpio116"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_state_on: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc2_state_off: sdc2-off-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + }; + + sram@290000 { + compatible = "qcom,rpm-stats"; + reg = <0x00290000 0x10000>; + }; + + spmi_bus: spmi@400f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0400f000 0x1000>, + <0x04400000 0x800000>, + <0x04c00000 0x800000>, + <0x05800000 0x200000>, + <0x0400a000 0x002100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + bus@0 { + power-domains = <&gcc AGGRE0_NOC_GDSC>; + compatible = "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xffffffff>; + + pcie0: pcie@600000 { + compatible = "qcom,pcie-msm8996"; + status = "disabled"; + power-domains = <&gcc PCIE0_GDSC>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + reg = <0x00600000 0x2000>, + <0x0c000000 0xf1d>, + <0x0c000f20 0xa8>, + <0x0c100000 0x100000>; + reg-names = "parf", "dbi", "elbi","config"; + + phys = <&pciephy_0>; + phy-names = "pciephy"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>, + <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; + + device_type = "pci"; + + interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie0_state_on>; + pinctrl-1 = <&pcie0_state_off>; + + linux,pci-domain = <0>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>; + + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave"; + }; + + pcie1: pcie@608000 { + compatible = "qcom,pcie-msm8996"; + power-domains = <&gcc PCIE1_GDSC>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + status = "disabled"; + + reg = <0x00608000 0x2000>, + <0x0d000000 0xf1d>, + <0x0d000f20 0xa8>, + <0x0d100000 0x100000>; + + reg-names = "parf", "dbi", "elbi","config"; + + phys = <&pciephy_1>; + phy-names = "pciephy"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>, + <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; + + device_type = "pci"; + + interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie1_state_on>; + pinctrl-1 = <&pcie1_state_off>; + + linux,pci-domain = <1>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>; + + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave"; + }; + + pcie2: pcie@610000 { + compatible = "qcom,pcie-msm8996"; + power-domains = <&gcc PCIE2_GDSC>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + status = "disabled"; + reg = <0x00610000 0x2000>, + <0x0e000000 0xf1d>, + <0x0e000f20 0xa8>, + <0x0e100000 0x100000>; + + reg-names = "parf", "dbi", "elbi","config"; + + phys = <&pciephy_2>; + phy-names = "pciephy"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>, + <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; + + device_type = "pci"; + + interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie2_state_on>; + pinctrl-1 = <&pcie2_state_off>; + + linux,pci-domain = <2>; + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, + <&gcc GCC_PCIE_2_AUX_CLK>, + <&gcc GCC_PCIE_2_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_AXI_CLK>; + + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave"; + }; + }; + + ufshc: ufshc@624000 { + compatible = "qcom,msm8996-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x00624000 0x2500>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + + phys = <&ufsphy_lane>; + phy-names = "ufsphy"; + + power-domains = <&gcc UFS_GDSC>; + + clock-names = + "core_clk_src", + "core_clk", + "bus_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro_src", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&gcc UFS_AXI_CLK_SRC>, + <&gcc GCC_UFS_AXI_CLK>, + <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, + <&gcc GCC_AGGRE2_UFS_AXI_CLK>, + <&gcc GCC_UFS_AHB_CLK>, + <&gcc UFS_ICE_CORE_CLK_SRC>, + <&gcc GCC_UFS_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_ICE_CORE_CLK>, + <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; + freq-table-hz = + <100000000 200000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <150000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + lanes-per-direction = <1>; + #reset-cells = <1>; + status = "disabled"; + }; + + ufsphy: phy@627000 { + compatible = "qcom,msm8996-qmp-ufs-phy"; + reg = <0x00627000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_UFS_CLKREF_CLK>; + clock-names = "ref"; + + resets = <&ufshc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufsphy_lane: phy@627400 { + reg = <0x627400 0x12c>, + <0x627600 0x200>, + <0x627c00 0x1b4>; + #clock-cells = <1>; + #phy-cells = <0>; + }; + }; + + camss: camss@a34000 { + compatible = "qcom,msm8996-camss"; + reg = <0x00a34000 0x1000>, + <0x00a00030 0x4>, + <0x00a35000 0x1000>, + <0x00a00038 0x4>, + <0x00a36000 0x1000>, + <0x00a00040 0x4>, + <0x00a30000 0x100>, + <0x00a30400 0x100>, + <0x00a30800 0x100>, + <0x00a30c00 0x100>, + <0x00a31000 0x500>, + <0x00a00020 0x10>, + <0x00a10000 0x1000>, + <0x00a14000 0x1000>; + reg-names = "csiphy0", + "csiphy0_clk_mux", + "csiphy1", + "csiphy1_clk_mux", + "csiphy2", + "csiphy2_clk_mux", + "csid0", + "csid1", + "csid2", + "csid3", + "ispif", + "csi_clk_mux", + "vfe0", + "vfe1"; + interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csiphy0", + "csiphy1", + "csiphy2", + "csid0", + "csid1", + "csid2", + "csid3", + "ispif", + "vfe0", + "vfe1"; + power-domains = <&mmcc VFE0_GDSC>, + <&mmcc VFE1_GDSC>; + clocks = <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_ISPIF_AHB_CLK>, + <&mmcc CAMSS_CSI0PHYTIMER_CLK>, + <&mmcc CAMSS_CSI1PHYTIMER_CLK>, + <&mmcc CAMSS_CSI2PHYTIMER_CLK>, + <&mmcc CAMSS_CSI0_AHB_CLK>, + <&mmcc CAMSS_CSI0_CLK>, + <&mmcc CAMSS_CSI0PHY_CLK>, + <&mmcc CAMSS_CSI0PIX_CLK>, + <&mmcc CAMSS_CSI0RDI_CLK>, + <&mmcc CAMSS_CSI1_AHB_CLK>, + <&mmcc CAMSS_CSI1_CLK>, + <&mmcc CAMSS_CSI1PHY_CLK>, + <&mmcc CAMSS_CSI1PIX_CLK>, + <&mmcc CAMSS_CSI1RDI_CLK>, + <&mmcc CAMSS_CSI2_AHB_CLK>, + <&mmcc CAMSS_CSI2_CLK>, + <&mmcc CAMSS_CSI2PHY_CLK>, + <&mmcc CAMSS_CSI2PIX_CLK>, + <&mmcc CAMSS_CSI2RDI_CLK>, + <&mmcc CAMSS_CSI3_AHB_CLK>, + <&mmcc CAMSS_CSI3_CLK>, + <&mmcc CAMSS_CSI3PHY_CLK>, + <&mmcc CAMSS_CSI3PIX_CLK>, + <&mmcc CAMSS_CSI3RDI_CLK>, + <&mmcc CAMSS_AHB_CLK>, + <&mmcc CAMSS_VFE0_CLK>, + <&mmcc CAMSS_CSI_VFE0_CLK>, + <&mmcc CAMSS_VFE0_AHB_CLK>, + <&mmcc CAMSS_VFE0_STREAM_CLK>, + <&mmcc CAMSS_VFE1_CLK>, + <&mmcc CAMSS_CSI_VFE1_CLK>, + <&mmcc CAMSS_VFE1_AHB_CLK>, + <&mmcc CAMSS_VFE1_STREAM_CLK>, + <&mmcc CAMSS_VFE_AHB_CLK>, + <&mmcc CAMSS_VFE_AXI_CLK>; + clock-names = "top_ahb", + "ispif_ahb", + "csiphy0_timer", + "csiphy1_timer", + "csiphy2_timer", + "csi0_ahb", + "csi0", + "csi0_phy", + "csi0_pix", + "csi0_rdi", + "csi1_ahb", + "csi1", + "csi1_phy", + "csi1_pix", + "csi1_rdi", + "csi2_ahb", + "csi2", + "csi2_phy", + "csi2_pix", + "csi2_rdi", + "csi3_ahb", + "csi3", + "csi3_phy", + "csi3_pix", + "csi3_rdi", + "ahb", + "vfe0", + "csi_vfe0", + "vfe0_ahb", + "vfe0_stream", + "vfe1", + "csi_vfe1", + "vfe1_ahb", + "vfe1_stream", + "vfe_ahb", + "vfe_axi"; + iommus = <&vfe_smmu 0>, + <&vfe_smmu 1>, + <&vfe_smmu 2>, + <&vfe_smmu 3>; + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci: cci@a0c000 { + compatible = "qcom,msm8996-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa0c000 0x1000>; + interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; + power-domains = <&mmcc CAMSS_GDSC>; + clocks = <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CLK>, + <&mmcc CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb", + "cci_ahb", + "cci", + "camss_ahb"; + assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CLK>; + assigned-clock-rates = <80000000>, <37500000>; + pinctrl-names = "default"; + pinctrl-0 = <&cci0_default &cci1_default>; + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + adreno_smmu: iommu@b40000 { + compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; + reg = <0x00b40000 0x10000>; + + #global-interrupts = <1>; + interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + + clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>, + <&mmcc GPU_AHB_CLK>; + clock-names = "bus", "iface"; + + power-domains = <&mmcc GPU_GDSC>; + }; + + venus: video-codec@c00000 { + compatible = "qcom,msm8996-venus"; + reg = <0x00c00000 0xff000>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&mmcc VENUS_GDSC>; + clocks = <&mmcc VIDEO_CORE_CLK>, + <&mmcc VIDEO_AHB_CLK>, + <&mmcc VIDEO_AXI_CLK>, + <&mmcc VIDEO_MAXI_CLK>; + clock-names = "core", "iface", "bus", "mbus"; + interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; + interconnect-names = "video-mem", "cpu-cfg"; + iommus = <&venus_smmu 0x00>, + <&venus_smmu 0x01>, + <&venus_smmu 0x0a>, + <&venus_smmu 0x07>, + <&venus_smmu 0x0e>, + <&venus_smmu 0x0f>, + <&venus_smmu 0x08>, + <&venus_smmu 0x09>, + <&venus_smmu 0x0b>, + <&venus_smmu 0x0c>, + <&venus_smmu 0x0d>, + <&venus_smmu 0x10>, + <&venus_smmu 0x11>, + <&venus_smmu 0x21>, + <&venus_smmu 0x28>, + <&venus_smmu 0x29>, + <&venus_smmu 0x2b>, + <&venus_smmu 0x2c>, + <&venus_smmu 0x2d>, + <&venus_smmu 0x31>; + memory-region = <&venus_mem>; + status = "disabled"; + + video-decoder { + compatible = "venus-decoder"; + clocks = <&mmcc VIDEO_SUBCORE0_CLK>; + clock-names = "core"; + power-domains = <&mmcc VENUS_CORE0_GDSC>; + }; + + video-encoder { + compatible = "venus-encoder"; + clocks = <&mmcc VIDEO_SUBCORE1_CLK>; + clock-names = "core"; + power-domains = <&mmcc VENUS_CORE1_GDSC>; + }; + }; + + mdp_smmu: iommu@d00000 { + compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; + reg = <0x00d00000 0x10000>; + + #global-interrupts = <1>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + clocks = <&mmcc SMMU_MDP_AXI_CLK>, + <&mmcc SMMU_MDP_AHB_CLK>; + clock-names = "bus", "iface"; + + power-domains = <&mmcc MDSS_GDSC>; + }; + + venus_smmu: iommu@d40000 { + compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; + reg = <0x00d40000 0x20000>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; + clocks = <&mmcc SMMU_VIDEO_AXI_CLK>, + <&mmcc SMMU_VIDEO_AHB_CLK>; + clock-names = "bus", "iface"; + #iommu-cells = <1>; + status = "okay"; + }; + + vfe_smmu: iommu@da0000 { + compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; + reg = <0x00da0000 0x10000>; + + #global-interrupts = <1>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; + clocks = <&mmcc SMMU_VFE_AXI_CLK>, + <&mmcc SMMU_VFE_AHB_CLK>; + clock-names = "bus", "iface"; + #iommu-cells = <1>; + }; + + lpass_q6_smmu: iommu@1600000 { + compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; + reg = <0x01600000 0x20000>; + #iommu-cells = <1>; + power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; + + #global-interrupts = <1>; + interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>, + <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>; + clock-names = "bus", "iface"; + }; + + slpi_pil: remoteproc@1c00000 { + compatible = "qcom,msm8996-slpi-pil"; + reg = <0x01c00000 0x4000>; + + interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&xo_board>, + <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; + clock-names = "xo", "aggre2"; + + memory-region = <&slpi_mem>; + + qcom,smem-states = <&slpi_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + power-domains = <&rpmpd MSM8996_VDDSSCX>; + power-domain-names = "ssc_cx"; + + status = "disabled"; + + smd-edge { + interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; + + label = "dsps"; + mboxes = <&apcs_glb 25>; + qcom,smd-edge = <3>; + qcom,remote-pid = <3>; + }; + }; + + mss_pil: remoteproc@2080000 { + compatible = "qcom,msm8996-mss-pil"; + reg = <0x2080000 0x100>, + <0x2180000 0x020>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, + <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", + "shutdown-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&xo_board>, + <&gcc GCC_MSS_GPLL0_DIV_CLK>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, + <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "iface", "bus", "mem", "xo", "gpll0_mss", + "snoc_axi", "mnoc_axi", "pnoc", "qdss"; + + resets = <&gcc GCC_MSS_RESTART>; + reset-names = "mss_restart"; + + power-domains = <&rpmpd MSM8996_VDDCX>, + <&rpmpd MSM8996_VDDMX>; + power-domain-names = "cx", "mx"; + + qcom,smem-states = <&mpss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>; + + status = "disabled"; + + mba { + memory-region = <&mba_mem>; + }; + + mpss { + memory-region = <&mpss_mem>; + }; + + metadata { + memory-region = <&mdata_mem>; + }; + + smd-edge { + interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; + + label = "mpss"; + mboxes = <&apcs_glb 12>; + qcom,smd-edge = <0>; + qcom,remote-pid = <1>; + }; + }; + + stm@3002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x3002000 0x1000>, + <0x8280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = + <&funnel0_in>; + }; + }; + }; + }; + + tpiu@3020000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x3020000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + tpiu_in: endpoint { + remote-endpoint = + <&replicator_out1>; + }; + }; + }; + }; + + funnel@3021000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x3021000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel0_in: endpoint { + remote-endpoint = + <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = + <&merge_funnel_in0>; + }; + }; + }; + }; + + funnel@3022000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x3022000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + funnel1_in: endpoint { + remote-endpoint = + <&apss_merge_funnel_out>; + }; + }; + }; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = + <&merge_funnel_in1>; + }; + }; + }; + }; + + funnel@3023000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x3023000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + + out-ports { + port { + funnel2_out: endpoint { + remote-endpoint = + <&merge_funnel_in2>; + }; + }; + }; + }; + + funnel@3025000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x3025000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = + <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + merge_funnel_in1: endpoint { + remote-endpoint = + <&funnel1_out>; + }; + }; + + port@2 { + reg = <2>; + merge_funnel_in2: endpoint { + remote-endpoint = + <&funnel2_out>; + }; + }; + }; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = + <&etf_in>; + }; + }; + }; + }; + + replicator@3026000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x3026000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = + <&etf_out>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = + <&etr_in>; + }; + }; + + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = + <&tpiu_in>; + }; + }; + }; + }; + + etf@3027000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x3027000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = + <&merge_funnel_out>; + }; + }; + }; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = + <&replicator_in>; + }; + }; + }; + }; + + etr@3028000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x3028000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = + <&replicator_out0>; + }; + }; + }; + }; + + debug@3810000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x3810000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU0>; + }; + + etm@3840000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x3840000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU0>; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&apss_funnel0_in0>; + }; + }; + }; + }; + + debug@3910000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x3910000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + }; + + etm@3940000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x3940000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU1>; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&apss_funnel0_in1>; + }; + }; + }; + }; + + funnel@39b0000 { /* APSS Funnel 0 */ + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x39b0000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel0_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel0_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + }; + + out-ports { + port { + apss_funnel0_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in0>; + }; + }; + }; + }; + + debug@3a10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x3a10000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU2>; + }; + + etm@3a40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x3a40000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU2>; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&apss_funnel1_in0>; + }; + }; + }; + }; + + debug@3b10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x3b10000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU3>; + }; + + etm@3b40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x3b40000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU3>; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&apss_funnel1_in1>; + }; + }; + }; + }; + + funnel@3bb0000 { /* APSS Funnel 1 */ + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x3bb0000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel1_in0: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel1_in1: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + + out-ports { + port { + apss_funnel1_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in1>; + }; + }; + }; + }; + + funnel@3bc0000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x3bc0000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_merge_funnel_in0: endpoint { + remote-endpoint = + <&apss_funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_merge_funnel_in1: endpoint { + remote-endpoint = + <&apss_funnel1_out>; + }; + }; + }; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = + <&funnel1_in>; + }; + }; + }; + }; + + kryocc: clock-controller@6400000 { + compatible = "qcom,msm8996-apcc"; + reg = <0x06400000 0x90000>; + + clock-names = "xo", "sys_apcs_aux"; + clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; + + #clock-cells = <1>; + }; + + usb3: usb@6af8800 { + compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; + reg = <0x06af8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "ss_phy_irq"; + + clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_AGGRE2_USB3_AXI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <120000000>; + + interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; + interconnect-names = "usb-ddr", "apps-usb"; + + power-domains = <&gcc USB30_GDSC>; + status = "disabled"; + + usb3_dwc3: usb@6a00000 { + compatible = "snps,dwc3"; + reg = <0x06a00000 0xcc00>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + phys = <&hsusb_phy1>, <&ssusb_phy_0>; + phy-names = "usb2-phy", "usb3-phy"; + snps,hird-threshold = /bits/ 8 <0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,is-utmi-l1-suspend; + tx-fifo-resize; + }; + }; + + usb3phy: phy@7410000 { + compatible = "qcom,msm8996-qmp-usb3-phy"; + reg = <0x07410000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_CLKREF_CLK>; + clock-names = "aux", "cfg_ahb", "ref"; + + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy", "common"; + status = "disabled"; + + ssusb_phy_0: phy@7410200 { + reg = <0x07410200 0x200>, + <0x07410400 0x130>, + <0x07410600 0x1a8>; + #phy-cells = <0>; + + #clock-cells = <0>; + clock-output-names = "usb3_phy_pipe_clk_src"; + clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "pipe0"; + }; + }; + + hsusb_phy1: phy@7411000 { + compatible = "qcom,msm8996-qusb2-phy"; + reg = <0x07411000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_RX1_USB2_CLKREF_CLK>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2p_hstx_trim>; + status = "disabled"; + }; + + hsusb_phy2: phy@7412000 { + compatible = "qcom,msm8996-qusb2-phy"; + reg = <0x07412000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_RX2_USB2_CLKREF_CLK>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + nvmem-cells = <&qusb2s_hstx_trim>; + status = "disabled"; + }; + + sdhc1: mmc@7464900 { + compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x07464900 0x11c>, <0x07464000 0x800>; + reg-names = "hc", "core"; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clock-names = "iface", "core", "xo"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + resets = <&gcc GCC_SDCC1_BCR>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + + bus-width = <8>; + non-removable; + status = "disabled"; + }; + + sdhc2: mmc@74a4900 { + compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x074a4900 0x314>, <0x074a4000 0x800>; + reg-names = "hc", "core"; + + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clock-names = "iface", "core", "xo"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + resets = <&gcc GCC_SDCC2_BCR>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_state_on>; + pinctrl-1 = <&sdc2_state_off>; + + bus-width = <4>; + status = "disabled"; + }; + + blsp1_dma: dma-controller@7544000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07544000 0x2b000>; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + qcom,controlled-remotely; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + blsp1_uart2: serial@7570000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x07570000 0x1000>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; + dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_spi1: spi@7575000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07575000 0x600>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_spi1_default>; + pinctrl-1 = <&blsp1_spi1_sleep>; + dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c3: i2c@7577000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x07577000 0x1000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c3_default>; + pinctrl-1 = <&blsp1_i2c3_sleep>; + dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c6: i2c@757a000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x757a000 0x1000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c6_default>; + pinctrl-1 = <&blsp1_i2c6_sleep>; + dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_dma: dma-controller@7584000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07584000 0x2b000>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + qcom,controlled-remotely; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + blsp2_uart2: serial@75b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x075b0000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp2_uart3: serial@75b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x075b1000 0x1000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp2_i2c1: i2c@75b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x075b5000 0x1000>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c1_default>; + pinctrl-1 = <&blsp2_i2c1_sleep>; + dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_i2c2: i2c@75b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x075b6000 0x1000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c2_default>; + pinctrl-1 = <&blsp2_i2c2_sleep>; + dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_i2c3: i2c@75b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x075b7000 0x1000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c3_default>; + pinctrl-1 = <&blsp2_i2c3_sleep>; + dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_i2c5: i2c@75b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x75b9000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_i2c5_default>; + dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_i2c6: i2c@75ba000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x75ba000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c6_default>; + pinctrl-1 = <&blsp2_i2c6_sleep>; + dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_spi6: spi@75ba000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x075ba000 0x600>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_spi6_default>; + pinctrl-1 = <&blsp2_spi6_sleep>; + dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usb2: usb@76f8800 { + compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; + reg = <0x076f8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq"; + + clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <60000000>; + + power-domains = <&gcc USB30_GDSC>; + qcom,select-utmi-as-pipe-clk; + status = "disabled"; + + usb2_dwc3: usb@7600000 { + compatible = "snps,dwc3"; + reg = <0x07600000 0xcc00>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + phys = <&hsusb_phy2>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + }; + }; + + slimbam: dma-controller@9184000 { + compatible = "qcom,bam-v1.7.0"; + qcom,controlled-remotely; + reg = <0x09184000 0x32000>; + num-channels = <31>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <1>; + qcom,num-ees = <2>; + }; + + slim_msm: slim-ngd@91c0000 { + compatible = "qcom,slim-ngd-v1.5.0"; + reg = <0x091c0000 0x2c000>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&slimbam 3>, <&slimbam 4>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + adsp_pil: remoteproc@9300000 { + compatible = "qcom,msm8996-adsp-pil"; + reg = <0x09300000 0x80000>; + + interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + memory-region = <&adsp_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + power-domains = <&rpmpd MSM8996_VDDCX>; + power-domain-names = "cx"; + + status = "disabled"; + + smd-edge { + interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; + + label = "lpass"; + mboxes = <&apcs_glb 8>; + qcom,smd-edge = <1>; + qcom,remote-pid = <2>; + + apr { + power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; + compatible = "qcom,apr-v2"; + qcom,smd-channels = "apr_audio_svc"; + qcom,domain = <APR_DOMAIN_ADSP>; + #address-cells = <1>; + #size-cells = <0>; + + service@3 { + reg = <APR_SVC_ADSP_CORE>; + compatible = "qcom,q6core"; + }; + + q6afe: service@4 { + compatible = "qcom,q6afe"; + reg = <APR_SVC_AFE>; + q6afedai: dais { + compatible = "qcom,q6afe-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + dai@1 { + reg = <1>; + }; + }; + }; + + q6asm: service@7 { + compatible = "qcom,q6asm"; + reg = <APR_SVC_ASM>; + q6asmdai: dais { + compatible = "qcom,q6asm-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + iommus = <&lpass_q6_smmu 1>; + }; + }; + + q6adm: service@8 { + compatible = "qcom,q6adm"; + reg = <APR_SVC_ADM>; + q6routing: routing { + compatible = "qcom,q6adm-routing"; + #sound-dai-cells = <0>; + }; + }; + }; + }; + }; + + apcs_glb: mailbox@9820000 { + compatible = "qcom,msm8996-apcs-hmss-global"; + reg = <0x09820000 0x1000>; + + #mbox-cells = <1>; + #clock-cells = <0>; + }; + + timer@9840000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x09840000 0x1000>; + clock-frequency = <19200000>; + + frame@9850000 { + frame-number = <0>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x09850000 0x1000>, + <0x09860000 0x1000>; + }; + + frame@9870000 { + frame-number = <1>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x09870000 0x1000>; + status = "disabled"; + }; + + frame@9880000 { + frame-number = <2>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x09880000 0x1000>; + status = "disabled"; + }; + + frame@9890000 { + frame-number = <3>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x09890000 0x1000>; + status = "disabled"; + }; + + frame@98a0000 { + frame-number = <4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x098a0000 0x1000>; + status = "disabled"; + }; + + frame@98b0000 { + frame-number = <5>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x098b0000 0x1000>; + status = "disabled"; + }; + + frame@98c0000 { + frame-number = <6>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x098c0000 0x1000>; + status = "disabled"; + }; + }; + + saw3: syscon@9a10000 { + compatible = "syscon"; + reg = <0x09a10000 0x1000>; + }; + + cbf: clock-controller@9a11000 { + compatible = "qcom,msm8996-cbf"; + reg = <0x09a11000 0x10000>; + clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; + #clock-cells = <0>; + #interconnect-cells = <1>; + }; + + intc: interrupt-controller@9bc0000 { + compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + reg = <0x09bc0000 0x10000>, + <0x09c00000 0x100000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + sound: sound { + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 5>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 8>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 10>; + + trips { + cpu3_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: cpu-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 6>; + + trips { + gpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-bottom-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 7>; + + trips { + gpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu2_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + m4m-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 1>; + + trips { + m4m_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + l3-or-venus-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 2>; + + trips { + l3_or_venus_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + cluster0-l2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 7>; + + trips { + cluster0_l2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + cluster1-l2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 12>; + + trips { + cluster1_l2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 1>; + + trips { + camera_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + q6-dsp-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 2>; + + trips { + q6_dsp_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 3>; + + trips { + mem_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + modemtx-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 4>; + + trips { + modemtx_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; +}; diff --git a/arch/arm/dts/mt7988-sd-rfb.dts b/arch/arm/dts/mt7988-sd-rfb.dts index a3df37d252d..9aa198b84ab 100644 --- a/arch/arm/dts/mt7988-sd-rfb.dts +++ b/arch/arm/dts/mt7988-sd-rfb.dts @@ -87,10 +87,12 @@ pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI", "SPI2_CLK", "SPI2_HOLD"; input-enable; + drive-strength = <MTK_DRIVE_4mA>; }; conf-clk { pins = "SPI2_WP"; + drive-strength = <MTK_DRIVE_4mA>; }; }; }; diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi index ac476d5cdd7..5c0c5bcfd6e 100644 --- a/arch/arm/dts/mt7988.dtsi +++ b/arch/arm/dts/mt7988.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/clock/mt7988-clk.h> #include <dt-bindings/reset/mt7988-reset.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/mt65xx.h> #include <dt-bindings/phy/phy.h> / { diff --git a/arch/arm/dts/pm8916.dtsi b/arch/arm/dts/pm8916.dtsi new file mode 100644 index 00000000000..f4de8678774 --- /dev/null +++ b/arch/arm/dts/pm8916.dtsi @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/iio/qcom,spmi-vadc.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +&spmi_bus { + + pm8916_0: pmic@0 { + compatible = "qcom,pm8916", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pon@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = <KEY_POWER>; + }; + + pm8916_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + status = "disabled"; + }; + + watchdog { + compatible = "qcom,pm8916-wdt"; + interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>; + timeout-sec = <60>; + }; + }; + + pm8916_usbin: usb-detect@1300 { + compatible = "qcom,pm8941-misc"; + reg = <0x1300>; + interrupts = <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "usb_vbus"; + status = "disabled"; + }; + + pm8916_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8916_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm8916_vadc: adc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@0 { + reg = <VADC_USBIN>; + qcom,pre-scaling = <1 10>; + }; + channel@7 { + reg = <VADC_VSYS>; + qcom,pre-scaling = <1 3>; + }; + channel@8 { + reg = <VADC_DIE_TEMP>; + }; + channel@9 { + reg = <VADC_REF_625MV>; + }; + channel@a { + reg = <VADC_REF_1250MV>; + }; + channel@e { + reg = <VADC_GND_REF>; + }; + channel@f { + reg = <VADC_VDD_VADC>; + }; + }; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pm8916_mpps: mpps@a000 { + compatible = "qcom,pm8916-mpp", "qcom,spmi-mpp"; + reg = <0xa000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8916_mpps 0 0 4>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8916_gpios: gpio@c000 { + compatible = "qcom,pm8916-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm8916_gpios 0 0 4>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8916_1: pmic@1 { + compatible = "qcom,pm8916", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8916_pwm: pwm { + compatible = "qcom,pm8916-pwm"; + + #pwm-cells = <2>; + + status = "disabled"; + }; + + pm8916_vib: vibrator@c000 { + compatible = "qcom,pm8916-vib"; + reg = <0xc000>; + status = "disabled"; + }; + + pm8916_codec: audio-codec@f000 { + compatible = "qcom,pm8916-wcd-analog-codec"; + reg = <0xf000>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>, + <0x1 0xf0 0x1 IRQ_TYPE_NONE>, + <0x1 0xf0 0x2 IRQ_TYPE_NONE>, + <0x1 0xf0 0x3 IRQ_TYPE_NONE>, + <0x1 0xf0 0x4 IRQ_TYPE_NONE>, + <0x1 0xf0 0x5 IRQ_TYPE_NONE>, + <0x1 0xf0 0x6 IRQ_TYPE_NONE>, + <0x1 0xf0 0x7 IRQ_TYPE_NONE>, + <0x1 0xf1 0x0 IRQ_TYPE_NONE>, + <0x1 0xf1 0x1 IRQ_TYPE_NONE>, + <0x1 0xf1 0x2 IRQ_TYPE_NONE>, + <0x1 0xf1 0x3 IRQ_TYPE_NONE>, + <0x1 0xf1 0x4 IRQ_TYPE_NONE>, + <0x1 0xf1 0x5 IRQ_TYPE_NONE>; + interrupt-names = "cdc_spk_cnp_int", + "cdc_spk_clip_int", + "cdc_spk_ocp_int", + "mbhc_ins_rem_det1", + "mbhc_but_rel_det", + "mbhc_but_press_det", + "mbhc_ins_rem_det", + "mbhc_switch_int", + "cdc_ear_ocp_int", + "cdc_hphr_ocp_int", + "cdc_hphl_ocp_det", + "cdc_ear_cnp_int", + "cdc_hphr_cnp_int", + "cdc_hphl_cnp_int"; + #sound-dai-cells = <1>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/pm8994.dtsi b/arch/arm/dts/pm8994.dtsi new file mode 100644 index 00000000000..d44a95caf04 --- /dev/null +++ b/arch/arm/dts/pm8994.dtsi @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/iio/qcom,spmi-vadc.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pm8994-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&pm8994_temp>; + + trips { + pm8994_alert0: pm8994-alert0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + pm8994_crit: pm8994-crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + + pmic@0 { + compatible = "qcom,pm8994", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pm8994_pon: pon@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = <KEY_POWER>; + }; + + pm8994_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + status = "disabled"; + }; + }; + + pm8994_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8994_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm8994_vadc: adc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@7 { + reg = <VADC_VSYS>; + qcom,pre-scaling = <1 3>; + label = "vph_pwr"; + }; + channel@8 { + reg = <VADC_DIE_TEMP>; + label = "die_temp"; + }; + channel@9 { + reg = <VADC_REF_625MV>; + label = "ref_625mv"; + }; + channel@a { + reg = <VADC_REF_1250MV>; + label = "ref_1250mv"; + }; + channel@e { + reg = <VADC_GND_REF>; + }; + channel@f { + reg = <VADC_VDD_VADC>; + }; + }; + + pm8994_gpios: gpio@c000 { + compatible = "qcom,pm8994-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm8994_gpios 0 0 22>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8994_mpps: mpps@a000 { + compatible = "qcom,pm8994-mpp", "qcom,spmi-mpp"; + reg = <0xa000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8994_mpps 0 0 8>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@1 { + compatible = "qcom,pm8994", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8994_lpg: pwm { + compatible = "qcom,pm8994-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + + pm8994_spmi_regulators: regulators { + compatible = "qcom,pm8994-regulators"; + }; + }; +}; diff --git a/arch/arm/dts/pm8998.dtsi b/arch/arm/dts/pm8998.dtsi new file mode 100644 index 00000000000..3f82715392c --- /dev/null +++ b/arch/arm/dts/pm8998.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* Copyright 2018 Google LLC. */ + +#include <dt-bindings/iio/qcom,spmi-vadc.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + thermal-zones { + pm8998-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&pm8998_temp>; + + trips { + pm8998_alert0: pm8998-alert0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + pm8998_crit: pm8998-crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pm8998_lsid0: pmic@0 { + compatible = "qcom,pm8998", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8998_pon: pon@800 { + compatible = "qcom,pm8998-pon"; + + reg = <0x800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; + + pm8998_pwrkey: pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = <KEY_POWER>; + }; + + pm8998_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + status = "disabled"; + }; + }; + + pm8998_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8998_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm8998_coincell: charger@2800 { + compatible = "qcom,pm8998-coincell", "qcom,pm8941-coincell"; + reg = <0x2800>; + + status = "disabled"; + }; + + pm8998_adc: adc@3100 { + compatible = "qcom,spmi-adc-rev2"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@6 { + reg = <ADC5_DIE_TEMP>; + label = "die_temp"; + }; + }; + + pm8998_adc_tm: adc-tm@3400 { + compatible = "qcom,spmi-adc-tm-hc"; + reg = <0x3400>; + interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pm8998_gpios: gpio@c000 { + compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm8998_gpios 0 0 26>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + pm8998_lsid1: pmic@1 { + compatible = "qcom,pm8998", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm/dts/pmi8994.dtsi b/arch/arm/dts/pmi8994.dtsi new file mode 100644 index 00000000000..36d6a1fb553 --- /dev/null +++ b/arch/arm/dts/pmi8994.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +&spmi_bus { + + pmic@2 { + compatible = "qcom,pmi8994", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmi8994_gpios: gpio@c000 { + compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pmi8994_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmi8994_mpps: mpps@a000 { + compatible = "qcom,pmi8994-mpp", "qcom,spmi-mpp"; + reg = <0xa000>; + gpio-controller; + gpio-ranges = <&pmi8994_mpps 0 0 4>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@3 { + compatible = "qcom,pmi8994", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmi8994_lpg: pwm { + compatible = "qcom,pmi8994-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + + pmi8994_spmi_regulators: regulators { + compatible = "qcom,pmi8994-regulators"; + }; + + pmi8994_wled: wled@d800 { + compatible = "qcom,pmi8994-wled"; + reg = <0xd800>, <0xd900>; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp", "short"; + qcom,cabc; + qcom,external-pfet; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/pmi8998.dtsi b/arch/arm/dts/pmi8998.dtsi new file mode 100644 index 00000000000..cd3f0790fd4 --- /dev/null +++ b/arch/arm/dts/pmi8998.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +&spmi_bus { + pmi8998_lsid0: pmic@2 { + compatible = "qcom,pmi8998", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmi8998_charger: charger@1000 { + compatible = "qcom,pmi8998-charger"; + reg = <0x1000>; + + interrupts = <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "usb-plugin", + "bat-ov", + "wdog-bark", + "usbin-icl-change"; + + io-channels = <&pmi8998_rradc 3>, + <&pmi8998_rradc 4>; + io-channel-names = "usbin_i", "usbin_v"; + + status = "disabled"; + }; + + pmi8998_gpios: gpio@c000 { + compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pmi8998_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmi8998_rradc: adc@4500 { + compatible = "qcom,pmi8998-rradc"; + reg = <0x4500>; + #io-channel-cells = <1>; + }; + }; + + pmi8998_lsid1: pmic@3 { + compatible = "qcom,pmi8998", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + labibb { + compatible = "qcom,pmi8998-lab-ibb"; + + ibb: ibb { + interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>, + <0x3 0xdc 0x0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sc-err", "ocp"; + }; + + lab: lab { + interrupts = <0x3 0xde 0x1 IRQ_TYPE_EDGE_RISING>, + <0x3 0xde 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sc-err", "ocp"; + }; + }; + + pmi8998_lpg: pwm { + compatible = "qcom,pmi8998-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + + pmi8998_flash: led-controller@d300 { + compatible = "qcom,pmi8998-flash-led", "qcom,spmi-flash-led"; + reg = <0xd300>; + status = "disabled"; + }; + + pmi8998_wled: leds@d800 { + compatible = "qcom,pmi8998-wled"; + reg = <0xd800>, <0xd900>; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp", "short"; + label = "backlight"; + + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/pms405.dtsi b/arch/arm/dts/pms405.dtsi new file mode 100644 index 00000000000..461ad97032f --- /dev/null +++ b/arch/arm/dts/pms405.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, Linaro Limited + */ + +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/iio/qcom,spmi-vadc.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + thermal-zones { + pms405-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&pms405_temp>; + + trips { + pms405_alert0: pms405-alert0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + pms405_crit: pms405-crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pms405_0: pms405@0 { + compatible = "qcom,pms405", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pms405_gpios: gpio@c000 { + compatible = "qcom,pms405-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pms405_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pon@800 { + compatible = "qcom,pms405-pon"; + reg = <0x0800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = <KEY_POWER>; + }; + }; + + pms405_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pms405_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pms405_adc: adc@3100 { + compatible = "qcom,pms405-adc", "qcom,spmi-adc-rev2"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@0 { + reg = <ADC5_REF_GND>; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + channel@1 { + reg = <ADC5_1P25VREF>; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + channel@131 { + reg = <ADC5_VPH_PWR>; + qcom,pre-scaling = <1 3>; + label = "vph_pwr"; + }; + + channel@6 { + reg = <ADC5_DIE_TEMP>; + qcom,pre-scaling = <1 1>; + label = "die_temp"; + }; + + channel@77 { + reg = <ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pa_therm1"; + }; + + channel@79 { + reg = <ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pa_therm3"; + }; + + channel@76 { + reg = <ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "xo_therm"; + }; + }; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + + pms405_1: pms405@1 { + compatible = "qcom,pms405", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + + pms405_spmi_regulators: regulators { + compatible = "qcom,pms405-regulators"; + }; + }; +}; diff --git a/arch/arm/dts/qcs404-evb-4000-u-boot.dtsi b/arch/arm/dts/qcs404-evb-4000-u-boot.dtsi new file mode 100644 index 00000000000..d3033ea42ec --- /dev/null +++ b/arch/arm/dts/qcs404-evb-4000-u-boot.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <dt-bindings/gpio/gpio.h> + +/delete-node/ &usb3_vbus_reg; +/delete-node/ &usb_vbus_boost_pin; + +/ { + /* U-Boot uses different bindings for GPIO regulators, this + * one is required for USB + */ + usb3_vbus_reg: usb3_vbus_reg { + compatible = "regulator-gpio"; + regulator-name = "usb3_vbus_reg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-gpios = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + states = <0 0>, <5000000 1>; + }; +}; + +&blsp1_uart2 { + /* This defines the bit clock divider which defines the baud rate. + * 0xFF is a divider of 16 for both the RX and TX lines. The QCS404 + * clock driver in U-Boot hardcodes a 1843200Hz frequency for the + * UART core clock, and 1843200 / 16 = 115200. + */ + bit-rate = <0xFF>; +}; + +&gcc { + /* The clock framework in U-Boot "sort of" has the idea of linking an + * individual clock to a device via uclass_priv. However the qcom clock + * driver instead associates many clocks with a single device. This is + * usually fine but it seems that assigned-clocks wreak havoc on this + * and we wind up having a reference to the XO clock which is associated + * with the qcom_clk device... + * For now we'll just remove these properties, no other board has these. + */ + /delete-property/ assigned-clock-rates; + /delete-property/ assigned-clocks; +}; + +&usb3_dwc3 { + /* Make sure the VBUS supply is switched on */ + vbus-supply = <&usb3_vbus_reg>; +}; diff --git a/arch/arm/dts/qcs404-evb-4000.dts b/arch/arm/dts/qcs404-evb-4000.dts new file mode 100644 index 00000000000..358827c2fbd --- /dev/null +++ b/arch/arm/dts/qcs404-evb-4000.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, Linaro Limited + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "qcs404-evb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS404 EVB 4000"; + compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb", + "qcom,qcs404"; +}; + +ðernet { + status = "okay"; + + snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 10000>; + + pinctrl-names = "default"; + pinctrl-0 = <ðernet_defaults>; + + phy-handle = <&phy1>; + phy-mode = "rgmii"; + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1: phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + device_type = "ethernet-phy"; + reg = <0x4>; + }; + }; +}; + +&tlmm { + ethernet_defaults: ethernet-defaults-state { + int-pins { + pins = "gpio61"; + function = "rgmii_int"; + bias-disable; + drive-strength = <2>; + }; + mdc-pins { + pins = "gpio76"; + function = "rgmii_mdc"; + bias-pull-up; + }; + mdio-pins { + pins = "gpio75"; + function = "rgmii_mdio"; + bias-pull-up; + }; + tx-pins { + pins = "gpio67", "gpio66", "gpio65", "gpio64"; + function = "rgmii_tx"; + bias-pull-up; + drive-strength = <16>; + }; + rx-pins { + pins = "gpio73", "gpio72", "gpio71", "gpio70"; + function = "rgmii_rx"; + bias-disable; + drive-strength = <2>; + }; + tx-ctl-pins { + pins = "gpio68"; + function = "rgmii_ctl"; + bias-pull-up; + drive-strength = <16>; + }; + rx-ctl-pins { + pins = "gpio74"; + function = "rgmii_ctl"; + bias-disable; + drive-strength = <2>; + }; + tx-ck-pins { + pins = "gpio63"; + function = "rgmii_ck"; + bias-pull-up; + drive-strength = <16>; + }; + rx-ck-pins { + pins = "gpio69"; + function = "rgmii_ck"; + bias-disable; + drive-strength = <2>; + }; + }; +}; diff --git a/arch/arm/dts/qcs404-evb-uboot.dtsi b/arch/arm/dts/qcs404-evb-uboot.dtsi deleted file mode 100644 index b4c5f3fa430..00000000000 --- a/arch/arm/dts/qcs404-evb-uboot.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * U-Boot addition to handle QCS404 EVB pre-relocation devices - * - * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org> - */ - -/ { - soc { - bootph-all; - - pinctrl_north@1300000 { - bootph-all; - }; - - clock-controller@1800000 { - bootph-all; - }; - - serial@78b1000 { - bootph-all; - }; - }; -}; - -&pms405_gpios { - usb_vbus_boost_pin { - gpios = <&pms405_gpios 2 0>; - }; -}; diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts deleted file mode 100644 index 07bf7dd0b32..00000000000 --- a/arch/arm/dts/qcs404-evb.dts +++ /dev/null @@ -1,390 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Qualcomm QCS404 based evaluation board device tree source - * - * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org> - */ - -/dts-v1/; - -#include "skeleton64.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/clock/qcom,gcc-qcs404.h> - -/ { - model = "Qualcomm Technologies, Inc. QCS404 EVB"; - compatible = "qcom,qcs404-evb", "qcom,qcs404"; - #address-cells = <0x2>; - #size-cells = <0x2>; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &debug_uart; - i2c0 = &blsp1_i2c0; - i2c1 = &blsp1_i2c1; - i2c2 = &blsp1_i2c2; - i2c3 = &blsp1_i2c3; - i2c4 = &blsp1_i2c4; - }; - - memory { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - soc { - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges = <0x0 0x0 0x0 0xffffffff>; - compatible = "simple-bus"; - - soc_gpios: pinctrl_north@1300000 { - compatible = "qcom,qcs404-pinctrl"; - reg = <0x1300000 0x200000>; - gpio-controller; - gpio-count = <120>; - gpio-bank-name="soc"; - #gpio-cells = <2>; - - blsp1_uart2: uart { - pins = "GPIO_17", "GPIO_18"; - function = "blsp_uart2"; - }; - - blsp1_i2c0_default: blsp1-i2c0-default { - pins = "GPIO_32", "GPIO_33"; - function = "blsp_i2c0"; - }; - - blsp1_i2c1_default: blsp1-i2c1-default { - pins = "GPIO_24", "GPIO_25"; - function = "blsp_i2c1"; - }; - - blsp1_i2c2_default: blsp1-i2c2-default { - sda { - pins = "GPIO_19"; - function = "blsp_i2c_sda_a2"; - }; - - scl { - pins = "GPIO_20"; - function = "blsp_i2c_scl_a2"; - }; - }; - - blsp1_i2c3_default: blsp1-i2c3-default { - pins = "GPIO_84", "GPIO_85"; - function = "blsp_i2c3"; - }; - - blsp1_i2c4_default: blsp1-i2c4-default { - pins = "GPIO_117", "GPIO_118"; - function = "blsp_i2c4"; - }; - - ethernet_defaults: ethernet-defaults { - int { - pins = "GPIO_61"; - function = "rgmii_int"; - bias-disable; - drive-strength = <2>; - }; - mdc { - pins = "GPIO_76"; - function = "rgmii_mdc"; - bias-pull-up; - }; - mdio { - pins = "GPIO_75"; - function = "rgmii_mdio"; - bias-pull-up; - }; - tx { - pins = "GPIO_67", "GPIO_66", "GPIO_65", "GPIO_64"; - function = "rgmii_tx"; - bias-pull-up; - drive-strength = <16>; - }; - rx { - pins = "GPIO_73", "GPIO_72", "GPIO_71", "GPIO_70"; - function = "rgmii_rx"; - bias-disable; - drive-strength = <2>; - }; - tx-ctl { - pins = "GPIO_68"; - function = "rgmii_ctl"; - bias-pull-up; - drive-strength = <16>; - }; - rx-ctl { - pins = "GPIO_74"; - function = "rgmii_ctl"; - bias-disable; - drive-strength = <2>; - }; - tx-ck { - pins = "GPIO_63"; - function = "rgmii_ck"; - bias-pull-up; - drive-strength = <16>; - }; - rx-ck { - pins = "GPIO_69"; - function = "rgmii_ck"; - bias-disable; - drive-strength = <2>; - }; - }; - }; - - blsp1_i2c0: i2c@78b5000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b5000 0x600>; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c0_default>; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c1: i2c@78b6000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b6000 0x600>; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c1_default>; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c2: i2c@78b7000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b7000 0x600>; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c2_default>; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c3: i2c@78b8000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b8000 0x600>; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c3_default>; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c4: i2c@78b9000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b9000 0x600>; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c4_default>; - #address-cells = <1>; - #size-cells = <0>; - }; - - gcc: clock-controller@1800000 { - compatible = "qcom,gcc-qcs404"; - reg = <0x1800000 0x80000>; - #address-cells = <0x1>; - #size-cells = <0x0>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - debug_uart: serial@78b1000 { - compatible = "qcom,msm-uartdm-v1.4"; - reg = <0x78b1000 0x200>; - clock = <&gcc GCC_BLSP1_UART2_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - bit-rate = <0xFF>; - pinctrl-names = "uart"; - pinctrl-0 = <&blsp1_uart2>; - }; - - sdhci@7804000 { - compatible = "qcom,sdhci-msm-v5"; - reg = <0x7804000 0x1000 0x7805000 0x1000>; - clock = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>; - bus-width = <0x8>; - index = <0x0>; - non-removable; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - }; - - usb3_phy: phy@78000 { - compatible = "qcom,usb-ss-28nm-phy"; - #phy-cells = <0>; - reg = <0x78000 0x400>; - clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, - <&gcc GCC_USB3_PHY_PIPE_CLK>; - clock-names = "ahb", "pipe"; - resets = <&gcc GCC_USB3_PHY_BCR>, - <&gcc GCC_USB3PHY_PHY_BCR>; - reset-names = "com", "phy"; - }; - - usb2_phy_prim: phy@7a000 { - compatible = "qcom,usb-hs-28nm-femtophy"; - #phy-cells = <0>; - reg = <0x7a000 0x200>; - clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, - <&gcc GCC_USB2A_PHY_SLEEP_CLK>; - clock-names = "ahb", "sleep"; - resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, - <&gcc GCC_USB2A_PHY_BCR>; - reset-names = "phy", "por"; - }; - - usb2_phy_sec: phy@7c000 { - compatible = "qcom,usb-hs-28nm-femtophy"; - #phy-cells = <0>; - reg = <0x7c000 0x200>; - clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, - <&gcc GCC_USB2A_PHY_SLEEP_CLK>; - clock-names = "ahb", "sleep"; - resets = <&gcc GCC_QUSB2_PHY_BCR>, - <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; - reset-names = "phy", "por"; - }; - - usb3: usb@7678800 { - compatible = "qcom,dwc3"; - reg = <0x7678800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - clocks = <&gcc GCC_USB30_MASTER_CLK>, - <&gcc GCC_SYS_NOC_USB3_CLK>, - <&gcc GCC_USB30_SLEEP_CLK>, - <&gcc GCC_USB30_MOCK_UTMI_CLK>; - clock-names = "core", "iface", "sleep", "mock_utmi"; - - dwc3@7580000 { - compatible = "snps,dwc3"; - reg = <0x7580000 0xcd00>; - phys = <&usb2_phy_prim>, <&usb3_phy>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "host"; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - snps,usb3_lpm_capable; - maximum-speed = "super-speed"; - }; - }; - - usb2: usb@79b8800 { - compatible = "qcom,dwc3"; - reg = <0x79b8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, - <&gcc GCC_PCNOC_USB2_CLK>, - <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, - <&gcc GCC_USB20_MOCK_UTMI_CLK>; - clock-names = "core", "iface", "sleep", "mock_utmi"; - - dwc3@78c0000 { - compatible = "snps,dwc3"; - reg = <0x78c0000 0xcc00>; - phys = <&usb2_phy_sec>; - phy-names = "usb2-phy"; - dr_mode = "peripheral"; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - snps,usb3_lpm_capable; - maximum-speed = "high-speed"; - }; - }; - - ethernet: ethernet@7a80000 { - compatible = "qcom,qcs404-ethqos"; - reg = <0x07a80000 0x10000>, - <0x07a96000 0x100>; - reg-names = "stmmaceth", "rgmii"; - clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; - clocks = <&gcc GCC_ETH_AXI_CLK>, - <&gcc GCC_ETH_SLAVE_AHB_CLK>, - <&gcc GCC_ETH_PTP_CLK>, - <&gcc GCC_ETH_RGMII_CLK>; - - resets = <&gcc GCC_EMAC_BCR>; - reset-names = "emac"; - - snps,tso; - rx-fifo-depth = <4096>; - tx-fifo-depth = <4096>; - - snps,reset-gpio = <&soc_gpios 60 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - - pinctrl-names = "default"; - pinctrl-0 = <ðernet_defaults>; - - phy-handle = <&phy1>; - phy-mode = "rgmii"; - max-speed = <1000>; - - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - compatible = "snps,dwmac-mdio"; - phy1: phy@3 { - compatible = "ethernet-phy-ieee802.3-c22"; - device_type = "ethernet-phy"; - reg = <0x3>; - }; - }; - }; - - spmi@200f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x200f000 0x001000>, - <0x2400000 0x800000>, - <0x2c00000 0x800000>; - reg-names = "core", "chnls", "obsrvr"; - #address-cells = <0x1>; - #size-cells = <0x1>; - - pms405_0: pms405@0 { - compatible = "qcom,spmi-pmic"; - reg = <0x0 0x1>; - #address-cells = <0x1>; - #size-cells = <0x1>; - - pms405_gpios: pms405_gpios@c000 { - compatible = "qcom,pms405-gpio"; - reg = <0xc000 0x400>; - gpio-controller; - gpio-ranges = <&pms405_gpios 0 0 12>; - #gpio-cells = <2>; - }; - }; - }; - }; -}; - -#include "qcs404-evb-uboot.dtsi" diff --git a/arch/arm/dts/qcs404-evb.dtsi b/arch/arm/dts/qcs404-evb.dtsi new file mode 100644 index 00000000000..10655401528 --- /dev/null +++ b/arch/arm/dts/qcs404-evb.dtsi @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, Linaro Limited + */ + +#include <dt-bindings/gpio/gpio.h> +#include "qcs404.dtsi" +#include "pms405.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +/ { + aliases { + serial0 = &blsp1_uart2; + serial1 = &blsp1_uart3; + }; + + chosen { + stdout-path = "serial0"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ch0_3p3: + vdd_esmps3_3p3: vdd-esmps3-3p3-regulator { + compatible = "regulator-fixed"; + regulator-name = "eSMPS3_3P3"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + usb3_vbus_reg: regulator-usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "VBUS_BOOST_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_vbus_boost_pin>; + vin-supply = <&vph_pwr>; + enable-active-high; + + /* TODO: Drop this when introducing role switching */ + regulator-always-on; + }; +}; + +&blsp1_uart3 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + vddio-supply = <&vreg_l6_1p8>; + vddxo-supply = <&vreg_l5_1p8>; + vddrf-supply = <&vreg_l1_1p3>; + vddch0-supply = <&vdd_ch0_3p3>; + + local-bd-address = [ 02 00 00 00 5a ad ]; + + max-speed = <3200000>; + }; +}; + +&blsp1_dma { + qcom,controlled-remotely; +}; + +&blsp2_dma { + qcom,controlled-remotely; +}; + +&gcc { + protected-clocks = <GCC_BIMC_CDSP_CLK>, + <GCC_CDSP_CFG_AHB_CLK>, + <GCC_CDSP_BIMC_CLK_SRC>, + <GCC_CDSP_TBU_CLK>, + <141>, /* GCC_WCSS_Q6_AHB_CLK */ + <142>; /* GCC_WCSS_Q6_AXIM_CLK */ +}; + +&pms405_spmi_regulators { + vdd_s3-supply = <&vph_pwr>; + + pms405_s3: s3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd_apc"; + regulator-initial-mode = <1>; + regulator-min-microvolt = <1048000>; + regulator-max-microvolt = <1384000>; + }; +}; + +&pcie { + status = "okay"; + + perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&perst_state>; +}; + +&pcie_phy { + status = "okay"; + + vdda-vp-supply = <&vreg_l3_1p05>; + vdda-vph-supply = <&vreg_l5_1p8>; +}; + +&remoteproc_adsp { + status = "okay"; +}; + +&remoteproc_cdsp { + status = "okay"; +}; + +&remoteproc_wcss { + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pms405-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_l1_l2-supply = <&vreg_s5_1p35>; + vdd_l3_l8-supply = <&vreg_s5_1p35>; + vdd_l4-supply = <&vreg_s5_1p35>; + vdd_l5_l6-supply = <&vreg_s4_1p8>; + vdd_l7-supply = <&vph_pwr>; + vdd_l9-supply = <&vreg_s5_1p35>; + vdd_l10_l11_l12_l13-supply = <&vph_pwr>; + + vreg_s4_1p8: s4 { + regulator-min-microvolt = <1728000>; + regulator-max-microvolt = <1920000>; + }; + + vreg_s5_1p35: s5 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_l1_1p3: l1 { + regulator-min-microvolt = <1240000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_l2_1p275: l2 { + regulator-min-microvolt = <1048000>; + regulator-max-microvolt = <1280000>; + }; + + vreg_l3_1p05: l3 { + regulator-min-microvolt = <1048000>; + regulator-max-microvolt = <1160000>; + }; + + vreg_l4_1p2: l4 { + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1256000>; + }; + + vreg_l5_1p8: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l6_1p8: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vreg_l7_1p8: l7 { + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <3000000>; + }; + + vreg_l8_1p2: l8 { + regulator-min-microvolt = <1136000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_l10_3p3: l10 { + regulator-min-microvolt = <2936000>; + regulator-max-microvolt = <3088000>; + }; + + vreg_l11_sdc2: l11 { + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l12_3p3: l12 { + regulator-min-microvolt = <3050000>; + regulator-max-microvolt = <3300000>; + }; + + vreg_l13_3p3: l13 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + }; +}; + +&sdcc1 { + status = "okay"; + + supports-cqe; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + non-removable; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&tlmm { + perst_state: perst-state { + pins = "gpio43"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + output-low; + }; + + sdc1_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + usb3_id_pin: usb3-id-state { + pins = "gpio116"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; +}; + +&pms405_gpios { + usb_vbus_boost_pin: usb-vbus-boost-state { + pinconf { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + power-source = <1>; + }; + }; + usb3_vbus_pin: usb3-vbus-state { + pinconf { + pins = "gpio12"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-down; + power-source = <1>; + }; + }; +}; + +&usb2 { + status = "okay"; +}; + +&usb2_phy_sec { + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + status = "okay"; +}; + +&usb3 { + status = "okay"; + +}; + +&usb3_dwc3 { + dr_mode = "host"; +}; + +&usb2_phy_prim { + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + status = "okay"; +}; + +&usb3_phy { + vdd-supply = <&vreg_l3_1p05>; + vdda1p8-supply = <&vreg_l5_1p8>; + status = "okay"; +}; + +&wifi { + status = "okay"; + vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>; + vdd-1.8-xo-supply = <&vreg_l5_1p8>; + vdd-1.3-rfa-supply = <&vreg_l1_1p3>; +}; + +/* PINCTRL - additions to nodes defined in qcs404.dtsi */ + +&blsp1_uart2_default { + rx-pins { + drive-strength = <2>; + bias-disable; + }; + + tx-pins { + drive-strength = <2>; + bias-disable; + }; +}; + +&blsp1_uart3_default { + cts-pins { + bias-disable; + }; + + rts-tx-pins { + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + bias-pull-up; + }; +}; diff --git a/arch/arm/dts/qcs404.dtsi b/arch/arm/dts/qcs404.dtsi new file mode 100644 index 00000000000..2721f32dfb7 --- /dev/null +++ b/arch/arm/dts/qcs404.dtsi @@ -0,0 +1,1829 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, Linaro Limited + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,gcc-qcs404.h> +#include <dt-bindings/clock/qcom,turingcc-qcs404.h> +#include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + power-domains = <&cpr>; + power-domain-names = "cpr"; + }; + + CPU1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + power-domains = <&cpr>; + power-domain-names = "cpr"; + }; + + CPU2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + power-domains = <&cpr>; + power-domain-names = "cpr"; + }; + + CPU3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + power-domains = <&cpr>; + power-domain-names = "cpr"; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "standalone-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <125>; + exit-latency-us = <180>; + min-residency-us = <595>; + local-timer-stop; + }; + }; + }; + + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2-kryo-cpu"; + opp-shared; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + required-opps = <&cpr_opp1>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + required-opps = <&cpr_opp2>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + required-opps = <&cpr_opp3>; + }; + }; + + cpr_opp_table: opp-table-cpr { + compatible = "operating-points-v2-qcom-level"; + + cpr_opp1: opp1 { + opp-level = <1>; + qcom,opp-fuse-level = <1>; + }; + cpr_opp2: opp2 { + opp-level = <2>; + qcom,opp-fuse-level = <2>; + }; + cpr_opp3: opp3 { + opp-level = <3>; + qcom,opp-fuse-level = <3>; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-qcs404", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rpm: remoteproc { + compatible = "qcom,qcs404-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-qcs404"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + rpmpd: power-controller { + compatible = "qcom,qcs404-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <16>; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = <32>; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = <48>; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = <64>; + }; + + rpmpd_opp_svs: opp5 { + opp-level = <128>; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = <192>; + }; + + rpmpd_opp_nom: opp7 { + opp-level = <256>; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = <320>; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = <384>; + }; + + rpmpd_opp_turbo_no_cpr: opp10 { + opp-level = <416>; + }; + + rpmpd_opp_turbo_plus: opp11 { + opp-level = <512>; + }; + }; + }; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz_apps_mem: memory@85900000 { + reg = <0 0x85900000 0 0x500000>; + no-map; + }; + + xbl_mem: memory@85e00000 { + reg = <0 0x85e00000 0 0x100000>; + no-map; + }; + + smem_region: memory@85f00000 { + reg = <0 0x85f00000 0 0x200000>; + no-map; + }; + + tz_mem: memory@86100000 { + reg = <0 0x86100000 0 0x300000>; + no-map; + }; + + wlan_fw_mem: memory@86400000 { + reg = <0 0x86400000 0 0x1100000>; + no-map; + }; + + adsp_fw_mem: memory@87500000 { + reg = <0 0x87500000 0 0x1a00000>; + no-map; + }; + + cdsp_fw_mem: memory@88f00000 { + reg = <0 0x88f00000 0 0x600000>; + no-map; + }; + + wlan_msa_mem: memory@89500000 { + reg = <0 0x89500000 0 0x100000>; + no-map; + }; + + uefi_mem: memory@9f800000 { + reg = <0 0x9f800000 0 0x800000>; + no-map; + }; + }; + + smem { + compatible = "qcom,smem"; + + memory-region = <&smem_region>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + + hwlocks = <&tcsr_mutex 3>; + }; + + soc: soc@0 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + turingcc: clock-controller@800000 { + compatible = "qcom,qcs404-turingcc"; + reg = <0x00800000 0x30000>; + clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + + status = "disabled"; + }; + + rpm_msg_ram: sram@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x00060000 0x6000>; + }; + + usb3_phy: phy@78000 { + compatible = "qcom,usb-ss-28nm-phy"; + reg = <0x00078000 0x400>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref", "ahb", "pipe"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + status = "disabled"; + }; + + usb2_phy_prim: phy@7a000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + reg = <0x0007a000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "ahb", "sleep"; + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&gcc GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + + usb2_phy_sec: phy@7c000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + reg = <0x0007c000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "ahb", "sleep"; + resets = <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + + qfprom: qfprom@a4000 { + compatible = "qcom,qcs404-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + cpr_efuse_speedbin: speedbin@13c { + reg = <0x13c 0x4>; + bits = <2 3>; + }; + + tsens_s0_p1: s0-p1@1f8 { + reg = <0x1f8 0x1>; + bits = <0 6>; + }; + + tsens_s0_p2: s0-p2@1f8 { + reg = <0x1f8 0x2>; + bits = <6 6>; + }; + + tsens_s1_p1: s1-p1@1f9 { + reg = <0x1f9 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@1fa { + reg = <0x1fa 0x1>; + bits = <2 6>; + }; + + tsens_s2_p1: s2-p1@1fb { + reg = <0x1fb 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2: s2-p2@1fb { + reg = <0x1fb 0x2>; + bits = <6 6>; + }; + + tsens_s3_p1: s3-p1@1fc { + reg = <0x1fc 0x2>; + bits = <4 6>; + }; + + tsens_s3_p2: s3-p2@1fd { + reg = <0x1fd 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1: s4-p1@1fe { + reg = <0x1fe 0x1>; + bits = <0 6>; + }; + + tsens_s4_p2: s4-p2@1fe { + reg = <0x1fe 0x2>; + bits = <6 6>; + }; + + tsens_s5_p1: s5-p1@200 { + reg = <0x200 0x1>; + bits = <0 6>; + }; + + tsens_s5_p2: s5-p2@200 { + reg = <0x200 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@201 { + reg = <0x201 0x2>; + bits = <4 6>; + }; + + tsens_s6_p2: s6-p2@202 { + reg = <0x202 0x1>; + bits = <2 6>; + }; + + tsens_s7_p1: s7-p1@203 { + reg = <0x203 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@203 { + reg = <0x203 0x2>; + bits = <6 6>; + }; + + tsens_s8_p1: s8-p1@204 { + reg = <0x204 0x2>; + bits = <4 6>; + }; + + tsens_s8_p2: s8-p2@205 { + reg = <0x205 0x1>; + bits = <2 6>; + }; + + tsens_s9_p1: s9-p1@206 { + reg = <0x206 0x1>; + bits = <0 6>; + }; + + tsens_s9_p2: s9-p2@206 { + reg = <0x206 0x2>; + bits = <6 6>; + }; + + tsens_mode: mode@208 { + reg = <0x208 1>; + bits = <0 3>; + }; + + tsens_base1: base1@208 { + reg = <0x208 2>; + bits = <3 8>; + }; + + tsens_base2: base2@208 { + reg = <0x209 2>; + bits = <3 8>; + }; + + cpr_efuse_quot_offset1: qoffset1@231 { + reg = <0x231 0x4>; + bits = <4 7>; + }; + cpr_efuse_quot_offset2: qoffset2@232 { + reg = <0x232 0x4>; + bits = <3 7>; + }; + cpr_efuse_quot_offset3: qoffset3@233 { + reg = <0x233 0x4>; + bits = <2 7>; + }; + cpr_efuse_init_voltage1: ivoltage1@229 { + reg = <0x229 0x4>; + bits = <4 6>; + }; + cpr_efuse_init_voltage2: ivoltage2@22a { + reg = <0x22a 0x4>; + bits = <2 6>; + }; + cpr_efuse_init_voltage3: ivoltage3@22b { + reg = <0x22b 0x4>; + bits = <0 6>; + }; + cpr_efuse_quot1: quot1@22b { + reg = <0x22b 0x4>; + bits = <6 12>; + }; + cpr_efuse_quot2: quot2@22d { + reg = <0x22d 0x4>; + bits = <2 12>; + }; + cpr_efuse_quot3: quot3@230 { + reg = <0x230 0x4>; + bits = <0 12>; + }; + cpr_efuse_ring1: ring1@228 { + reg = <0x228 0x4>; + bits = <0 3>; + }; + cpr_efuse_ring2: ring2@228 { + reg = <0x228 0x4>; + bits = <4 3>; + }; + cpr_efuse_ring3: ring3@229 { + reg = <0x229 0x4>; + bits = <0 3>; + }; + cpr_efuse_revision: revision@218 { + reg = <0x218 0x4>; + bits = <3 3>; + }; + }; + + rng: rng@e3000 { + compatible = "qcom,prng-ee"; + reg = <0x000e3000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + bimc: interconnect@400000 { + reg = <0x00400000 0x80000>; + compatible = "qcom,qcs404-bimc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2"; + #qcom,sensors = <10>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + #thermal-sensor-cells = <1>; + }; + + pcnoc: interconnect@500000 { + reg = <0x00500000 0x15080>; + compatible = "qcom,qcs404-pcnoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_PNOC_CLK>, + <&rpmcc RPM_SMD_PNOC_A_CLK>; + }; + + snoc: interconnect@580000 { + reg = <0x00580000 0x23080>; + compatible = "qcom,qcs404-snoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + + remoteproc_cdsp: remoteproc@b00000 { + compatible = "qcom,qcs404-cdsp-pas"; + reg = <0x00b00000 0x4040>; + + interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&xo_board>; + clock-names = "xo"; + + /* + * If the node was using the PIL binding, then include properties: + * clocks = <&xo_board>, + * <&gcc GCC_CDSP_CFG_AHB_CLK>, + * <&gcc GCC_CDSP_TBU_CLK>, + * <&gcc GCC_BIMC_CDSP_CLK>, + * <&turingcc TURING_WRAPPER_AON_CLK>, + * <&turingcc TURING_Q6SS_AHBS_AON_CLK>, + * <&turingcc TURING_Q6SS_AHBM_AON_CLK>, + * <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; + * clock-names = "xo", + * "sway", + * "tbu", + * "bimc", + * "ahb_aon", + * "q6ss_slave", + * "q6ss_master", + * "q6_axim"; + * resets = <&gcc GCC_CDSP_RESTART>; + * reset-names = "restart"; + * qcom,halt-regs = <&tcsr 0x19004>; + */ + + memory-region = <&cdsp_fw_mem>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; + + qcom,remote-pid = <5>; + mboxes = <&apcs_glb 12>; + + label = "cdsp"; + }; + }; + + usb3: usb@7678800 { + compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; + reg = <0x07678800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + status = "disabled"; + + usb3_dwc3: usb@7580000 { + compatible = "snps,dwc3"; + reg = <0x07580000 0xcd00>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2_phy_prim>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + dr_mode = "otg"; + }; + }; + + usb2: usb@79b8800 { + compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; + reg = <0x079b8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, + <&gcc GCC_PCNOC_USB2_CLK>, + <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + status = "disabled"; + + usb@78c0000 { + compatible = "snps,dwc3"; + reg = <0x078c0000 0xcc00>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2_phy_sec>; + phy-names = "usb2-phy"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + dr_mode = "peripheral"; + }; + }; + + tlmm: pinctrl@1000000 { + compatible = "qcom,qcs404-pinctrl"; + reg = <0x01000000 0x200000>, + <0x01300000 0x200000>, + <0x07b00000 0x200000>; + reg-names = "south", "north", "east"; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&tlmm 0 0 120>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1_i2c0_default: blsp1-i2c0-default-state { + pins = "gpio32", "gpio33"; + function = "blsp_i2c0"; + }; + + blsp1_i2c1_default: blsp1-i2c1-default-state { + pins = "gpio24", "gpio25"; + function = "blsp_i2c1"; + }; + + blsp1_i2c2_default: blsp1-i2c2-default-state { + sda-pins { + pins = "gpio19"; + function = "blsp_i2c_sda_a2"; + }; + + scl-pins { + pins = "gpio20"; + function = "blsp_i2c_scl_a2"; + }; + }; + + blsp1_i2c3_default: blsp1-i2c3-default-state { + pins = "gpio84", "gpio85"; + function = "blsp_i2c3"; + }; + + blsp1_i2c4_default: blsp1-i2c4-default-state { + pins = "gpio117", "gpio118"; + function = "blsp_i2c4"; + }; + + blsp1_uart0_default: blsp1-uart0-default-state { + pins = "gpio30", "gpio31", "gpio32", "gpio33"; + function = "blsp_uart0"; + }; + + blsp1_uart1_default: blsp1-uart1-default-state { + pins = "gpio22", "gpio23"; + function = "blsp_uart1"; + }; + + blsp1_uart2_default: blsp1-uart2-default-state { + rx-pins { + pins = "gpio18"; + function = "blsp_uart_rx_a2"; + }; + + tx-pins { + pins = "gpio17"; + function = "blsp_uart_tx_a2"; + }; + }; + + blsp1_uart3_default: blsp1-uart3-default-state { + cts-pins { + pins = "gpio84"; + function = "blsp_uart3"; + }; + + rts-tx-pins { + pins = "gpio85", "gpio82"; + function = "blsp_uart3"; + }; + + rx-pins { + pins = "gpio83"; + function = "blsp_uart3"; + }; + }; + + blsp2_i2c0_default: blsp2-i2c0-default-state { + pins = "gpio28", "gpio29"; + function = "blsp_i2c5"; + }; + + blsp1_spi0_default: blsp1-spi0-default-state { + pins = "gpio30", "gpio31", "gpio32", "gpio33"; + function = "blsp_spi0"; + }; + + blsp1_spi1_default: blsp1-spi1-default-state { + mosi-pins { + pins = "gpio22"; + function = "blsp_spi_mosi_a1"; + }; + + miso-pins { + pins = "gpio23"; + function = "blsp_spi_miso_a1"; + }; + + cs-n-pins { + pins = "gpio24"; + function = "blsp_spi_cs_n_a1"; + }; + + clk-pins { + pins = "gpio25"; + function = "blsp_spi_clk_a1"; + }; + }; + + blsp1_spi2_default: blsp1-spi2-default-state { + pins = "gpio17", "gpio18", "gpio19", "gpio20"; + function = "blsp_spi2"; + }; + + blsp1_spi3_default: blsp1-spi3-default-state { + pins = "gpio82", "gpio83", "gpio84", "gpio85"; + function = "blsp_spi3"; + }; + + blsp1_spi4_default: blsp1-spi4-default-state { + pins = "gpio37", "gpio38", "gpio117", "gpio118"; + function = "blsp_spi4"; + }; + + blsp2_spi0_default: blsp2-spi0-default-state { + pins = "gpio26", "gpio27", "gpio28", "gpio29"; + function = "blsp_spi5"; + }; + + blsp2_uart0_default: blsp2-uart0-default-state { + pins = "gpio26", "gpio27", "gpio28", "gpio29"; + function = "blsp_uart5"; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-qcs404"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + clocks = <&xo_board>, + <&sleep_clk>, + <&pcie_phy>, + <0>, + <0>, + <0>; + + assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; + assigned-clock-rates = <19200000>; + }; + + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1937000 { + compatible = "qcom,qcs404-tcsr", "syscon"; + reg = <0x01937000 0x25000>; + }; + + sram@290000 { + compatible = "qcom,rpm-stats"; + reg = <0x00290000 0x10000>; + }; + + spmi_bus: spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0200f000 0x001000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + remoteproc_wcss: remoteproc@7400000 { + compatible = "qcom,qcs404-wcss-pas"; + reg = <0x07400000 0x4040>; + + interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&xo_board>; + clock-names = "xo"; + + memory-region = <&wlan_fw_mem>; + + qcom,smem-states = <&wcss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; + + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 16>; + + label = "wcss"; + }; + }; + + pcie_phy: phy@7786000 { + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; + reg = <0x07786000 0xb8>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, + <&gcc GCC_PCIE_0_PIPE_ARES>; + reset-names = "phy", "pipe"; + + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + #phy-cells = <0>; + + status = "disabled"; + }; + + sdcc1: mmc@7804000 { + compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x07804000 0x1000>, <0x7805000 0x1000>; + reg-names = "hc", "cqhci"; + + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + + status = "disabled"; + }; + + blsp1_dma: dma-controller@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x25000>; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "okay"; + }; + + blsp1_uart0: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart0_default>; + status = "disabled"; + }; + + blsp1_uart1: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart1_default>; + status = "disabled"; + }; + + blsp1_uart2: serial@78b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b1000 0x200>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart2_default>; + status = "okay"; + }; + + ethernet: ethernet@7a80000 { + compatible = "qcom,qcs404-ethqos"; + reg = <0x07a80000 0x10000>, + <0x07a96000 0x100>; + reg-names = "stmmaceth", "rgmii"; + clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; + clocks = <&gcc GCC_ETH_AXI_CLK>, + <&gcc GCC_ETH_SLAVE_AHB_CLK>, + <&gcc GCC_ETH_PTP_CLK>, + <&gcc GCC_ETH_RGMII_CLK>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_lpi"; + + snps,tso; + rx-fifo-depth = <4096>; + tx-fifo-depth = <4096>; + + status = "disabled"; + }; + + wifi: wifi@a000000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0xa000000 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_msa_mem>; + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + blsp1_uart3: serial@78b2000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b2000 0x200>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart3_default>; + status = "disabled"; + }; + + blsp1_i2c0: i2c@78b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b5000 0x600>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c0_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_spi0: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b5000 0x600>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi0_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c1: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b6000 0x600>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c1_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_spi1: spi@78b6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b6000 0x600>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi1_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c2: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c2_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_spi2: spi@78b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi2_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c3: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b8000 0x600>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c3_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_spi3: spi@78b8000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b8000 0x600>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi3_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c4: i2c@78b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b9000 0x600>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c4_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_spi4: spi@78b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b9000 0x600>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi4_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_dma: dma-controller@7ac4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07ac4000 0x17000>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + blsp2_uart0: serial@7aef000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x07aef000 0x200>; + interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_uart0_default>; + status = "disabled"; + }; + + blsp2_i2c0: i2c@7af5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x07af5000 0x600>; + interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_i2c0_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_spi0: spi@7af5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07af5000 0x600>; + interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi0_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sram@8600000 { + compatible = "qcom,qcs404-imem", "syscon", "simple-mfd"; + reg = <0x08600000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0x08600000 0x1000>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + apcs_glb: mailbox@b011000 { + compatible = "qcom,qcs404-apcs-apps-global", + "qcom,msm8916-apcs-kpss-global", "syscon"; + reg = <0x0b011000 0x1000>; + #mbox-cells = <1>; + clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; + clock-names = "pll", "aux"; + #clock-cells = <0>; + }; + + apcs_hfpll: clock-controller@b016000 { + compatible = "qcom,hfpll"; + reg = <0x0b016000 0x30>; + #clock-cells = <0>; + clock-output-names = "apcs_hfpll"; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + watchdog@b017000 { + compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; + reg = <0x0b017000 0x1000>; + clocks = <&sleep_clk>; + }; + + cpr: power-controller@b018000 { + compatible = "qcom,qcs404-cpr", "qcom,cpr"; + reg = <0x0b018000 0x1000>; + interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; + clocks = <&xo_board>; + clock-names = "ref"; + vdd-apc-supply = <&pms405_s3>; + #power-domain-cells = <0>; + operating-points-v2 = <&cpr_opp_table>; + acc-syscon = <&tcsr>; + + nvmem-cells = <&cpr_efuse_quot_offset1>, + <&cpr_efuse_quot_offset2>, + <&cpr_efuse_quot_offset3>, + <&cpr_efuse_init_voltage1>, + <&cpr_efuse_init_voltage2>, + <&cpr_efuse_init_voltage3>, + <&cpr_efuse_quot1>, + <&cpr_efuse_quot2>, + <&cpr_efuse_quot3>, + <&cpr_efuse_ring1>, + <&cpr_efuse_ring2>, + <&cpr_efuse_ring3>, + <&cpr_efuse_revision>; + nvmem-cell-names = "cpr_quotient_offset1", + "cpr_quotient_offset2", + "cpr_quotient_offset3", + "cpr_init_voltage1", + "cpr_init_voltage2", + "cpr_init_voltage3", + "cpr_quotient1", + "cpr_quotient2", + "cpr_quotient3", + "cpr_ring_osc1", + "cpr_ring_osc2", + "cpr_ring_osc3", + "cpr_fuse_revision"; + }; + + timer@b120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + clock-frequency = <19200000>; + + frame@b121000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b123000 0x1000>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b125000 0x1000>; + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b126000 0x1000>; + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb127000 0x1000>; + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b128000 0x1000>; + status = "disabled"; + }; + }; + + remoteproc_adsp: remoteproc@c700000 { + compatible = "qcom,qcs404-adsp-pas"; + reg = <0x0c700000 0x4040>; + + interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&xo_board>; + clock-names = "xo"; + + memory-region = <&adsp_fw_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; + + qcom,remote-pid = <2>; + mboxes = <&apcs_glb 8>; + + label = "adsp"; + }; + }; + + pcie: pci@10000000 { + compatible = "qcom,pcie-qcs404"; + reg = <0x10000000 0xf1d>, + <0x10000f20 0xa8>, + <0x07780000 0x2000>, + <0x10001000 0x2000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */ + <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */ + + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>; + clock-names = "iface", "aux", "master_bus", "slave_bus"; + + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_AHB_ARES>; + reset-names = "axi_m", + "axi_s", + "axi_m_sticky", + "pipe_sticky", + "pwr", + "ahb"; + + phys = <&pcie_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 2 0xff08>, + <GIC_PPI 3 0xff08>, + <GIC_PPI 4 0xff08>, + <GIC_PPI 1 0xff08>; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apcs_glb 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apcs_glb 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-wcss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apcs_glb 18>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + wcss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wcss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + thermal-zones { + aoss-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 0>; + + trips { + aoss_alert0: trip-point0 { + temperature = <105000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + q6-hvx-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 1>; + + trips { + q6_hvx_alert0: trip-point0 { + temperature = <105000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + lpass-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + + trips { + lpass_alert0: trip-point0 { + temperature = <105000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 3>; + + trips { + wlan_alert0: trip-point0 { + temperature = <105000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + cluster-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 4>; + + trips { + cluster_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + cluster_alert1: trip-point1 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + cluster_crit: cluster-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cluster_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu0_alert1: trip-point1 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu0_crit: cpu-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu0_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu1_alert1: trip-point1 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu1_crit: cpu-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu1_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu2_alert1: trip-point1 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu2_crit: cpu-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu2_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + cpu3_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu3_alert1: trip-point1 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu3_crit: cpu-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu3_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 9>; + + trips { + gpu_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts b/arch/arm/dts/r7s72100-gr-peach-u-boot.dtsi index 0ae9f91fbe8..34fba29e859 100644 --- a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts +++ b/arch/arm/dts/r7s72100-gr-peach-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com> */ -#include "r7s72100-gr-peach.dts" / { aliases { diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts b/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dtsi index b735e972214..3ad619bdb90 100644 --- a/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts +++ b/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2021 Renesas Electronics Corporation */ -#include "r8a774a1-hihope-rzg2m-ex.dts" #include "r8a774a1-u-boot.dtsi" &gpio3 { diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dtsi index 0bdc6909bfb..6f2f6c71c2f 100644 --- a/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts +++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ -#include "r8a774b1-hihope-rzg2n-ex.dts" #include "r8a774b1-u-boot.dtsi" &gpio3 { diff --git a/arch/arm/dts/r8a774c0-ek874-u-boot.dts b/arch/arm/dts/r8a774c0-ek874-u-boot.dtsi index 8fa6d8074b3..dcdddd9aed6 100644 --- a/arch/arm/dts/r8a774c0-ek874-u-boot.dts +++ b/arch/arm/dts/r8a774c0-ek874-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2021 Renesas Electronisc Corporation */ -#include "r8a774c0-ek874.dts" #include "r8a774c0-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dtsi index 03a17bac7ec..8e57e03c899 100644 --- a/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts +++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ -#include "r8a774e1-hihope-rzg2h-ex.dts" #include "r8a774e1-u-boot.dtsi" &gpio3 { diff --git a/arch/arm/dts/r8a7790-lager-u-boot.dts b/arch/arm/dts/r8a7790-lager-u-boot.dtsi index 28b8b604c37..ed1891706ce 100644 --- a/arch/arm/dts/r8a7790-lager-u-boot.dts +++ b/arch/arm/dts/r8a7790-lager-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7790-lager.dts" #include "r8a7790-u-boot.dtsi" &scif0 { diff --git a/arch/arm/dts/r8a7790-stout-u-boot.dts b/arch/arm/dts/r8a7790-stout-u-boot.dtsi index 85bcb787613..3b393045e36 100644 --- a/arch/arm/dts/r8a7790-stout-u-boot.dts +++ b/arch/arm/dts/r8a7790-stout-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7790-stout.dts" #include "r8a7790-u-boot.dtsi" &scifa0 { diff --git a/arch/arm/dts/r8a7791-koelsch-u-boot.dts b/arch/arm/dts/r8a7791-koelsch-u-boot.dtsi index c5a1332131d..541c4191d69 100644 --- a/arch/arm/dts/r8a7791-koelsch-u-boot.dts +++ b/arch/arm/dts/r8a7791-koelsch-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7791-koelsch.dts" #include "r8a7791-u-boot.dtsi" &scif0 { diff --git a/arch/arm/dts/r8a7791-porter-u-boot.dts b/arch/arm/dts/r8a7791-porter-u-boot.dtsi index bfec1fc6d62..cbf2c5265d8 100644 --- a/arch/arm/dts/r8a7791-porter-u-boot.dts +++ b/arch/arm/dts/r8a7791-porter-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7791-porter.dts" #include "r8a7791-u-boot.dtsi" &scif0 { diff --git a/arch/arm/dts/r8a7792-blanche-u-boot.dts b/arch/arm/dts/r8a7792-blanche-u-boot.dtsi index 1f33df81cef..8c36a3e5850 100644 --- a/arch/arm/dts/r8a7792-blanche-u-boot.dts +++ b/arch/arm/dts/r8a7792-blanche-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7792-blanche.dts" #include "r8a7792-u-boot.dtsi" &iic3 { diff --git a/arch/arm/dts/r8a7793-gose-u-boot.dts b/arch/arm/dts/r8a7793-gose-u-boot.dtsi index dd0932ceca9..41c4361c6e1 100644 --- a/arch/arm/dts/r8a7793-gose-u-boot.dts +++ b/arch/arm/dts/r8a7793-gose-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7793-gose.dts" #include "r8a7793-u-boot.dtsi" &scif0 { diff --git a/arch/arm/dts/r8a7794-alt-u-boot.dts b/arch/arm/dts/r8a7794-alt-u-boot.dtsi index 0a39039fc97..e156b4c93c7 100644 --- a/arch/arm/dts/r8a7794-alt-u-boot.dts +++ b/arch/arm/dts/r8a7794-alt-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7794-alt.dts" #include "r8a7794-u-boot.dtsi" &i2c7 { diff --git a/arch/arm/dts/r8a7794-silk-u-boot.dts b/arch/arm/dts/r8a7794-silk-u-boot.dtsi index 3fcb535a3ac..e448ea7e146 100644 --- a/arch/arm/dts/r8a7794-silk-u-boot.dts +++ b/arch/arm/dts/r8a7794-silk-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7794-silk.dts" #include "r8a7794-u-boot.dtsi" &scif2 { diff --git a/arch/arm/dts/r8a77950-salvator-x-u-boot.dts b/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi index ba7cf521d0d..744f4aaaad9 100644 --- a/arch/arm/dts/r8a77950-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi @@ -5,8 +5,7 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77950-salvator-x.dts" -#include "r8a77950-u-boot.dtsi" +#include "r8a77951-u-boot.dtsi" / { sysinfo { diff --git a/arch/arm/dts/r8a77950-u-boot.dtsi b/arch/arm/dts/r8a77951-u-boot.dtsi index 92907ea09bf..4cbec591479 100644 --- a/arch/arm/dts/r8a77950-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-u-boot.dtsi @@ -30,7 +30,6 @@ /delete-node/ &can1; /delete-node/ &canfd; /delete-node/ &csi20; -/delete-node/ &csi21; /delete-node/ &csi40; /delete-node/ &csi41; /delete-node/ &drif00; @@ -44,16 +43,13 @@ /delete-node/ &du; /delete-node/ &fcpf0; /delete-node/ &fcpf1; -/delete-node/ &fcpf2; /delete-node/ &fcpvb0; /delete-node/ &fcpvb1; /delete-node/ &fcpvd0; /delete-node/ &fcpvd1; /delete-node/ &fcpvd2; -/delete-node/ &fcpvd3; /delete-node/ &fcpvi0; /delete-node/ &fcpvi1; -/delete-node/ &fcpvi2; /delete-node/ &hdmi0; /delete-node/ &hdmi1; /delete-node/ &lvds0; @@ -72,10 +68,8 @@ /delete-node/ &vspd0; /delete-node/ &vspd1; /delete-node/ &vspd2; -/delete-node/ &vspd3; /delete-node/ &vspi0; /delete-node/ &vspi1; -/delete-node/ &vspi2; / { /delete-node/ cvbs-in; diff --git a/arch/arm/dts/r8a77950-ulcb-u-boot.dts b/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi index e371cde349f..305c4861520 100644 --- a/arch/arm/dts/r8a77950-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi @@ -5,8 +5,7 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77950-ulcb.dts" -#include "r8a77950-u-boot.dtsi" +#include "r8a77951-u-boot.dtsi" / { cpld { diff --git a/arch/arm/dts/r8a77960-salvator-x-u-boot.dts b/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi index 2a9f0aa2180..84a28bf885c 100644 --- a/arch/arm/dts/r8a77960-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77960-salvator-x.dts" #include "r8a77960-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a77960-ulcb-u-boot.dts b/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi index 79042b20852..6372f953956 100644 --- a/arch/arm/dts/r8a77960-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77960-ulcb.dts" #include "r8a77960-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts b/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi index e5421f9ca8f..d9a28fe9bab 100644 --- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77965-salvator-x.dts" #include "r8a77965-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a77965-ulcb-u-boot.dts b/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi index 969911d89ce..aa5de3d0465 100644 --- a/arch/arm/dts/r8a77965-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77965-ulcb.dts" #include "r8a77965-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a77970-eagle-u-boot.dts b/arch/arm/dts/r8a77970-eagle-u-boot.dtsi index eb868eda414..c7971b9e9ce 100644 --- a/arch/arm/dts/r8a77970-eagle-u-boot.dts +++ b/arch/arm/dts/r8a77970-eagle-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77970-eagle.dts" #include "r8a77970-u-boot.dtsi" #include <dt-bindings/gpio/gpio.h> diff --git a/arch/arm/dts/r8a77970-v3msk-u-boot.dts b/arch/arm/dts/r8a77970-v3msk-u-boot.dtsi index 6ee06d7c000..c7b2e07793d 100644 --- a/arch/arm/dts/r8a77970-v3msk-u-boot.dts +++ b/arch/arm/dts/r8a77970-v3msk-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2019 Cogent Embedded, Inc. */ -#include "r8a77970-v3msk.dts" #include "r8a77970-u-boot.dtsi" #include <dt-bindings/gpio/gpio.h> diff --git a/arch/arm/dts/r8a77980-condor-u-boot.dts b/arch/arm/dts/r8a77980-condor-u-boot.dtsi index f4a3b43b8ff..34a735ae5b2 100644 --- a/arch/arm/dts/r8a77980-condor-u-boot.dts +++ b/arch/arm/dts/r8a77980-condor-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77980-condor.dts" #include "r8a77980-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a77980-v3hsk-u-boot.dts b/arch/arm/dts/r8a77980-v3hsk-u-boot.dtsi index d083df65f9a..2901d0e7b57 100644 --- a/arch/arm/dts/r8a77980-v3hsk-u-boot.dts +++ b/arch/arm/dts/r8a77980-v3hsk-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2019 Cogent Embedded, Inc. */ -#include "r8a77980-v3hsk.dts" #include "r8a77980-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dts b/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi index fc1c4a79294..b6b7b8f3609 100644 --- a/arch/arm/dts/r8a77990-ebisu-u-boot.dts +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77990-ebisu.dts" #include "r8a77990-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a77995-draak-u-boot.dts b/arch/arm/dts/r8a77995-draak-u-boot.dtsi index 41ceae1da77..1922c40a438 100644 --- a/arch/arm/dts/r8a77995-draak-u-boot.dts +++ b/arch/arm/dts/r8a77995-draak-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77995-draak.dts" #include "r8a77995-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a779a0-falcon-u-boot.dts b/arch/arm/dts/r8a779a0-falcon-u-boot.dtsi index 9d28791c605..3b8a017cb41 100644 --- a/arch/arm/dts/r8a779a0-falcon-u-boot.dts +++ b/arch/arm/dts/r8a779a0-falcon-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ -#include "r8a779a0-falcon.dts" #include "r8a779a0-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a779f0-spider-u-boot.dts b/arch/arm/dts/r8a779f0-spider-u-boot.dtsi index 26fc8bcf440..2fc7e7789a2 100644 --- a/arch/arm/dts/r8a779f0-spider-u-boot.dts +++ b/arch/arm/dts/r8a779f0-spider-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ -#include "r8a779f0-spider.dts" #include "r8a779f0-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi index bd756036645..a102639010d 100644 --- a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts +++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ -#include "r8a779g0-white-hawk.dts" #include "r8a779g0-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dts b/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dtsi index 935ba9465dc..92c13151613 100644 --- a/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dts +++ b/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2023 Renesas Electronics Corp. */ -#include "r8a779h0-gray-hawk.dts" #include "r8a779h0-u-boot.dtsi" / { diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi index 12b68df1ac6..38ad3cc16d0 100644 --- a/arch/arm/dts/rk3328-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi @@ -44,3 +44,7 @@ /* Integrated PHY unsupported by U-Boot */ status = "broken"; }; + +&vcc_sd { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index ff6b466e0e0..1eef5504445 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -11,6 +11,7 @@ compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2phy; mmc0 = &sdmmc; mmc1 = &sdio; mmc2 = &emmc; diff --git a/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi index f8adb9e5e1f..1dc3c022c50 100644 --- a/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi @@ -1,9 +1,3 @@ // SPDX-License-Identifier: GPL-2.0-or-later #include "rk3328-nanopi-r2c-u-boot.dtsi" - -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; -}; diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi index 78d37ab4755..4fa170eeaf8 100644 --- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi @@ -6,35 +6,23 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-ddr4-666.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; -}; -&gpio0 { +&gpio1 { bootph-pre-ram; }; -&pinctrl { - bootph-pre-ram; +&sdio_vcc_pin { + bootph-all; }; -&sdmmc0m1_pin { - bootph-pre-ram; +&usb20_otg { + dr_mode = "peripheral"; }; -&pcfg_pull_up_4ma { +&vcc_io_sdio { bootph-pre-ram; }; -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ &vcc_sd { bootph-pre-ram; }; - -&gmac2io { - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; -}; diff --git a/arch/arm/dts/rk3328-nanopi-r2s.dts b/arch/arm/dts/rk3328-nanopi-r2s.dts index 3857d487ab8..a4399da7d8b 100644 --- a/arch/arm/dts/rk3328-nanopi-r2s.dts +++ b/arch/arm/dts/rk3328-nanopi-r2s.dts @@ -14,6 +14,7 @@ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2io; ethernet1 = &rtl8153; mmc0 = &sdmmc; }; @@ -34,7 +35,7 @@ pinctrl-0 = <&reset_button_pin>; pinctrl-names = "default"; - reset { + key-reset { label = "reset"; gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; linux,code = <KEY_RESTART>; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi index ebe33e48cb9..0a9423cd9c7 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi @@ -6,41 +6,37 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-lpddr3-666.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; -}; -&gpio0 { +&spi0 { bootph-pre-ram; + bootph-some-ram; + + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; }; -&pinctrl { +&spi0m2_clk { bootph-pre-ram; }; -&sdmmc0m1_pin { +&spi0m2_cs0 { bootph-pre-ram; }; -&pcfg_pull_up_4ma { +&spi0m2_rx { bootph-pre-ram; }; -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ -&vcc_sd { +&spi0m2_tx { bootph-pre-ram; }; -&gmac2io { - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; +&usb20_otg { + dr_mode = "peripheral"; }; -&spi0 { - spi_flash: spiflash@0 { - bootph-all; - }; +&vcc_sd { + bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts index 5d7d567283e..4237f2ee8fe 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts @@ -26,9 +26,11 @@ compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + motorcomm,auto-sleep-disabled; motorcomm,clk-out-frequency-hz = <125000000>; motorcomm,keep-pll-enabled; - motorcomm,auto-sleep-disabled; + motorcomm,rx-clk-drv-microamp = <5020>; + motorcomm,rx-data-drv-microamp = <5020>; pinctrl-0 = <ð_phy_reset_pin>; pinctrl-names = "default"; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi index 637c70adf19..1096821fc5d 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi @@ -6,41 +6,37 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-ddr4-666.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; -}; -&gpio0 { +&spi0 { bootph-pre-ram; + bootph-some-ram; + + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; }; -&pinctrl { +&spi0m2_clk { bootph-pre-ram; }; -&sdmmc0m1_pin { +&spi0m2_cs0 { bootph-pre-ram; }; -&pcfg_pull_up_4ma { +&spi0m2_rx { bootph-pre-ram; }; -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ -&vcc_sd { +&spi0m2_tx { bootph-pre-ram; }; -&gmac2io { - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; +&usb20_otg { + dr_mode = "peripheral"; }; -&spi0 { - spi_flash: spiflash@0 { - bootph-all; - }; +&vcc_sd { + bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus.dts b/arch/arm/dts/rk3328-orangepi-r1-plus.dts index dc83d74045a..f20662929c7 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus.dts +++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts @@ -15,6 +15,7 @@ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2io; ethernet1 = &rtl8153; mmc0 = &sdmmc; }; diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi index 2062f34bf82..582d6ba49b4 100644 --- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi +++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi @@ -5,11 +5,8 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-ddr4-666.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; +/ { smbios { compatible = "u-boot,sysinfo-smbios"; @@ -32,23 +29,10 @@ }; }; -&gpio0 { - bootph-pre-ram; -}; - -&pinctrl { - bootph-pre-ram; -}; - -&sdmmc0m1_pin { - bootph-pre-ram; -}; - -&pcfg_pull_up_4ma { - bootph-pre-ram; +&usb20_otg { + hnp-srp-disable; }; -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ &vcc_sd { bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts index aa22a0c2226..414897a57e7 100644 --- a/arch/arm/dts/rk3328-roc-cc.dts +++ b/arch/arm/dts/rk3328-roc-cc.dts @@ -11,6 +11,7 @@ compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2io; mmc0 = &sdmmc; mmc1 = &emmc; }; @@ -96,7 +97,6 @@ linux,default-trigger = "heartbeat"; gpios = <&rk805 1 GPIO_ACTIVE_LOW>; default-state = "on"; - mode = <0x23>; }; user_led: led-1 { @@ -104,7 +104,6 @@ linux,default-trigger = "mmc1"; gpios = <&rk805 0 GPIO_ACTIVE_LOW>; default-state = "off"; - mode = <0x05>; }; }; }; diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi index 1f220c6dcd0..d314bfad6fc 100644 --- a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi @@ -29,23 +29,15 @@ }; }; -&gpio0 { - bootph-pre-ram; -}; - -&pinctrl { - bootph-pre-ram; +&u2phy_host { + phy-supply = <&vcc_host_5v>; }; -&sdmmc0m1_pin { - bootph-pre-ram; -}; - -&pcfg_pull_up_4ma { - bootph-pre-ram; +&vcc_host_5v { + /delete-property/ regulator-always-on; + /delete-property/ regulator-boot-on; }; -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ &vcc_sd { bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-rock-pi-e.dts b/arch/arm/dts/rk3328-rock-pi-e.dts index 018a3a5075c..3cda6c627b6 100644 --- a/arch/arm/dts/rk3328-rock-pi-e.dts +++ b/arch/arm/dts/rk3328-rock-pi-e.dts @@ -21,6 +21,8 @@ compatible = "radxa,rockpi-e", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2io; + ethernet1 = &gmac2phy; mmc0 = &sdmmc; mmc1 = &emmc; }; @@ -180,6 +182,59 @@ status = "okay"; }; +&gpio0 { + gpio-line-names = + /* GPIO0_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_B0 - B7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_D0 - D7 */ + "", "", "", "pin-15 [GPIO0_D3]", "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_B0 - B7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_D0 - D7 */ + "", "", "", "", "pin-07 [GPIO1_D4]", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0 - A7 */ + "pin-08 [GPIO2_A0]", "pin-10 [GPIO2_A1]", "pin-11 [GPIO2_A2]", + "pin-13 [GPIO2-A3]", "pin-27 [GPIO2_A4]", "pin-28 [GPIO2_A5]", + "pin-33 [GPIO2_A6]", "", + /* GPIO2_B0 - B7 */ + "", "", "", "", "pin-26 [GPIO2_B4]", "", "", "pin-36 [GPIO2_B7]", + /* GPIO2_C0 - C7 */ + "pin-32 [GPIO2_C0]", "pin-35 [GPIO2_C1]", "pin-12 [GPIO2_C2]", + "pin-38 [GPIO2_C3]", "pin-29 [GPIO2_C4]", "pin-31 [GPIO2_C5]", + "pin-37 [GPIO2_C6]", "pin-40 [GPIO2_C7]", + /* GPIO2_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0 - A7 */ + "pin-23 [GPIO3_A0]", "pin-19 [GPIO3_A1]", "pin-21 [GPIO3_A2]", + "", "pin-03 [GPIO3_A4]", "", "pin-05 [GPIO3_A6]", "", + /* GPIO3_B0 - B7 */ + "pin-24 [GPIO3_B0]", "", "", "", "", "", "", "", + /* GPIO3_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO3_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + &i2c1 { status = "okay"; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 6904515b969..551cff6f24f 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -5,11 +5,8 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-lpddr3-1600.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; +/ { smbios { compatible = "u-boot,sysinfo-smbios"; @@ -32,29 +29,36 @@ }; }; -&gpio0 { +&spi0 { bootph-pre-ram; + bootph-some-ram; + + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; }; -&pinctrl { +&spi0m2_clk { bootph-pre-ram; }; -&sdmmc0m1_pin { +&spi0m2_cs0 { bootph-pre-ram; }; -&pcfg_pull_up_4ma { +&spi0m2_rx { bootph-pre-ram; }; -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ -&vcc_sd { +&spi0m2_tx { bootph-pre-ram; }; -&spi0 { - spi_flash: flash@0 { - bootph-all; - }; +&usb20_otg { + hnp-srp-disable; +}; + +&vcc_sd { + bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts index 0a27fa5271f..229fe9da9c2 100644 --- a/arch/arm/dts/rk3328-rock64.dts +++ b/arch/arm/dts/rk3328-rock64.dts @@ -11,6 +11,7 @@ compatible = "pine64,rock64", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2io; mmc0 = &sdmmc; mmc1 = &emmc; }; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index a9f2536de2a..7c5067cf002 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -13,7 +13,7 @@ }; chosen { - u-boot,spl-boot-order = &emmc, &sdmmc; + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; }; dmc: dmc { @@ -26,45 +26,121 @@ 0x0 0xff720000 0x0 0x1000 0x0 0xff798000 0x0 0x1000>; }; - - rng: rng@ff060000 { - compatible = "rockchip,cryptov1-rng"; - reg = <0x0 0xff060000 0x0 0x4000>; - status = "okay"; - }; }; &cru { bootph-all; }; +&emmc { + bootph-pre-ram; + bootph-some-ram; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; +}; + +&emmc_bus8 { + bootph-pre-ram; +}; + +&emmc_clk { + bootph-pre-ram; +}; + +&emmc_cmd { + bootph-pre-ram; +}; + +&gpio0 { + bootph-pre-ram; +}; + &grf { bootph-all; }; -&uart2 { +&pcfg_pull_none { bootph-all; - clock-frequency = <24000000>; }; -&emmc { +&pcfg_pull_none_8ma { + bootph-pre-ram; +}; + +&pcfg_pull_none_12ma { + bootph-pre-ram; +}; + +&pcfg_pull_up { bootph-all; +}; - /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */ - u-boot,spl-fifo-mode; +&pcfg_pull_up_4ma { + bootph-pre-ram; +}; + +&pcfg_pull_up_8ma { + bootph-pre-ram; +}; + +&pcfg_pull_up_12ma { + bootph-pre-ram; +}; + +&pinctrl { + bootph-pre-ram; + bootph-some-ram; }; &sdmmc { - bootph-all; + bootph-pre-ram; + bootph-some-ram; - /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */ + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ u-boot,spl-fifo-mode; }; -&usb20_otg { - hnp-srp-disable; +&sdmmc0_bus4 { + bootph-pre-ram; }; -&spi0 { +&sdmmc0_clk { + bootph-pre-ram; +}; + +&sdmmc0_cmd { + bootph-pre-ram; +}; + +&sdmmc0_dectn { + bootph-pre-ram; +}; + +&sdmmc0m1_pin { + bootph-pre-ram; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; +}; + +&uart2m1_xfer { bootph-all; }; + +&vop { + bootph-all; +}; + +#ifdef CONFIG_ROCKCHIP_SPI_IMAGE +&binman { + simple-bin-spi { + mkimage { + args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; + offset = <0x8000>; + }; + }; +}; +#endif diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index e8d8f00be8a..fb5dcf6e932 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -20,6 +20,10 @@ #size-cells = <2>; aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -27,8 +31,6 @@ i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; - ethernet0 = &gmac2io; - ethernet1 = &gmac2phy; }; cpus { @@ -102,10 +104,12 @@ l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; - cpu0_opp_table: opp_table0 { + cpu0_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -306,6 +310,10 @@ }; power-domain@RK3328_PD_VIDEO { reg = <RK3328_PD_VIDEO>; + clocks = <&cru ACLK_RKVDEC>, + <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; #power-domain-cells = <0>; }; power-domain@RK3328_PD_VPU { @@ -489,7 +497,7 @@ status = "disabled"; }; - dmac: dmac@ff1f0000 { + dmac: dma-controller@ff1f0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff1f0000 0x0 0x4000>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, @@ -599,7 +607,7 @@ gpu: gpu@ff300000 { compatible = "rockchip,rk3328-mali", "arm,mali-450"; - reg = <0x0 0xff300000 0x0 0x40000>; + reg = <0x0 0xff300000 0x0 0x30000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, @@ -623,7 +631,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff330200 0 0x100>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "h265e_mmu"; clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; clock-names = "aclk", "iface"; #iommu-cells = <0>; @@ -634,7 +641,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff340800 0x0 0x40>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vepu_mmu"; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; clock-names = "aclk", "iface"; #iommu-cells = <0>; @@ -656,22 +662,34 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff350800 0x0 0x40>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vpu_mmu"; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; clock-names = "aclk", "iface"; #iommu-cells = <0>; power-domains = <&power RK3328_PD_VPU>; }; - rkvdec_mmu: iommu@ff360480 { + vdec: video-codec@ff360000 { + compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; + reg = <0x0 0xff360000 0x0 0x480>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; + assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + assigned-clock-rates = <400000000>, <400000000>, <300000000>; + iommus = <&vdec_mmu>; + power-domains = <&power RK3328_PD_VIDEO>; + }; + + vdec_mmu: iommu@ff360480 { compatible = "rockchip,iommu"; reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "rkvdec_mmu"; clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; - status = "disabled"; + power-domains = <&power RK3328_PD_VIDEO>; }; vop: vop@ff370000 { @@ -700,7 +718,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff373f00 0x0 0x100>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vop_mmu"; clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; clock-names = "aclk", "iface"; #iommu-cells = <0>; @@ -901,6 +918,8 @@ resets = <&cru SRST_GMAC2IO_A>; reset-names = "stmmaceth"; rockchip,grf = <&grf>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; snps,txpbl = <0x4>; status = "disabled"; }; @@ -923,6 +942,8 @@ reset-names = "stmmaceth"; phy-mode = "rmii"; phy-handle = <&phy>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; snps,txpbl = <0x4>; clock_in_out = "output"; status = "disabled"; @@ -944,6 +965,22 @@ }; }; + usb20_otg: usb@ff580000 { + compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff580000 0x0 0x40000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + usb_host0_ehci: usb@ff5c0000 { compatible = "generic-ehci"; reg = <0x0 0xff5c0000 0x0 0x10000>; @@ -983,31 +1020,6 @@ status = "disabled"; }; - /* - * U-Boot Specific Change - * - * The OTG controller must come after the USB host pair for it - * to work. This is likely due to lack of support for the USB - * PHYs. This must be manually changed after each device tree - * sync. There is no clean way to handle this in -u-boot.dtsi - * files. - */ - usb20_otg: usb@ff580000 { - compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff580000 0x0 0x40000>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - gic: interrupt-controller@ff811000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -1021,6 +1033,17 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + crypto: crypto@ff060000 { + compatible = "rockchip,rk3328-crypto"; + reg = <0x0 0xff060000 0x0 0x4000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>, + <&cru SCLK_CRYPTO>; + clock-names = "hclk_master", "hclk_slave", "sclk"; + resets = <&cru SRST_CRYPTO>; + reset-names = "crypto-rst"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3328-pinctrl"; rockchip,grf = <&grf>; @@ -1028,7 +1051,7 @@ #size-cells = <2>; ranges; - gpio0: gpio0@ff210000 { + gpio0: gpio@ff210000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff210000 0x0 0x100>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; @@ -1041,7 +1064,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@ff220000 { + gpio1: gpio@ff220000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff220000 0x0 0x100>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; @@ -1054,7 +1077,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@ff230000 { + gpio2: gpio@ff230000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff230000 0x0 0x100>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; @@ -1067,7 +1090,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio3@ff240000 { + gpio3: gpio@ff240000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff240000 0x0 0x100>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 3423b882c43..87b173e5957 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -30,7 +30,7 @@ }; rng: rng@ff8b8000 { - compatible = "rockchip,cryptov1-rng"; + compatible = "rockchip,rk3399-crypto"; reg = <0x0 0xff8b8000 0x0 0x1000>; status = "okay"; }; diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi index fa3df73c33d..791f16b206f 100644 --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi @@ -14,37 +14,6 @@ }; }; -&cru { - assigned-clocks = - <&pmucru CLK_RTC_32K>, - <&pmucru PLL_PPLL>, - <&pmucru PCLK_PMU>, <&cru PLL_CPLL>, - <&cru PLL_GPLL>, - <&cru ACLK_BUS>, <&cru PCLK_BUS>, - <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>, - <&cru HCLK_TOP>, <&cru PCLK_TOP>, - <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>, - <&cru CPLL_500M>, <&cru CPLL_333M>, - <&cru CPLL_250M>, <&cru CPLL_125M>, - <&cru CPLL_100M>, <&cru CPLL_62P5M>, - <&cru CPLL_50M>, <&cru CPLL_25M>; - assigned-clock-rates = - <32768>, - <200000000>, - <100000000>, <1000000000>, - <1188000000>, - <150000000>, <100000000>, - <500000000>, <400000000>, - <150000000>, <100000000>, - <300000000>, <150000000>, - <500000000>, <333333333>, - <250000000>, <125000000>, - <100000000>, <62500000>, - <50000000>, <25000000>; - assigned-clock-parents = - <&pmucru CLK_RTC32K_FRAC>; -}; - &dsi_dphy0 { status = "okay"; }; diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts index 404dddfafbf..c393c8d07af 100644 --- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts +++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dts @@ -12,7 +12,17 @@ * set the correct dtb name for loading mainline Linux automatically. */ model = "RGXX3"; - compatible = "anbernic,rg353m", "anbernic,rg353p", - "anbernic,rg353v", "anbernic,rg353vs", - "anbernic,rg503", "rockchip,rk3566"; + compatible = "anbernic,rg-arc-d", "anbernic,rg-arc-s", + "anbernic,rg353m", "anbernic,rg353p", + "anbernic,rg353ps", "anbernic,rg353v", + "anbernic,rg353vs", "anbernic,rg503", + "powkiddy,rgb10max3", "powkiddy,rgb30", + "powkiddy,rk2023", "rockchip,rk3566"; +}; + +&cru { + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, + <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates = <32768>, <1200000000>, + <200000000>, <241500000>; }; diff --git a/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi b/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi new file mode 100644 index 00000000000..4aa6ab1c848 --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk356x-u-boot.dtsi" + +&fspi_dual_io_pins { + bootph-all; +}; + +&gpio0 { + bootph-all; +}; + +&i2c0 { + bootph-pre-ram; +}; + +&rk817 { + bootph-pre-ram; + + regulators { + bootph-pre-ram; + }; +}; + +&sdhci { + cap-mmc-highspeed; +}; + +&sdmmc_pwren_l { + bootph-all; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + + flash@0 { + bootph-pre-ram; + }; +}; + +&vcc3v3_sd { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi b/arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi new file mode 100644 index 00000000000..061dc3c2c37 --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3566-pinetab2-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-pinetab2-v0.1.dts b/arch/arm/dts/rk3566-pinetab2-v0.1.dts new file mode 100644 index 00000000000..5fe6ca5da9d --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2-v0.1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-pinetab2.dtsi" + +/ { + model = "Pine64 PineTab2 v0.1"; + compatible = "pine64,pinetab2-v0.1", "pine64,pinetab2", "rockchip,rk3566"; +}; + +&lcd { + reset-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>; +}; + +&pinctrl { + lcd0 { + lcd0_rst_l: lcd0-rst-l { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc1 { + vmmc-supply = <&vcc3v3_sys>; +}; diff --git a/arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi b/arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi new file mode 100644 index 00000000000..061dc3c2c37 --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3566-pinetab2-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-pinetab2-v2.0.dts b/arch/arm/dts/rk3566-pinetab2-v2.0.dts new file mode 100644 index 00000000000..9349541cbbd --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2-v2.0.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-pinetab2.dtsi" + +/ { + model = "Pine64 PineTab2 v2.0"; + compatible = "pine64,pinetab2-v2.0", "pine64,pinetab2", "rockchip,rk3566"; +}; + +&gpio_keys { + pinctrl-0 = <&kb_id_det>, <&hall_int_l>; + + event-hall-sensor { + debounce-interval = <20>; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + label = "Hall Sensor"; + linux,code = <SW_LID>; + linux,input-type = <EV_SW>; + wakeup-event-action = <EV_ACT_DEASSERTED>; + wakeup-source; + }; +}; + +&lcd { + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>; +}; + +&pinctrl { + lcd0 { + lcd0_rst_l: lcd0-rst-l { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hall { + hall_int_l: hall-int-l { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc1 { + vmmc-supply = <&vcc_sys>; +}; diff --git a/arch/arm/dts/rk3566-pinetab2.dtsi b/arch/arm/dts/rk3566-pinetab2.dtsi new file mode 100644 index 00000000000..db40281eafb --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2.dtsi @@ -0,0 +1,943 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include <dt-bindings/usb/pd.h> +#include "rk3566.dtsi" + +/ { + chassis-type = "tablet"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <25>; + + button-vol-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <297500>; + }; + + button-vol-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <1750>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = <20 220>; + num-interpolated-steps = <200>; + default-brightness-level = <100>; + power-supply = <&vcc_sys>; + }; + + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <6000000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <2000000>; + constant-charge-voltage-max-microvolt = <4300000>; + voltage-max-design-microvolt = <4350000>; + voltage-min-design-microvolt = <3400000>; + + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4322000 100>, <4250000 95>, <4192000 90>, <4136000 85>, + <4080000 80>, <4022000 75>, <3972000 70>, <3928000 65>, + <3885000 60>, <3833000 55>, <3798000 50>, <3780000 45>, + <3776000 40>, <3773000 35>, <3755000 30>, <3706000 25>, + <3640000 20>, <3589000 15>, <3535000 10>, <3492000 5>, + <3400000 0>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&kb_id_det>; + + tablet-mode-switch { + debounce-interval = <20>; + gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + label = "Tablet Mode"; + linux,input-type = <EV_SW>; + linux,code = <SW_TABLET_MODE>; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + led-0 { + compatible = "regulator-led"; + vled-supply = <&vcc5v0_flashled>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_FLASH; + }; + + rk817-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det_l>; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rk817_ext"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + + simple-audio-card,routing = + "MICR", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "Speaker Amplifier OUTL", + "Internal Speakers", "Speaker Amplifier OUTR", + "Speaker Amplifier INL", "HPOL", + "Speaker Amplifier INR", "HPOR"; + simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + simple-audio-card,aux-devs = <&speaker_amp>; + simple-audio-card,pin-switches = "Internal Speakers"; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + }; + + speaker_amp: speaker-amplifier { + compatible = "simple-audio-amplifier"; + pinctrl-names = "default"; + pinctrl-0 = <&spk_ctl>; + enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + sound-name-prefix = "Speaker Amplifier"; + VCC-supply = <&vcc_bat>; + }; + + vcc_3v3: vcc-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_minipcie: vcc3v3-minipcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren_h>; + regulator-name = "vcc3v3_minipcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_sd: vcc3v3-sd-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren_l>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_flashled: vcc5v0-flashled-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&flash_led_en_h>; + regulator-name = "vcc5v0_flashled"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_midu>; + }; + + vcc5v0_usb_host0: vcc5v0-usb-host0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren1_h>; + regulator-name = "vcc5v0_usb_host0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_midu>; + }; + + vcc5v0_usb_host2: vcc5v0-usb-host2-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren2_h>; + regulator-name = "vcc5v0_usb_host2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_midu>; + }; + + vcc_bat: vcc-bat-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_bat"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_bat>; + }; + + vdd1v2_dvp: vdd1v2-dvp-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd1v2_dvp"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_3v3>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&cru { + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, + <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates = <32768>, <1200000000>, <200000000>, <500000000>; + assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; +}; + +&csi_dphy { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + clock-master; + #address-cells = <1>; + #size-cells = <0>; + + lcd: panel@0 { + compatible = "boe,th101mb31ig002-28a"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + rotation = <90>; + power-supply = <&vcc_3v3>; + + port@0 { + panel_in_dsi: endpoint@0 { + remote-endpoint = <&dsi0_out_con>; + }; + }; + }; +}; + +&dsi0_in { + dsi0_in_vp1: endpoint { + remote-endpoint = <&vp1_out_dsi0>; + }; +}; + +&dsi0_out { + dsi0_out_con: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; +}; + +&dsi_dphy0 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_npu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda_0v9_p>; + avdd-1v8-supply = <&vcc_1v8>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc5v_midu>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu_npu: DCDC_REG2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdda_0v9_p: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9_p"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v_midu: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vbus: OTG_SWITCH { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <300000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_l_pmuio2>, <&tp_rst_l_pmuio2>; + AVDD28-supply = <&vcc3v3_pmu>; + VDDIO-supply = <&vcca1v8_pmu>; + irq-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; + + vcm@c { + compatible = "dongwoon,dw9714"; + reg = <0x0c>; + vcc-supply = <&vcc1v8_dvp>; + }; + + camera@36 { + compatible = "ovti,ov5648"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&camerab_pdn_l &camerab_rst_l>; + + clocks = <&cru CLK_CIF_OUT>; + assigned-clocks = <&cru CLK_CIF_OUT>; + assigned-clock-rates = <24000000>; + + avdd-supply = <&vcc2v8_dvp>; + dvdd-supply = <&vdd1v2_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + powerdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + + port { + endpoint { + data-lanes = <1 2>; + remote-endpoint = <0>; + link-frequencies = /bits/ 64 <210000000 168000000>; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + accelerometer@18 { + compatible = "silan,sc7a20"; + reg = <0x18>; + interrupt-parent = <&gpio3>; + interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&gsensor_int_l>; + st,drdy-int-pin = <1>; + vdd-supply = <&vcc_1v8>; + vddio-supply = <&vcc_1v8>; + mount-matrix = "1", "0", "0", + "0", "0", "1", + "0", "1", "0"; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + +&pinctrl { + camerab { + camerab_pdn_l: camerab-pdn-l { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + camerab_rst_l: camerab-rst-l { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cameraf { + cameraf_pdn_l: cameraf-pdn-l { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cameraf_rst_l: cameraf-rst-l { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + flash { + flash_led_en_h: flash-led-en-h { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fspi { + fspi_dual_io_pins: fspi-dual-io-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + gsensor { + gsensor_int_l: gsensor-int-l { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + kb { + kb_id_det: kb-id-det { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_pwren_h: lcd-pwren-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwren_h: pcie-pwren-h { + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_pwren_l: sdmmc-pwren-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_det_l: hp-det-l { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + spk_ctl: spk-ctl { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tp { + tp_int_l_pmuio2: tp-int-l-pmuio2 { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + tp_rst_l_pmuio2: tp-rst-l-pmuio2 { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usbcc_int_l: usbcc-int-l { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host_pwren1_h: usb-host-pwren1-h { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host_pwren2_h: usb-host-pwren2-h { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + host_wake_wl: host-wake-wl { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcca1v8_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc1v8_dvp>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs200-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 + &emmc_clk + &emmc_cmd + &emmc_datastrobe + &emmc_rstnout>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 + &sdmmc0_clk + &sdmmc0_cmd + &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 + &sdmmc1_cmd + &sdmmc1_clk>; + sd-uhs-sdr104; + vqmmc-supply = <&vcca1v8_pmu>; + status = "okay"; +}; + +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspi_dual_io_pins>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host0>; + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host2>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&vp1 { + vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { + reg = <ROCKCHIP_VOP2_EP_MIPI0>; + remote-endpoint = <&dsi0_in_vp1>; + }; +}; diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi new file mode 100644 index 00000000000..ed15b14ea0e --- /dev/null +++ b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-u-boot.dtsi" + +&fspim2_pins { + bootph-all; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + status = "okay"; + + flash@0 { + bootph-pre-ram; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb.dts b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts new file mode 100644 index 00000000000..a4946cdc3bb --- /dev/null +++ b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include "rk3588-coolpi-cm5.dtsi" + +/ { + model = "RK3588 CoolPi CM5 EVB"; + compatible = "coolpi,pi-cm5-evb", "coolpi,pi-cm5", "rockchip,rk3588"; + + backlight: backlight { + compatible = "pwm-backlight"; + enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + power-supply = <&vcc12v_dcin>; + pwms = <&pwm2 0 25000 0>; + }; + + leds: leds { + compatible = "gpio-leds"; + + green_led: led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_lcd: vcc3v3-lcd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd"; + enable-active-high; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcdpwr_en>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_usb_host1: vcc5v0_usb_host2: vcc5v0-usb-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +/* M.2 E-Key */ +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreq &pcie_wake &pcie_rst &wifi_pwron &bt_pwron>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +/* Standard pcie */ +&pcie3x2 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +/* M.2 M-Key ssd */ +&pcie3x4 { + num-lanes = <2>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&pinctrl { + lcd { + lcdpwr_en: lcdpwr-en { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bl_en: bl-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + usb_otg_pwren: usb-otg-pwren { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + bt_pwron: bt-pwron { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pcie_clkreq: pcie-clkreq { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pcie_rst: pcie-rst { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_pwron: wifi-pwron { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pcie_wake: pcie-wake { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_usb_host1>; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_usb_host2>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-coolpi-cm5.dtsi b/arch/arm/dts/rk3588-coolpi-cm5.dtsi new file mode 100644 index 00000000000..9cb6d566da6 --- /dev/null +++ b/arch/arm/dts/rk3588-coolpi-cm5.dtsi @@ -0,0 +1,649 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588.dtsi" + +/ { + compatible = "coolpi,pi-cm5", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + analog-sound { + compatible = "audio-graph-card"; + dais = <&i2s0_8ch_p0>; + label = "rk3588-es8316"; + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + avdd0v85_pcie20: avdd0v85-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd0v85_pcie20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + avdd1v8_pcie20: avdd1v8-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd1v8_pcie20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + avdd0v75_pcie30: avdd0v75-pcie30-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd0v75_pcie30"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: avdd1v8-pcie30-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-rxid"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + pinctrl-names = "default"; + rx_delay = <0x00>; + tx_delay = <0x43>; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2c7 { + pinctrl-0 = <&i2c7m0_xfer>; + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@1 { + /* YT8531C/H */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&yt8531_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + +/* ethernet */ +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&yt6801_isolate>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + yt6801 { + yt6801_isolate: yt6801-isolate { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + yt8531 { + yt8531_rst: yt8531-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_2v0_pldo_s3>; + vcc14-supply = <&vcc_2v0_pldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi b/arch/arm/dts/rk3588-generic-u-boot.dtsi new file mode 100644 index 00000000000..853ed58cfe5 --- /dev/null +++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588s-u-boot.dtsi" diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts new file mode 100644 index 00000000000..e4721d97a87 --- /dev/null +++ b/arch/arm/dts/rk3588-generic.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Minimal generic DT for RK3588S/RK3588 with eMMC and SD-card enabled + */ + +/dts-v1/; +#include "rk3588s.dtsi" + +/ { + model = "Generic RK3588S/RK3588"; + compatible = "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-jaguar-u-boot.dtsi b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi new file mode 100644 index 00000000000..dcda4f99d6e --- /dev/null +++ b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH + */ + +#include "rk3588-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; +}; + +&emmc_pwrseq { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_reset { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdhci { + /* U-Boot currently cannot handle anything below HS200 for eMMC on RK3588 */ + /delete-property/ mmc-ddr-1_8v; + /delete-property/ cap-mmc-highspeed; +}; diff --git a/arch/arm/dts/rk3588-jaguar.dts b/arch/arm/dts/rk3588-jaguar.dts new file mode 100644 index 00000000000..4ce70fb75a3 --- /dev/null +++ b/arch/arm/dts/rk3588-jaguar.dts @@ -0,0 +1,803 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/usb/pd.h> +#include "rk3588.dtsi" + +/ { + model = "Theobroma Systems RK3588-SBC Jaguar"; + compatible = "tsd,rk3588-jaguar", "rockchip,rk3588"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + /* Can be controlled through SW2 but also GPIO1 on CP2102 on P20 */ + button-bios-disable { + label = "BIOS_DISABLE"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <0>; + }; + }; + + aliases { + ethernet0 = &gmac0; + mmc0 = &sdhci; + mmc1 = &sdmmc; + rtc0 = &rtc_twi; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + /* DCIN is 12-24V but standard is 12V */ + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led1_pin>; + status = "okay"; + + /* LED1 on PCB */ + led-1 { + gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + color = <LED_COLOR_ID_AMBER>; + }; + }; + + pps { + compatible = "pps-gpio"; + gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v2_s3: vcc-1v2-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v2_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* Exposed on P14 and P15 */ + vcc_2v8_s3: vcc-2v8-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_5v0_usb_a: vcc-5v0-usb-a-regulator { + compatible = "regulator-fixed"; + regulator-name = "usb_a_vcc"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc_5v0_usb_c1: vcc-5v0-usb-c1-regulator { + compatible = "regulator-fixed"; + regulator-name = "5v_usbc1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc_5v0_usb_c2: vcc-5v0-usb-c2-regulator { + compatible = "regulator-fixed"; + regulator-name = "5v_usbc2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc3v3_mdot2: vcc3v3-mdot2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_mdot2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy1_ps { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii"; + phy-supply = <&vcc_1v2_s3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_rx_bus2 + &gmac0_tx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + ð0_pins + ð_reset>; + tx_delay = <0x10>; + rx_delay = <0x10>; + snps,reset-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 100000>; + + status = "okay"; +}; + +&gpio1 { + mdot2e-w-disable1-n-hog { + gpios = <RK_PB1 GPIO_ACTIVE_LOW>; + output-low; + line-name = "m.2 E-key W_DISABLE1#"; + gpio-hog; + }; +}; + +&gpio4 { + mdot2e-w-disable2-n-hog { + gpios = <RK_PC1 GPIO_ACTIVE_LOW>; + output-low; + line-name = "m.2 E-key W_DISABLE2#"; + gpio-hog; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + }; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rtc_twi: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1m4_xfer>; +}; + +&i2c6 { + pinctrl-0 = <&i2c6m4_xfer>; +}; + +&i2c7 { + status = "okay"; + + /* SE050 Secure Element at 0x48; GPIO1_A4 for enable pin */ + + /* Also on 0x55 */ + eeprom@54 { + compatible = "st,24c04", "atmel,24c04"; + reg = <0x54>; + pagesize = <16>; + vcc-supply = <&vcc_3v3_s3>; + }; +}; + +&i2c8 { + pinctrl-0 = <&i2c8m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@6 { + /* KSZ9031 or KSZ9131 */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x6>; + clocks = <&cru REFCLKO25M_ETH0_OUT>; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; /* WIFI_PERST0# */ + vpcie3v3-supply = <&vcc3v3_mdot2>; + status = "okay"; +}; + +&pinctrl { + emmc { + emmc_reset: emmc-reset { + rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet { + eth_reset: eth-reset { + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led1_pin: led1-pin { + rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + mmc-pwrseq = <&emmc_pwrseq>; + no-sdio; + no-sd; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>; + supports-cqe; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc_1v8_s3>; + status = "okay"; +}; + +&sdmmc { + broken-cd; + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_cmd &sdmmc_clk>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-name = "vcca_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-name = "vdda_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-name = "vcca_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdda_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdda_0v75_s0: nldo-reg3 { + regulator-name = "vdda_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-name = "vdda_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc_5v0_usb_a>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +/* Mule-ATtiny debug UART; typically baudrate 9600 */ +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +/* Main debug interface on P20 micro-USB B port and P21 header */ +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +/* RS485 on P19 */ +&uart3 { + pinctrl-0 = <&uart3m2_xfer &uart3_rtsn>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +/* Mule-ATtiny UPDI flashing UART */ +&uart7 { + pinctrl-0 = <&uart7m0_xfer>; + status = "okay"; +}; + +/* host0 on P10 USB-A */ +&usb_host0_ehci { + status = "okay"; +}; + +/* host0 on P10 USB-A */ +&usb_host0_ohci { + status = "okay"; +}; + +/* host1 on M.2 E-key */ +&usb_host1_ehci { + status = "okay"; +}; + +/* host1 on M.2 E-key */ +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi b/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi new file mode 100644 index 00000000000..1aeb5410e43 --- /dev/null +++ b/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include "rk3588-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci; + }; +}; diff --git a/arch/arm/dts/rk3588-toybrick-x0.dts b/arch/arm/dts/rk3588-toybrick-x0.dts new file mode 100644 index 00000000000..9090c5c99f2 --- /dev/null +++ b/arch/arm/dts/rk3588-toybrick-x0.dts @@ -0,0 +1,688 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588.dtsi" + +/ { + model = "Rockchip Toybrick TB-RK3588X Board"; + compatible = "rockchip,rk3588-toybrick-x0", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-vol-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <17000>; + }; + + button-vol-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <417000>; + }; + + button-menu { + label = "Menu"; + linux,code = <KEY_MENU>; + press-threshold-microvolt = <890000>; + }; + + button-escape { + label = "Escape"; + linux,code = <KEY_ESC>; + press-threshold-microvolt = <1235000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc12v_dcin>; + pwms = <&pwm2 0 25000 0>; + }; + + pcie20_avdd0v85: pcie20-avdd0v85-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-rxid"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + pinctrl-names = "default"; + rx_delay = <0x00>; + tx_delay = <0x43>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi new file mode 100644 index 00000000000..6e4b97028d7 --- /dev/null +++ b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588s-u-boot.dtsi" + +&fspim2_pins { + bootph-all; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + status = "okay"; + + flash@0 { + bootph-pre-ram; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; diff --git a/arch/arm/dts/rk3588s-coolpi-4b.dts b/arch/arm/dts/rk3588s-coolpi-4b.dts new file mode 100644 index 00000000000..e037bf9db75 --- /dev/null +++ b/arch/arm/dts/rk3588s-coolpi-4b.dts @@ -0,0 +1,812 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588s.dtsi" + +/ { + model = "RK3588S CoolPi 4 Model B"; + compatible = "coolpi,pi-4b", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + analog-sound { + compatible = "audio-graph-card"; + dais = <&i2s0_8ch_p0>; + label = "rk3588-es8316"; + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_leds>; + + led0: led-green { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led1: led-red { + color = <LED_COLOR_ID_RED>; + default-state = "off"; + function = LED_FUNCTION_WLAN; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + avdd0v85_pcie20: avdd0v85-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd0v85_pcie20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + avdd1v8_pcie20: avdd1v8-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd1v8_pcie20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc3v3_mipi: vcc3v3-mipi-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_mipi"; + regulator-boot-on; + regulator-always-on; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_u3host_en>; + regulator-name = "vcc5v0_otg"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + }; +}; + +&i2c7 { + pinctrl-0 = <&i2c7m0_xfer>; + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&rtl8111_isolate>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + led { + gpio_leds: gpio-leds { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>, + <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + rtl8111 { + rtl8111_isolate: rtl8111-isolate { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_u3host_en: vcc5v0-u3host-en { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + bt_reset_gpio: bt-reset-pin { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_irq: bt-wake-host-irq { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_pin: wifi-poweren-pin { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + pinctrl-0 = <&pwm2m1_pins>; + status = "okay"; +}; + +&pwm13 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm13m2_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + max-frequency = <150000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-sd; + no-mmc; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>,<&wifi_poweren_pin>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +/* bt */ +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index bf3b1ea8a3c..ac67c777ade 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -188,11 +188,13 @@ &sdmmc { bootph-pre-ram; + bootph-some-ram; u-boot,spl-fifo-mode; }; &sdhci { bootph-pre-ram; + bootph-some-ram; u-boot,spl-fifo-mode; }; diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi index 746a5ba347e..a17c58cbfcd 100644 --- a/arch/arm/dts/sama7g5.dtsi +++ b/arch/arm/dts/sama7g5.dtsi @@ -871,6 +871,30 @@ }; }; + flx10: flexcom@e2820000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe2820000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe2820000 0x800>; + status = "disabled"; + + i2c10: i2c@600 { + compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; + atmel,fifo-size = <32>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>, + <&dma0 AT91_XDMAC_DT_PERID(25)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + flx11: flexcom@e2824000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe2824000 0x200>; diff --git a/arch/arm/dts/sdm845-db845c-u-boot.dtsi b/arch/arm/dts/sdm845-db845c-u-boot.dtsi new file mode 100644 index 00000000000..906f9faa545 --- /dev/null +++ b/arch/arm/dts/sdm845-db845c-u-boot.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Needed for Linux to boot from USB, otherwise if PCIe driver is not in initramfs + * the VBUS supply will never get turned on. + * https://lore.kernel.org/linux-arm-msm/20240320122515.3243711-1-caleb.connolly@linaro.org/ + */ +&pcie0_3p3v_dual { + regulator-always-on; +}; diff --git a/arch/arm/dts/sdm845-db845c.dts b/arch/arm/dts/sdm845-db845c.dts new file mode 100644 index 00000000000..c7eba6c491b --- /dev/null +++ b/arch/arm/dts/sdm845-db845c.dts @@ -0,0 +1,1190 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019, Linaro Ltd. + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/sound/qcom,q6afe.h> +#include <dt-bindings/sound/qcom,q6asm.h> +#include "sdm845.dtsi" +#include "sdm845-wcd9340.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" + +/ { + model = "Thundercomm Dragonboard 845c"; + compatible = "thundercomm,db845c", "qcom,sdm845"; + qcom,msm-id = <341 0x20001>; + qcom,board-id = <8 0>; + + aliases { + serial0 = &uart9; + serial1 = &uart6; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* Fixed crystal oscillator dedicated to MCP2517FD */ + clk40M: can-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + + dc12v: dc12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "DC12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_pin_a>; + + key-vol-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "green:user4"; + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pm8998_gpios 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "panic-indicator"; + default-state = "off"; + }; + + led-1 { + label = "yellow:wlan"; + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_YELLOW>; + gpios = <&pm8998_gpios 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + led-2 { + label = "blue:bt"; + function = LED_FUNCTION_BLUETOOTH; + color = <LED_COLOR_ID_BLUE>; + gpios = <&pm8998_gpios 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + reserved-memory { + /* Cont splash region set up by the bootloader */ + cont_splash_mem: framebuffer@9d400000 { + reg = <0x0 0x9d400000 0x0 0x2400000>; + no-map; + }; + }; + + lt9611_1v8: lt9611-vdd18-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V8"; + + vin-supply = <&vdc_5v>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + lt9611_3v3: lt9611-3v3 { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + + vin-supply = <&vdc_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + /* + * TODO: make it possible to drive same GPIO from two clients + * gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; + * enable-active-high; + */ + }; + + pcie0_1p05v: pcie-0-1p05v-regulator { + compatible = "regulator-fixed"; + regulator-name = "PCIE0_1.05V"; + + vin-supply = <&vbat>; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + + /* + * TODO: make it possible to drive same GPIO from two clients + * gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; + * enable-active-high; + */ + }; + + cam0_dvdd_1v2: cam0-dvdd-1v2-regulator { + compatible = "regulator-fixed"; + regulator-name = "CAM0_DVDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + enable-active-high; + gpio = <&pm8998_gpios 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_dvdd_1v2_en_default>; + vin-supply = <&vbat>; + }; + + cam0_avdd_2v8: cam0-avdd-2v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "CAM0_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&pm8998_gpios 10 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_avdd_2v8_en_default>; + vin-supply = <&vbat>; + }; + + /* This regulator is enabled when the VREG_LVS1A_1P8 trace is enabled */ + cam3_avdd_2v8: cam3-avdd-2v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "CAM3_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + vin-supply = <&vbat>; + }; + + pcie0_3p3v_dual: vldo-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "VLDO_3V3"; + + vin-supply = <&vbat>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pwren_state>; + }; + + v5p0_hdmiout: v5p0-hdmiout-regulator { + compatible = "regulator-fixed"; + regulator-name = "V5P0_HDMIOUT"; + + vin-supply = <&vdc_5v>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <500000>; + + /* + * TODO: make it possible to drive same GPIO from two clients + * gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; + * enable-active-high; + */ + }; + + vbat: vbat-regulator { + compatible = "regulator-fixed"; + regulator-name = "VBAT"; + + vin-supply = <&dc12v>; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + }; + + vbat_som: vbat-som-regulator { + compatible = "regulator-fixed"; + regulator-name = "VBAT_SOM"; + + vin-supply = <&dc12v>; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + }; + + vdc_3v3: vdc-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "VDC_3V3"; + vin-supply = <&dc12v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdc_5v: vdc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "VDC_5V"; + + vin-supply = <&dc12v>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <500000>; + regulator-always-on; + }; + + vreg_s4a_1p8: vreg-s4a-1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + + vin-supply = <&vbat_som>; + }; +}; + +&adsp_pas { + status = "okay"; + + firmware-name = "qcom/sdm845/adsp.mbn"; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + vdd-s13-supply = <&vph_pwr>; + vdd-l1-l27-supply = <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; + vdd-l3-l11-supply = <&vreg_s7a_1p025>; + vdd-l4-l5-supply = <&vreg_s7a_1p025>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + vdd-l9-supply = <&vreg_bob>; + vdd-l10-l23-l25-supply = <&vreg_bob>; + vdd-l13-l19-l21-supply = <&vreg_bob>; + vdd-l16-l28-supply = <&vreg_bob>; + vdd-l18-l22-supply = <&vreg_bob>; + vdd-l20-l24-supply = <&vreg_bob>; + vdd-l26-supply = <&vreg_s3a_1p35>; + vin-lvs-1-2-supply = <&vreg_s4a_1p8>; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2968000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2968000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + + regulators-1 { + compatible = "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-bypass; + }; + }; +}; + +&camss { + status = "okay"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; +}; + +&cdsp_pas { + status = "okay"; + firmware-name = "qcom/sdm845/cdsp.mbn"; +}; + +&gcc { + protected-clocks = <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <GCC_LPASS_Q6_AXI_CLK>, + <GCC_LPASS_SWAY_CLK>; +}; + +&gmu { + status = "okay"; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sdm845/a630_zap.mbn"; + }; +}; + +&i2c10 { + status = "okay"; + clock-frequency = <400000>; + + lt9611_codec: hdmi-bridge@3b { + compatible = "lontium,lt9611"; + reg = <0x3b>; + #sound-dai-cells = <1>; + + interrupts-extended = <&tlmm 84 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v8>; + vcc-supply = <<9611_3v3>; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_irq_pin>, <&dsi_sw_sel>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + lt9611_b: endpoint { + remote-endpoint = <&mdss_dsi1_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&i2c11 { + /* On Low speed expansion */ + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c14 { + /* On Low speed expansion */ + clock-frequency = <100000>; + status = "okay"; +}; + +&mdss { + memory-region = <&cont_splash_mem>; + status = "okay"; +}; + +&mdss_dsi0 { + status = "okay"; + vdda-supply = <&vreg_l26a_1p2>; + + qcom,dual-dsi-mode; + qcom,master-dsi; + + ports { + port@1 { + endpoint { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l1a_0p875>; +}; + +&mdss_dsi1 { + vdda-supply = <&vreg_l26a_1p2>; + + qcom,dual-dsi-mode; + + /* DSI1 is slave, so use DSI0 clocks */ + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + status = "okay"; + + ports { + port@1 { + endpoint { + remote-endpoint = <<9611_b>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&mdss_dsi1_phy { + vdds-supply = <&vreg_l1a_0p875>; + status = "okay"; +}; + +&mss_pil { + status = "okay"; + firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn"; +}; + +&pcie0 { + status = "okay"; + perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>; + + vddpe-3v3-supply = <&pcie0_3p3v_dual>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; +}; + +&pcie0_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; +}; + +&pcie1 { + status = "okay"; + perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; +}; + +&pcie1_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; +}; + +&pm8998_gpios { + gpio-line-names = + "NC", + "NC", + "WLAN_SW_CTRL", + "NC", + "PM_GPIO5_BLUE_BT_LED", + "VOL_UP_N", + "NC", + "ADC_IN1", + "PM_GPIO9_YEL_WIFI_LED", + "CAM0_AVDD_EN", + "NC", + "CAM0_DVDD_EN", + "PM_GPIO13_GREEN_U4_LED", + "DIV_CLK2", + "NC", + "NC", + "NC", + "SMB_STAT", + "NC", + "NC", + "ADC_IN2", + "OPTION1", + "WCSS_PWR_REQ", + "PM845_GPIO24", + "OPTION2", + "PM845_SLB"; + + cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en-state { + pins = "gpio12"; + function = "normal"; + + bias-pull-up; + drive-push-pull; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; + }; + + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state { + pins = "gpio10"; + function = "normal"; + + bias-pull-up; + drive-push-pull; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; + }; + + vol_up_pin_a: vol-up-active-state { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; + }; +}; + +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pmi8998_lpg { + status = "okay"; + + qcom,power-source = <1>; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <3>; + + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led@4 { + reg = <4>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + }; + + led@5 { + reg = <5>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + }; +}; + +/* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */ +&q6afedai { + dai@22 { + reg = <QUATERNARY_MI2S_RX>; + qcom,sd-lines = <0 1 2 3>; + }; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; + + dai@3 { + reg = <3>; + direction = <2>; + is-compress-dai; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; + + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vreg_l13a_2p95>; + + bus-width = <4>; + cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; +}; + +&sound { + compatible = "qcom,db845c-sndcard", "qcom,sdm845-sndcard"; + pinctrl-0 = <&quat_mi2s_active + &quat_mi2s_sd0_active + &quat_mi2s_sd1_active + &quat_mi2s_sd2_active + &quat_mi2s_sd3_active>; + pinctrl-names = "default"; + model = "DB845c"; + audio-routing = + "RX_BIAS", "MCLK", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "DMIC0", "MIC BIAS1", + "DMIC1", "MIC BIAS1", + "DMIC2", "MIC BIAS3", + "DMIC3", "MIC BIAS3", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT", + "MM_DL1", "MultiMedia1 Playback", + "MM_DL2", "MultiMedia2 Playback", + "MM_DL4", "MultiMedia4 Playback", + "MultiMedia3 Capture", "MM_UL3"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + mm4-dai-link { + link-name = "MultiMedia4"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA4>; + }; + }; + + hdmi-dai-link { + link-name = "HDMI Playback"; + cpu { + sound-dai = <&q6afedai QUATERNARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <<9611_codec 0>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 1>; + }; + }; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + cs-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; + + can@0 { + compatible = "microchip,mcp2517fd"; + reg = <0>; + clocks = <&clk40M>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <10000000>; + vdd-supply = <&vdc_5v>; + xceiver-supply = <&vdc_5v>; + }; +}; + +&spi2 { + /* On Low speed expansion */ + status = "okay"; +}; + +&tlmm { + cam0_default: cam0-default-state { + rst-pins { + pins = "gpio9"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + }; + + mclk0-pins { + pins = "gpio13"; + function = "cam_mclk"; + + drive-strength = <16>; + bias-disable; + }; + }; + + cam3_default: cam3-default-state { + rst-pins { + function = "gpio"; + pins = "gpio21"; + + drive-strength = <16>; + bias-disable; + }; + + mclk3-pins { + function = "cam_mclk"; + pins = "gpio16"; + + drive-strength = <16>; + bias-disable; + }; + }; + + dsi_sw_sel: dsi-sw-sel-state { + pins = "gpio120"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + output-high; + }; + + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio84"; + function = "gpio"; + bias-disable; + }; + + pcie0_default_state: pcie0-default-state { + clkreq-pins { + pins = "gpio36"; + function = "pci_e0"; + bias-pull-up; + }; + + reset-n-pins { + pins = "gpio35"; + function = "gpio"; + + drive-strength = <2>; + output-low; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio37"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_pwren_state: pcie0-pwren-state { + pins = "gpio90"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + pcie1_default_state: pcie1-default-state { + perst-n-pins { + pins = "gpio102"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + }; + + clkreq-pins { + pins = "gpio103"; + function = "pci_e1"; + bias-pull-up; + }; + + wake-n-pins { + pins = "gpio11"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + + reset-n-pins { + pins = "gpio75"; + function = "gpio"; + + drive-strength = <16>; + bias-pull-up; + output-high; + }; + }; + + sdc2_default_state: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + + /* + * It seems that mmc_test reports errors if drive + * strength is not 16 on clk, cmd, and data pins. + */ + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio126"; + function = "gpio"; + bias-pull-up; + }; +}; + +&uart3 { + label = "LS-UART0"; + pinctrl-0 = <&qup_uart3_4pin>; + + status = "disabled"; +}; + +&uart6 { + status = "okay"; + + pinctrl-0 = <&qup_uart6_4pin>; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; + }; +}; + +&uart9 { + label = "LS-UART1"; + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdd-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; + qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; + qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l26a_1p2>; + vdda-pll-supply = <&vreg_l1a_0p875>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdd-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>; +}; + +&usb_2_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l26a_1p2>; + vdda-pll-supply = <&vreg_l1a_0p875>; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <800000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; +}; + +&venus { + status = "okay"; +}; + +&wcd9340 { + reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + + swm: swm@c85 { + left_spkr: speaker@0,1 { + compatible = "sdw10217201000"; + reg = <0 1>; + powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #sound-dai-cells = <0>; + }; + + right_spkr: speaker@0,2 { + compatible = "sdw10217201000"; + powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; + reg = <0 2>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrRight"; + #sound-dai-cells = <0>; + }; + }; +}; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + + qcom,snoc-host-cap-8bit-quirk; + qcom,ath10k-calibration-variant = "Thundercomm_DB845C"; +}; + +/* PINCTRL - additions to nodes defined in sdm845.dtsi */ +&qup_spi2_default { + drive-strength = <16>; +}; + +&qup_i2c10_default { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart9_rx { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_uart9_tx { + drive-strength = <2>; + bias-disable; +}; + +/* PINCTRL - additions to nodes defined in sdm845.dtsi */ +&qup_spi0_default { + drive-strength = <6>; + bias-disable; +}; diff --git a/arch/arm/dts/sdm845-samsung-starqltechn-u-boot.dtsi b/arch/arm/dts/sdm845-samsung-starqltechn-u-boot.dtsi new file mode 100644 index 00000000000..c78bd6e9240 --- /dev/null +++ b/arch/arm/dts/sdm845-samsung-starqltechn-u-boot.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + chosen { + stdout-path = "serial0:921600n8"; + }; +}; + +&tlmm { + muic-i2c-n { + pins = "gpio33", "gpio34"; + drive-strength = <0x2>; + function = "gpio"; + bias-disable; + }; +}; diff --git a/arch/arm/dts/sdm845-samsung-starqltechn.dts b/arch/arm/dts/sdm845-samsung-starqltechn.dts new file mode 100644 index 00000000000..d37a433130b --- /dev/null +++ b/arch/arm/dts/sdm845-samsung-starqltechn.dts @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM845 Samsung S9 (SM-G9600) (starqltechn / star2qltechn) common device tree source + * + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sdm845.dtsi" + +/ { + chassis-type = "handset"; + model = "Samsung Galaxy S9 SM-G9600"; + compatible = "samsung,starqltechn", "qcom,sdm845"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + framebuffer: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;//2400000 + width = <1440>; + height = <2960>; + stride = <(1440 * 4)>; + format = "a8r8g8b8"; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + /* + * Apparently RPMh does not provide support for PM8998 S4 because it + * is always-on; model it as a fixed regulator. + */ + vreg_s4a_1p8: pm8998-smps4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + reserved-memory { + memory@9d400000 { + reg = <0x0 0x9d400000 0x0 0x02400000>; + no-map; + }; + + memory@a1300000 { + compatible = "ramoops"; + reg = <0x0 0xa1300000 0x0 0x100000>; + record-size = <0x40000>; + console-size = <0x40000>; + ftrace-size = <0x40000>; + pmsg-size = <0x40000>; + }; + }; +}; + + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + vdd-s13-supply = <&vph_pwr>; + vdd-l1-l27-supply = <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; + vdd-l3-l11-supply = <&vreg_s7a_1p025>; + vdd-l4-l5-supply = <&vreg_s7a_1p025>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + vdd-l26-supply = <&vreg_s3a_1p35>; + vin-lvs-1-2-supply = <&vreg_s4a_1p8>; + + vreg_s2a_1p125: smps2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vdd_qusb_hs0: + vdda_hp_pcie_core: + vdda_mipi_csi0_0p9: + vdda_mipi_csi1_0p9: + vdda_mipi_csi2_0p9: + vdda_mipi_dsi0_pll: + vdda_mipi_dsi1_pll: + vdda_qlink_lv: + vdda_qlink_lv_ck: + vdda_qrefs_0p875: + vdda_pcie_core: + vdda_pll_cc_ebi01: + vdda_pll_cc_ebi23: + vdda_sp_sensor: + vdda_ufs1_core: + vdda_ufs2_core: + vdda_usb1_ss_core: + vdda_usb2_ss_core: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vddpx_10: + vreg_l2a_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdd_wcss_cx: + vdd_wcss_mx: + vdda_wcss_pll: + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vddpx_13: + vreg_l6a_1p8: ldo6 { + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <1856000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8a_1p2: ldo8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1248000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9a_1p8: ldo9 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11a_1p0: ldo11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1048000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdd_qfprom: + vdd_qfprom_sp: + vdda_apc1_cs_1p8: + vdda_gfx_cs_1p8: + vdda_qrefs_1p8: + vdda_qusb_hs0_1p8: + vddpx_11: + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vddpx_2: + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14a_1p88: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l18a_2p7: ldo18 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l19a_3p0: ldo19 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l22a_2p85: ldo22 { + regulator-min-microvolt = <2864000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l23a_3p3: ldo23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdda_qusb_hs0_3p1: + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdda_hp_pcie_1p2: + vdda_hv_ebi0: + vdda_hv_ebi1: + vdda_hv_ebi2: + vdda_hv_ebi3: + vdda_mipi_csi_1p25: + vdda_mipi_dsi0_1p2: + vdda_mipi_dsi1_1p2: + vdda_pcie_1p2: + vdda_ufs1_1p2: + vdda_ufs2_1p2: + vdda_usb1_ss_1p2: + vdda_usb2_ss_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l28a_3p0: ldo28 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s3c_0p6: smps3 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + }; + }; +}; + +&gcc { + protected-clocks = <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <GCC_LPASS_Q6_AXI_CLK>, + <GCC_LPASS_SWAY_CLK>; +}; + +&i2c10 { + clock-frequency = <400000>; + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&uart9 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; + status = "okay"; +}; + +&sdhc_2 { + pinctrl-names = "default"; + pinctrl-0 = <&sdc2_clk_state &sdc2_cmd_state &sdc2_data_state &sd_card_det_n_state>; + cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vddpx_2>; + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + /* Until we have Type C hooked up we'll force this as peripheral. */ + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; + qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; + qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vdda_usb1_ss_1p2>; + vdda-pll-supply = <&vdda_usb1_ss_core>; + status = "okay"; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <27 4>, <81 4>, <85 4>; + + sdc2_clk_state: sdc2-clk-state { + pins = "sdc2_clk"; + bias-disable; + + /* + * It seems that mmc_test reports errors if drive + * strength is not 16 on clk, cmd, and data pins. + */ + drive-strength = <16>; + }; + + sdc2_cmd_state: sdc2-cmd-state { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <16>; + }; + + sdc2_data_state: sdc2-data-state { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <16>; + }; + + sd_card_det_n_state: sd-card-det-n-state { + pins = "gpio126"; + function = "gpio"; + bias-pull-up; + }; +}; diff --git a/arch/arm/dts/sdm845-wcd9340.dtsi b/arch/arm/dts/sdm845-wcd9340.dtsi new file mode 100644 index 00000000000..c15d4886064 --- /dev/null +++ b/arch/arm/dts/sdm845-wcd9340.dtsi @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM845 SoC device tree source + * + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +&slim { + status = "okay"; + + slim@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + + wcd9340_ifd: ifd@0,0 { + compatible = "slim217,250"; + reg = <0 0>; + }; + + wcd9340: codec@1,0 { + compatible = "slim217,250"; + reg = <1 0>; + slim-ifc-dev = <&wcd9340_ifd>; + + #sound-dai-cells = <1>; + + interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + clock-names = "extclk"; + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; + + #clock-cells = <0>; + clock-frequency = <9600000>; + clock-output-names = "mclk"; + + pinctrl-0 = <&wcd_intr_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + + #address-cells = <1>; + #size-cells = <1>; + + wcdgpio: gpio-controller@42 { + compatible = "qcom,wcd9340-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x42 0x2>; + }; + + swm: swm@c85 { + compatible = "qcom,soundwire-v1.3.0"; + reg = <0xc85 0x40>; + interrupts-extended = <&wcd9340 20>; + + qcom,dout-ports = <6>; + qcom,din-ports = <2>; + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x7 0x1f 0x3f 0x0f 0x0f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x6 0x12 0x0d 0x07 0x0a>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1f 0x00 0x00 0x1f 0x00 0x00>; + + #sound-dai-cells = <1>; + clocks = <&wcd9340>; + clock-names = "iface"; + #address-cells = <2>; + #size-cells = <0>; + }; + }; + }; +}; + +&tlmm { + wcd_intr_default: wcd-intr-default-state { + pins = "gpio54"; + function = "gpio"; + + bias-pull-down; + drive-strength = <2>; + }; +}; diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi index 96c9749a52c..bf5e6eb9d31 100644 --- a/arch/arm/dts/sdm845.dtsi +++ b/arch/arm/dts/sdm845.dtsi @@ -1,119 +1,5752 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* - * Qualcomm SDM845 chip device tree source - * - * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> + * SDM845 SoC device tree source * + * Copyright (c) 2018, The Linux Foundation. All rights reserved. */ -/dts-v1/; - +#include <dt-bindings/clock/qcom,camcc-sdm845.h> +#include <dt-bindings/clock/qcom,dispcc-sdm845.h> #include <dt-bindings/clock/qcom,gcc-sdm845.h> -#include "skeleton64.dtsi" +#include <dt-bindings/clock/qcom,gpucc-sdm845.h> +#include <dt-bindings/clock/qcom,lpass-sdm845.h> +#include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,videocc-sdm845.h> +#include <dt-bindings/dma/qcom-gpi.h> +#include <dt-bindings/firmware/qcom,scm.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interconnect/qcom,osm-l3.h> +#include <dt-bindings/interconnect/qcom,sdm845.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy-qcom-qmp.h> +#include <dt-bindings/phy/phy-qcom-qusb2.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/reset/qcom,sdm845-aoss.h> +#include <dt-bindings/reset/qcom,sdm845-pdc.h> +#include <dt-bindings/soc/qcom,apr.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/clock/qcom,gcc-sdm845.h> +#include <dt-bindings/thermal/thermal.h> / { - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + i2c14 = &i2c14; + i2c15 = &i2c15; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + spi5 = &spi5; + spi6 = &spi6; + spi7 = &spi7; + spi8 = &spi8; + spi9 = &spi9; + spi10 = &spi10; + spi11 = &spi11; + spi12 = &spi12; + spi13 = &spi13; + spi14 = &spi14; + spi15 = &spi15; + }; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + }; + }; + + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + capacity-dmips-mhz = <611>; + dynamic-power-coefficient = <154>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + capacity-dmips-mhz = <611>; + dynamic-power-coefficient = <154>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + #cooling-cells = <2>; + next-level-cache = <&L2_100>; + L2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + capacity-dmips-mhz = <611>; + dynamic-power-coefficient = <154>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + #cooling-cells = <2>; + next-level-cache = <&L2_200>; + L2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + capacity-dmips-mhz = <611>; + dynamic-power-coefficient = <154>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + #cooling-cells = <2>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + next-level-cache = <&L2_300>; + L2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x400>; + clocks = <&cpufreq_hw 1>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <442>; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + #cooling-cells = <2>; + next-level-cache = <&L2_400>; + L2_400: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x500>; + clocks = <&cpufreq_hw 1>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <442>; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + #cooling-cells = <2>; + next-level-cache = <&L2_500>; + L2_500: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <442>; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + #cooling-cells = <2>; + next-level-cache = <&L2_600>; + L2_600: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x700>; + clocks = <&cpufreq_hw 1>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <442>; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + #cooling-cells = <2>; + next-level-cache = <&L2_700>; + L2_700: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + cpu_idle_states: idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <350>; + exit-latency-us = <461>; + min-residency-us = <1890>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <264>; + exit-latency-us = <621>; + min-residency-us = <952>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100c244>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9987>; + }; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-sdm845", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <800000 4800000>; + }; + + cpu0_opp2: opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + opp-peak-kBps = <800000 4800000>; + }; + + cpu0_opp3: opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-peak-kBps = <800000 6451200>; + }; + + cpu0_opp4: opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <800000 6451200>; + }; + + cpu0_opp5: opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-peak-kBps = <800000 7680000>; + }; + + cpu0_opp6: opp-748800000 { + opp-hz = /bits/ 64 <748800000>; + opp-peak-kBps = <1804000 9216000>; + }; + + cpu0_opp7: opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-peak-kBps = <1804000 9216000>; + }; + + cpu0_opp8: opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <1804000 10444800>; + }; + + cpu0_opp9: opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-peak-kBps = <1804000 11980800>; + }; + + cpu0_opp10: opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <1804000 11980800>; + }; + + cpu0_opp11: opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + opp-peak-kBps = <2188000 13516800>; + }; + + cpu0_opp12: opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-peak-kBps = <2188000 15052800>; + }; + + cpu0_opp13: opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <2188000 16588800>; + }; + + cpu0_opp14: opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; + opp-peak-kBps = <3072000 18124800>; + }; + + cpu0_opp15: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <3072000 19353600>; + }; + + cpu0_opp16: opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <4068000 19353600>; + }; + + cpu0_opp17: opp-1689600000 { + opp-hz = /bits/ 64 <1689600000>; + opp-peak-kBps = <4068000 20889600>; + }; + + cpu0_opp18: opp-1766400000 { + opp-hz = /bits/ 64 <1766400000>; + opp-peak-kBps = <4068000 22425600>; + }; + }; + + cpu4_opp_table: opp-table-cpu4 { + compatible = "operating-points-v2"; + opp-shared; + + cpu4_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <800000 4800000>; + }; + + cpu4_opp2: opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + opp-peak-kBps = <800000 4800000>; + }; + + cpu4_opp3: opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-peak-kBps = <1804000 4800000>; + }; + + cpu4_opp4: opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <1804000 4800000>; + }; + + cpu4_opp5: opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-peak-kBps = <1804000 4800000>; + }; + + cpu4_opp6: opp-748800000 { + opp-hz = /bits/ 64 <748800000>; + opp-peak-kBps = <1804000 4800000>; + }; + + cpu4_opp7: opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-peak-kBps = <2188000 9216000>; + }; + + cpu4_opp8: opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <2188000 9216000>; + }; + + cpu4_opp9: opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-peak-kBps = <2188000 9216000>; + }; + + cpu4_opp10: opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <3072000 9216000>; + }; + + cpu4_opp11: opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + opp-peak-kBps = <3072000 11980800>; + }; + + cpu4_opp12: opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-peak-kBps = <4068000 11980800>; + }; + + cpu4_opp13: opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <4068000 11980800>; + }; + + cpu4_opp14: opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <4068000 15052800>; + }; + + cpu4_opp15: opp-1459200000 { + opp-hz = /bits/ 64 <1459200000>; + opp-peak-kBps = <4068000 15052800>; + }; + + cpu4_opp16: opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <5412000 15052800>; + }; + + cpu4_opp17: opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <5412000 15052800>; + }; + + cpu4_opp18: opp-1689600000 { + opp-hz = /bits/ 64 <1689600000>; + opp-peak-kBps = <5412000 19353600>; + }; + + cpu4_opp19: opp-1766400000 { + opp-hz = /bits/ 64 <1766400000>; + opp-peak-kBps = <6220000 19353600>; + }; + + cpu4_opp20: opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + opp-peak-kBps = <6220000 19353600>; + }; + + cpu4_opp21: opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-peak-kBps = <7216000 19353600>; + }; + + cpu4_opp22: opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + opp-peak-kBps = <7216000 20889600>; + }; + + cpu4_opp23: opp-2092800000 { + opp-hz = /bits/ 64 <2092800000>; + opp-peak-kBps = <7216000 20889600>; + }; + + cpu4_opp24: opp-2169600000 { + opp-hz = /bits/ 64 <2169600000>; + opp-peak-kBps = <7216000 20889600>; + }; + + cpu4_opp25: opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + opp-peak-kBps = <7216000 20889600>; + }; + + cpu4_opp26: opp-2323200000 { + opp-hz = /bits/ 64 <2323200000>; + opp-peak-kBps = <7216000 20889600>; + }; + + cpu4_opp27: opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-peak-kBps = <7216000 22425600>; + }; + + cpu4_opp28: opp-2476800000 { + opp-hz = /bits/ 64 <2476800000>; + opp-peak-kBps = <7216000 22425600>; + }; + + cpu4_opp29: opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <7216000 22425600>; + }; + + cpu4_opp30: opp-2649600000 { + opp-hz = /bits/ 64 <2649600000>; + opp-peak-kBps = <7216000 22425600>; + }; + + cpu4_opp31: opp-2745600000 { + opp-hz = /bits/ 64 <2745600000>; + opp-peak-kBps = <7216000 25497600>; + }; + + cpu4_opp32: opp-2803200000 { + opp-hz = /bits/ 64 <2803200000>; + opp-peak-kBps = <7216000 25497600>; + }; + }; + + dsi_opp_table: opp-table-dsi { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-328580000 { + opp-hz = /bits/ 64 <328580000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + qspi_opp_table: opp-table-qspi { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp-mem@85700000 { + reg = <0 0x85700000 0 0x600000>; + no-map; + }; + + xbl_mem: xbl-mem@85e00000 { + reg = <0 0x85e00000 0 0x100000>; + no-map; + }; + + aop_mem: aop-mem@85fc0000 { + reg = <0 0x85fc0000 0 0x20000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x85fe0000 0 0x20000>; + no-map; + }; + + smem@86000000 { + compatible = "qcom,smem"; + reg = <0x0 0x86000000 0 0x200000>; + no-map; + hwlocks = <&tcsr_mutex 3>; + }; + + tz_mem: tz@86200000 { + reg = <0 0x86200000 0 0x2d00000>; + no-map; + }; + + rmtfs_mem: rmtfs@88f00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0x88f00000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + qseecom_mem: qseecom@8ab00000 { + reg = <0 0x8ab00000 0 0x1400000>; + no-map; + }; + + camera_mem: camera-mem@8bf00000 { + reg = <0 0x8bf00000 0 0x500000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@8c400000 { + reg = <0 0x8c400000 0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@8c410000 { + reg = <0 0x8c410000 0 0x5000>; + no-map; + }; + + gpu_mem: gpu@8c415000 { + reg = <0 0x8c415000 0 0x2000>; + no-map; + }; + + adsp_mem: adsp@8c500000 { + reg = <0 0x8c500000 0 0x1a00000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@8df00000 { + reg = <0 0x8df00000 0 0x100000>; + no-map; + }; + + mpss_region: mpss@8e000000 { + reg = <0 0x8e000000 0 0x7800000>; + no-map; + }; + + venus_mem: venus@95800000 { + reg = <0 0x95800000 0 0x500000>; + no-map; + }; + + cdsp_mem: cdsp@95d00000 { + reg = <0 0x95d00000 0 0x800000>; + no-map; + }; + + mba_region: mba@96500000 { + reg = <0 0x96500000 0 0x200000>; + no-map; + }; + + slpi_mem: slpi@96700000 { + reg = <0 0x96700000 0 0x1400000>; + no-map; + }; + + spss_mem: spss@97b00000 { + reg = <0 0x97b00000 0 0x100000>; + no-map; + }; + + mdata_mem: mpss-metadata { + alloc-ranges = <0 0xa0000000 0 0x20000000>; + size = <0 0x4000>; + no-map; + }; + + fastrpc_mem: fastrpc { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + reusable; + }; + }; + + adsp_pas: remoteproc-adsp { + compatible = "qcom,sdm845-adsp-pas"; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + memory-region = <&adsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; + label = "lpass"; + qcom,remote-pid = <2>; + mboxes = <&apss_shared 8>; + + apr { + compatible = "qcom,apr-v2"; + qcom,glink-channels = "apr_audio_svc"; + qcom,domain = <APR_DOMAIN_ADSP>; + #address-cells = <1>; + #size-cells = <0>; + qcom,intents = <512 20>; + + service@3 { + reg = <APR_SVC_ADSP_CORE>; + compatible = "qcom,q6core"; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + + q6afe: service@4 { + compatible = "qcom,q6afe"; + reg = <APR_SVC_AFE>; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + q6afedai: dais { + compatible = "qcom,q6afe-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + }; + }; + + q6asm: service@7 { + compatible = "qcom,q6asm"; + reg = <APR_SVC_ASM>; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + q6asmdai: dais { + compatible = "qcom,q6asm-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + iommus = <&apps_smmu 0x1821 0x0>; + }; + }; + + q6adm: service@8 { + compatible = "qcom,q6adm"; + reg = <APR_SVC_ADM>; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + q6routing: routing { + compatible = "qcom,q6adm-routing"; + #sound-dai-cells = <0>; + }; + }; + }; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1823 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1824 0x0>; + }; + }; + }; + }; + + cdsp_pas: remoteproc-cdsp { + compatible = "qcom,sdm845-cdsp-pas"; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + memory-region = <&cdsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; + label = "turing"; + qcom,remote-pid = <5>; + mboxes = <&apss_shared 4>; + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x1401 0x30>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x1402 0x30>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1403 0x30>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1404 0x30>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1405 0x30>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1406 0x30>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1407 0x30>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1408 0x30>; + }; + }; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + + interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apss_shared 6>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-lpass { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apss_shared 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apss_shared 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-slpi { + compatible = "qcom,smp2p"; + qcom,smem = <481>, <430>; + interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apss_shared 26>; + qcom,local-pid = <0>; + qcom,remote-pid = <3>; + + slpi_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + slpi_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; compatible = "simple-bus"; gcc: clock-controller@100000 { compatible = "qcom,gcc-sdm845"; - reg = <0x100000 0x1f0000>; + reg = <0 0x00100000 0 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&pcie0_phy>, + <&pcie1_phy>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk", + "pcie_0_pipe_clk", + "pcie_1_pipe_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SDM845_CX>; }; - tlmm: pinctrl@3400000 { - compatible = "qcom,sdm845-pinctrl"; - reg = <0x3400000 0xc00000>; - gpio-count = <150>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 150>; + qfprom@784000 { + compatible = "qcom,sdm845-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x8ff>; + #address-cells = <1>; + #size-cells = <1>; - /* DEBUG UART */ - qup_uart9: qup-uart9-default { - pins = "GPIO_4", "GPIO_5"; - function = "qup9"; + qusb2p_hstx_trim: hstx-trim-primary@1eb { + reg = <0x1eb 0x1>; + bits = <1 4>; + }; + + qusb2s_hstx_trim: hstx-trim-secondary@1eb { + reg = <0x1eb 0x2>; + bits = <6 4>; }; }; + rng: rng@793000 { + compatible = "qcom,prng-ee"; + reg = <0 0x00793000 0 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + gpi_dma0: dma-controller@800000 { + #dma-cells = <3>; + compatible = "qcom,sdm845-gpi-dma"; + reg = <0 0x00800000 0 0x60000>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + iommus = <&apps_smmu 0x0016 0x0>; + status = "disabled"; + }; + + qupv3_id_0: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x008c0000 0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core"; + status = "disabled"; + + i2c0: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi0: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart0: serial@880000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart0_default>; + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c1: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00884000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_default>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi1: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00884000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_default>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart1: serial@884000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00884000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart1_default>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c2: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi2: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi2_default>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart2: serial@888000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart2_default>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c3: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c3_default>; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi3: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi3_default>; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart3: serial@88c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart3_default>; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c4: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_default>; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi4: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_default>; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart4: serial@890000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart4_default>; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c5: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_default>; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi5: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi5_default>; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart5: serial@894000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart5_default>; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c6: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00898000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_default>; + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi6: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00898000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi6_default>; + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart6: serial@898000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00898000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart6_default>; + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c7: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0089c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c7_default>; + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + + spi7: spi@89c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0089c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi7_default>; + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart7: serial@89c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x0089c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart7_default>; + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + #dma-cells = <3>; + compatible = "qcom,sdm845-gpi-dma"; + reg = <0 0x00a00000 0 0x60000>; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + iommus = <&apps_smmu 0x06d6 0x0>; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; - reg = <0x00ac0000 0x6000>; - #address-cells = <1>; - #size-cells = <1>; + reg = <0 0x00ac0000 0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x6c3 0x0>; + #address-cells = <2>; + #size-cells = <2>; ranges; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core"; + status = "disabled"; + + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a80000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_default>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a80000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi8_default>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart8: serial@a80000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a80000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart8_default>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c9_default>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a84000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi9_default>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; uart9: serial@a84000 { compatible = "qcom,geni-debug-uart"; - reg = <0xa84000 0x4000>; + reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_uart9>; + pinctrl-0 = <&qup_uart9_default>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_default>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi10_default>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart10: serial@a88000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart10_default>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c11_default>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a8c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi11_default>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart11: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a8c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart11_default>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a90000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c12_default>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a90000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi12_default>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart12: serial@a90000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a90000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart12_default>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c13_default>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi13_default>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart13: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart13_default>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a98000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c14_default>; + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi14: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a98000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi14_default>; + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart14: serial@a98000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a98000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart14_default>; + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a9c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c15_default>; + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + }; + + spi15: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a9c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi15_default>; + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart15: serial@a9c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a9c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart15_default>; + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + }; + + llcc: system-cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; + }; + + dma@10a2000 { + compatible = "qcom,sdm845-dcc", "qcom,dcc"; + reg = <0x0 0x010a2000 0x0 0x1000>, + <0x0 0x010ae000 0x0 0x2000>; + }; + + pmu@114a000 { + compatible = "qcom,sdm845-llcc-bwmon"; + reg = <0 0x0114a000 0 0x1000>; + interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* + * The interconnect path bandwidth taken from + * cpu4_opp_table bandwidth for gladiator_noc-mem_noc + * interconnect. This also matches the + * bandwidth table of qcom,llccbw (qcom,bw-tbl, + * bus width: 4 bytes) from msm-4.9 downstream + * kernel. + */ + opp-0 { + opp-peak-kBps = <800000>; + }; + opp-1 { + opp-peak-kBps = <1804000>; + }; + opp-2 { + opp-peak-kBps = <3072000>; + }; + opp-3 { + opp-peak-kBps = <5412000>; + }; + opp-4 { + opp-peak-kBps = <7216000>; + }; + }; + }; + + pmu@1436400 { + compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x01436400 0 0x600>; + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* + * The interconnect path bandwidth taken from + * cpu4_opp_table bandwidth for OSM L3 + * interconnect. This also matches the OSM L3 + * from bandwidth table of qcom,cpu4-l3lat-mon + * (qcom,core-dev-table, bus width: 16 bytes) + * from msm-4.9 downstream kernel. + */ + opp-0 { + opp-peak-kBps = <4800000>; + }; + opp-1 { + opp-peak-kBps = <9216000>; + }; + opp-2 { + opp-peak-kBps = <15052800>; + }; + opp-3 { + opp-peak-kBps = <20889600>; + }; + opp-4 { + opp-peak-kBps = <25497600>; + }; + }; + }; + + pcie0: pci@1c00000 { + compatible = "qcom,pcie-sdm845"; + reg = <0 0x01c00000 0 0x2000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60100000 0 0x100000>, + <0 0x01c07000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "config", "mhi"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu"; + + iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, + <0x100 &apps_smmu 0x1c11 0x1>, + <0x200 &apps_smmu 0x1c12 0x1>, + <0x300 &apps_smmu 0x1c13 0x1>, + <0x400 &apps_smmu 0x1c14 0x1>, + <0x500 &apps_smmu 0x1c15 0x1>, + <0x600 &apps_smmu 0x1c16 0x1>, + <0x700 &apps_smmu 0x1c17 0x1>, + <0x800 &apps_smmu 0x1c18 0x1>, + <0x900 &apps_smmu 0x1c19 0x1>, + <0xa00 &apps_smmu 0x1c1a 0x1>, + <0xb00 &apps_smmu 0x1c1b 0x1>, + <0xc00 &apps_smmu 0x1c1c 0x1>, + <0xd00 &apps_smmu 0x1c1d 0x1>, + <0xe00 &apps_smmu 0x1c1e 0x1>, + <0xf00 &apps_smmu 0x1c1f 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie0_phy: phy@1c06000 { + compatible = "qcom,sdm845-qmp-pcie-phy"; + reg = <0 0x01c06000 0 0x1000>; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + }; + + pcie1: pci@1c08000 { + compatible = "qcom,pcie-sdm845"; + reg = <0 0x01c08000 0 0x2000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40100000 0 0x100000>, + <0 0x01c0c000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "config", "mhi"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>, + <0x200 &apps_smmu 0x1c02 0x1>, + <0x300 &apps_smmu 0x1c03 0x1>, + <0x400 &apps_smmu 0x1c04 0x1>, + <0x500 &apps_smmu 0x1c05 0x1>, + <0x600 &apps_smmu 0x1c06 0x1>, + <0x700 &apps_smmu 0x1c07 0x1>, + <0x800 &apps_smmu 0x1c08 0x1>, + <0x900 &apps_smmu 0x1c09 0x1>, + <0xa00 &apps_smmu 0x1c0a 0x1>, + <0xb00 &apps_smmu 0x1c0b 0x1>, + <0xc00 &apps_smmu 0x1c0c 0x1>, + <0xd00 &apps_smmu 0x1c0d 0x1>, + <0xe00 &apps_smmu 0x1c0e 0x1>, + <0xf00 &apps_smmu 0x1c0f 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_1_GDSC>; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie1_phy: phy@1c0a000 { + compatible = "qcom,sdm845-qhp-pcie-phy"; + reg = <0 0x01c0a000 0 0x2000>; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_PCIE_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + }; + + mem_noc: interconnect@1380000 { + compatible = "qcom,sdm845-mem-noc"; + reg = <0 0x01380000 0 0x27200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + dc_noc: interconnect@14e0000 { + compatible = "qcom,sdm845-dc-noc"; + reg = <0 0x014e0000 0 0x400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect@1500000 { + compatible = "qcom,sdm845-config-noc"; + reg = <0 0x01500000 0 0x5080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sdm845-system-noc"; + reg = <0 0x01620000 0 0x18080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sdm845-aggre1-noc"; + reg = <0 0x016e0000 0 0x15080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sdm845-aggre2-noc"; + reg = <0 0x01700000 0 0x1f300>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sdm845-mmss-noc"; + reg = <0 0x01740000 0 0x1c100>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sdm845-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x2500>, + <0 0x01d90000 0 0x8000>; + reg-names = "std", "ice"; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + power-domains = <&gcc UFS_PHY_GDSC>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + iommus = <&apps_smmu 0x100 0xf>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk", + "ice_core_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <75000000 300000000>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sdm845-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0x18c>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: phy@1d87400 { + reg = <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x108>, + <0 0x01d87a00 0 0x1e0>; + #phy-cells = <0>; }; }; - spmi@c440000 { + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x24000>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rpmhcc RPMH_CE_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + iommus = <&apps_smmu 0x704 0x1>, + <&apps_smmu 0x706 0x1>, + <&apps_smmu 0x714 0x1>, + <&apps_smmu 0x716 0x1>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,crypto-v5.4"; + reg = <0 0x01dfa000 0 0x6000>; + clocks = <&gcc GCC_CE1_AHB_CLK>, + <&gcc GCC_CE1_AXI_CLK>, + <&rpmhcc RPMH_CE_CLK>; + clock-names = "iface", "bus", "core"; + dmas = <&cryptobam 6>, <&cryptobam 7>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x704 0x1>, + <&apps_smmu 0x706 0x1>, + <&apps_smmu 0x714 0x1>, + <&apps_smmu 0x716 0x1>; + }; + + ipa: ipa@1e40000 { + compatible = "qcom,sdm845-ipa"; + + iommus = <&apps_smmu 0x720 0x0>, + <&apps_smmu 0x722 0x0>; + reg = <0 0x01e40000 0 0x7000>, + <0 0x01e47000 0 0x2000>, + <0 0x01e04000 0 0x2c000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, + <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; + interconnect-names = "memory", + "imem", + "config"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + status = "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0 0x01f40000 0 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr_regs_1: syscon@1f60000 { + compatible = "qcom,sdm845-tcsr", "syscon"; + reg = <0 0x01f60000 0 0x20000>; + }; + + tlmm: pinctrl@3400000 { + compatible = "qcom,sdm845-pinctrl"; + reg = <0 0x03400000 0 0xc00000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 151>; + wakeup-parent = <&pdc_intc>; + + cci0_default: cci0-default-state { + /* SDA, SCL */ + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci0_sleep: cci0-sleep-state { + /* SDA, SCL */ + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + + cci1_default: cci1-default-state { + /* SDA, SCL */ + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci1_sleep: cci1-sleep-state { + /* SDA, SCL */ + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + + qspi_clk: qspi-clk-state { + pins = "gpio95"; + function = "qspi_clk"; + }; + + qspi_cs0: qspi-cs0-state { + pins = "gpio90"; + function = "qspi_cs"; + }; + + qspi_cs1: qspi-cs1-state { + pins = "gpio89"; + function = "qspi_cs"; + }; + + qspi_data0: qspi-data0-state { + pins = "gpio91"; + function = "qspi_data"; + }; + + qspi_data1: qspi-data1-state { + pins = "gpio92"; + function = "qspi_data"; + }; + + qspi_data23: qspi-data23-state { + pins = "gpio93", "gpio94"; + function = "qspi_data"; + }; + + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0"; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio17", "gpio18"; + function = "qup1"; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio27", "gpio28"; + function = "qup2"; + }; + + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio41", "gpio42"; + function = "qup3"; + }; + + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio89", "gpio90"; + function = "qup4"; + }; + + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio85", "gpio86"; + function = "qup5"; + }; + + qup_i2c6_default: qup-i2c6-default-state { + pins = "gpio45", "gpio46"; + function = "qup6"; + }; + + qup_i2c7_default: qup-i2c7-default-state { + pins = "gpio93", "gpio94"; + function = "qup7"; + }; + + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio65", "gpio66"; + function = "qup8"; + }; + + qup_i2c9_default: qup-i2c9-default-state { + pins = "gpio6", "gpio7"; + function = "qup9"; + }; + + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio55", "gpio56"; + function = "qup10"; + }; + + qup_i2c11_default: qup-i2c11-default-state { + pins = "gpio31", "gpio32"; + function = "qup11"; + }; + + qup_i2c12_default: qup-i2c12-default-state { + pins = "gpio49", "gpio50"; + function = "qup12"; + }; + + qup_i2c13_default: qup-i2c13-default-state { + pins = "gpio105", "gpio106"; + function = "qup13"; + }; + + qup_i2c14_default: qup-i2c14-default-state { + pins = "gpio33", "gpio34"; + function = "qup14"; + }; + + qup_i2c15_default: qup-i2c15-default-state { + pins = "gpio81", "gpio82"; + function = "qup15"; + }; + + qup_spi0_default: qup-spi0-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qup0"; + }; + + qup_spi1_default: qup-spi1-default-state { + pins = "gpio17", "gpio18", "gpio19", "gpio20"; + function = "qup1"; + }; + + qup_spi2_default: qup-spi2-default-state { + pins = "gpio27", "gpio28", "gpio29", "gpio30"; + function = "qup2"; + }; + + qup_spi3_default: qup-spi3-default-state { + pins = "gpio41", "gpio42", "gpio43", "gpio44"; + function = "qup3"; + }; + + qup_spi4_default: qup-spi4-default-state { + pins = "gpio89", "gpio90", "gpio91", "gpio92"; + function = "qup4"; + }; + + qup_spi5_default: qup-spi5-default-state { + pins = "gpio85", "gpio86", "gpio87", "gpio88"; + function = "qup5"; + }; + + qup_spi6_default: qup-spi6-default-state { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "qup6"; + }; + + qup_spi7_default: qup-spi7-default-state { + pins = "gpio93", "gpio94", "gpio95", "gpio96"; + function = "qup7"; + }; + + qup_spi8_default: qup-spi8-default-state { + pins = "gpio65", "gpio66", "gpio67", "gpio68"; + function = "qup8"; + }; + + qup_spi9_default: qup-spi9-default-state { + pins = "gpio6", "gpio7", "gpio4", "gpio5"; + function = "qup9"; + }; + + qup_spi10_default: qup-spi10-default-state { + pins = "gpio55", "gpio56", "gpio53", "gpio54"; + function = "qup10"; + }; + + qup_spi11_default: qup-spi11-default-state { + pins = "gpio31", "gpio32", "gpio33", "gpio34"; + function = "qup11"; + }; + + qup_spi12_default: qup-spi12-default-state { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + function = "qup12"; + }; + + qup_spi13_default: qup-spi13-default-state { + pins = "gpio105", "gpio106", "gpio107", "gpio108"; + function = "qup13"; + }; + + qup_spi14_default: qup-spi14-default-state { + pins = "gpio33", "gpio34", "gpio31", "gpio32"; + function = "qup14"; + }; + + qup_spi15_default: qup-spi15-default-state { + pins = "gpio81", "gpio82", "gpio83", "gpio84"; + function = "qup15"; + }; + + qup_uart0_default: qup-uart0-default-state { + qup_uart0_tx: tx-pins { + pins = "gpio2"; + function = "qup0"; + }; + + qup_uart0_rx: rx-pins { + pins = "gpio3"; + function = "qup0"; + }; + }; + + qup_uart1_default: qup-uart1-default-state { + qup_uart1_tx: tx-pins { + pins = "gpio19"; + function = "qup1"; + }; + + qup_uart1_rx: rx-pins { + pins = "gpio20"; + function = "qup1"; + }; + }; + + qup_uart2_default: qup-uart2-default-state { + qup_uart2_tx: tx-pins { + pins = "gpio29"; + function = "qup2"; + }; + + qup_uart2_rx: rx-pins { + pins = "gpio30"; + function = "qup2"; + }; + }; + + qup_uart3_default: qup-uart3-default-state { + qup_uart3_tx: tx-pins { + pins = "gpio43"; + function = "qup3"; + }; + + qup_uart3_rx: rx-pins { + pins = "gpio44"; + function = "qup3"; + }; + }; + + qup_uart3_4pin: qup-uart3-4pin-state { + qup_uart3_4pin_cts: cts-pins { + pins = "gpio41"; + function = "qup3"; + }; + + qup_uart3_4pin_rts_tx: rts-tx-pins { + pins = "gpio42", "gpio43"; + function = "qup3"; + }; + + qup_uart3_4pin_rx: rx-pins { + pins = "gpio44"; + function = "qup3"; + }; + }; + + qup_uart4_default: qup-uart4-default-state { + qup_uart4_tx: tx-pins { + pins = "gpio91"; + function = "qup4"; + }; + + qup_uart4_rx: rx-pins { + pins = "gpio92"; + function = "qup4"; + }; + }; + + qup_uart5_default: qup-uart5-default-state { + qup_uart5_tx: tx-pins { + pins = "gpio87"; + function = "qup5"; + }; + + qup_uart5_rx: rx-pins { + pins = "gpio88"; + function = "qup5"; + }; + }; + + qup_uart6_default: qup-uart6-default-state { + qup_uart6_tx: tx-pins { + pins = "gpio47"; + function = "qup6"; + }; + + qup_uart6_rx: rx-pins { + pins = "gpio48"; + function = "qup6"; + }; + }; + + qup_uart6_4pin: qup-uart6-4pin-state { + qup_uart6_4pin_cts: cts-pins { + pins = "gpio45"; + function = "qup6"; + bias-pull-down; + }; + + qup_uart6_4pin_rts_tx: rts-tx-pins { + pins = "gpio46", "gpio47"; + function = "qup6"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart6_4pin_rx: rx-pins { + pins = "gpio48"; + function = "qup6"; + bias-pull-up; + }; + }; + + qup_uart7_default: qup-uart7-default-state { + qup_uart7_tx: tx-pins { + pins = "gpio95"; + function = "qup7"; + }; + + qup_uart7_rx: rx-pins { + pins = "gpio96"; + function = "qup7"; + }; + }; + + qup_uart8_default: qup-uart8-default-state { + qup_uart8_tx: tx-pins { + pins = "gpio67"; + function = "qup8"; + }; + + qup_uart8_rx: rx-pins { + pins = "gpio68"; + function = "qup8"; + }; + }; + + qup_uart9_default: qup-uart9-default-state { + qup_uart9_tx: tx-pins { + pins = "gpio4"; + function = "qup9"; + }; + + qup_uart9_rx: rx-pins { + pins = "gpio5"; + function = "qup9"; + }; + }; + + qup_uart10_default: qup-uart10-default-state { + qup_uart10_tx: tx-pins { + pins = "gpio53"; + function = "qup10"; + }; + + qup_uart10_rx: rx-pins { + pins = "gpio54"; + function = "qup10"; + }; + }; + + qup_uart11_default: qup-uart11-default-state { + qup_uart11_tx: tx-pins { + pins = "gpio33"; + function = "qup11"; + }; + + qup_uart11_rx: rx-pins { + pins = "gpio34"; + function = "qup11"; + }; + }; + + qup_uart12_default: qup-uart12-default-state { + qup_uart12_tx: tx-pins { + pins = "gpio51"; + function = "qup0"; + }; + + qup_uart12_rx: rx-pins { + pins = "gpio52"; + function = "qup0"; + }; + }; + + qup_uart13_default: qup-uart13-default-state { + qup_uart13_tx: tx-pins { + pins = "gpio107"; + function = "qup13"; + }; + + qup_uart13_rx: rx-pins { + pins = "gpio108"; + function = "qup13"; + }; + }; + + qup_uart14_default: qup-uart14-default-state { + qup_uart14_tx: tx-pins { + pins = "gpio31"; + function = "qup14"; + }; + + qup_uart14_rx: rx-pins { + pins = "gpio32"; + function = "qup14"; + }; + }; + + qup_uart15_default: qup-uart15-default-state { + qup_uart15_tx: tx-pins { + pins = "gpio83"; + function = "qup15"; + }; + + qup_uart15_rx: rx-pins { + pins = "gpio84"; + function = "qup15"; + }; + }; + + quat_mi2s_sleep: quat-mi2s-sleep-state { + pins = "gpio58", "gpio59"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + quat_mi2s_active: quat-mi2s-active-state { + pins = "gpio58", "gpio59"; + function = "qua_mi2s"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state { + pins = "gpio60"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { + pins = "gpio60"; + function = "qua_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state { + pins = "gpio61"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { + pins = "gpio61"; + function = "qua_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { + pins = "gpio62"; + function = "qua_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { + pins = "gpio63"; + function = "qua_mi2s"; + drive-strength = <8>; + bias-disable; + }; + }; + + mss_pil: remoteproc@4080000 { + compatible = "qcom,sdm845-mss-pil"; + reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = + <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", + "shutdown-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&gcc GCC_PRNG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bus", "mem", "gpll0_mss", + "snoc_axi", "mnoc_axi", "prng", "xo"; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; + + power-domains = <&rpmhpd SDM845_CX>, + <&rpmhpd SDM845_MX>, + <&rpmhpd SDM845_MSS>; + power-domain-names = "cx", "mx", "mss"; + + status = "disabled"; + + mba { + memory-region = <&mba_region>; + }; + + mpss { + memory-region = <&mpss_region>; + }; + + metadata { + memory-region = <&mdata_mem>; + }; + + glink-edge { + interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apss_shared 12>; + }; + }; + + gpucc: clock-controller@5090000 { + compatible = "qcom,sdm845-gpucc"; + reg = <0 0x05090000 0 0x9000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + }; + + slpi_pas: remoteproc@5c00000 { + compatible = "qcom,sdm845-slpi-pas"; + reg = <0 0x5c00000 0 0x4000>; + + interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + qcom,qmp = <&aoss_qmp>; + + power-domains = <&rpmhpd SDM845_CX>, + <&rpmhpd SDM845_MX>; + power-domain-names = "lcx", "lmx"; + + memory-region = <&slpi_mem>; + + qcom,smem-states = <&slpi_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; + label = "dsps"; + qcom,remote-pid = <3>; + mboxes = <&apss_shared 24>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "sdsp"; + qcom,non-secure-domain; + qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA + QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>; + memory-region = <&fastrpc_mem>; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@0 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <0>; + }; + }; + }; + }; + + stm@6002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x06002000 0 0x1000>, + <0 0x16280000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = + <&funnel0_in7>; + }; + }; + }; + }; + + funnel@6041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06041000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = + <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@6043000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06043000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel2_out: endpoint { + remote-endpoint = + <&merge_funnel_in2>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + funnel2_in5: endpoint { + remote-endpoint = + <&apss_merge_funnel_out>; + }; + }; + }; + }; + + funnel@6045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06045000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = + <&funnel0_out>; + }; + }; + + port@2 { + reg = <2>; + merge_funnel_in2: endpoint { + remote-endpoint = + <&funnel2_out>; + }; + }; + }; + }; + + replicator@6046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x06046000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + replicator_out: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etf@6047000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06047000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = + <&replicator_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + etf_in: endpoint { + remote-endpoint = + <&merge_funnel_out>; + }; + }; + }; + }; + + etr@6048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06048000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = + <&replicator_out>; + }; + }; + }; + }; + + etm@7040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07040000 0 0x1000>; + + cpu = <&CPU0>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&apss_funnel_in0>; + }; + }; + }; + }; + + etm@7140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07140000 0 0x1000>; + + cpu = <&CPU1>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&apss_funnel_in1>; + }; + }; + }; + }; + + etm@7240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07240000 0 0x1000>; + + cpu = <&CPU2>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&apss_funnel_in2>; + }; + }; + }; + }; + + etm@7340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07340000 0 0x1000>; + + cpu = <&CPU3>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&apss_funnel_in3>; + }; + }; + }; + }; + + etm@7440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07440000 0 0x1000>; + + cpu = <&CPU4>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = + <&apss_funnel_in4>; + }; + }; + }; + }; + + etm@7540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07540000 0 0x1000>; + + cpu = <&CPU5>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = + <&apss_funnel_in5>; + }; + }; + }; + }; + + etm@7640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07640000 0 0x1000>; + + cpu = <&CPU6>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = + <&apss_funnel_in6>; + }; + }; + }; + }; + + etm@7740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07740000 0 0x1000>; + + cpu = <&CPU7>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = + <&apss_funnel_in7>; + }; + }; + }; + }; + + funnel@7800000 { /* APSS Funnel */ + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07800000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel_in0: endpoint { + remote-endpoint = + <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel_in1: endpoint { + remote-endpoint = + <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel_in2: endpoint { + remote-endpoint = + <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel_in3: endpoint { + remote-endpoint = + <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel_in4: endpoint { + remote-endpoint = + <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel_in5: endpoint { + remote-endpoint = + <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel_in6: endpoint { + remote-endpoint = + <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel_in7: endpoint { + remote-endpoint = + <&etm7_out>; + }; + }; + }; + }; + + funnel@7810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07810000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = + <&funnel2_in5>; + }; + }; + }; + + in-ports { + port { + apss_merge_funnel_in: endpoint { + remote-endpoint = + <&apss_funnel_out>; + }; + }; + }; + }; + + sdhc_2: mmc@8804000 { + compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0xa0 0xf>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-9600000 { + opp-hz = /bits/ 64 <9600000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-201500000 { + opp-hz = /bits/ 64 <201500000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + qspi: spi@88df000 { + compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; + reg = <0 0x088df000 0 0x600>; + iommus = <&apps_smmu 0x160 0x0>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <&gcc GCC_QSPI_CORE_CLK>; + clock-names = "iface", "core"; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&qspi_opp_table>; + status = "disabled"; + }; + + slim: slim-ngd@171c0000 { + compatible = "qcom,slim-ngd-v2.1.0"; + reg = <0 0x171c0000 0 0x2c000>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + + dmas = <&slimbam 3>, <&slimbam 4>; + dma-names = "rx", "tx"; + + iommus = <&apps_smmu 0x1806 0x0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + lmh_cluster1: lmh@17d70800 { + compatible = "qcom,sdm845-lmh"; + reg = <0 0x17d70800 0 0x400>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + cpus = <&CPU4>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + lmh_cluster0: lmh@17d78800 { + compatible = "qcom,sdm845-lmh"; + reg = <0 0x17d78800 0 0x400>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + cpus = <&CPU0>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + usb_1_hsphy: phy@88e2000 { + compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; + reg = <0 0x088e2000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + nvmem-cells = <&qusb2p_hstx_trim>; + }; + + usb_2_hsphy: phy@88e3000 { + compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; + reg = <0 0x088e3000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + + nvmem-cells = <&qusb2s_hstx_trim>; + }; + + usb_1_qmpphy: phy@88e8000 { + compatible = "qcom,sdm845-qmp-usb3-dp-phy"; + reg = <0 0x088e8000 0 0x3000>; + status = "disabled"; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe", + "cfg_ahb"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + }; + + usb_2_qmpphy: phy@88eb000 { + compatible = "qcom,sdm845-qmp-usb3-uni-phy"; + reg = <0 0x088eb000 0 0x18c>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "com_aux"; + + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy", "common"; + + usb_2_ssphy: phy@88eb200 { + reg = <0 0x088eb200 0 0x128>, + <0 0x088eb400 0 0x1fc>, + <0 0x088eb800 0 0x218>, + <0 0x088eb600 0 0x70>; + #clock-cells = <0>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + }; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <150000000>; + + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x740 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usb_2: usb@a8f8800 { + compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; + reg = <0 0x0a8f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <150000000>; + + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_SEC_GDSC>; + + resets = <&gcc GCC_USB30_SEC_BCR>; + + interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + usb_2_dwc3: usb@a800000 { + compatible = "snps,dwc3"; + reg = <0 0x0a800000 0 0xcd00>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x760 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_2_hsphy>, <&usb_2_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + venus: video-codec@aa00000 { + compatible = "qcom,sdm845-venus-v2"; + reg = <0 0x0aa00000 0 0xff000>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&videocc VENUS_GDSC>, + <&videocc VCODEC0_GDSC>, + <&videocc VCODEC1_GDSC>, + <&rpmhpd SDM845_CX>; + power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; + operating-points-v2 = <&venus_opp_table>; + clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, + <&videocc VIDEO_CC_VENUS_AHB_CLK>, + <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, + <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, + <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, + <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, + <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; + clock-names = "core", "iface", "bus", + "vcodec0_core", "vcodec0_bus", + "vcodec1_core", "vcodec1_bus"; + iommus = <&apps_smmu 0x10a0 0x8>, + <&apps_smmu 0x10b0 0x0>; + memory-region = <&venus_mem>; + interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; + interconnect-names = "video-mem", "cpu-cfg"; + + status = "disabled"; + + video-core0 { + compatible = "venus-decoder"; + }; + + video-core1 { + compatible = "venus-encoder"; + }; + + venus_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-533000097 { + opp-hz = /bits/ 64 <533000097>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + videocc: clock-controller@ab00000 { + compatible = "qcom,sdm845-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; + + camss: camss@acb3000 { + compatible = "qcom,sdm845-camss"; + + reg = <0 0x0acb3000 0 0x1000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acc8000 0 0x1000>, + <0 0x0ac65000 0 0x1000>, + <0 0x0ac66000 0 0x1000>, + <0 0x0ac67000 0 0x1000>, + <0 0x0ac68000 0 0x1000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acc4000 0 0x4000>; + reg-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe_lite"; + + interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe_lite"; + + power-domains = <&clock_camcc IFE_0_GDSC>, + <&clock_camcc IFE_1_GDSC>, + <&clock_camcc TITAN_TOP_GDSC>; + + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY1_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY2_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY3_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_AXI_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cphy_rx_src", + "csi0", + "csi0_src", + "csi1", + "csi1_src", + "csi2", + "csi2_src", + "csiphy0", + "csiphy0_timer", + "csiphy0_timer_src", + "csiphy1", + "csiphy1_timer", + "csiphy1_timer_src", + "csiphy2", + "csiphy2_timer", + "csiphy2_timer_src", + "csiphy3", + "csiphy3_timer", + "csiphy3_timer_src", + "gcc_camera_ahb", + "gcc_camera_axi", + "slow_ahb_src", + "soc_ahb", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe0_src", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe1_src", + "vfe_lite", + "vfe_lite_cphy_rx", + "vfe_lite_src"; + + iommus = <&apps_smmu 0x0808 0x0>, + <&apps_smmu 0x0810 0x8>, + <&apps_smmu 0x0c08 0x0>, + <&apps_smmu 0x0c10 0x8>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + }; + }; + + cci: cci@ac4a000 { + compatible = "qcom,sdm845-cci", "qcom,msm8996-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac4a000 0 0x4000>; + interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CCI_CLK>, + <&clock_camcc CAM_CC_CCI_CLK_SRC>; + clock-names = "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_CCI_CLK>; + assigned-clock-rates = <80000000>, <37500000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + clock_camcc: clock-controller@ad00000 { + compatible = "qcom,sdm845-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + }; + + mdss: display-subsystem@ae00000 { + compatible = "qcom,sdm845-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SDM845_CX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-171428571 { + opp-hz = /bits/ 64 <171428571>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-344000000 { + opp-hz = /bits/ 64 <344000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp: displayport-controller@ae90000 { + status = "disabled"; + compatible = "qcom,sdm845-dp"; + + reg = <0 0x0ae90000 0 0x200>, + <0 0x0ae90200 0 0x200>, + <0 0x0ae90400 0 0x600>, + <0 0x0ae90a00 0 0x600>, + <0 0x0ae91000 0 0x600>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", "core_aux", "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SDM845_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sdm845-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM845_CX>; + + phys = <&mdss_dsi0_phy>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94a00 0 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,sdm845-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM845_CX>; + + phys = <&mdss_dsi1_phy>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96a00 0 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + gpu: gpu@5000000 { + compatible = "qcom,adreno-630.2", "qcom,adreno"; + + reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem"; + + /* + * Look ma, no clocks! The GPU clocks and power are + * controlled entirely by the GMU + */ + + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&adreno_smmu 0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "gfx-mem"; + + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-710000000 { + opp-hz = /bits/ 64 <710000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + opp-peak-kBps = <7216000>; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + opp-peak-kBps = <7216000>; + }; + + opp-596000000 { + opp-hz = /bits/ 64 <596000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + opp-peak-kBps = <6220000>; + }; + + opp-520000000 { + opp-hz = /bits/ 64 <520000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + opp-peak-kBps = <6220000>; + }; + + opp-414000000 { + opp-hz = /bits/ 64 <414000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <4068000>; + }; + + opp-342000000 { + opp-hz = /bits/ 64 <342000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + opp-peak-kBps = <2724000>; + }; + + opp-257000000 { + opp-hz = /bits/ 64 <257000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + opp-peak-kBps = <1648000>; + }; + }; + }; + + adreno_smmu: iommu@5040000 { + compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; + reg = <0 0x05040000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "bus", "iface"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + + gmu: gmu@506a000 { + compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; + + reg = <0 0x0506a000 0 0x30000>, + <0 0x0b280000 0 0x10000>, + <0 0x0b480000 0 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + + status = "disabled"; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sdm845-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk_src", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_link_clk_divsel_ten", + "dp_vco_divided_clk_src_mux"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + pdc_intc: interrupt-controller@b220000 { + compatible = "qcom,sdm845-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>; + qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + pdc_reset: reset-controller@b2e0000 { + compatible = "qcom,sdm845-pdc-global"; + reg = <0 0x0b2e0000 0 0x20000>; + #reset-cells = <1>; + }; + + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x1ff>; /* SROT */ + #qcom,sensors = <13>; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x1ff>; /* SROT */ + #qcom,sensors = <8>; + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + aoss_reset: reset-controller@c2a0000 { + compatible = "qcom,sdm845-aoss-cc"; + reg = <0 0x0c2a0000 0 0x31000>; + #reset-cells = <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x400>; + interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apss_shared 0>; + + #clock-cells = <0>; + + cx_cdev: cx { + #cooling-cells = <2>; + }; + + ebi_cdev: ebi { + #cooling-cells = <2>; + }; + }; + + sram@c3f0000 { + compatible = "qcom,sdm845-rpmh-stats"; + reg = <0 0x0c3f0000 0 0x400>; + }; + + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0xc440000 0x1100>, - <0xc600000 0x2000000>, - <0xe600000 0x100000>; - reg-names = "core", "chnls", "obsrvr"; - #address-cells = <0x1>; - #size-cells = <0x1>; + reg = <0 0x0c440000 0 0x1100>, + <0 0x0c600000 0 0x2000000>, + <0 0x0e600000 0 0x100000>, + <0 0x0e700000 0 0xa0000>, + <0 0x0c40a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + sram@146bf000 { + compatible = "qcom,sdm845-imem", "syscon", "simple-mfd"; + reg = <0 0x146bf000 0 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; - qcom,revid@100 { - compatible = "qcom,qpnp-revid"; - reg = <0x100 0x100>; + ranges = <0 0 0x146bf000 0x1000>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; + }; + + lpasscc: clock-controller@17014000 { + compatible = "qcom,sdm845-lpasscc"; + reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; + reg-names = "cc", "qdsp6ss"; + #clock-cells = <1>; + status = "disabled"; + }; + + gladiator_noc: interconnect@17900000 { + compatible = "qcom,sdm845-gladiator-noc"; + reg = <0 0x17900000 0 0xd080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + watchdog@17980000 { + compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; + reg = <0 0x17980000 0 0x1000>; + clocks = <&sleep_clk>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + + apss_shared: mailbox@17990000 { + compatible = "qcom,sdm845-apss-shared"; + reg = <0 0x17990000 0 0x1000>; + #mbox-cells = <1>; + }; + + apps_rsc: rsc@179c0000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0 0x179c0000 0 0x10000>, + <0 0x179d0000 0 0x10000>, + <0 0x179e0000 0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 2>, + <SLEEP_TCS 3>, + <WAKE_TCS 3>, + <CONTROL_TCS 1>; + power-domains = <&CLUSTER_PD>; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sdm845-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sdm845-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; - pmic0: pm8998@0 { - compatible = "qcom,spmi-pmic"; - reg = <0x0 0x1>; - #address-cells = <0x1>; - #size-cells = <0x1>; + rpmhpd_opp_svs: opp4 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; - pm8998_pon: pon@800 { - compatible = "qcom,pm8998-pon"; + rpmhpd_opp_svs_l1: opp5 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; - reg = <0x800 0x100>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; + rpmhpd_opp_nom: opp6 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; - pm8998_pwrkey: pwrkey { - compatible = "qcom,pm8941-pwrkey"; - debounce = <15625>; - bias-pull-up; + rpmhpd_opp_nom_l1: opp7 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; }; - pm8998_resin: resin { - compatible = "qcom,pm8941-resin"; - debounce = <15625>; - bias-pull-up; - status = "disabled"; + rpmhpd_opp_nom_l2: opp8 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; }; + + rpmhpd_opp_turbo: opp9 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0 0x17a00000 0 0x10000>, /* GICD */ + <0 0x17a60000 0 0x100000>; /* GICR * 8 */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + msi-controller@17a40000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0 0x17a40000 0 0x20000>; + status = "disabled"; + }; + }; + + slimbam: dma-controller@17184000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + qcom,controlled-remotely; + reg = <0 0x17184000 0 0x2a000>; + num-channels = <31>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <1>; + qcom,num-ees = <2>; + iommus = <&apps_smmu 0x1806 0x0>; + }; + + timer@17c90000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; + compatible = "arm,armv7-timer-mem"; + reg = <0 0x17c90000 0 0x1000>; + + frame@17ca0000 { + frame-number = <0>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17ca0000 0x1000>, + <0x17cb0000 0x1000>; + }; + + frame@17cc0000 { + frame-number = <1>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17cc0000 0x1000>; + status = "disabled"; + }; + + frame@17cd0000 { + frame-number = <2>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17cd0000 0x1000>; + status = "disabled"; + }; + + frame@17ce0000 { + frame-number = <3>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17ce0000 0x1000>; + status = "disabled"; + }; + + frame@17cf0000 { + frame-number = <4>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17cf0000 0x1000>; + status = "disabled"; + }; + + frame@17d00000 { + frame-number = <5>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17d00000 0x1000>; + status = "disabled"; + }; + + frame@17d10000 { + frame-number = <6>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17d10000 0x1000>; + status = "disabled"; + }; + }; + + osm_l3: interconnect@17d41000 { + compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3"; + reg = <0 0x17d41000 0 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + + cpufreq_hw: cpufreq@17d43000 { + compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw"; + reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + + interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + + wifi: wifi@18800000 { + compatible = "qcom,wcn3990-wifi"; + status = "disabled"; + reg = <0 0x18800000 0 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_msa_mem>; + clock-names = "cxo_ref_clk_pin"; + clocks = <&rpmhcc RPMH_RF_CLK2>; + interrupts = + <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x0040 0x1>; + }; + }; + + sound: sound { + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpu3_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 7>; + + trips { + cpu4_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 8>; + + trips { + cpu5_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 9>; + + trips { + cpu6_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 10>; + + trips { + cpu7_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 0>; + + trips { + aoss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; }; + }; + }; + + cluster0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 5>; + + trips { + cluster0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + cluster0_crit: cluster0_crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cluster1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; - pm8998_gpios: pm8998_gpios@c000 { - compatible = "qcom,pm8998-gpio"; - reg = <0xc000 0x1a00>; - gpio-controller; - gpio-ranges = <&pm8998_gpios 0 0 26>; - #gpio-cells = <2>; + thermal-sensors = <&tsens0 6>; + + trips { + cluster1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + cluster1_crit: cluster1_crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; }; }; + }; + + gpu-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 11>; - pmic1: pm8998@1 { - compatible = "qcom,spmi-pmic"; - reg = <0x1 0x0>; - #address-cells = <0x2>; - #size-cells = <0x0>; + trips { + gpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; }; }; + + gpu-bottom-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 12>; + + trips { + gpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 0>; + + trips { + aoss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + q6-modem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 1>; + + trips { + q6_modem_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 2>; + + trips { + mem_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 3>; + + trips { + wlan_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + q6-hvx-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 4>; + + trips { + q6_hvx_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 5>; + + trips { + camera_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 6>; + + trips { + video_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + modem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 7>; + + trips { + modem_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi new file mode 100644 index 00000000000..a8167e5c14a --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */ + +#include "socfpga_soc64_fit-u-boot.dtsi" + +/{ + memory { + #address-cells = <2>; + #size-cells = <2>; + bootph-all; + }; +}; + +&clkmgr { + bootph-all; +}; + +&i2c0 { + reset-names = "i2c"; +}; + +&i2c1 { + reset-names = "i2c"; +}; + +&i2c2 { + reset-names = "i2c"; +}; + +&i2c3 { + reset-names = "i2c"; +}; + +&mmc { + resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&qspi { + bootph-all; +}; + +&rst { + compatible = "altr,rst-mgr"; + altr,modrst-offset = <0x24>; + bootph-all; +}; + +&sysmgr { + compatible = "altr,sys-mgr", "syscon"; + bootph-all; +}; + +&uart0 { + bootph-all; +}; + +&watchdog0 { + bootph-all; +}; diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi new file mode 100644 index 00000000000..03b55040497 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5.dtsi @@ -0,0 +1,575 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */ + +/dts-v1/; +#include <dt-bindings/reset/altr,rst-mgr-agx5.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/agilex5-clock.h> + +/ { + compatible = "intel,socfpga-agilex"; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + service_reserved: svcbuffer@0 { + compatible = "shared-dma-pool"; + reg = <0x0 0x0 0x0 0x1000000>; + alignment = <0x1000>; + no-map; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x1>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a76"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a76"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x3>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 170 4>, + <0 171 4>, + <0 172 4>, + <0 173 4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + interrupt-parent = <&intc>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + intc: intc@fffc1000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1d000000 0x0 0x10000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges = <0 0 0 0xffffffff>; + + base_fpga_region { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr>; + }; + + clkmgr: clock-controller@10d10000 { + compatible = "intel,agilex5-clkmgr"; + reg = <0x10d10000 0x1000>; + #clock-cells = <1>; + }; + + clocks { + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + cb_intosc_ls_clk: cb-intosc-ls-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_free_clk: f2s-free-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + qspi_clk: qspi-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + gmac0: ethernet@10810000 { + compatible = "intel,socfpga-dwxgmac", "snps,dwxgmac-2.10", "snps,dwxgmac"; + reg = <0x10810000 0x3500>; + interrupts = <0 190 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + iommus = <&smmu 1>; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; + clocks = <&clkmgr AGILEX5_EMAC0_CLK>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + + gmac1: ethernet@10820000 { + compatible = "intel,socfpga-dwxgmac", "snps,dwxgmac-2.10", "snps,dwxgmac"; + reg = <0x10820000 0x3500>; + interrupts = <0 207 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + iommus = <&smmu 2>; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; + clocks = <&clkmgr AGILEX5_EMAC1_CLK>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + + gmac2: ethernet@10830000 { + compatible = "intel,socfpga-dwxgmac", "snps,dwxgmac-2.10", "snps,dwxgmac"; + reg = <0x10830000 0x3500>; + interrupts = <0 224 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + iommus = <&smmu 3>; + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; + clocks = <&clkmgr AGILEX5_EMAC2_CLK>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + + gpio0: gpio@10c03200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x10c03200 0x80>; + resets = <&rst GPIO0_RESET>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 110 4>; + }; + }; + + gpio1: gpio@10c03300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x10c03300 0x80>; + resets = <&rst GPIO1_RESET>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 111 4>; + }; + }; + + i2c0: i2c@10c02800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02800 0x100>; + interrupts = <0 103 4>; + resets = <&rst I2C0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c1: i2c@10c02900 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02900 0x100>; + interrupts = <0 104 4>; + resets = <&rst I2C1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c2: i2c@10c02a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02a00 0x100>; + interrupts = <0 105 4>; + resets = <&rst I2C2_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c3: i2c@10c02b00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02b00 0x100>; + interrupts = <0 106 4>; + resets = <&rst I2C3_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c4: i2c@10c02c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02c00 0x100>; + interrupts = <0 107 4>; + resets = <&rst I2C4_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i3c0: i3c@10da0000 { + compatible = "snps,dw-i3c-master-1.00a"; + reg = <0x10da0000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 164 4>; + resets = <&rst I3C0_RESET>; + max_devices = <11>; + clocks = <&clkmgr AGILEX5_L4_MP_CLK>; + status = "disabled"; + }; + + i3c1: i3c@10da1000 { + compatible = "snps,dw-i3c-master-1.00a"; + reg = <0x10da1000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 165 4>; + resets = <&rst I3C1_RESET>; + clocks = <&clkmgr AGILEX5_L4_MP_CLK>; + max_devices = <11>; + status = "disabled"; + }; + + combophy0: combophy@0 { + #phy-cells = <0>; + phy-type = <1>; + compatible = "cdns,combophy"; + reg = <0x10808000 0x1000>; + resets = <&rst COMBOPHY_RESET>; + reset-names = "reset"; + status = "disabled"; + }; + + mmc: mmc0@10808000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cdns,sd4hc"; + reg = <0x10808000 0x1000>; + interrupts = <0 96 4>; + phys = <&combophy0>; + phy-names = "combo-phy"; + clocks = <&clkmgr AGILEX5_L4_MP_CLK>, + <&clkmgr AGILEX5_SDMMC_CLK>; + clock-names = "biu", "ciu"; + fifo-depth = <0x800>; + resets = <&rst SDMMC_RESET>; + reset-names = "reset"; + iommus = <&smmu 5>; + status = "disabled"; + }; + + ocram: sram@00000000 { + compatible = "mmio-sram"; + reg = <0x00000000 0x200000>; + }; + + rst: rstmgr@10d11000 { + #reset-cells = <1>; + compatible = "altr,stratix10-rst-mgr"; + reg = <0x10d11000 0x1000>; + }; + + smmu: iommu@16000000 { + compatible = "arm,mmu-500", "arm,smmu-v2"; + reg = <0x16000000 0x40000>; + #global-interrupts = <2>; + #iommu-cells = <1>; + interrupt-parent = <&intc>; + interrupts = <0 128 4>, /* Global Secure Fault */ + <0 129 4>, /* Global Non-secure Fault */ + /* Non-secure Context Interrupts (32) */ + <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, + <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, + <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, + <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, + <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, + <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, + <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, + <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; + stream-match-mask = <0x7ff0>; + status = "disabled"; + }; + + spi0: spi@10da4000 { + compatible = "intel,agilex-spi", + "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10da4000 0x1000>; + interrupts = <0 99 4>; + resets = <&rst SPIM0_RESET>; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; + status = "disabled"; + }; + + spi1: spi@10da5000 { + compatible = "intel,agilex-spi", + "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10da5000 0x1000>; + interrupts = <0 100 4>; + resets = <&rst SPIM1_RESET>; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; + status = "disabled"; + }; + + sysmgr: sysmgr@10d12000 { + compatible = "altr,sys-mgr-s10","altr,sys-mgr"; + reg = <0x10d12000 0x500>; + }; + + /* Local timer */ + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + timer0: timer0@10c03000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 113 4>; + reg = <0x10c03000 0x100>; + resets = <&rst SPTIMER0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + status = "disabled"; + }; + + timer1: timer1@10c03100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 114 4>; + reg = <0x10c03100 0x100>; + resets = <&rst SPTIMER1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + status = "disabled"; + }; + + timer2: timer2@10d00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 115 4>; + reg = <0x10d00000 0x100>; + resets = <&rst L4SYSTIMER0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + clock-names = "timer"; + status = "disabled"; + }; + + timer3: timer3@10d00100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 116 4>; + reg = <0x10d00100 0x100>; + resets = <&rst L4SYSTIMER1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + clock-names = "timer"; + status = "disabled"; + }; + + uart0: serial0@10c02000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10c02000 0x100>; + interrupts = <0 108 4>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART0_RESET>; + status = "disabled"; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-frequency = <100000000>; + }; + + uart1: serial1@10c02100 { + compatible = "snps,dw-apb-uart"; + reg = <0x10c02100 0x100>; + interrupts = <0 109 4>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&clkmgr AGILEX5_USB_CLK>; + status = "disabled"; + }; + + usb0: usb@10b00000 { + compatible = "snps,dwc2"; + reg = <0x10b00000 0x40000>; + interrupts = <0 93 4>; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; + reset-names = "dwc2", "dwc2-ecc"; + clocks = <&clkmgr AGILEX5_USB_CLK>; + iommus = <&smmu 6>; + status = "disabled"; + }; + + usb31: usb31@11000000 { + compatible = "snps,dwc3"; + reg = <0x11000000 0x100000>; + resets = <&rst USB1_RESET>; + phys = <&usbphy0>, <&usbphy0>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + maximum-speed = "super-speed"; + snps,dis_u2_susphy_quirk; + status = "disabled"; + }; + + watchdog0: watchdog@10d00200 { + compatible = "snps,dw-wdt"; + reg = <0x10d00200 0x100>; + interrupts = <0 117 4>; + resets = <&rst WATCHDOG0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog1: watchdog@10d00300 { + compatible = "snps,dw-wdt"; + reg = <0x10d00300 0x100>; + interrupts = <0 118 4>; + resets = <&rst WATCHDOG1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog2: watchdog@10d00400 { + compatible = "snps,dw-wdt"; + reg = <0x10d00400 0x100>; + interrupts = <0 125 4>; + resets = <&rst WATCHDOG2_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog3: watchdog@10d00500 { + compatible = "snps,dw-wdt"; + reg = <0x10d00500 0x100>; + interrupts = <0 126 4>; + resets = <&rst WATCHDOG3_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog4: watchdog@10d00600 { + compatible = "snps,dw-wdt"; + reg = <0x10d00600 0x100>; + interrupts = <0 175 4>; + resets = <&rst WATCHDOG4_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + /* QSPI address not available yet */ + qspi: spi@108d2000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x108d2000 0x100>, + <0x10900000 0x100000>; + interrupts = <0 3 4>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + + status = "disabled"; + }; + + firmware { + svc { + compatible = "intel,stratix10-svc"; + method = "smc"; + memory-region = <&service_reserved>; + + fpga_mgr: fpga-mgr { + compatible = "intel,stratix10-soc-fpga-mgr"; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi new file mode 100644 index 00000000000..9eb21d65428 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */ + +#include "socfpga_agilex5-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@0x20000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0x20000450 0x00000010>; + status = "disabled"; + }; + }; + + memory { + /* 8GB */ + reg = <0 0x80000000 0 0x80000000>, + <8 0x80000000 1 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &mmc,&flash0,"/memory"; + }; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + bootph-all; + /delete-property/ cdns,read-delay; +}; + +&i3c0 { + bootph-all; +}; + +&i3c1 { + bootph-all; +}; + +&mmc { + status = "okay"; + bus-width = <4>; + sd-uhs-sdr50; + cap-mmc-highspeed; + bootph-all; +}; + +&combophy0 { + status = "okay"; + bootph-all; + cdns,phy-use-ext-lpbk-dqs = <1>; + cdns,phy-use-lpbk-dqs = <1>; + cdns,phy-use-phony-dqs = <1>; + cdns,phy-use-phony-dqs-cmd = <1>; + cdns,phy-io-mask-always-on = <0>; + cdns,phy-io-mask-end = <5>; + cdns,phy-io-mask-start = <0>; + cdns,phy-data-select-oe-end = <1>; + cdns,phy-sync-method = <1>; + cdns,phy-sw-half-cycle-shift = <0>; + cdns,phy-rd-del-sel = <52>; + cdns,phy-underrun-suppress = <1>; + cdns,phy-gate-cfg-always-on = <1>; + cdns,phy-param-dll-bypass-mode = <1>; + cdns,phy-param-phase-detect-sel = <2>; + cdns,phy-param-dll-start-point = <254>; + cdns,phy-read-dqs-cmd-delay = <0>; + cdns,phy-clk-wrdqs-delay = <0>; + cdns,phy-clk-wr-delay = <0>; + cdns,phy-read-dqs-delay = <0>; + cdns,phy-phony-dqs-timing = <0>; + cdns,hrs09-rddata-en = <1>; + cdns,hrs09-rdcmd-en = <1>; + cdns,hrs09-extended-wr-mode = <1>; + cdns,hrs09-extended-rd-mode = <1>; + cdns,hrs10-hcsdclkadj = <3>; + cdns,hrs16-wrdata1-sdclk-dly = <0>; + cdns,hrs16-wrdata0-sdclk-dly = <0>; + cdns,hrs16-wrcmd1-sdclk-dly = <0>; + cdns,hrs16-wrcmd0-sdclk-dly = <0>; + cdns,hrs16-wrdata1-dly = <0>; + cdns,hrs16-wrdata0-dly = <0>; + cdns,hrs16-wrcmd1-dly = <0>; + cdns,hrs16-wrcmd0-dly = <0>; + cdns,hrs07-rw-compensate = <10>; + cdns,hrs07-idelay-val = <0>; +}; + +&qspi { + status = "okay"; +}; + +&timer0 { + bootph-all; +}; + +&timer1 { + bootph-all; +}; + +&timer2 { + bootph-all; +}; + +&timer3 { + bootph-all; +}; + +&watchdog0 { + bootph-all; +}; + diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts new file mode 100644 index 00000000000..852e1e5ae3c --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk.dts @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex5 SoCDK"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet2 = &gmac2; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + soc { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i3c0 { + status = "okay"; +}; + +&i3c1 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog0 { + status = "okay"; +}; + +&watchdog1 { + status = "okay"; +}; + +&watchdog2 { + status = "okay"; +}; + +&watchdog3 { + status = "okay"; +}; + +&watchdog4 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&qspi { + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mt25qu02g"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "u-boot"; + reg = <0x0 0x04200000>; + }; + + root: partition@4200000 { + label = "root"; + reg = <0x04200000 0x0BE00000>; + }; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi index 84b91e8df09..15306db6002 100644 --- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi @@ -2,7 +2,7 @@ /* * U-Boot additions * - * Copyright (C) 2020 Intel Corporation <www.intel.com> + * Copyright (C) 2020-2024 Intel Corporation <www.intel.com> */ #if defined(CONFIG_FIT) @@ -21,14 +21,18 @@ description = "FIT with firmware and bootloader"; #address-cells = <1>; - images { + images: images { uboot { description = "U-Boot SoC64"; type = "standalone"; os = "U-Boot"; arch = "arm64"; compression = "none"; + #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + load = <0x80200000>; + #else load = <0x00200000>; + #endif uboot_blob: blob-ext { filename = "u-boot-nodtb.bin"; }; @@ -43,8 +47,13 @@ os = "arm-trusted-firmware"; arch = "arm64"; compression = "none"; + #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + load = <0x80000000>; + entry = <0x80000000>; + #else load = <0x00001000>; entry = <0x00001000>; + #endif atf_blob: blob-ext { filename = "bl31.bin"; }; @@ -53,11 +62,11 @@ }; }; - fdt { - description = "U-Boot SoC64 flat device-tree"; + fdt-0 { + description = "socfpga_socdk"; type = "flat_dt"; compression = "none"; - uboot_fdt_blob: blob-ext { + fdt_0_blob: blob-ext { filename = "u-boot.dtb"; }; hash { @@ -66,17 +75,18 @@ }; }; - configurations { - default = "conf"; - conf { - description = "Intel SoC64 FPGA"; + board_config: configurations { + default = "board-0"; + + board-0 { + description = "board_0"; firmware = "atf"; loadables = "uboot"; - fdt = "fdt"; + fdt = "fdt-0"; signature { algo = "crc32"; key-name-hint = "dev"; - sign-images = "atf", "fdt", "uboot"; + sign-images = "atf", "uboot", "fdt-0"; }; }; }; @@ -96,8 +106,8 @@ arch = "arm64"; os = "linux"; compression = "none"; - load = <0x4080000>; - entry = <0x4080000>; + load = <0x6000000>; + entry = <0x6000000>; kernel_blob: blob-ext { filename = "Image"; }; @@ -146,7 +156,7 @@ filename = "signed-bl31.bin"; }; -&uboot_fdt_blob { +&fdt_0_blob { filename = "signed-u-boot.dtb"; }; diff --git a/arch/arm/dts/starqltechn-uboot.dtsi b/arch/arm/dts/starqltechn-uboot.dtsi deleted file mode 100644 index 55c6d18412b..00000000000 --- a/arch/arm/dts/starqltechn-uboot.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * U-Boot addition to handle Samsung S9 SM-G9600 (starqltechn) pins - * - * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> - * - */ - -/ -{ - framebuffer@9D400000 { - bootph-all; - }; - soc { - bootph-all; - serial@a84000 { - bootph-all; - }; - clock-controller@100000 { - bootph-all; - }; - pinctrl@3400000 { - bootph-all; - }; - }; -}; - diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts deleted file mode 100644 index 0842e19adb6..00000000000 --- a/arch/arm/dts/starqltechn.dts +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Samsung S9 SM-G9600 (starqltechn) board device tree source - * - * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> - * - */ - -/dts-v1/; - -#include "sdm845.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -/ { - model = "Samsung S9 (SM-G9600)"; - compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; - #address-cells = <2>; - #size-cells = <2>; - - chosen { - stdout-path = "serial0:921600n8"; - }; - - aliases { - serial0 = &uart9; - }; - - memory { - device_type = "memory"; - reg = <0 0x80000000 0 0xfe1bffff>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - framebuffer: framebuffer@9D400000 { - compatible = "simple-framebuffer"; - reg = <0 0x9D400000 0 (2960 * 1440 * 4)>;//2400000 - width = <1440>; - height = <2960>; - stride = <(1440 * 4)>; - format = "a8r8g8b8"; - }; - - soc: soc { - serial@a84000 { - status = "okay"; - }; - }; -}; - -&pm8998_resin { - status = "okay"; -}; - -&tlmm { - muic_i2c: muic-i2c-n { - pins = "GPIO_33", "GPIO_34"; - drive-strength = <0x2>; - function = "gpio"; - bias-disable; - }; -}; - -#include "starqltechn-uboot.dtsi" diff --git a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi index ba0c02489d1..f004e9840a2 100644 --- a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi +++ b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi @@ -16,11 +16,26 @@ u-boot,mmc-env-partition = "u-boot-env"; }; + gpio-keys { + button-user-1 { + label = "User-1"; + linux,code = <BTN_2>; + gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-user { + /* update label to match the label requested in board_key_check() */ + label = "User-2"; + }; + }; + leds { + led-blue { + /delete-property/default-state; + }; + led-red { - color = <LED_COLOR_ID_RED>; gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - default-state = "off"; }; }; }; diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi index 20728f27ee1..a5158fec7ef 100644 --- a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi @@ -3,6 +3,7 @@ * Copyright : STMicroelectronics 2022 */ +#include <dt-bindings/input/linux-event-codes.h> #include "stm32mp15-scmi-u-boot.dtsi" / { @@ -12,20 +13,35 @@ }; config { - u-boot,boot-led = "heartbeat"; - u-boot,error-led = "error"; + u-boot,boot-led = "led-blue"; + u-boot,error-led = "led-red"; u-boot,mmc-env-partition = "u-boot-env"; st,adc_usb_pd = <&adc1 18>, <&adc1 19>; - st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = <BTN_1>; + gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-user-2 { + label = "User-2"; + linux,code = <BTN_2>; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; }; led { - red { - label = "error"; + led-blue { + /delete-property/label; + }; + + led-red { gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - status = "okay"; }; }; }; diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index a16358266a2..f97debaa0e4 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/stm32mp1-clksrc.h> +#include <dt-bindings/input/linux-event-codes.h> #include "stm32mp15-u-boot.dtsi" #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" @@ -14,12 +15,10 @@ }; config { - u-boot,boot-led = "heartbeat"; - u-boot,error-led = "error"; + u-boot,boot-led = "led-blue"; + u-boot,error-led = "led-red"; u-boot,mmc-env-partition = "fip"; st,adc_usb_pd = <&adc1 18>, <&adc1 19>; - st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; }; #if defined(CONFIG_STM32MP15X_STM32IMAGE) || defined(CONFIG_SPL) @@ -48,12 +47,29 @@ }; #endif + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = <BTN_1>; + gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-user-2 { + label = "User-2"; + linux,code = <BTN_2>; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; + led { - red { - label = "error"; + led-blue { + /delete-property/label; + }; + + led-red { gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - status = "okay"; }; }; }; diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi index 4d763bd3a2c..7c0d1bab11a 100644 --- a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi @@ -3,6 +3,7 @@ * Copyright : STMicroelectronics 2022 */ +#include <dt-bindings/input/linux-event-codes.h> #include "stm32mp15-scmi-u-boot.dtsi" / { @@ -11,19 +12,36 @@ }; config { - u-boot,boot-led = "heartbeat"; - u-boot,error-led = "error"; + u-boot,boot-led = "led-blue"; + u-boot,error-led = "led-red"; u-boot,mmc-env-partition = "u-boot-env"; - st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = <BTN_1>; + gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-user-2 { + label = "User-2"; + linux,code = <BTN_2>; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; }; led { - red { - label = "error"; + compatible = "gpio-leds"; + + led-blue { + gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>; + }; + + led-red { gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - status = "okay"; }; }; }; diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index ef91088aa37..d93359f967c 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/stm32mp1-clksrc.h> +#include <dt-bindings/input/linux-event-codes.h> #include "stm32mp15-u-boot.dtsi" #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" @@ -13,11 +14,9 @@ }; config { - u-boot,boot-led = "heartbeat"; - u-boot,error-led = "error"; + u-boot,boot-led = "led-blue"; + u-boot,error-led = "led-red"; u-boot,mmc-env-partition = "fip"; - st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; }; #if defined(CONFIG_STM32MP15X_STM32IMAGE) || defined(CONFIG_SPL) @@ -43,12 +42,31 @@ }; #endif + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = <BTN_1>; + gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-user-2 { + label = "User-2"; + linux,code = <BTN_2>; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; + led { - red { - label = "error"; + compatible = "gpio-leds"; + + led-blue { + gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>; + }; + + led-red { gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - status = "okay"; }; }; }; diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi index 139940bd5d4..3515347e91d 100644 --- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi @@ -33,11 +33,11 @@ label = "fsbl1"; reg = <0x00000000 0x00040000>; }; - partition@80000 { + partition@40000 { label = "fsbl2"; reg = <0x00040000 0x00040000>; }; - partition@100000 { + partition@80000 { label = "ssbl"; reg = <0x00080000 0x00200000>; }; @@ -58,7 +58,7 @@ label = "fsbl2"; reg = <0x00040000 0x00040000>; }; - partition@100000 { + partition@80000 { label = "fip"; reg = <0x00080000 0x00400000>; }; @@ -112,7 +112,7 @@ label = "fip2"; reg = <0x00600000 0x00400000>; }; - partition@1200000 { + partition@a00000 { label = "UBI"; reg = <0x00a00000 0x3f600000>; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index 2f70b0690d2..1b445619325 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -106,15 +106,15 @@ label = "fsbl2"; reg = <0x00040000 0x00040000>; }; - partition@500000 { + partition@80000 { label = "uboot"; reg = <0x00080000 0x00160000>; }; - partition@900000 { + partition@1e0000 { label = "env1"; reg = <0x001E0000 0x00010000>; }; - partition@980000 { + partition@1f0000 { label = "env2"; reg = <0x001F0000 0x00010000>; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 552b35db3c7..ba84db679e1 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -42,15 +42,15 @@ label = "fsbl2"; reg = <0x00040000 0x00040000>; }; - partition@500000 { + partition@80000 { label = "uboot"; reg = <0x00080000 0x00160000>; }; - partition@900000 { + partition@1e0000 { label = "env1"; reg = <0x001E0000 0x00010000>; }; - partition@980000 { + partition@1f0000 { label = "env2"; reg = <0x001F0000 0x00010000>; }; diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts deleted file mode 100644 index b04e89971c7..00000000000 --- a/arch/arm/dts/stv0991.dts +++ /dev/null @@ -1,55 +0,0 @@ -/dts-v1/; - -/ { - model = "ST STV0991 application board"; - compatible = "st,stv0991"; - #address-cells = <1>; - #size-cells = <1>; - - chosen { - stdout-path = &uart0; - }; - - memory { - device_type="memory"; - reg = <0x0 0x198000>; - }; - - uart0: serial@0x80406000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80406000 0x1000>; - clock = <2700000>; - }; - - aliases { - spi0 = "/spi@80203000"; /* QSPI */ - }; - - qspi: spi@80203000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80203000 0x100>, - <0x40000000 0x1000000>; - clocks = <3750000>; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x40000000>; - status = "okay"; - - flash0: n25q32@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; /* chip select */ - spi-max-frequency = <50000000>; - m25p,fast-read; - page-size = <256>; - block-size = <16>; /* 2^16, 64KB */ - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - }; - }; -}; diff --git a/arch/arm/dts/tegra114-u-boot.dtsi b/arch/arm/dts/tegra114-u-boot.dtsi index 7c119725528..6a02714a258 100644 --- a/arch/arm/dts/tegra114-u-boot.dtsi +++ b/arch/arm/dts/tegra114-u-boot.dtsi @@ -1,3 +1,16 @@ #include <config.h> #include "tegra-u-boot.dtsi" + +/ { + host1x@50000000 { + bootph-all; + dc@54200000 { + bootph-all; + }; + + dc@54240000 { + bootph-all; + }; + }; +}; diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index 68ee7f31656..250d692f6bf 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -42,7 +42,7 @@ }; dc@54200000 { - compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra114-dc"; reg = <0x54200000 0x00040000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_DISP1>, @@ -61,7 +61,7 @@ }; dc@54240000 { - compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra114-dc"; reg = <0x54240000 0x00040000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_DISP2>, diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts index 5cf604e8659..f851767a55f 100644 --- a/arch/arm/dts/tegra20-paz00.dts +++ b/arch/arm/dts/tegra20-paz00.dts @@ -35,22 +35,6 @@ status = "okay"; nvidia,panel = <&panel>; - - display-timings { - timing@0 { - /* PAZ00 has 1024x600 */ - clock-frequency = <54030000>; - hactive = <1024>; - vactive = <600>; - hback-porch = <160>; - hfront-porch = <24>; - hsync-len = <136>; - vback-porch = <3>; - vfront-porch = <61>; - vsync-len = <6>; - hsync-active = <1>; - }; - }; }; }; diff --git a/arch/arm/dts/tegra30-asus-grouper-common.dtsi b/arch/arm/dts/tegra30-asus-grouper-common.dtsi index e8a3511a9f7..d437ddc4dce 100644 --- a/arch/arm/dts/tegra30-asus-grouper-common.dtsi +++ b/arch/arm/dts/tegra30-asus-grouper-common.dtsi @@ -829,6 +829,12 @@ gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; linux,code = <KEY_DOWN>; }; + + switch-hall-sensor { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + }; }; panel: panel { diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts index 350443d55eb..243ff2bda26 100644 --- a/arch/arm/dts/tegra30-asus-p1801-t.dts +++ b/arch/arm/dts/tegra30-asus-p1801-t.dts @@ -118,8 +118,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* SDMMC3 pinmux */ @@ -203,7 +203,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; gen2_i2c { nvidia,pins = "gen2_i2c_scl_pt5", @@ -213,7 +213,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; cam_i2c { nvidia,pins = "cam_i2c_scl_pbb1", @@ -223,7 +223,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; ddc_i2c { nvidia,pins = "ddc_scl_pv4", @@ -232,7 +232,7 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; pwr_i2c { nvidia,pins = "pwr_i2c_scl_pz6", @@ -242,7 +242,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; hotplug_i2c { nvidia,pins = "pu4"; @@ -260,7 +260,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; hdmi_hpd { nvidia,pins = "hdmi_int_pn7"; @@ -632,8 +632,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_ENABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* GPIO keys pinmux */ @@ -718,8 +718,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; vi_d10_pt2 { nvidia,pins = "vi_d10_pt2", @@ -838,8 +838,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; vi_mclk_pt1 { nvidia,pins = "vi_mclk_pt1"; diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts index f49e7341fe0..3ddd78b3df6 100644 --- a/arch/arm/dts/tegra30-asus-tf600t.dts +++ b/arch/arm/dts/tegra30-asus-tf600t.dts @@ -90,6 +90,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* SDMMC2 pinmux */ @@ -98,21 +100,15 @@ "vi_d2_pl0", "vi_d3_pl1", "vi_d5_pl3", - "vi_d7_pl5"; - nvidia,function = "sdmmc2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - vi_d8_pl6 { - nvidia,pins = "vi_d8_pl6", + "vi_d7_pl5", + "vi_d8_pl6", "vi_d9_pl7"; nvidia,function = "sdmmc2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* SDMMC3 pinmux */ @@ -146,6 +142,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; sdmmc4_cmd { nvidia,pins = "sdmmc4_cmd_pt7", @@ -161,6 +159,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; sdmmc4_rst_n { nvidia,pins = "sdmmc4_rst_n_pcc3"; @@ -469,6 +469,42 @@ nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; + /* SPI pinmux */ + spi1_ctrl { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_sck { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_cs1_n { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi4_ctrl { + nvidia,pins = "gmi_a16_pj7", + "gmi_a17_pb0", + "gmi_a18_pb1", + "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + /* Display A pinmux */ lcd_pwr0_pb2 { nvidia,pins = "lcd_pwr0_pb2", @@ -577,8 +613,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_ENABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* GPIO keys pinmux */ @@ -657,18 +693,19 @@ nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; vi_vsync_pd6 { - nvidia,pins = "vi_vsync_pd6", + nvidia,pins = "vi_d0_pt4", + "vi_d10_pt2", + "vi_vsync_pd6", "vi_hsync_pd7"; nvidia,function = "rsvd2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; - vi_d10_pt2 { - nvidia,pins = "vi_d10_pt2", - "vi_d0_pt4", "pbb0"; + pbb0 { + nvidia,pins = "pbb0"; nvidia,function = "rsvd2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; @@ -783,21 +820,15 @@ nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; - vi_d4_pl2 { - nvidia,pins = "vi_d4_pl2"; - nvidia,function = "vi"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - vi_d6_pl4 { - nvidia,pins = "vi_d6_pl4"; + vi_d4 { + nvidia,pins = "vi_d4_pl2", + "vi_d6_pl4"; nvidia,function = "vi"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; vi_mclk_pt1 { nvidia,pins = "vi_mclk_pt1"; @@ -805,6 +836,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; jtag { @@ -1089,6 +1122,16 @@ clock-output-names = "pmic-oscillator"; }; + extcon-keys { + compatible = "gpio-keys"; + + switch-dock-hall-sensor { + label = "Lid sensor"; + gpios = <&gpio TEGRA_GPIO(BB, 6) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + }; + }; + gpio-keys { compatible = "gpio-keys"; diff --git a/arch/arm/dts/tegra30-asus-tf700t.dts b/arch/arm/dts/tegra30-asus-tf700t.dts index cc03f5a7ec2..6dc760b90d6 100644 --- a/arch/arm/dts/tegra30-asus-tf700t.dts +++ b/arch/arm/dts/tegra30-asus-tf700t.dts @@ -7,7 +7,18 @@ model = "ASUS Transformer Infinity TF700T"; compatible = "asus,tf700t", "nvidia,tegra30"; - /delete-node/ host1x@50000000; + host1x@50000000 { + dc@54200000 { + clocks = <&tegra_car TEGRA30_CLK_DISP1>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + + rgb { + status = "okay"; + + nvidia,panel = <&tc358768>; + }; + }; + }; pinmux@70000868 { state_default: pinmux { @@ -62,5 +73,92 @@ }; }; - /delete-node/ panel; + tc358768_refclk: clock-tc358768 { + compatible = "fixed-clock"; + clock-frequency = <23100000>; + clock-accuracy = <100>; + #clock-cells = <0>; + }; + + tc358768_osc: clock-tc358768-osc-gate { + compatible = "gpio-gate-clock"; + enable-gpios = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>; + clocks = <&tc358768_refclk>; + #clock-cells = <0>; + }; + + i2c-mux { + compatible = "i2c-mux-gpio"; + + mux-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>; + i2c-parent = <&gen1_i2c>; + idle-state = <0x0>; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + tc358768: dsi@7 { + compatible = "toshiba,tc358768"; + reg = <0x7>; + + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&tc358768_osc>; + clock-names = "refclk"; + + reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + + vddc-supply = <&vdd_1v2_mipi>; + vddio-supply = <&vdd_1v8_vio>; + vddmipi-supply = <&vdd_1v2_mipi>; + + panel = <&panel>; + }; + }; + }; + + panel: panel { + compatible = "panasonic,vvx10f004b00"; + + power-supply = <&vdd_pnl_reg>; + backlight = <&backlight>; + + /delete-property/ enable-gpios; + + display-timings { + timing@0 { + /* 1920x1200@60Hz */ + clock-frequency = <154000000>; + + hactive = <1920>; + hfront-porch = <48>; + hback-porch = <80>; + hsync-len = <32>; + hsync-active = <1>; + + vactive = <1200>; + vfront-porch = <3>; + vback-porch = <26>; + vsync-len = <6>; + vsync-active = <1>; + }; + }; + }; + + vdd_1v2_mipi: regulator-mipi { + compatible = "regulator-fixed"; + regulator-name = "tc358768_1v2_vdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <10000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi index e6cc6e7105f..03ba8fb9604 100644 --- a/arch/arm/dts/tegra30-asus-transformer.dtsi +++ b/arch/arm/dts/tegra30-asus-transformer.dtsi @@ -99,8 +99,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,io-reset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* SDMMC3 pinmux */ @@ -189,7 +189,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; gen2_i2c { @@ -200,7 +200,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; cam_i2c { @@ -211,7 +211,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; ddc_i2c { @@ -221,7 +221,7 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; pwr_i2c { @@ -232,7 +232,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; hotplug_i2c { @@ -647,8 +647,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_ENABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,io-reset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* GPIO keys pinmux */ @@ -741,8 +741,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,io-reset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; vi_d10_pt2 { @@ -879,8 +879,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,lock = <0>; - nvidia,io-reset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; vi_mclk_pt1 { @@ -1150,6 +1150,16 @@ clock-output-names = "pmic-oscillator"; }; + extcon-keys { + compatible = "gpio-keys"; + + switch-dock-hall-sensor { + label = "Lid sensor"; + gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + }; + }; + gpio-keys { compatible = "gpio-keys"; diff --git a/arch/arm/dts/tegra30-u-boot.dtsi b/arch/arm/dts/tegra30-u-boot.dtsi index 3038227dbed..6a02714a258 100644 --- a/arch/arm/dts/tegra30-u-boot.dtsi +++ b/arch/arm/dts/tegra30-u-boot.dtsi @@ -8,5 +8,9 @@ dc@54200000 { bootph-all; }; + + dc@54240000 { + bootph-all; + }; }; }; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index f198bc0edbe..1177e2ab1f4 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -158,7 +158,7 @@ }; dc@54200000 { - compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra30-dc"; reg = <0x54200000 0x00040000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_DISP1>, diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts index e0517cf4601..5889d436edb 100644 --- a/arch/arm/dts/zynqmp-mini-nand.dts +++ b/arch/arm/dts/zynqmp-mini-nand.dts @@ -50,6 +50,12 @@ #size-cells = <1>; arasan,has-mdma; num-cs = <2>; + nand@0 { + reg = <0>; + #address-cells = <2>; + #size-cells = <1>; + nand-ecc-mode = "hw"; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts index 8517bdad6f4..c1d713b5d89 100644 --- a/arch/arm/dts/zynqmp-sc-revB.dts +++ b/arch/arm/dts/zynqmp-sc-revB.dts @@ -49,7 +49,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - fwuen { + key-fwuen { label = "sw16"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; linux,code = <BTN_MISC>; @@ -192,7 +192,7 @@ status = "okay"; /* QSPI should also have PINCTRL setup */ flash@0 { - compatible = "mt25qu512a", "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ + compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index 5202b7c4819..1727a1cc15c 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -356,6 +356,8 @@ &uart0 { status = "okay"; + rts-gpios = <&gpio 72 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; assigned-clock-rates = <100000000>; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index 6c29f657413..0a0cbd2b69a 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -66,6 +66,18 @@ #clock-cells = <0>; clock-frequency = <74250000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ @@ -130,6 +142,14 @@ phy-names = "dp-phy0"; phys = <&psgtr 1 PHY_TYPE_DP 0 1>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; + + ports { + port@5 { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; + }; + }; }; &zynqmp_dpdma { diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index 6d0d5c487d2..561b546e37f 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -342,6 +342,7 @@ slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; bias-disable; + output-enable; }; conf-cd { diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index a4b4465d203..64683e0ccbb 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -63,6 +63,18 @@ #clock-cells = <0>; clock-frequency = <27000000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -97,6 +109,14 @@ phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; + + ports { + port@5 { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; + }; + }; }; &zynqmp_dpdma { @@ -329,6 +349,7 @@ slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; bias-disable; + output-enable; }; conf-cd { diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts index 2a3bbe17047..b626d1aacf5 100644 --- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts +++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts @@ -47,7 +47,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - j383 { + key-j383 { label = "j383"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; linux,code = <BTN_MISC>; diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts index e0e4f1b13ad..e0632883e4e 100644 --- a/arch/arm/dts/zynqmp-vpk120-revA.dts +++ b/arch/arm/dts/zynqmp-vpk120-revA.dts @@ -47,7 +47,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw16 { + button-16 { label = "sw16"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; linux,code = <BTN_MISC>; diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index b97f7ee8d44..48ab619472e 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -136,8 +136,7 @@ reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "bch"; + nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-0"; nand-ecc-step-size = <1024>; @@ -173,8 +172,7 @@ reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "bch"; + nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-1"; nand-ecc-step-size = <1024>; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index b4e24745a9a..a113e475082 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -46,7 +46,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw19 { + switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = <KEY_DOWN>; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 6f593e80841..4d7d5d2e5ef 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -46,7 +46,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw19 { + switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = <KEY_DOWN>; diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts index 7f70904f44e..def3b53cef7 100644 --- a/arch/arm/dts/zynqmp-zcu670-revA.dts +++ b/arch/arm/dts/zynqmp-zcu670-revA.dts @@ -49,7 +49,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw1 { + switch-1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = <BTN_MISC>; diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts index 0adb2062aef..41f9a23d06a 100644 --- a/arch/arm/dts/zynqmp-zcu670-revB.dts +++ b/arch/arm/dts/zynqmp-zcu670-revB.dts @@ -49,7 +49,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw1 { + switch-1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = <BTN_MISC>; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index b50b83b7723..53a606c340a 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -168,7 +168,7 @@ bootph-all; }; - pmu { + pmu: pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, @@ -1001,14 +1001,14 @@ status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupt-names = "host", "peripheral", "otg"; + interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; /* iommus = <&smmu 0x860>; */ snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; - snps,enable_guctl1_ipd_quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; @@ -1033,14 +1033,14 @@ status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupt-names = "host", "peripheral", "otg"; + interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; /* iommus = <&smmu 0x861>; */ snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; - snps,enable_guctl1_ipd_quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; diff --git a/arch/arm/include/asm/arch-imx9/mu.h b/arch/arm/include/asm/arch-imx9/mu.h index b8604992914..649b8a60df8 100644 --- a/arch/arm/include/asm/arch-imx9/mu.h +++ b/arch/arm/include/asm/arch-imx9/mu.h @@ -8,6 +8,6 @@ #include <event.h> -int imx9_probe_mu(void *ctx, struct event *event); +int imx9_probe_mu(void); #endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h index 226744d67d9..4ad1d33e056 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h @@ -62,6 +62,40 @@ check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c); enum apll_frequencies { APLL_816_MHZ, APLL_600_MHZ, + + /* CRU_CLK_SEL37_CON */ + ACLK_VIO_PLL_SEL_CPLL = 0, + ACLK_VIO_PLL_SEL_GPLL = 1, + ACLK_VIO_PLL_SEL_HDMIPHY = 2, + ACLK_VIO_PLL_SEL_USB480M = 3, + ACLK_VIO_PLL_SEL_SHIFT = 6, + ACLK_VIO_PLL_SEL_MASK = 3 << ACLK_VIO_PLL_SEL_SHIFT, + ACLK_VIO_DIV_CON_SHIFT = 0, + ACLK_VIO_DIV_CON_MASK = 0x1f << ACLK_VIO_DIV_CON_SHIFT, + HCLK_VIO_DIV_CON_SHIFT = 8, + HCLK_VIO_DIV_CON_MASK = 0x1f << HCLK_VIO_DIV_CON_SHIFT, + + /* CRU_CLK_SEL39_CON */ + ACLK_VOP_PLL_SEL_CPLL = 0, + ACLK_VOP_PLL_SEL_GPLL = 1, + ACLK_VOP_PLL_SEL_HDMIPHY = 2, + ACLK_VOP_PLL_SEL_USB480M = 3, + ACLK_VOP_PLL_SEL_SHIFT = 6, + ACLK_VOP_PLL_SEL_MASK = 3 << ACLK_VOP_PLL_SEL_SHIFT, + ACLK_VOP_DIV_CON_SHIFT = 0, + ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, + + /* CRU_CLK_SEL40_CON */ + DCLK_LCDC_PLL_SEL_GPLL = 0, + DCLK_LCDC_PLL_SEL_CPLL = 1, + DCLK_LCDC_PLL_SEL_SHIFT = 0, + DCLK_LCDC_PLL_SEL_MASK = 1 << DCLK_LCDC_PLL_SEL_SHIFT, + DCLK_LCDC_SEL_HDMIPHY = 0, + DCLK_LCDC_SEL_PLL = 1, + DCLK_LCDC_SEL_SHIFT = 1, + DCLK_LCDC_SEL_MASK = 1 << DCLK_LCDC_SEL_SHIFT, + DCLK_LCDC_DIV_CON_SHIFT = 8, + DCLK_LCDC_DIV_CON_MASK = 0xFf << DCLK_LCDC_DIV_CON_SHIFT, }; void rk3328_configure_cpu(struct rk3328_cru *cru, diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h index 7f4a9085392..a4507e5fdd7 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h @@ -63,6 +63,8 @@ struct rk3588_pll { unsigned int reserved0[3]; }; +#define CRU_BASE 0xfd7c0000 + struct rk3588_cru { struct rk3588_pll pll[18]; unsigned int reserved0[16];/* Address Offset: 0x0240 */ diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3588.h b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h index e0694068bb1..f0ecff97f0b 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3588.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h @@ -32,4 +32,28 @@ struct rk3588_pmu1grf { check_member(rk3588_pmu1grf, sd_detect_cnt, 0x03b0); +#define SYS_GRF_BASE 0xfd58c000 + +struct rk3588_sysgrf { + unsigned int wdt_con0; + unsigned int reserved0[(0x0010 - 0x0000) / 4 - 1]; + unsigned int uart_con[2]; + unsigned int reserved1[(0x00c0 - 0x0014) / 4 - 1]; + unsigned int gic_con0; + unsigned int reserved2[(0x0200 - 0x00c0) / 4 - 1]; + unsigned int memcfg_con[32]; + unsigned int reserved3[(0x0300 - 0x027c) / 4 - 1]; + /* soc_con0 is reserved */ + unsigned int soc_con[14]; + unsigned int reserved4[(0x0380 - 0x0334) / 4 - 1]; + unsigned int soc_status[4]; + unsigned int reserved5[(0x0500 - 0x038c) / 4 - 1]; + unsigned int otp_key08; + unsigned int otp_key0d; + unsigned int otp_key0e; + unsigned int reserved6[(0x0600 - 0x0508) / 4 - 1]; + unsigned int chip_id; +}; + +check_member(rk3588_sysgrf, chip_id, 0x0600); #endif /*__SOC_ROCKCHIP_RK3588_GRF_H__ */ diff --git a/arch/arm/include/asm/arch-rockchip/hardware.h b/arch/arm/include/asm/arch-rockchip/hardware.h index 62e8bed8f31..e4662a2d52d 100644 --- a/arch/arm/include/asm/arch-rockchip/hardware.h +++ b/arch/arm/include/asm/arch-rockchip/hardware.h @@ -6,6 +6,8 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H +#include <asm/io.h> + #define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | (set)) #define RK_SETBITS(set) RK_CLRSETBITS(0, set) #define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) diff --git a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h index 5a656f850c7..7ad98466c39 100644 --- a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h +++ b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h @@ -5,6 +5,8 @@ #ifndef _ASM_ARCH_IOC_RK3588_H #define _ASM_ARCH_IOC_RK3588_H +#define BUS_IOC_BASE 0xfd5f8000 + struct rk3588_bus_ioc { unsigned int reserved0000[3]; /* Address Offset: 0x0000 */ unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x000C */ @@ -48,6 +50,8 @@ struct rk3588_bus_ioc { check_member(rk3588_bus_ioc, gpio4d_iomux_sel_h, 0x009C); +#define PMU1_IOC_BASE 0xfd5f0000 + struct rk3588_pmu1_ioc { unsigned int gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */ unsigned int gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */ @@ -70,6 +74,8 @@ struct rk3588_pmu1_ioc { check_member(rk3588_pmu1_ioc, xin_con, 0x0040); +#define PMU2_IOC_BASE 0xfd5f4000 + struct rk3588_pmu2_ioc { unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x0000 */ unsigned int gpio0c_iomux_sel_l; /* Address Offset: 0x0004 */ diff --git a/arch/arm/include/asm/arch-rockchip/misc.h b/arch/arm/include/asm/arch-rockchip/misc.h deleted file mode 100644 index 4155af8c3b0..00000000000 --- a/arch/arm/include/asm/arch-rockchip/misc.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * RK3399: Architecture common definitions - * - * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/ - * Rohan Garg <rohan.garg@collabora.com> - */ - -int rockchip_cpuid_from_efuse(const u32 cpuid_offset, - const u32 cpuid_length, - u8 *cpuid); -int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length); -int rockchip_setup_macaddr(void); -void rockchip_capsule_update_board_setup(void); diff --git a/arch/arm/include/asm/arch-stv0991/gpio.h b/arch/arm/include/asm/arch-stv0991/gpio.h deleted file mode 100644 index b27f4078582..00000000000 --- a/arch/arm/include/asm/arch-stv0991/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef __ASM_ARCH_STV0991_GPIO_H -#define __ASM_ARCH_STV0991_GPIO_H - -enum gpio_direction { - GPIO_DIRECTION_IN, - GPIO_DIRECTION_OUT, -}; - -struct gpio_regs { - u32 data; /* offset 0x0 */ - u32 reserved[0xff]; /* 0x4--0x3fc */ - u32 dir; /* offset 0x400 */ -}; - -#endif /* __ASM_ARCH_STV0991_GPIO_H */ diff --git a/arch/arm/include/asm/arch-stv0991/hardware.h b/arch/arm/include/asm/arch-stv0991/hardware.h deleted file mode 100644 index ea8f8206300..00000000000 --- a/arch/arm/include/asm/arch-stv0991/hardware.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _ASM_ARCH_HARDWARE_H -#define _ASM_ARCH_HARDWARE_H - -/* STV0991 */ -#define SRAM0_BASE_ADDR 0x00000000UL -#define SRAM1_BASE_ADDR 0x00068000UL -#define SRAM2_BASE_ADDR 0x000D0000UL -#define SRAM3_BASE_ADDR 0x00138000UL -#define CFS_SRAM0_BASE_ADDR 0x00198000UL -#define CFS_SRAM1_BASE_ADDR 0x001B8000UL -#define FAST_SRAM_BASE_ADDR 0x001D8000UL -#define FLASH_BASE_ADDR 0x40000000UL -#define PL310_BASE_ADDR 0x70000000UL -#define HSAXIM_BASE_ADDR 0x70100000UL -#define IMGSS_BASE_ADDR 0x70200000UL -#define ADC_BASE_ADDR 0x80000000UL -#define GPIOA_BASE_ADDR 0x80001000UL -#define GPIOB_BASE_ADDR 0x80002000UL -#define GPIOC_BASE_ADDR 0x80003000UL -#define HDM_BASE_ADDR 0x80004000UL -#define THSENS_BASE_ADDR 0x80200000UL -#define GPTIMER2_BASE_ADDR 0x80201000UL -#define GPTIMER1_BASE_ADDR 0x80202000UL -#define QSPI_BASE_ADDR 0x80203000UL -#define CGU_BASE_ADDR 0x80204000UL -#define CREG_BASE_ADDR 0x80205000UL -#define PEC_BASE_ADDR 0x80206000UL -#define WDRU_BASE_ADDR 0x80207000UL -#define BSEC_BASE_ADDR 0x80208000UL -#define DAP_ROM_BASE_ADDR 0x80210000UL -#define SOC_CTI_BASE_ADDR 0x80211000UL -#define TPIU_BASE_ADDR 0x80212000UL -#define TMC_ETF_BASE_ADDR 0x80213000UL -#define R4_ETM_BASE_ADDR 0x80214000UL -#define R4_CTI_BASE_ADDR 0x80215000UL -#define R4_DBG_BASE_ADDR 0x80216000UL -#define GMAC_BASE_ADDR 0x80300000UL -#define RNSS_BASE_ADDR 0x80302000UL -#define CRYP_BASE_ADDR 0x80303000UL -#define HASH_BASE_ADDR 0x80304000UL -#define GPDMA_BASE_ADDR 0x80305000UL -#define ISA_BASE_ADDR 0x8032A000UL -#define HCI_BASE_ADDR 0x80400000UL -#define I2C1_BASE_ADDR 0x80401000UL -#define I2C2_BASE_ADDR 0x80402000UL -#define SAI_BASE_ADDR 0x80403000UL -#define USI_BASE_ADDR 0x80404000UL -#define SPI1_BASE_ADDR 0x80405000UL -#define UART_BASE_ADDR 0x80406000UL -#define SPI2_BASE_ADDR 0x80500000UL -#define CAN_BASE_ADDR 0x80501000UL -#define USART1_BASE_ADDR 0x80502000UL -#define USART2_BASE_ADDR 0x80503000UL -#define USART3_BASE_ADDR 0x80504000UL -#define USART4_BASE_ADDR 0x80505000UL -#define USART5_BASE_ADDR 0x80506000UL -#define USART6_BASE_ADDR 0x80507000UL -#define SDI2_BASE_ADDR 0x80600000UL -#define SDI1_BASE_ADDR 0x80601000UL -#define VICA_BASE_ADDR 0x81000000UL -#define VICB_BASE_ADDR 0x81001000UL -#define STM_CHANNELS_BASE_ADDR 0x81100000UL -#define STM_BASE_ADDR 0x81110000UL -#define SROM_BASE_ADDR 0xFFFF0000UL - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h deleted file mode 100644 index df9dd54e5a8..00000000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _STV0991_CGU_H -#define _STV0991_CGU_H - -struct stv0991_cgu_regs { - u32 cpu_freq; /* offset 0x0 */ - u32 icn2_freq; /* offset 0x4 */ - u32 dma_freq; /* offset 0x8 */ - u32 isp_freq; /* offset 0xc */ - u32 h264_freq; /* offset 0x10 */ - u32 osif_freq; /* offset 0x14 */ - u32 ren_freq; /* offset 0x18 */ - u32 tim_freq; /* offset 0x1c */ - u32 sai_freq; /* offset 0x20 */ - u32 eth_freq; /* offset 0x24 */ - u32 i2c_freq; /* offset 0x28 */ - u32 spi_freq; /* offset 0x2c */ - u32 uart_freq; /* offset 0x30 */ - u32 qspi_freq; /* offset 0x34 */ - u32 sdio_freq; /* offset 0x38 */ - u32 usi_freq; /* offset 0x3c */ - u32 can_line_freq; /* offset 0x40 */ - u32 debug_freq; /* offset 0x44 */ - u32 trace_freq; /* offset 0x48 */ - u32 stm_freq; /* offset 0x4c */ - u32 eth_ctrl; /* offset 0x50 */ - u32 reserved[3]; /* offset 0x54 */ - u32 osc_ctrl; /* offset 0x60 */ - u32 pll1_ctrl; /* offset 0x64 */ - u32 pll1_freq; /* offset 0x68 */ - u32 pll1_fract; /* offset 0x6c */ - u32 pll1_spread; /* offset 0x70 */ - u32 pll1_status; /* offset 0x74 */ - u32 pll2_ctrl; /* offset 0x78 */ - u32 pll2_freq; /* offset 0x7c */ - u32 pll2_fract; /* offset 0x80 */ - u32 pll2_spread; /* offset 0x84 */ - u32 pll2_status; /* offset 0x88 */ - u32 cgu_enable_1; /* offset 0x8c */ - u32 cgu_enable_2; /* offset 0x90 */ - u32 cgu_isp_pulse; /* offset 0x94 */ - u32 cgu_h264_pulse; /* offset 0x98 */ - u32 cgu_osif_pulse; /* offset 0x9c */ - u32 cgu_ren_pulse; /* offset 0xa0 */ - -}; - -/* CGU Timer */ -#define CLK_TMR_OSC 0 -#define CLK_TMR_MCLK 1 -#define CLK_TMR_PLL1 2 -#define CLK_TMR_PLL2 3 -#define MDIV_SHIFT_TMR 3 -#define DIV_SHIFT_TMR 6 - -#define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \ - | 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK) - -/* Clock Enable/Disable */ - -#define TIMER1_CLK_EN (1 << 15) - -/* CGU Uart config */ -#define CLK_UART_MCLK 0 -#define CLK_UART_PLL1 1 -#define CLK_UART_PLL2 2 - -#define MDIV_SHIFT_UART 3 -#define DIV_SHIFT_UART 6 - -#define UART_CLK_CFG (4 << DIV_SHIFT_UART \ - | 1 << MDIV_SHIFT_UART | CLK_UART_MCLK) - -/* CGU Ethernet clock config */ -#define CLK_ETH_MCLK 0 -#define CLK_ETH_PLL1 1 -#define CLK_ETH_PLL2 2 - -#define MDIV_SHIFT_ETH 3 -#define DIV_SHIFT_ETH 6 -#define DIV_ETH_125 9 -#define DIV_ETH_50 12 -#define DIV_ETH_P2P 15 - -#define ETH_CLK_CFG (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \ - | 1 << DIV_ETH_125 \ - | 0 << DIV_SHIFT_ETH \ - | 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1) - /* CGU Ethernet control */ - -#define ETH_CLK_TX_EXT_PHY 0 -#define ETH_CLK_TX_125M 1 -#define ETH_CLK_TX_25M 2 -#define ETH_CLK_TX_2M5 3 -#define ETH_CLK_TX_DIS 7 - -#define ETH_CLK_RX_EXT_PHY 0 -#define ETH_CLK_RX_25M 1 -#define ETH_CLK_RX_2M5 2 -#define ETH_CLK_RX_DIS 3 -#define RX_CLK_SHIFT 3 -#define ETH_CLK_MASK ~(0x1F) - -#define ETH_PHY_MODE_GMII 0 -#define ETH_PHY_MODE_RMII 1 -#define ETH_PHY_CLK_DIS 1 - -#define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \ - | ETH_CLK_TX_EXT_PHY) -/* CGU qspi clock */ -#define DIV_HCLK1_SHIFT 9 -#define DIV_CRYP_SHIFT 6 -#define MDIV_QSPI_SHIFT 3 - -#define CLK_QSPI_OSC 0 -#define CLK_QSPI_MCLK 1 -#define CLK_QSPI_PLL1 2 -#define CLK_QSPI_PLL2 3 - -#define QSPI_CLK_CTRL (3 << DIV_HCLK1_SHIFT \ - | 1 << DIV_CRYP_SHIFT \ - | 0 << MDIV_QSPI_SHIFT \ - | CLK_QSPI_OSC) - -#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_creg.h b/arch/arm/include/asm/arch-stv0991/stv0991_creg.h deleted file mode 100644 index 4d444a6df16..00000000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_creg.h +++ /dev/null @@ -1,103 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _STV0991_CREG_H -#define _STV0991_CREG_H - -struct stv0991_creg { - u32 version; /* offset 0x0 */ - u32 hdpctl; /* offset 0x4 */ - u32 hdpval; /* offset 0x8 */ - u32 hdpgposet; /* offset 0xc */ - u32 hdpgpoclr; /* offset 0x10 */ - u32 hdpgpoval; /* offset 0x14 */ - u32 stm_mux; /* offset 0x18 */ - u32 sysctrl_1; /* offset 0x1c */ - u32 sysctrl_2; /* offset 0x20 */ - u32 sysctrl_3; /* offset 0x24 */ - u32 sysctrl_4; /* offset 0x28 */ - u32 reserved_1[0x35]; /* offset 0x2C-0xFC */ - u32 mux1; /* offset 0x100 */ - u32 mux2; /* offset 0x104 */ - u32 mux3; /* offset 0x108 */ - u32 mux4; /* offset 0x10c */ - u32 mux5; /* offset 0x110 */ - u32 mux6; /* offset 0x114 */ - u32 mux7; /* offset 0x118 */ - u32 mux8; /* offset 0x11c */ - u32 mux9; /* offset 0x120 */ - u32 mux10; /* offset 0x124 */ - u32 mux11; /* offset 0x128 */ - u32 mux12; /* offset 0x12c */ - u32 mux13; /* offset 0x130 */ - u32 reserved_2[0x33]; /* offset 0x134-0x1FC */ - u32 cfg_pad1; /* offset 0x200 */ - u32 cfg_pad2; /* offset 0x204 */ - u32 cfg_pad3; /* offset 0x208 */ - u32 cfg_pad4; /* offset 0x20c */ - u32 cfg_pad5; /* offset 0x210 */ - u32 cfg_pad6; /* offset 0x214 */ - u32 cfg_pad7; /* offset 0x218 */ - u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */ - u32 vdd_pad1; /* offset 0x300 */ - u32 vdd_pad2; /* offset 0x304 */ - u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */ - u32 vdd_comp1; /* offset 0x400 */ -}; - -/* CREG MUX 13 register */ -#define FLASH_CS_NC_SHIFT 4 -#define FLASH_CS_NC_MASK ~(7 << FLASH_CS_NC_SHIFT) -#define CFG_FLASH_CS_NC (0 << FLASH_CS_NC_SHIFT) - -#define FLASH_CLK_SHIFT 0 -#define FLASH_CLK_MASK ~(7 << FLASH_CLK_SHIFT) -#define CFG_FLASH_CLK (0 << FLASH_CLK_SHIFT) - -/* CREG MUX 12 register */ -#define GPIOC_30_MUX_SHIFT 24 -#define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT) -#define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT) - -#define GPIOC_31_MUX_SHIFT 28 -#define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT) -#define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT) - -/* CREG MUX 7 register */ -#define GPIOB_16_MUX_SHIFT 0 -#define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT) -#define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT) - -#define GPIOB_17_MUX_SHIFT 4 -#define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT) -#define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT) - -/* CREG CFG_PAD6 register */ - -#define GPIOC_31_MODE_SHIFT 30 -#define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT) -#define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT) -#define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT) - -#define GPIOC_30_MODE_SHIFT 28 -#define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT) -#define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT) -#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT) - -/* CREG Ethernet pad config */ - -#define VDD_ETH_PS_1V8 0 -#define VDD_ETH_PS_2V5 2 -#define VDD_ETH_PS_3V3 3 -#define VDD_ETH_PS_MASK 0x3 - -#define VDD_ETH_PS_SHIFT 12 -#define ETH_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT) - -#define VDD_ETH_M_PS_SHIFT 28 -#define ETH_M_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT) - -#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_defs.h b/arch/arm/include/asm/arch-stv0991/stv0991_defs.h deleted file mode 100644 index 98d7cde85bc..00000000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_defs.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef __STV0991_DEFS_H__ -#define __STV0991_DEFS_H__ -#include <asm/arch/stv0991_periph.h> - -extern int stv0991_pinmux_config(enum periph_id); -extern int clock_setup(enum periph_clock); - -#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h deleted file mode 100644 index eb1ddca6002..00000000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _STV0991_GPT_H -#define _STV0991_GPT_H - -#include <asm/arch-stv0991/hardware.h> - -struct gpt_regs { - u32 cr1; - u32 cr2; - u32 reserved_1; - u32 dier; /* dma_int_en */ - u32 sr; /* status reg */ - u32 egr; /* event gen */ - u32 reserved_2[3]; /* offset 0x18--0x20*/ - u32 cnt; - u32 psc; - u32 arr; -}; - -struct gpt_regs *const gpt1_regs_ptr = - (struct gpt_regs *) GPTIMER1_BASE_ADDR; - -/* Timer control1 register */ -#define GPT_CR1_CEN 0x0001 -#define GPT_MODE_AUTO_RELOAD (1 << 7) - -/* Timer prescalar reg */ -#define GPT_PRESCALER_128 0x128 - -/* Auto reload register for free running config */ -#define GPT_FREE_RUNNING 0xFFFF - -/* Timer, HZ specific defines */ -#define CFG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128) - -#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_periph.h b/arch/arm/include/asm/arch-stv0991/stv0991_periph.h deleted file mode 100644 index 7a50be183d4..00000000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_periph.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef __ASM_ARM_ARCH_PERIPH_H -#define __ASM_ARM_ARCH_PERIPH_H - -/* - * Peripherals required for pinmux configuration. List will - * grow with support for more devices getting added. - * Numbering based on interrupt table. - * - */ -enum periph_id { - UART_GPIOC_30_31 = 0, - UART_GPIOB_16_17, - ETH_GPIOB_10_31_C_0_4, - QSPI_CS_CLK_PAD, - PERIPH_ID_I2C0, - PERIPH_ID_I2C1, - PERIPH_ID_I2C2, - PERIPH_ID_I2C3, - PERIPH_ID_I2C4, - PERIPH_ID_I2C5, - PERIPH_ID_I2C6, - PERIPH_ID_I2C7, - PERIPH_ID_SPI0, - PERIPH_ID_SPI1, - PERIPH_ID_SPI2, - PERIPH_ID_SDMMC0, - PERIPH_ID_SDMMC1, - PERIPH_ID_SDMMC2, - PERIPH_ID_SDMMC3, - PERIPH_ID_I2S1, -}; - -enum periph_clock { - UART_CLOCK_CFG = 0, - ETH_CLOCK_CFG, - QSPI_CLOCK_CFG, -}; - -#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h b/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h deleted file mode 100644 index 8cb8a8a6137..00000000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _STV0991_WD_RST_H -#define _STV0991_WD_RST_H -#include <asm/arch-stv0991/hardware.h> - -struct stv0991_wd_ru { - u32 wdru_config; - u32 wdru_ctrl1; - u32 wdru_ctrl2; - u32 wdru_tim; - u32 wdru_count; - u32 wdru_stat; - u32 wdru_wrlock; -}; - -struct stv0991_wd_ru *const stv0991_wd_ru_ptr = \ - (struct stv0991_wd_ru *)WDRU_BASE_ADDR; - -/* Watchdog control register */ -#define WDRU_RST_SYS 0x1 - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h index fe6b8ba2732..0264bfe1c50 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -220,10 +220,7 @@ struct sunxi_ccm_reg { #ifndef __ASSEMBLY__ void clock_set_pll1(unsigned int clk); -void clock_set_pll2(unsigned int clk); -void clock_set_pll4(unsigned int clk); void clock_set_pll6(unsigned int clk); -void clock_set_pll12(unsigned int clk); unsigned int clock_get_pll4_periph0(void); #endif diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h b/arch/arm/include/asm/arch-sunxi/tzpc.h index 7a6fcaebdb5..92696088a39 100644 --- a/arch/arm/include/asm/arch-sunxi/tzpc.h +++ b/arch/arm/include/asm/arch-sunxi/tzpc.h @@ -28,6 +28,12 @@ struct sunxi_tzpc { #define SUN8I_H3_TZPC_DECPORT1_ALL 0xff #define SUN8I_H3_TZPC_DECPORT2_ALL 0x7f +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 void tzpc_init(void); +#else +static inline void tzpc_init(void) +{ +} +#endif #endif /* _SUNXI_TZPC_H */ diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h index 7613d84f221..ca3718411ab 100644 --- a/arch/arm/include/asm/arch-tegra/dc.h +++ b/arch/arm/include/asm/arch-tegra/dc.h @@ -443,6 +443,11 @@ enum win_color_depth_id { #define WINDOW_D_SELECT BIT(7) #define WINDOW_H_SELECT BIT(8) +/* DC_COM_PIN_OUTPUT_POLARITY1 0x307 */ +#define LHS_OUTPUT_POLARITY_LOW BIT(30) +#define LVS_OUTPUT_POLARITY_LOW BIT(28) +#define LSC0_OUTPUT_POLARITY_LOW BIT(24) + /* DC_DISP_DISP_WIN_OPTIONS 0x402 */ #define CURSOR_ENABLE BIT(16) #define SOR_ENABLE BIT(25) @@ -569,12 +574,4 @@ enum { #define DC_N_WINDOWS 5 #define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5) -#define TEGRA_DSI_A "dsi@54300000" -#define TEGRA_DSI_B "dsi@54400000" - -struct tegra_dc_plat { - struct udevice *dev; /* Display controller device */ - struct dc_ctlr *dc; /* Display controller regmap */ -}; - #endif /* __ASM_ARCH_TEGRA_DC_H */ diff --git a/arch/arm/include/asm/arch-tegra114/pwm.h b/arch/arm/include/asm/arch-tegra114/pwm.h new file mode 100644 index 00000000000..af391518035 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/pwm.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Tegra pulse width frequency modulator definitions + * + * Copyright (c) 2011 The Chromium OS Authors. + */ + +#ifndef __ASM_ARCH_TEGRA114_PWM_H +#define __ASM_ARCH_TEGRA114_PWM_H + +#include <asm/arch-tegra/pwm.h> + +#endif /* __ASM_ARCH_TEGRA114_PWM_H */ diff --git a/arch/arm/include/asm/arch-tegra20/display.h b/arch/arm/include/asm/arch-tegra20/display.h deleted file mode 100644 index e7b3cffd466..00000000000 --- a/arch/arm/include/asm/arch-tegra20/display.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __ASM_ARCH_TEGRA_DISPLAY_H -#define __ASM_ARCH_TEGRA_DISPLAY_H - -#include <asm/arch-tegra/dc.h> - -/* This holds information about a window which can be displayed */ -struct disp_ctl_win { - enum win_color_depth_id fmt; /* Color depth/format */ - unsigned bpp; /* Bits per pixel */ - phys_addr_t phys_addr; /* Physical address in memory */ - unsigned x; /* Horizontal address offset (bytes) */ - unsigned y; /* Veritical address offset (bytes) */ - unsigned w; /* Width of source window */ - unsigned h; /* Height of source window */ - unsigned stride; /* Number of bytes per line */ - unsigned out_x; /* Left edge of output window (col) */ - unsigned out_y; /* Top edge of output window (row) */ - unsigned out_w; /* Width of output window in pixels */ - unsigned out_h; /* Height of output window in pixels */ -}; - -#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/arch/arm/include/asm/arch-tegra30/display.h b/arch/arm/include/asm/arch-tegra30/display.h deleted file mode 100644 index 9411525799d..00000000000 --- a/arch/arm/include/asm/arch-tegra30/display.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __ASM_ARCH_TEGRA_DISPLAY_H -#define __ASM_ARCH_TEGRA_DISPLAY_H - -#include <asm/arch-tegra/dc.h> - -/* This holds information about a window which can be displayed */ -struct disp_ctl_win { - enum win_color_depth_id fmt; /* Color depth/format */ - unsigned int bpp; /* Bits per pixel */ - phys_addr_t phys_addr; /* Physical address in memory */ - unsigned int x; /* Horizontal address offset (bytes) */ - unsigned int y; /* Veritical address offset (bytes) */ - unsigned int w; /* Width of source window */ - unsigned int h; /* Height of source window */ - unsigned int stride; /* Number of bytes per line */ - unsigned int out_x; /* Left edge of output window (col) */ - unsigned int out_y; /* Top edge of output window (row) */ - unsigned int out_w; /* Width of output window in pixels */ - unsigned int out_h; /* Height of output window in pixels */ -}; - -#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/arch/arm/include/asm/arch-tegra30/dsi.h b/arch/arm/include/asm/arch-tegra30/dsi.h deleted file mode 100644 index 7ade132613f..00000000000 --- a/arch/arm/include/asm/arch-tegra30/dsi.h +++ /dev/null @@ -1,217 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __ASM_ARCH_TEGRA_DSI_H -#define __ASM_ARCH_TEGRA_DSI_H - -#ifndef __ASSEMBLY__ -#include <linux/bitops.h> -#endif - -/* Register definitions for the Tegra display serial interface */ - -/* DSI syncpoint register 0x000 ~ 0x002 */ -struct dsi_syncpt_reg { - /* Address 0x000 ~ 0x002 */ - uint incr_syncpt; /* _INCR_SYNCPT_0 */ - uint incr_syncpt_ctrl; /* _INCR_SYNCPT_CNTRL_0 */ - uint incr_syncpt_err; /* _INCR_SYNCPT_ERROR_0 */ -}; - -/* DSI misc register 0x008 ~ 0x015 */ -struct dsi_misc_reg { - /* Address 0x008 ~ 0x015 */ - uint ctxsw; /* _CTXSW_0 */ - uint dsi_rd_data; /* _DSI_RD_DATA_0 */ - uint dsi_wr_data; /* _DSI_WR_DATA_0 */ - uint dsi_pwr_ctrl; /* _DSI_POWER_CONTROL_0 */ - uint int_enable; /* _INT_ENABLE_0 */ - uint int_status; /* _INT_STATUS_0 */ - uint int_mask; /* _INT_MASK_0 */ - uint host_dsi_ctrl; /* _HOST_DSI_CONTROL_0 */ - uint dsi_ctrl; /* _DSI_CONTROL_0 */ - uint dsi_sol_delay; /* _DSI_SOL_DELAY_0 */ - uint dsi_max_threshold; /* _DSI_MAX_THRESHOLD_0 */ - uint dsi_trigger; /* _DSI_TRIGGER_0 */ - uint dsi_tx_crc; /* _DSI_TX_CRC_0 */ - uint dsi_status; /* _DSI_STATUS_0 */ -}; - -/* DSI init sequence register 0x01a ~ 0x022 */ -struct dsi_init_seq_reg { - /* Address 0x01a ~ 0x022 */ - uint dsi_init_seq_ctrl; /* _DSI_INIT_SEQ_CONTROL_0 */ - uint dsi_init_seq_data_0; /* _DSI_INIT_SEQ_DATA_0_0 */ - uint dsi_init_seq_data_1; /* _DSI_INIT_SEQ_DATA_1_0 */ - uint dsi_init_seq_data_2; /* _DSI_INIT_SEQ_DATA_2_0 */ - uint dsi_init_seq_data_3; /* _DSI_INIT_SEQ_DATA_3_0 */ - uint dsi_init_seq_data_4; /* _DSI_INIT_SEQ_DATA_4_0 */ - uint dsi_init_seq_data_5; /* _DSI_INIT_SEQ_DATA_5_0 */ - uint dsi_init_seq_data_6; /* _DSI_INIT_SEQ_DATA_6_0 */ - uint dsi_init_seq_data_7; /* _DSI_INIT_SEQ_DATA_7_0 */ -}; - -/* DSI packet sequence register 0x023 ~ 0x02e */ -struct dsi_pkt_seq_reg { - /* Address 0x023 ~ 0x02e */ - uint dsi_pkt_seq_0_lo; /* _DSI_PKT_SEQ_0_LO_0 */ - uint dsi_pkt_seq_0_hi; /* _DSI_PKT_SEQ_0_HI_0 */ - uint dsi_pkt_seq_1_lo; /* _DSI_PKT_SEQ_1_LO_0 */ - uint dsi_pkt_seq_1_hi; /* _DSI_PKT_SEQ_1_HI_0 */ - uint dsi_pkt_seq_2_lo; /* _DSI_PKT_SEQ_2_LO_0 */ - uint dsi_pkt_seq_2_hi; /* _DSI_PKT_SEQ_2_HI_0 */ - uint dsi_pkt_seq_3_lo; /* _DSI_PKT_SEQ_3_LO_0 */ - uint dsi_pkt_seq_3_hi; /* _DSI_PKT_SEQ_3_HI_0 */ - uint dsi_pkt_seq_4_lo; /* _DSI_PKT_SEQ_4_LO_0 */ - uint dsi_pkt_seq_4_hi; /* _DSI_PKT_SEQ_4_HI_0 */ - uint dsi_pkt_seq_5_lo; /* _DSI_PKT_SEQ_5_LO_0 */ - uint dsi_pkt_seq_5_hi; /* _DSI_PKT_SEQ_5_HI_0 */ -}; - -/* DSI packet length register 0x033 ~ 0x037 */ -struct dsi_pkt_len_reg { - /* Address 0x033 ~ 0x037 */ - uint dsi_dcs_cmds; /* _DSI_DCS_CMDS_0 */ - uint dsi_pkt_len_0_1; /* _DSI_PKT_LEN_0_1_0 */ - uint dsi_pkt_len_2_3; /* _DSI_PKT_LEN_2_3_0 */ - uint dsi_pkt_len_4_5; /* _DSI_PKT_LEN_4_5_0 */ - uint dsi_pkt_len_6_7; /* _DSI_PKT_LEN_6_7_0 */ -}; - -/* DSI PHY timing register 0x03c ~ 0x03f */ -struct dsi_timing_reg { - /* Address 0x03c ~ 0x03f */ - uint dsi_phy_timing_0; /* _DSI_PHY_TIMING_0_0 */ - uint dsi_phy_timing_1; /* _DSI_PHY_TIMING_1_0 */ - uint dsi_phy_timing_2; /* _DSI_PHY_TIMING_2_0 */ - uint dsi_bta_timing; /* _DSI_BTA_TIMING_0 */ -}; - -/* DSI timeout register 0x044 ~ 0x046 */ -struct dsi_timeout_reg { - /* Address 0x044 ~ 0x046 */ - uint dsi_timeout_0; /* _DSI_TIMEOUT_0_0 */ - uint dsi_timeout_1; /* _DSI_TIMEOUT_1_0 */ - uint dsi_to_tally; /* _DSI_TO_TALLY_0 */ -}; - -/* DSI PAD control register 0x04b ~ 0x04e */ -struct dsi_pad_ctrl_reg { - /* Address 0x04b ~ 0x04e */ - uint pad_ctrl; /* _PAD_CONTROL_0 */ - uint pad_ctrl_cd; /* _PAD_CONTROL_CD_0 */ - uint pad_cd_status; /* _PAD_CD_STATUS_0 */ - uint dsi_vid_mode_control; /* _DSI_VID_MODE_CONTROL_0 */ -}; - -/* Display Serial Interface (DSI_) regs */ -struct dsi_ctlr { - struct dsi_syncpt_reg syncpt; /* SYNCPT register 0x000 ~ 0x002 */ - uint reserved0[5]; /* reserved_0[5] */ - - struct dsi_misc_reg misc; /* MISC register 0x008 ~ 0x015 */ - uint reserved1[4]; /* reserved_1[4] */ - - struct dsi_init_seq_reg init; /* INIT register 0x01a ~ 0x022 */ - struct dsi_pkt_seq_reg pkt; /* PKT register 0x023 ~ 0x02e */ - uint reserved2[4]; /* reserved_2[4] */ - - struct dsi_pkt_len_reg len; /* LEN registers 0x033 ~ 0x037 */ - uint reserved3[4]; /* reserved_3[4] */ - - struct dsi_timing_reg ptiming; /* TIMING registers 0x03c ~ 0x03f */ - uint reserved4[4]; /* reserved_4[4] */ - - struct dsi_timeout_reg timeout; /* TIMEOUT registers 0x044 ~ 0x046 */ - uint reserved5[4]; /* reserved_5[4] */ - - struct dsi_pad_ctrl_reg pad; /* PAD registers 0x04b ~ 0x04e */ -}; - -#define DSI_POWER_CONTROL_ENABLE BIT(0) - -#define DSI_HOST_CONTROL_FIFO_RESET BIT(21) -#define DSI_HOST_CONTROL_CRC_RESET BIT(20) -#define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12) -#define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12) -#define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12) -#define DSI_HOST_CONTROL_RAW BIT(6) -#define DSI_HOST_CONTROL_HS BIT(5) -#define DSI_HOST_CONTROL_FIFO_SEL BIT(4) -#define DSI_HOST_CONTROL_IMM_BTA BIT(3) -#define DSI_HOST_CONTROL_PKT_BTA BIT(2) -#define DSI_HOST_CONTROL_CS BIT(1) -#define DSI_HOST_CONTROL_ECC BIT(0) - -#define DSI_CONTROL_HS_CLK_CTRL BIT(20) -#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16) -#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12) -#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8) -#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4) -#define DSI_CONTROL_DCS_ENABLE BIT(3) -#define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2) -#define DSI_CONTROL_VIDEO_ENABLE BIT(1) -#define DSI_CONTROL_HOST_ENABLE BIT(0) - -#define DSI_TRIGGER_HOST BIT(1) -#define DSI_TRIGGER_VIDEO BIT(0) - -#define DSI_STATUS_IDLE BIT(10) -#define DSI_STATUS_UNDERFLOW BIT(9) -#define DSI_STATUS_OVERFLOW BIT(8) - -#define DSI_TIMING_FIELD(value, period, hwinc) \ - ((DIV_ROUND_CLOSEST(value, period) - (hwinc)) & 0xff) - -#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16) -#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0) -#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16) -#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0) - -#define DSI_TALLY_TA(x) (((x) & 0xff) << 16) -#define DSI_TALLY_LRX(x) (((x) & 0xff) << 8) -#define DSI_TALLY_HTX(x) (((x) & 0xff) << 0) - -#define DSI_PAD_CONTROL_PAD_PULLDN_ENAB(x) (((x) & 0x1) << 28) -#define DSI_PAD_CONTROL_PAD_SLEWUPADJ(x) (((x) & 0x7) << 24) -#define DSI_PAD_CONTROL_PAD_SLEWDNADJ(x) (((x) & 0x7) << 20) -#define DSI_PAD_CONTROL_PAD_PREEMP_EN(x) (((x) & 0x1) << 19) -#define DSI_PAD_CONTROL_PAD_PDIO_CLK(x) (((x) & 0x1) << 18) -#define DSI_PAD_CONTROL_PAD_PDIO(x) (((x) & 0x3) << 16) -#define DSI_PAD_CONTROL_PAD_LPUPADJ(x) (((x) & 0x3) << 14) -#define DSI_PAD_CONTROL_PAD_LPDNADJ(x) (((x) & 0x3) << 12) - -/* - * pixel format as used in the DSI_CONTROL_FORMAT field - */ -enum tegra_dsi_format { - TEGRA_DSI_FORMAT_16P, - TEGRA_DSI_FORMAT_18NP, - TEGRA_DSI_FORMAT_18P, - TEGRA_DSI_FORMAT_24P, -}; - -/* DSI calibration in VI region */ -#define TEGRA_VI_BASE 0x54080000 - -#define CSI_CILA_MIPI_CAL_CONFIG_0 0x22a -#define MIPI_CAL_TERMOSA(x) (((x) & 0x1f) << 0) - -#define CSI_CILB_MIPI_CAL_CONFIG_0 0x22b -#define MIPI_CAL_TERMOSB(x) (((x) & 0x1f) << 0) - -#define CSI_CIL_PAD_CONFIG 0x229 -#define PAD_CIL_PDVREG(x) (((x) & 0x01) << 1) - -#define CSI_DSI_MIPI_CAL_CONFIG 0x234 -#define MIPI_CAL_HSPDOSD(x) (((x) & 0x1f) << 16) -#define MIPI_CAL_HSPUOSD(x) (((x) & 0x1f) << 8) - -#define CSI_MIPIBIAS_PAD_CONFIG 0x235 -#define PAD_DRIV_DN_REF(x) (((x) & 0x7) << 16) -#define PAD_DRIV_UP_REF(x) (((x) & 0x7) << 8) - -#endif /* __ASM_ARCH_TEGRA_DSI_H */ diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h index bd3a80cdf70..fb64ba076d7 100644 --- a/arch/arm/include/asm/gic.h +++ b/arch/arm/include/asm/gic.h @@ -57,6 +57,7 @@ #define GICR_TYPER 0x0008 #define GICR_STATUSR 0x0010 #define GICR_WAKER 0x0014 +#define GICR_PWRR 0x0024 #define GICR_SETLPIR 0x0040 #define GICR_CLRLPIR 0x0048 #define GICR_SEIR 0x0068 diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index cfd4ecebb62..a29b849d903 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -24,6 +24,7 @@ #define ELE_GET_FW_VERSION_REQ (0x9D) #define ELE_RET_LIFECYCLE_UP_REQ (0xA0) #define ELE_GET_EVENTS_REQ (0xA2) +#define ELE_COMMIT_REQ (0xA8) #define ELE_START_RNG (0xA3) #define ELE_GENERATE_DEK_BLOB (0xAF) #define ELE_ENABLE_PATCH_REQ (0xC3) @@ -142,6 +143,7 @@ int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respon int ele_release_caam(u32 core_did, u32 *response); int ele_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response); int ele_get_events(u32 *events, u32 *events_cnt, u32 *response); +int ele_commit(u16 fuse_id, u32 *response, u32 *info_type); int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32 max_output_size); int ele_dump_buffer(u32 *buffer, u32 buffer_length); int ele_get_info(struct ele_get_info_data *info, u32 *response); diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index b1bcd374662..67275fba616 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -85,6 +85,8 @@ obj-y += psci-dt.o obj-$(CONFIG_DEBUG_LL) += debug.o +obj-$(CONFIG_BLOBLIST) += xferlist.o + # For EABI conformant tool chains, provide eabi_compat() ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) extra-y += eabi_compat.o diff --git a/arch/arm/lib/crt0_aarch64_efi.S b/arch/arm/lib/crt0_aarch64_efi.S index 3c2cef6ec73..fe6eca576ec 100644 --- a/arch/arm/lib/crt0_aarch64_efi.S +++ b/arch/arm/lib/crt0_aarch64_efi.S @@ -66,7 +66,11 @@ extra_header_fields: .long _start - ImageBase /* SizeOfHeaders */ .long 0 /* CheckSum */ .short IMAGE_SUBSYSTEM_EFI_APPLICATION /* Subsystem */ +#if CONFIG_VENDOR_EFI .short 0 /* DllCharacteristics */ +#else + .short IMAGE_DLLCHARACTERISTICS_NX_COMPAT +#endif .quad 0 /* SizeOfStackReserve */ .quad 0 /* SizeOfStackCommit */ .quad 0 /* SizeOfHeapReserve */ diff --git a/arch/arm/lib/crt0_arm_efi.S b/arch/arm/lib/crt0_arm_efi.S index 75ee37b7d31..b5dfd4e3819 100644 --- a/arch/arm/lib/crt0_arm_efi.S +++ b/arch/arm/lib/crt0_arm_efi.S @@ -23,7 +23,7 @@ pe_header: .long IMAGE_NT_SIGNATURE /* 'PE' */ coff_header: .short IMAGE_FILE_MACHINE_THUMB /* Mixed ARM/Thumb */ - .short 2 /* nr_sections */ + .short 3 /* nr_sections */ .long 0 /* TimeDateStamp */ .long 0 /* PointerToSymbolTable */ .long 0 /* NumberOfSymbols */ @@ -65,7 +65,11 @@ extra_header_fields: .long _start - image_base /* SizeOfHeaders */ .long 0 /* CheckSum */ .short IMAGE_SUBSYSTEM_EFI_APPLICATION /* Subsystem */ +#if CONFIG_VENDOR_EFI .short 0 /* DllCharacteristics */ +#else + .short IMAGE_DLLCHARACTERISTICS_NX_COMPAT +#endif .long 0 /* SizeOfStackReserve */ .long 0 /* SizeOfStackCommit */ .long 0 /* SizeOfHeapReserve */ @@ -98,31 +102,53 @@ section_table: .long 0 /* PointerToLineNumbers */ .short 0 /* NumberOfRelocations */ .short 0 /* NumberOfLineNumbers */ - .long 0x42100040 /* Characteristics (section flags) */ + /* Characteristics (section flags) */ + .long (IMAGE_SCN_MEM_READ | \ + IMAGE_SCN_MEM_DISCARDABLE | \ + IMAGE_SCN_CNT_INITIALIZED_DATA) .ascii ".text" .byte 0 .byte 0 .byte 0 /* end of 0 padding of section name */ - .long _edata - _start /* VirtualSize */ + .long _text_size /* VirtualSize */ .long _start - image_base /* VirtualAddress */ - .long _edata - _start /* SizeOfRawData */ + .long _text_size /* SizeOfRawData */ .long _start - image_base /* PointerToRawData */ + .long 0 /* PointerToRelocations */ + .long 0 /* PointerToLineNumbers */ + .short 0 /* NumberOfRelocations */ + .short 0 /* NumberOfLineNumbers */ + /* Characteristics (section flags) */ + .long (IMAGE_SCN_MEM_READ | \ + IMAGE_SCN_MEM_EXECUTE | \ + IMAGE_SCN_CNT_CODE) - .long 0 /* PointerToRelocations (0 for executables) */ - .long 0 /* PointerToLineNumbers (0 for executables) */ - .short 0 /* NumberOfRelocations (0 for executables) */ - .short 0 /* NumberOfLineNumbers (0 for executables) */ - .long 0xe0500020 /* Characteristics (section flags) */ + .ascii ".data" + .byte 0 + .byte 0 + .byte 0 /* end of 0 padding of section name */ + .long _data_size /* VirtualSize */ + .long _data - image_base /* VirtualAddress */ + .long _data_size /* SizeOfRawData */ + .long _data - image_base /* PointerToRawData */ + .long 0 /* PointerToRelocations */ + .long 0 /* PointerToLineNumbers */ + .short 0 /* NumberOfRelocations */ + .short 0 /* NumberOfLineNumbers */ + /* Characteristics (section flags) */ + .long (IMAGE_SCN_MEM_WRITE | \ + IMAGE_SCN_MEM_READ | \ + IMAGE_SCN_CNT_INITIALIZED_DATA) - .align 9 + .align 12 _start: stmfd sp!, {r0-r2, lr} adr r1, .L_DYNAMIC ldr r0, [r1] add r1, r0, r1 - adr r0, image_base + adrl r0, image_base bl _relocate teq r0, #0 bne 0f diff --git a/arch/arm/lib/elf_arm_efi.lds b/arch/arm/lib/elf_arm_efi.lds index 767ebda6351..41440594aa6 100644 --- a/arch/arm/lib/elf_arm_efi.lds +++ b/arch/arm/lib/elf_arm_efi.lds @@ -7,6 +7,12 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) + +PHDRS +{ + data PT_LOAD FLAGS(3); /* PF_W | PF_X */ +} + ENTRY(_start) SECTIONS { @@ -18,11 +24,13 @@ SECTIONS *(.gnu.linkonce.t.*) *(.srodata) *(.rodata*) + . = ALIGN(16); + *(.dynamic); . = ALIGN(512); } _etext = .; _text_size = . - _text; - .dynamic : { *(.dynamic) } + . = ALIGN(4096); .data : { _data = .; *(.sdata) @@ -47,14 +55,20 @@ SECTIONS . = ALIGN(512); _bss_end = .; _edata = .; - } - .rel.dyn : { *(.rel.dyn) } - .rel.plt : { *(.rel.plt) } - .rel.got : { *(.rel.got) } - .rel.data : { *(.rel.data) *(.rel.data*) } - _data_size = . - _etext; + } :data + _data_size = . - _data; /DISCARD/ : { + /* + * We don't support relocations. These would have to be + * translated from ELF to PE format and added to the .reloc + * section. + */ + *(.rel.dyn) + *(.rel.plt) + *(.rel.got) + *(.rel.data) + *(.rel.data*) *(.rel.reloc) *(.eh_frame) *(.note.GNU-stack) diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S index 86cd882fc75..7fa48648d9d 100644 --- a/arch/arm/lib/gic_64.S +++ b/arch/arm/lib/gic_64.S @@ -92,8 +92,16 @@ ENTRY(gic_init_secure_percpu) add x9, x9, #(2 << 16) b 1b +2: +#if defined(CONFIG_GICV3_SUPPORT_GIC600) + mov w10, #0x0 /* Power on redistributor */ + str w10, [x9, GICR_PWRR] +5: ldr w10, [x9, GICR_PWRR] /* Wait until the power on state is reflected */ + tbnz w10, #1, 5b /* If RDPD == 0 then powered on */ +#endif + /* x9: ReDistributor Base Address of Current CPU */ -2: mov w10, #~0x2 + mov w10, #~0x2 ldr w11, [x9, GICR_WAKER] and w11, w11, w10 /* Clear ProcessorSleep */ str w11, [x9, GICR_WAKER] diff --git a/arch/arm/lib/save_prev_bl_data.c b/arch/arm/lib/save_prev_bl_data.c index f7b23faf0d6..b286bac9bf0 100644 --- a/arch/arm/lib/save_prev_bl_data.c +++ b/arch/arm/lib/save_prev_bl_data.c @@ -45,6 +45,11 @@ bool is_addr_accessible(phys_addr_t addr) return false; } +phys_addr_t get_prev_bl_fdt_addr(void) +{ + return reg0; +} + int save_prev_bl_data(void) { struct fdt_header *fdt_blob; diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c index 857879711c6..db5463b2bbb 100644 --- a/arch/arm/lib/sections.c +++ b/arch/arm/lib/sections.c @@ -19,18 +19,8 @@ * aliasing warnings. */ -char __bss_start[0] __section(".__bss_start"); -char __bss_end[0] __section(".__bss_end"); -char __image_copy_start[0] __section(".__image_copy_start"); -char __image_copy_end[0] __section(".__image_copy_end"); -char __rel_dyn_start[0] __section(".__rel_dyn_start"); -char __rel_dyn_end[0] __section(".__rel_dyn_end"); char __secure_start[0] __section(".__secure_start"); char __secure_end[0] __section(".__secure_end"); char __secure_stack_start[0] __section(".__secure_stack_start"); char __secure_stack_end[0] __section(".__secure_stack_end"); -char __efi_runtime_start[0] __section(".__efi_runtime_start"); -char __efi_runtime_stop[0] __section(".__efi_runtime_stop"); -char __efi_runtime_rel_start[0] __section(".__efi_runtime_rel_start"); -char __efi_runtime_rel_stop[0] __section(".__efi_runtime_rel_stop"); char _end[0] __section(".__end"); diff --git a/arch/arm/lib/xferlist.c b/arch/arm/lib/xferlist.c new file mode 100644 index 00000000000..f9c5d88bd47 --- /dev/null +++ b/arch/arm/lib/xferlist.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Linaro Limited + * Author: Raymond Mao <raymond.mao@linaro.org> + */ +#include <linux/types.h> +#include <errno.h> +#include <bloblist.h> +#include "xferlist.h" + +int xferlist_from_boot_arg(ulong addr, ulong size) +{ + int ret; + + ret = bloblist_check(saved_args[3], size); + if (ret) + return ret; + + ret = bloblist_check_reg_conv(saved_args[0], saved_args[2], + saved_args[1]); + if (ret) + return ret; + + return bloblist_reloc((void *)addr, size); +} diff --git a/arch/arm/lib/xferlist.h b/arch/arm/lib/xferlist.h new file mode 100644 index 00000000000..60d79c1a8eb --- /dev/null +++ b/arch/arm/lib/xferlist.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause */ +/* + * Copyright (C) 2023 Linaro Limited + * Author: Raymond Mao <raymond.mao@linaro.org> + */ + +#ifndef _XFERLIST_H_ +#define _XFERLIST_H_ + +/* + * Boot parameters saved from start.S + * saved_args[0]: FDT base address + * saved_args[1]: Bloblist signature + * saved_args[2]: must be 0 + * saved_args[3]: Bloblist base address + */ +extern unsigned long saved_args[]; + +#endif /* _XFERLIST_H_ */ diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds index 37f0ccd9220..ada6570d971 100644 --- a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds +++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds @@ -22,9 +22,9 @@ SECTIONS . = 0x00000000; . = ALIGN(4); + __image_copy_start = ADDR(.text); .text : { - __image_copy_start = .; *(.vectors) CPUDIR/start.o (.text*) *(.text*) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index c5fd8692721..8a8ac53e4f8 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -286,6 +286,15 @@ config TARGET_SAMA7G5EK select BOARD_EARLY_INIT_F select BOARD_LATE_INIT +config TARGET_SAMA7G54_CURIOSITY + bool "SAMA7G54 CURIOSITY board" + select SAMA7G5 + select CPU_V7A + help + The SAMA7G54 Curiosity embeds SAMA7G54D2G SiP (System in Package) + with 2Gbit DDR3-SDRAM, 64Mbit QSPI nor-flash with MAC-address, + 4Gbit SLC nand-flash, MCP16502 PMIC, 2 x Mikrobus connectors, + 1 x SD-Card connector, 1 x M.2 slot, 3 x USB config TARGET_TAURUS bool "Support taurus" @@ -366,6 +375,7 @@ source "board/atmel/at91sam9x5ek/Kconfig" source "board/atmel/sam9x60ek/Kconfig" source "board/atmel/sam9x60_curiosity/Kconfig" source "board/atmel/sama7g5ek/Kconfig" +source "board/atmel/sama7g54_curiosity/Kconfig" source "board/atmel/sama5d2_ptc_ek/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d27_som1_ek/Kconfig" diff --git a/arch/arm/mach-imx/ddrmc-vf610-calibration.c b/arch/arm/mach-imx/ddrmc-vf610-calibration.c index cd7e95e61d0..7d787d04598 100644 --- a/arch/arm/mach-imx/ddrmc-vf610-calibration.c +++ b/arch/arm/mach-imx/ddrmc-vf610-calibration.c @@ -45,7 +45,7 @@ * based on trace length differences from their * layout. * Mismatches up to 25% or tCK (clock period) are - * allowed, so the value in the filed doesn’t have + * allowed, so the value in the filed doesn't have * to be very accurate. * * - 0x2 (b'10) - RDLVL_DL_0/1 - refers to adjusting the DQS strobe in relation @@ -184,14 +184,14 @@ static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr) debug("RDLVL: PHY_RDLVL_EDGE:\t 0x%x\n", (tmp >> DDRMC_CR101_PHY_RDLVL_EDGE_OFF) & 0x1); //set 0 - /* Program Leveling mode - CR93[SW_LVL_MODE] to ’b10 */ + /* Program Leveling mode - CR93[SW_LVL_MODE] to 'b10 */ clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SW_LVL_MODE(0x3), DDRMC_CR93_SW_LVL_MODE(0x2)); tmp = readl(&ddrmr->cr[93]); debug("RDLVL: SW_LVL_MODE:\t 0x%x\n", (tmp >> DDRMC_CR93_SW_LVL_MODE_OFF) & 0x3); - /* Start procedure - CR93[SWLVL_START] to ’b1 */ + /* Start procedure - CR93[SWLVL_START] to 'b1 */ sw_leveling_start; /* Poll CR94[SWLVL_OP_DONE] */ @@ -211,7 +211,7 @@ static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr) 0xFFFF << DDRMC_CR105_RDLVL_DL_0_OFF, i << DDRMC_CR105_RDLVL_DL_0_OFF); - /* Load values CR93[SWLVL_LOAD] to ’b1 */ + /* Load values CR93[SWLVL_LOAD] to 'b1 */ sw_leveling_load_value; /* Poll CR94[SWLVL_OP_DONE] */ @@ -263,7 +263,7 @@ static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr) 0xFFFF << DDRMC_CR110_RDLVL_DL_1_OFF, i << DDRMC_CR110_RDLVL_DL_1_OFF); - /* Load values CR93[SWLVL_LOAD] to ’b1 */ + /* Load values CR93[SWLVL_LOAD] to 'b1 */ sw_leveling_load_value; /* Poll CR94[SWLVL_OP_DONE] */ @@ -317,7 +317,7 @@ static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr) sw_leveling_load_value; sw_leveling_op_done; - /* Exit procedure - CR94[SWLVL_EXIT] to ’b1 */ + /* Exit procedure - CR94[SWLVL_EXIT] to 'b1 */ sw_leveling_exit; /* Poll CR94[SWLVL_OP_DONE] */ diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 295c055ad0a..d02316ed6cb 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -625,6 +625,29 @@ static int do_ahab_return_lifecycle(struct cmd_tbl *cmdtp, int flag, int argc, c return CMD_RET_SUCCESS; } +static int do_ahab_commit(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + u32 index; + u32 resp; + u32 info_type; + + if (argc < 2) + return CMD_RET_USAGE; + + index = simple_strtoul(argv[1], NULL, 16); + printf("Commit index is 0x%x\n", index); + + if (ele_commit(index, &resp, &info_type)) { + printf("Error in AHAB commit\n"); + return -EIO; + } + + printf("Ahab commit succeeded. Information type is 0x%x\n", info_type); + + return 0; +} + U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate, "autenticate OS container via AHAB", "addr\n" @@ -657,3 +680,9 @@ U_BOOT_CMD(ahab_return_lifecycle, CONFIG_SYS_MAXARGS, 1, do_ahab_return_lifecycl "addr\n" "addr - Return lifecycle message block signed by OEM SRK\n" ); + +U_BOOT_CMD(ahab_commit, CONFIG_SYS_MAXARGS, 1, do_ahab_commit, + "commit into the fuses any new SRK revocation and FW version information\n" + "that have been found into the NXP (ELE FW) and OEM containers", + "" +); diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index c9455fe222a..35da0ae0425 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -262,7 +262,7 @@ static int get_imageset_end(void *dev, int dev_type) } #ifdef CONFIG_SPL_SPI_LOAD -unsigned long spl_spi_get_uboot_offs(struct spi_flash *flash) +unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash) { int end; diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 0b91e448a5d..6e643188f40 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -84,6 +84,10 @@ static char *get_reset_cause(void) } } +__weak void reset_cpu(void) +{ +} + int arch_cpu_init(void) { #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 328c3e38805..23d9217fcc2 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -53,6 +53,7 @@ config TARGET_IMX8MQ_EVK select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_IMX8MQ_PHANBELL bool "imx8mq_phanbell" @@ -78,6 +79,7 @@ config TARGET_IMX8MM_EVK select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_IMX8MM_ICORE_MX8MM bool "Engicam i.Core MX8M Mini SOM" @@ -119,6 +121,7 @@ config TARGET_IMX8MM_VENICE select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_KONTRON_MX8MM bool "Kontron Electronics N80xx" @@ -148,6 +151,7 @@ config TARGET_IMX8MN_EVK select IMX8M_LPDDR4 select FSL_CAAM select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_IMX8MN_DDR4_EVK bool "imx8mn DDR4 EVK board" @@ -156,6 +160,7 @@ config TARGET_IMX8MN_DDR4_EVK select IMX8M_DDR4 select FSL_CAAM select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_IMX8MN_VENICE bool "Support Gateworks Venice iMX8M Nano module" @@ -167,6 +172,7 @@ config TARGET_IMX8MN_VENICE select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_IMX8MP_DATA_MODUL_EDM_SBC bool "Data Modul eDM SBC i.MX8M Plus" @@ -182,6 +188,7 @@ config TARGET_IMX8MP_BEACON select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_IMX8MP_DEBIX_MODEL_A bool "Polyhex i.MX8M Plus Debix Model A SBC" @@ -216,6 +223,7 @@ config TARGET_IMX8MP_EVK select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_IMX8MP_VENICE bool "Support Gateworks Venice iMX8M Plus module" @@ -227,6 +235,7 @@ config TARGET_IMX8MP_VENICE select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_PICO_IMX8MQ bool "Support Technexion Pico iMX8MQ" @@ -253,12 +262,14 @@ config TARGET_VERDIN_IMX8MM select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_VERDIN_IMX8MP bool "Support Toradex Verdin iMX8M Plus module" select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_IMX8MM_BEACON bool "imx8mm Beacon Embedded devkit" @@ -268,6 +279,7 @@ config TARGET_IMX8MM_BEACON select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_IMX8MN_BEACON bool "imx8mn Beacon Embedded devkit" @@ -277,6 +289,7 @@ config TARGET_IMX8MN_BEACON select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_PHYCORE_IMX8MM bool "PHYTEC PHYCORE i.MX8MM" diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index f06339f1388..2117489f232 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -262,7 +262,7 @@ static struct mm_region imx93_mem_map[] = { /* Flexible Serial Peripheral Interface */ .virt = 0x28000000UL, .phys = 0x28000000UL, - .size = 0x30000000UL, + .size = 0x08000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN @@ -622,6 +622,7 @@ int imx9_probe_mu(void) return 0; } EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx9_probe_mu); +EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, imx9_probe_mu); int timer_init(void) { diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 1bdc568f9b1..e0da9c23958 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -714,10 +714,10 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) /* * Register: PLL_VIDEO * Bit Field: POST_DIV_SELECT - * 00 — Divide by 4. - * 01 — Divide by 2. - * 10 — Divide by 1. - * 11 — Reserved + * 00 - Divide by 4. + * 01 - Divide by 2. + * 10 - Divide by 1. + * 11 - Reserved * No need to check post_div(1) */ for (post_div = 2; post_div <= 4; post_div <<= 1) { diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index 699a2569cb7..0b71fa40344 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -631,9 +631,9 @@ __secure void psci_system_suspend(u32 __always_unused function_id, * Workaround: * If both CPU0/CPU1 are IDLE, the last IDLE CPU should * disable GIC first, then REG_BYPASS_COUNTER is used - * to mask wakeup INT, and then execute “wfi” is used to + * to mask wakeup INT, and then execute "wfi" is used to * bring the system into power down processing safely. - * The counter must be enabled as close to the “wfi” state + * The counter must be enabled as close to the "wfi" state * as possible. The following equation can be used to * determine the RBC counter value: * RBC_COUNT * (1/32K RTC frequency) >= diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 03898424c95..2bb970c2d4c 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -4,6 +4,18 @@ choice prompt "Texas Instruments' K3 based SoC select" optional +config SOC_K3_AM625 + bool "TI's K3 based AM625 SoC Family Support" + +config SOC_K3_AM62A7 + bool "TI's K3 based AM62A7 SoC Family Support" + +config SOC_K3_AM62P5 + bool "TI's K3 based AM62P5 SoC Family Support" + +config SOC_K3_AM642 + bool "TI's K3 based AM642 SoC Family Support" + config SOC_K3_AM654 bool "TI's K3 based AM654 SoC Family Support" @@ -13,14 +25,8 @@ config SOC_K3_J721E config SOC_K3_J721S2 bool "TI's K3 based J721S2 SoC Family Support" -config SOC_K3_AM642 - bool "TI's K3 based AM642 SoC Family Support" - -config SOC_K3_AM625 - bool "TI's K3 based AM625 SoC Family Support" - -config SOC_K3_AM62A7 - bool "TI's K3 based AM62A7 SoC Family Support" +config SOC_K3_J784S4 + bool "TI's K3 based J784S4 SoC Family Support" endchoice @@ -35,7 +41,7 @@ config SYS_SOC config SYS_K3_NON_SECURE_MSRAM_SIZE hex default 0x80000 if SOC_K3_AM654 - default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2 + default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4 default 0x1c0000 if SOC_K3_AM642 default 0x3c000 if SOC_K3_AM625 || SOC_K3_AM62A7 help @@ -47,7 +53,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE hex default 0x58000 if SOC_K3_AM654 - default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2 + default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4 default 0x180000 if SOC_K3_AM642 default 0x38000 if SOC_K3_AM625 || SOC_K3_AM62A7 help @@ -57,15 +63,14 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE config SYS_K3_MCU_SCRATCHPAD_BASE hex default 0x40280000 if SOC_K3_AM654 - default 0x41cff9fc if SOC_K3_J721S2 - default 0x41cff9fc if SOC_K3_J721E + default 0x41cff9fc if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4 help Describes the base address of MCU Scratchpad RAM. config SYS_K3_MCU_SCRATCHPAD_SIZE hex default 0x200 if SOC_K3_AM654 - default 0x200 if SOC_K3_J721E || SOC_K3_J721S2 + default 0x200 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4 help Describes the size of MCU Scratchpad RAM. @@ -73,11 +78,12 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX hex default 0x41c7fbfc if SOC_K3_AM654 default 0x41cffbfc if SOC_K3_J721E - default 0x41cfdbfc if SOC_K3_J721S2 + default 0x41cfdbfc if SOC_K3_J721S2 || SOC_K3_J784S4 default 0x701bebfc if SOC_K3_AM642 default 0x43c3f290 if SOC_K3_AM625 default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R default 0x7000f290 if SOC_K3_AM62A7 && ARM64 + default 0x43c4f290 if SOC_K3_AM62P5 help Address at which ROM stores the value which determines if SPL is booted up by primary boot media or secondary boot media. @@ -114,23 +120,24 @@ config K3_EARLY_CONS_IDX Use this option to set the index of the serial device to be used for the early console during SPL execution. -config SYS_K3_SPL_ATF - bool "Start Cortex-A from SPL" - depends on CPU_V7R - help - Enabling this will try to start Cortex-A (typically with ATF) - after SPL from R5. - config K3_ATF_LOAD_ADDR hex "Load address of ATF image" + default 0x80000000 if (SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_AM62P5) default 0x70000000 help - The load address for the ATF image. This value defaults to 0x70000000 + The load address for the ATF image. This value is used to build the + FIT image header that places ATF in memory where it will run. + +config K3_OPTEE_LOAD_ADDR + hex "Load address of OPTEE image" + default 0x9e800000 + help + The load address for the OPTEE image. This value defaults to 0x9e800000 if not provided in the board defconfig file. config K3_DM_FW bool "Separate DM firmware image" - depends on CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN + depends on CPU_V7R && !SOC_K3_AM642 && !SOC_K3_AM654 && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN default y help Enabling this will indicate that the system has separate DM @@ -153,7 +160,9 @@ source "arch/arm/mach-k3/am65x/Kconfig" source "arch/arm/mach-k3/am64x/Kconfig" source "arch/arm/mach-k3/am62x/Kconfig" source "arch/arm/mach-k3/am62ax/Kconfig" +source "arch/arm/mach-k3/am62px/Kconfig" source "arch/arm/mach-k3/j721e/Kconfig" source "arch/arm/mach-k3/j721s2/Kconfig" +source "arch/arm/mach-k3/j784s4/Kconfig" endif diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index 42161376469..1bd523329a4 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -3,15 +3,16 @@ # Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ # Lokesh Vutla <lokeshvutla@ti.com> +obj-$(CONFIG_ARM64) += arm64/ obj-$(CONFIG_CPU_V7R) += r5/ -obj-$(CONFIG_ARM64) += arm64-mmu.o -obj-$(CONFIG_ARM64) += cache.o obj-$(CONFIG_OF_LIBFDT) += common_fdt.o ifeq ($(CONFIG_OF_LIBFDT)$(CONFIG_OF_SYSTEM_SETUP),yy) obj-$(CONFIG_SOC_K3_AM654) += am654_fdt.o obj-$(CONFIG_SOC_K3_J721E) += j721e_fdt.o obj-$(CONFIG_SOC_K3_J721S2) += j721s2_fdt.o obj-$(CONFIG_SOC_K3_AM625) += am625_fdt.o +obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_fdt.o +obj-$(CONFIG_SOC_K3_J784S4) += j784s4_fdt.o endif ifeq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_SOC_K3_AM654) += am654_init.o @@ -20,5 +21,8 @@ obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o obj-$(CONFIG_SOC_K3_AM642) += am642_init.o obj-$(CONFIG_SOC_K3_AM625) += am625_init.o obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o +obj-$(CONFIG_SOC_K3_J784S4) += j784s4_init.o +obj-$(CONFIG_SOC_K3_AM62P5) += am62p5_init.o endif obj-y += common.o security.o +obj-$(CONFIG_SOC_K3_AM625) += am62x/ diff --git a/arch/arm/mach-k3/am625_fdt.c b/arch/arm/mach-k3/am625_fdt.c index 970dd3447de..c56adef13bd 100644 --- a/arch/arm/mach-k3/am625_fdt.c +++ b/arch/arm/mach-k3/am625_fdt.c @@ -38,11 +38,50 @@ static void fdt_fixup_pru_node_am625(void *blob, int has_pru) fdt_del_node_path(blob, "/bus@f0000/pruss@30040000"); } +static int fdt_fixup_trips_node(void *blob, int zoneoffset, int maxc) +{ + int node, trip; + + node = fdt_subnode_offset(blob, zoneoffset, "trips"); + if (node < 0) + return -1; + + fdt_for_each_subnode(trip, blob, node) { + const char *type = fdt_getprop(blob, trip, "type", NULL); + + if (!type || (strncmp(type, "critical", 8) != 0)) + continue; + + if (fdt_setprop_u32(blob, trip, "temperature", 1000 * maxc) < 0) + return -1; + } + + return 0; +} + +static void fdt_fixup_thermal_zone_nodes_am625(void *blob, int maxc) +{ + int node, zone; + + node = fdt_path_offset(blob, "/thermal-zones"); + if (node < 0) + return; + + fdt_for_each_subnode(zone, blob, node) { + if (fdt_fixup_trips_node(blob, zone, maxc) < 0) + printf("Failed to set temperature in %s critical trips\n", + fdt_get_name(blob, zone, NULL)); + } +} + int ft_system_setup(void *blob, struct bd_info *bd) { fdt_fixup_cores_nodes_am625(blob, k3_get_core_nr()); fdt_fixup_gpu_nodes_am625(blob, k3_has_gpu()); fdt_fixup_pru_node_am625(blob, k3_has_pru()); + fdt_fixup_thermal_zone_nodes_am625(blob, k3_get_max_temp()); + fdt_fixup_reserved(blob, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000); + fdt_fixup_reserved(blob, "optee", CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000); return 0; } diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c index 6c96e881146..668f9a51ef4 100644 --- a/arch/arm/mach-k3/am625_init.c +++ b/arch/arm/mach-k3/am625_init.c @@ -14,6 +14,7 @@ #include <dm.h> #include <dm/uclass-internal.h> #include <dm/pinctrl.h> +#include <dm/ofnode.h> #define RTC_BASE_ADDRESS 0x2b1f0000 #define REG_K3RTC_S_CNT_LSW (RTC_BASE_ADDRESS + 0x18) @@ -24,6 +25,9 @@ #define K3RTC_KICK0_UNLOCK_VALUE 0x83e70b13 #define K3RTC_KICK1_UNLOCK_VALUE 0x95a4f1e0 +/* TISCI DEV ID for A53 Clock */ +#define AM62X_DEV_A53SS0_CORE_0_DEV_ID 135 + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -112,6 +116,62 @@ static __maybe_unused void rtc_erratumi2327_init(void) writel(K3RTC_KICK1_UNLOCK_VALUE, REG_K3RTC_KICK1); } +#if CONFIG_IS_ENABLED(OF_CONTROL) +static int get_a53_cpu_clock_index(ofnode node) +{ + int count, i; + struct ofnode_phandle_args *args; + ofnode clknode; + + clknode = ofnode_path("/bus@f0000/system-controller@44043000/clock-controller"); + if (!ofnode_valid(clknode)) + return -1; + + count = ofnode_count_phandle_with_args(node, "assigned-clocks", "#clock-cells", 0); + + for (i = 0; i < count; i++) { + if (!ofnode_parse_phandle_with_args(node, "assigned-clocks", + "#clock-cells", 0, i, args)) { + if (ofnode_equal(clknode, args->node) && + args->args[0] == AM62X_DEV_A53SS0_CORE_0_DEV_ID) + return i; + } + } + + return -1; +} + +static void fixup_a53_cpu_freq_by_speed_grade(void) +{ + int index, size; + u32 *rates; + ofnode node; + + node = ofnode_path("/a53@0"); + if (!ofnode_valid(node)) + return; + + rates = fdt_getprop_w(ofnode_to_fdt(node), ofnode_to_offset(node), + "assigned-clock-rates", &size); + + index = get_a53_cpu_clock_index(node); + + if (!rates || index < 0 || index >= (size / sizeof(u32))) { + printf("Wrong A53 assigned-clocks configuration\n"); + return; + } + + rates[index] = cpu_to_fdt32(k3_get_a53_max_frequency()); + + printf("Changed A53 CPU frequency to %dHz (%c grade) in DT\n", + k3_get_a53_max_frequency(), k3_get_speed_grade()); +} +#else +static void fixup_a53_cpu_freq_by_speed_grade(void) +{ +} +#endif + void board_init_f(ulong dummy) { struct udevice *dev; @@ -176,6 +236,14 @@ void board_init_f(ulong dummy) } /* + * Relocate boot information to OCRAM (after TIFS has opend this + * region for us) so the next bootloader stages can keep access to + * primary vs backup bootmodes. + */ + if (IS_ENABLED(CONFIG_CPU_V7R)) + writel(bootindex, K3_BOOT_PARAM_TABLE_INDEX_OCRAM); + + /* * Force probe of clk_k3 driver here to ensure basic default clock * configuration is always done. */ @@ -210,6 +278,8 @@ void board_init_f(ulong dummy) panic("DRAM init failed: %d\n", ret); } spl_enable_cache(); + + fixup_a53_cpu_freq_by_speed_grade(); } u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) @@ -235,100 +305,7 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) } } -static u32 __get_backup_bootmedia(u32 devstat) -{ - u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> - MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; - u32 bkup_bootmode_cfg = - (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> - MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; - - switch (bkup_bootmode) { - case BACKUP_BOOT_DEVICE_UART: - return BOOT_DEVICE_UART; - - case BACKUP_BOOT_DEVICE_USB: - return BOOT_DEVICE_USB; - - case BACKUP_BOOT_DEVICE_ETHERNET: - return BOOT_DEVICE_ETHERNET; - - case BACKUP_BOOT_DEVICE_MMC: - if (bkup_bootmode_cfg) - return BOOT_DEVICE_MMC2; - return BOOT_DEVICE_MMC1; - - case BACKUP_BOOT_DEVICE_SPI: - return BOOT_DEVICE_SPI; - - case BACKUP_BOOT_DEVICE_I2C: - return BOOT_DEVICE_I2C; - - case BACKUP_BOOT_DEVICE_DFU: - if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) - return BOOT_DEVICE_USB; - return BOOT_DEVICE_DFU; - }; - - return BOOT_DEVICE_RAM; -} - -static u32 __get_primary_bootmedia(u32 devstat) -{ - u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> - MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; - u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> - MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; - - switch (bootmode) { - case BOOT_DEVICE_OSPI: - fallthrough; - case BOOT_DEVICE_QSPI: - fallthrough; - case BOOT_DEVICE_XSPI: - fallthrough; - case BOOT_DEVICE_SPI: - return BOOT_DEVICE_SPI; - - case BOOT_DEVICE_ETHERNET_RGMII: - fallthrough; - case BOOT_DEVICE_ETHERNET_RMII: - return BOOT_DEVICE_ETHERNET; - - case BOOT_DEVICE_EMMC: - return BOOT_DEVICE_MMC1; - - case BOOT_DEVICE_MMC: - if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> - MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) - return BOOT_DEVICE_MMC2; - return BOOT_DEVICE_MMC1; - - case BOOT_DEVICE_DFU: - if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> - MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) - return BOOT_DEVICE_USB; - return BOOT_DEVICE_DFU; - - case BOOT_DEVICE_NOBOOT: - return BOOT_DEVICE_RAM; - } - - return bootmode; -} - u32 spl_boot_device(void) { - u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); - u32 bootmedia; - - if (bootindex == K3_PRIMARY_BOOTMODE) - bootmedia = __get_primary_bootmedia(devstat); - else - bootmedia = __get_backup_bootmedia(devstat); - - debug("am625_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n", - __func__, devstat, bootmedia, bootindex); - - return bootmedia; + return get_boot_device(); } diff --git a/arch/arm/mach-k3/am62a7_fdt.c b/arch/arm/mach-k3/am62a7_fdt.c new file mode 100644 index 00000000000..d67f012a5dc --- /dev/null +++ b/arch/arm/mach-k3/am62a7_fdt.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <asm/hardware.h> +#include "common_fdt.h" +#include <fdt_support.h> + +int ft_system_setup(void *blob, struct bd_info *bd) +{ + fdt_fixup_reserved(blob, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000); + fdt_fixup_reserved(blob, "optee", CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000); + + return 0; +} diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c index 080274e3af5..2a0221a3718 100644 --- a/arch/arm/mach-k3/am62a7_init.c +++ b/arch/arm/mach-k3/am62a7_init.c @@ -128,6 +128,9 @@ void board_init_f(ulong dummy) panic("ROM has not loaded TIFS firmware\n"); k3_sysfw_loader(true, NULL, NULL); + + /* Disable ROM configured firewalls right after loading sysfw */ + remove_fwl_configs(cbass_main_fwls, ARRAY_SIZE(cbass_main_fwls)); #endif #if defined(CONFIG_CPU_V7R) @@ -156,9 +159,6 @@ void board_init_f(ulong dummy) /* Output System Firmware version info */ k3_sysfw_print_ver(); - /* Disable ROM configured firewalls right after loading sysfw */ - remove_fwl_configs(cbass_main_fwls, ARRAY_SIZE(cbass_main_fwls)); - #if defined(CONFIG_K3_AM62A_DDRSS) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) diff --git a/arch/arm/mach-k3/am62ax/Kconfig b/arch/arm/mach-k3/am62ax/Kconfig index c5f1ef87126..bbd5497f2ae 100644 --- a/arch/arm/mach-k3/am62ax/Kconfig +++ b/arch/arm/mach-k3/am62ax/Kconfig @@ -13,6 +13,7 @@ config TARGET_AM62A7_A53_EVM bool "TI K3 based AM62A7 EVM running on A53" select ARM64 select BINMAN + select OF_SYSTEM_SETUP imply BOARD imply SPL_BOARD imply TI_I2C_BOARD_DETECT diff --git a/arch/arm/mach-k3/am62p5_init.c b/arch/arm/mach-k3/am62p5_init.c new file mode 100644 index 00000000000..aab99aa0c95 --- /dev/null +++ b/arch/arm/mach-k3/am62p5_init.c @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62P5: SoC specific initialization + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <spl.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include "sysfw-loader.h" +#include "common.h" +#include <dm.h> +#include <dm/uclass-internal.h> +#include <dm/pinctrl.h> + +struct fwl_data cbass_main_fwls[] = { + { "FSS_DAT_REG3", 7, 8 }, +}; + +/* + * This uninitialized global variable would normal end up in the .bss section, + * but the .bss is cleared between writing and reading this variable, so move + * it to the .data section. + */ +u32 bootindex __section(".data"); +static struct rom_extended_boot_data bootdata __section(".data"); + +static void store_boot_info_from_rom(void) +{ + bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); + memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO, + sizeof(struct rom_extended_boot_data)); +} + +static void ctrl_mmr_unlock(void) +{ + /* Unlock all WKUP_CTRL_MMR0 module registers */ + mmr_unlock(WKUP_CTRL_MMR0_BASE, 0); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 1); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 2); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 3); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 4); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 5); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 6); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 7); + + /* Unlock all CTRL_MMR0 module registers */ + mmr_unlock(CTRL_MMR0_BASE, 0); + mmr_unlock(CTRL_MMR0_BASE, 1); + mmr_unlock(CTRL_MMR0_BASE, 2); + mmr_unlock(CTRL_MMR0_BASE, 4); + mmr_unlock(CTRL_MMR0_BASE, 5); + mmr_unlock(CTRL_MMR0_BASE, 6); + + /* Unlock all MCU_CTRL_MMR0 module registers */ + mmr_unlock(MCU_CTRL_MMR0_BASE, 0); + mmr_unlock(MCU_CTRL_MMR0_BASE, 1); + mmr_unlock(MCU_CTRL_MMR0_BASE, 2); + mmr_unlock(MCU_CTRL_MMR0_BASE, 3); + mmr_unlock(MCU_CTRL_MMR0_BASE, 4); + mmr_unlock(MCU_CTRL_MMR0_BASE, 6); + + /* Unlock PADCFG_CTRL_MMR padconf registers */ + mmr_unlock(PADCFG_MMR0_BASE, 1); + mmr_unlock(PADCFG_MMR1_BASE, 1); +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + if (IS_ENABLED(CONFIG_CPU_V7R)) + setup_k3_mpu_regions(); + + /* + * Cannot delay this further as there is a chance that + * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section. + */ + store_boot_info_from_rom(); + + ctrl_mmr_unlock(); + + /* Init DM early */ + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed: %d\n", ret); + + /* + * Process pinctrl for the serial0 and serial3, aka WKUP_UART0 and + * MAIN_UART1 modules and continue regardless of the result of pinctrl. + * Do this without probing the device, but instead by searching the + * device that would request the given sequence number if probed. The + * UARTs will be used by the DM firmware and TIFS firmware images + * respectively and the firmware depend on SPL to initialize the pin + * settings. + */ + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev); + if (!ret) + pinctrl_select_state(dev, "default"); + + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev); + if (!ret) + pinctrl_select_state(dev, "default"); + + /* + * Allow establishing an early console as required for example when + * doing a UART-based boot. Note that this console may not "survive" + * through a SYSFW PM-init step and will need a re-init in some way + * due to changing module clock frequencies. + */ + if (IS_ENABLED(CONFIG_K3_EARLY_CONS)) { + ret = early_console_init(); + if (ret) + panic("early_console_init() failed: %d\n", ret); + } + + /* + * Configure and start up system controller firmware. Provide + * the U-Boot console init function to the SYSFW post-PM configuration + * callback hook, effectively switching on (or over) the console + * output. + */ + if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) { + ret = is_rom_loaded_sysfw(&bootdata); + if (!ret) + panic("ROM has not loaded TIFS firmware\n"); + + k3_sysfw_loader(true, NULL, NULL); + + /* Disable ROM configured firewalls */ + remove_fwl_configs(cbass_main_fwls, + ARRAY_SIZE(cbass_main_fwls)); + } + + /* + * Force probe of clk_k3 driver here to ensure basic default clock + * configuration is always done. + */ + if (IS_ENABLED(CONFIG_SPL_CLK_K3)) { + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(ti_clk), + &dev); + if (ret) + printf("Failed to initialize clk-k3!\n"); + } + + preloader_console_init(); + + /* Output System Firmware version info */ + k3_sysfw_print_ver(); + + if (IS_ENABLED(CONFIG_K3_AM62A_DDRSS)) { + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("DRAM init failed: %d\n", ret); + } + + spl_enable_cache(); + debug("am62px_init: %s done\n", __func__); +} + +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_EMMC: + return MMCSD_MODE_EMMCBOOT; + case BOOT_DEVICE_MMC: + if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK) + return MMCSD_MODE_RAW; + default: + return MMCSD_MODE_FS; + } +} + +static u32 __get_backup_bootmedia(u32 devstat) +{ + u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; + u32 bkup_bootmode_cfg = + (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; + + switch (bkup_bootmode) { + case BACKUP_BOOT_DEVICE_UART: + return BOOT_DEVICE_UART; + + case BACKUP_BOOT_DEVICE_USB: + return BOOT_DEVICE_USB; + + case BACKUP_BOOT_DEVICE_ETHERNET: + return BOOT_DEVICE_ETHERNET; + + case BACKUP_BOOT_DEVICE_MMC: + if (bkup_bootmode_cfg) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BACKUP_BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BACKUP_BOOT_DEVICE_I2C: + return BOOT_DEVICE_I2C; + + case BACKUP_BOOT_DEVICE_DFU: + if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + }; + + return BOOT_DEVICE_RAM; +} + +static u32 __get_primary_bootmedia(u32 devstat) +{ + u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_OSPI: + fallthrough; + case BOOT_DEVICE_QSPI: + fallthrough; + case BOOT_DEVICE_XSPI: + fallthrough; + case BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BOOT_DEVICE_ETHERNET_RGMII: + fallthrough; + case BOOT_DEVICE_ETHERNET_RMII: + return BOOT_DEVICE_ETHERNET; + + case BOOT_DEVICE_EMMC: + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_SPI_NAND: + return BOOT_DEVICE_SPINAND; + + case BOOT_DEVICE_MMC: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> + MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_DFU: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + + case BOOT_DEVICE_NOBOOT: + return BOOT_DEVICE_RAM; + } + + return bootmode; +} + +u32 spl_boot_device(void) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmedia; + + if (bootindex == K3_PRIMARY_BOOTMODE) + bootmedia = __get_primary_bootmedia(devstat); + else + bootmedia = __get_backup_bootmedia(devstat); + + debug("am62px_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n", + __func__, devstat, bootmedia, bootindex); + return bootmedia; +} diff --git a/arch/arm/mach-k3/am62px/Kconfig b/arch/arm/mach-k3/am62px/Kconfig new file mode 100644 index 00000000000..38a9e6811b1 --- /dev/null +++ b/arch/arm/mach-k3/am62px/Kconfig @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# + +if SOC_K3_AM62P5 + +choice + prompt "TI K3 AM62Px based boards" + optional + +config TARGET_AM62P5_A53_EVM + bool "TI K3 based AM62P5 EVM running on A53" + select ARM64 + select BINMAN + +config TARGET_AM62P5_R5_EVM + bool "TI K3 based AM62P5 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + +endchoice + +source "board/ti/am62px/Kconfig" + +endif diff --git a/arch/arm/mach-k3/am62x/Kconfig b/arch/arm/mach-k3/am62x/Kconfig index 935d596c879..9786751874d 100644 --- a/arch/arm/mach-k3/am62x/Kconfig +++ b/arch/arm/mach-k3/am62x/Kconfig @@ -13,6 +13,7 @@ config TARGET_AM625_A53_EVM bool "TI K3 based AM625 EVM running on A53" select ARM64 select BINMAN + select OF_SYSTEM_SETUP config TARGET_AM625_R5_EVM bool "TI K3 based AM625 EVM running on R5" @@ -29,6 +30,7 @@ config TARGET_PHYCORE_AM62X_A53 bool "PHYTEC phyCORE-AM62x running on A53" select ARM64 select BINMAN + select OF_SYSTEM_SETUP config TARGET_PHYCORE_AM62X_R5 bool "PHYTEC phyCORE-AM62x running on R5" @@ -45,6 +47,8 @@ config TARGET_VERDIN_AM62_A53 bool "Toradex Verdin AM62 running on A53" select ARM64 select BINMAN + select OF_SYSTEM_SETUP + imply OF_UPSTREAM config TARGET_VERDIN_AM62_R5 bool "Toradex Verdin AM62 running on R5" diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/am62x/Makefile new file mode 100644 index 00000000000..acf09c3426c --- /dev/null +++ b/arch/arm/mach-k3/am62x/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0+ +obj-y += boot.o diff --git a/arch/arm/mach-k3/am62x/boot.c b/arch/arm/mach-k3/am62x/boot.c new file mode 100644 index 00000000000..132b42f7edb --- /dev/null +++ b/arch/arm/mach-k3/am62x/boot.c @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/am62_spl.h> + +static u32 __get_backup_bootmedia(u32 devstat) +{ + u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; + u32 bkup_bootmode_cfg = + (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; + + switch (bkup_bootmode) { + case BACKUP_BOOT_DEVICE_UART: + return BOOT_DEVICE_UART; + + case BACKUP_BOOT_DEVICE_USB: + return BOOT_DEVICE_USB; + + case BACKUP_BOOT_DEVICE_ETHERNET: + return BOOT_DEVICE_ETHERNET; + + case BACKUP_BOOT_DEVICE_MMC: + if (bkup_bootmode_cfg) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BACKUP_BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BACKUP_BOOT_DEVICE_I2C: + return BOOT_DEVICE_I2C; + + case BACKUP_BOOT_DEVICE_DFU: + if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + }; + + return BOOT_DEVICE_RAM; +} + +static u32 __get_primary_bootmedia(u32 devstat) +{ + u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_OSPI: + fallthrough; + case BOOT_DEVICE_QSPI: + fallthrough; + case BOOT_DEVICE_XSPI: + fallthrough; + case BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BOOT_DEVICE_ETHERNET_RGMII: + fallthrough; + case BOOT_DEVICE_ETHERNET_RMII: + return BOOT_DEVICE_ETHERNET; + + case BOOT_DEVICE_EMMC: + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_MMC: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> + MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_DFU: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + + case BOOT_DEVICE_NOBOOT: + return BOOT_DEVICE_RAM; + } + + return bootmode; +} + +u32 get_boot_device(void) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmode = *(u32 *)(K3_BOOT_PARAM_TABLE_INDEX_OCRAM); + u32 bootmedia; + + if (bootmode == K3_PRIMARY_BOOTMODE) + bootmedia = __get_primary_bootmedia(devstat); + else + bootmedia = __get_backup_bootmedia(devstat); + + debug("%s: devstat = 0x%x bootmedia = 0x%x bootmode = %d\n", + __func__, devstat, bootmedia, bootmode); + + return bootmedia; +} diff --git a/arch/arm/mach-k3/am64x/Kconfig b/arch/arm/mach-k3/am64x/Kconfig index 6f7b0039615..b8fea8716ec 100644 --- a/arch/arm/mach-k3/am64x/Kconfig +++ b/arch/arm/mach-k3/am64x/Kconfig @@ -29,8 +29,27 @@ config TARGET_AM642_R5_EVM imply SYS_K3_SPL_ATF imply TI_I2C_BOARD_DETECT +config TARGET_PHYCORE_AM64X_A53 + bool "PHYTEC phyCORE-AM64x running on A53" + select ARM64 + select BINMAN + imply BOARD + imply SPL_BOARD + +config TARGET_PHYCORE_AM64X_R5 + bool "PHYTEC phyCORE-AM64x running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + endchoice +source "board/phytec/phycore_am64x/Kconfig" source "board/ti/am64x/Kconfig" endif diff --git a/arch/arm/mach-k3/arm64/Makefile b/arch/arm/mach-k3/arm64/Makefile new file mode 100644 index 00000000000..f3d322e17f8 --- /dev/null +++ b/arch/arm/mach-k3/arm64/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + +obj-y += arm64-mmu.o +obj-y += cache.o diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64/arm64-mmu.c index 0e07b1b7ce0..0e07b1b7ce0 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64/arm64-mmu.c diff --git a/arch/arm/mach-k3/cache.S b/arch/arm/mach-k3/arm64/cache.S index 17cfb12f108..17cfb12f108 100644 --- a/arch/arm/mach-k3/cache.S +++ b/arch/arm/mach-k3/arm64/cache.S diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index b54f2ddc472..1a269d6934a 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -24,33 +24,13 @@ #include <asm/io.h> #include <fs_loader.h> #include <fs.h> +#include <efi_loader.h> #include <env.h> #include <elf.h> #include <soc.h> #include <asm/arch/k3-qos.h> -#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF) -enum { - IMAGE_ID_ATF, - IMAGE_ID_OPTEE, - IMAGE_ID_SPL, - IMAGE_ID_DM_FW, - IMAGE_AMT, -}; - -#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS) -static const char *image_os_match[IMAGE_AMT] = { - "arm-trusted-firmware", - "tee", - "U-Boot", - "DM", -}; -#endif - -static struct image_info fit_image_info[IMAGE_AMT]; -#endif - struct ti_sci_handle *get_ti_sci_handle(void) { struct udevice *dev; @@ -130,233 +110,12 @@ int early_console_init(void) } #endif -#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF) - -void init_env(void) -{ -#ifdef CONFIG_SPL_ENV_SUPPORT - char *part; - - env_init(); - env_relocate(); - switch (spl_boot_device()) { - case BOOT_DEVICE_MMC2: - part = env_get("bootpart"); - env_set("storage_interface", "mmc"); - env_set("fw_dev_part", part); - break; - case BOOT_DEVICE_SPI: - env_set("storage_interface", "ubi"); - env_set("fw_ubi_mtdpart", "UBI"); - env_set("fw_ubi_volume", "UBI0"); - break; - default: - printf("%s from device %u not supported!\n", - __func__, spl_boot_device()); - return; - } -#endif -} - -int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr) -{ - struct udevice *fsdev; - char *name = NULL; - int size = 0; - - if (!IS_ENABLED(CONFIG_FS_LOADER)) - return 0; - - *loadaddr = 0; -#ifdef CONFIG_SPL_ENV_SUPPORT - switch (spl_boot_device()) { - case BOOT_DEVICE_MMC2: - name = env_get(name_fw); - *loadaddr = env_get_hex(name_loadaddr, *loadaddr); - break; - default: - printf("Loading rproc fw image from device %u not supported!\n", - spl_boot_device()); - return 0; - } -#endif - if (!*loadaddr) - return 0; - - if (!get_fs_loader(&fsdev)) { - size = request_firmware_into_buf(fsdev, name, (void *)*loadaddr, - 0, 0); - } - - return size; -} - -void release_resources_for_core_shutdown(void) -{ - struct ti_sci_handle *ti_sci = get_ti_sci_handle(); - struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops; - struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops; - int ret; - u32 i; - - /* Iterate through list of devices to put (shutdown) */ - for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) { - u32 id = put_device_ids[i]; - - ret = dev_ops->put_device(ti_sci, id); - if (ret) - panic("Failed to put device %u (%d)\n", id, ret); - } - - /* Iterate through list of cores to put (shutdown) */ - for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) { - u32 id = put_core_ids[i]; - - /* - * Queue up the core shutdown request. Note that this call - * needs to be followed up by an actual invocation of an WFE - * or WFI CPU instruction. - */ - ret = proc_ops->proc_shutdown_no_wait(ti_sci, id); - if (ret) - panic("Failed sending core %u shutdown message (%d)\n", - id, ret); - } -} - -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) -{ - typedef void __noreturn (*image_entry_noargs_t)(void); - struct ti_sci_handle *ti_sci = get_ti_sci_handle(); - u32 loadaddr = 0; - int ret, size = 0, shut_cpu = 0; - - /* Release all the exclusive devices held by SPL before starting ATF */ - ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci); - - ret = rproc_init(); - if (ret) - panic("rproc failed to be initialized (%d)\n", ret); - - init_env(); - - if (!fit_image_info[IMAGE_ID_DM_FW].image_start) { - size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load", - &loadaddr); - } - - /* - * It is assumed that remoteproc device 1 is the corresponding - * Cortex-A core which runs ATF. Make sure DT reflects the same. - */ - if (!fit_image_info[IMAGE_ID_ATF].image_start) - fit_image_info[IMAGE_ID_ATF].image_start = - spl_image->entry_point; - - ret = rproc_load(1, fit_image_info[IMAGE_ID_ATF].image_start, 0x200); - if (ret) - panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret); - -#if (CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS) && IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)) - /* Authenticate ATF */ - void *image_addr = (void *)fit_image_info[IMAGE_ID_ATF].image_start; - - debug("%s: Authenticating image: addr=%lx, size=%ld, os=%s\n", __func__, - fit_image_info[IMAGE_ID_ATF].image_start, - fit_image_info[IMAGE_ID_ATF].image_len, - image_os_match[IMAGE_ID_ATF]); - - ti_secure_image_post_process(&image_addr, - (size_t *)&fit_image_info[IMAGE_ID_ATF].image_len); - - /* Authenticate OPTEE */ - image_addr = (void *)fit_image_info[IMAGE_ID_OPTEE].image_start; - - debug("%s: Authenticating image: addr=%lx, size=%ld, os=%s\n", __func__, - fit_image_info[IMAGE_ID_OPTEE].image_start, - fit_image_info[IMAGE_ID_OPTEE].image_len, - image_os_match[IMAGE_ID_OPTEE]); - - ti_secure_image_post_process(&image_addr, - (size_t *)&fit_image_info[IMAGE_ID_OPTEE].image_len); - -#endif - - if (!fit_image_info[IMAGE_ID_DM_FW].image_len && - !(size > 0 && valid_elf_image(loadaddr))) { - shut_cpu = 1; - goto start_arm64; - } - - if (!fit_image_info[IMAGE_ID_DM_FW].image_start) { - loadaddr = load_elf_image_phdr(loadaddr); - } else { - loadaddr = fit_image_info[IMAGE_ID_DM_FW].image_start; - if (valid_elf_image(loadaddr)) - loadaddr = load_elf_image_phdr(loadaddr); - } - - debug("%s: jumping to address %x\n", __func__, loadaddr); - -start_arm64: - /* Add an extra newline to differentiate the ATF logs from SPL */ - printf("Starting ATF on ARM64 core...\n\n"); - - ret = rproc_start(1); - if (ret) - panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret); - - if (shut_cpu) { - debug("Shutting down...\n"); - release_resources_for_core_shutdown(); - - while (1) - asm volatile("wfe"); - } - image_entry_noargs_t image_entry = (image_entry_noargs_t)loadaddr; - - image_entry(); -} -#endif - -#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS) +#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS) && !IS_ENABLED(CONFIG_SYS_K3_SPL_ATF) void board_fit_image_post_process(const void *fit, int node, void **p_image, size_t *p_size) { -#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF) - int len; - int i; - const char *os; - u32 addr; - - os = fdt_getprop(fit, node, "os", &len); - addr = fdt_getprop_u32_default_node(fit, node, 0, "entry", -1); - - debug("%s: processing image: addr=%x, size=%d, os=%s\n", __func__, - addr, *p_size, os); - - for (i = 0; i < IMAGE_AMT; i++) { - if (!strcmp(os, image_os_match[i])) { - fit_image_info[i].image_start = addr; - fit_image_info[i].image_len = *p_size; - debug("%s: matched image for ID %d\n", __func__, i); - break; - } - } - /* - * Only DM and the DTBs are being authenticated here, - * rest will be authenticated when A72 cluster is up - */ - if ((i != IMAGE_ID_ATF) && (i != IMAGE_ID_OPTEE)) -#endif - { - ti_secure_image_check_binary(p_image, p_size); - ti_secure_image_post_process(p_image, p_size); - } -#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF) - else - ti_secure_image_check_binary(p_image, p_size); -#endif + ti_secure_image_check_binary(p_image, p_size); + ti_secure_image_post_process(p_image, p_size); } #endif @@ -455,75 +214,6 @@ void board_prep_linux(struct bootm_headers *images) } #endif -#ifdef CONFIG_CPU_V7R -void disable_linefill_optimization(void) -{ - u32 actlr; - - /* - * On K3 devices there are 2 conditions where R5F can deadlock: - * 1.When software is performing series of store operations to - * cacheable write back/write allocate memory region and later - * on software execute barrier operation (DSB or DMB). R5F may - * hang at the barrier instruction. - * 2.When software is performing a mix of load and store operations - * within a tight loop and store operations are all writing to - * cacheable write back/write allocates memory regions, R5F may - * hang at one of the load instruction. - * - * To avoid the above two conditions disable linefill optimization - * inside Cortex R5F. - */ - asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr)); - actlr |= (1 << 13); /* Set DLFO bit */ - asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr)); -} -#endif - -static void remove_fwl_regions(struct fwl_data fwl_data, size_t num_regions, - enum k3_firewall_region_type fwl_type) -{ - struct ti_sci_fwl_ops *fwl_ops; - struct ti_sci_handle *ti_sci; - struct ti_sci_msg_fwl_region region; - size_t j; - - ti_sci = get_ti_sci_handle(); - fwl_ops = &ti_sci->ops.fwl_ops; - - for (j = 0; j < fwl_data.regions; j++) { - region.fwl_id = fwl_data.fwl_id; - region.region = j; - region.n_permission_regs = 3; - - fwl_ops->get_fwl_region(ti_sci, ®ion); - - /* Don't disable the background regions */ - if (region.control != 0 && - ((region.control >> K3_FIREWALL_BACKGROUND_BIT) & 1) == fwl_type) { - pr_debug("Attempting to disable firewall %5d (%25s)\n", - region.fwl_id, fwl_data.name); - region.control = 0; - - if (fwl_ops->set_fwl_region(ti_sci, ®ion)) - pr_err("Could not disable firewall %5d (%25s)\n", - region.fwl_id, fwl_data.name); - } - } -} - -void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) -{ - size_t i; - - for (i = 0; i < fwl_data_size; i++) { - remove_fwl_regions(fwl_data[i], fwl_data[i].regions, - K3_FIREWALL_REGION_FOREGROUND); - remove_fwl_regions(fwl_data[i], fwl_data[i].regions, - K3_FIREWALL_REGION_BACKGROUND); - } -} - void spl_enable_cache(void) { #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) @@ -581,6 +271,17 @@ int misc_init_r(void) printf("Failed to probe am65_cpsw_nuss driver\n"); } + if (IS_ENABLED(CONFIG_TI_ICSSG_PRUETH)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(prueth), + &dev); + if (ret) + printf("Failed to probe prueth driver\n"); + } + /* Default FIT boot on HS-SE devices */ if (get_device_type() == K3_DEVICE_TYPE_HS_SE) env_set("boot_fit", "1"); @@ -607,3 +308,14 @@ void setup_qos(void) writel(qos_data[i].val, (uintptr_t)qos_data[i].reg); } #endif + +void efi_add_known_memory(void) +{ + if (IS_ENABLED(CONFIG_EFI_LOADER)) + /* + * Memory over ram_top can be used by various firmware + * Declare to EFI only memory area below ram_top + */ + efi_add_memory_map(gd->ram_base, gd->ram_top - gd->ram_base, + EFI_CONVENTIONAL_MEMORY); +} diff --git a/arch/arm/mach-k3/common_fdt.c b/arch/arm/mach-k3/common_fdt.c index 645c4de42f7..3bdedd7b509 100644 --- a/arch/arm/mach-k3/common_fdt.c +++ b/arch/arm/mach-k3/common_fdt.c @@ -112,3 +112,55 @@ int fdt_del_node_path(void *blob, const char *path) return ret; } + +int fdt_fixup_reserved(void *blob, const char *name, + unsigned int new_address, unsigned int new_size) +{ + int nodeoffset, subnode; + int ret; + + /* Find reserved-memory */ + nodeoffset = fdt_subnode_offset(blob, 0, "reserved-memory"); + if (nodeoffset < 0) { + debug("Could not find reserved-memory node\n"); + return 0; + } + + /* Find existing matching subnode and remove it */ + fdt_for_each_subnode(subnode, blob, nodeoffset) { + const char *node_name; + fdt_addr_t addr; + fdt_size_t size; + + /* Name matching */ + node_name = fdt_get_name(blob, subnode, NULL); + if (!name) + return -EINVAL; + if (!strncmp(node_name, name, strlen(name))) { + /* Read out old size first */ + addr = fdtdec_get_addr_size(blob, subnode, "reg", &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + new_size = size; + + /* Delete node */ + ret = fdt_del_node(blob, subnode); + if (ret < 0) + return ret; + + /* Only one matching node */ + break; + } + } + + struct fdt_memory carveout = { + .start = new_address, + .end = new_address + new_size - 1, + }; + ret = fdtdec_add_reserved_memory(blob, name, &carveout, NULL, 0, NULL, + FDTDEC_RESERVED_MEMORY_NO_MAP); + if (ret < 0) + return ret; + + return 0; +} diff --git a/arch/arm/mach-k3/common_fdt.h b/arch/arm/mach-k3/common_fdt.h index 4d23ae638ca..52c07957483 100644 --- a/arch/arm/mach-k3/common_fdt.h +++ b/arch/arm/mach-k3/common_fdt.h @@ -8,5 +8,7 @@ int fdt_fixup_msmc_ram_k3(void *blob); int fdt_del_node_path(void *blob, const char *path); +int fdt_fixup_reserved(void *blob, const char *name, + unsigned int new_address, unsigned int new_size); #endif /* _COMMON_FDT_H */ diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index 54380f36e16..bcbc4821c82 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -42,6 +42,10 @@ #define JTAG_DEV_FEATURE_NO_PRU 0x4 +#define JTAG_DEV_TEMP_COMMERCIAL 0x3 +#define JTAG_DEV_TEMP_INDUSTRIAL 0x4 +#define JTAG_DEV_TEMP_AUTOMOTIVE 0x5 + #define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3) #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 @@ -75,7 +79,11 @@ #define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170) +/* Debounce register configuration */ +#define CTRLMMR_DBOUNCE_CFG(index) (MCU_CTRL_MMR0_BASE + 0x4080 + (index * 4)) + #define ROM_EXTENDED_BOOT_DATA_INFO 0x43c3f1e0 +#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000 @@ -102,6 +110,34 @@ static inline int k3_get_temp_grade(void) return (full_devid & JTAG_DEV_TEMP_MASK) >> JTAG_DEV_TEMP_SHIFT; } +static inline int k3_get_max_temp(void) +{ + switch (k3_get_temp_grade()) { + case JTAG_DEV_TEMP_INDUSTRIAL: + return 105; + case JTAG_DEV_TEMP_AUTOMOTIVE: + return 125; + case JTAG_DEV_TEMP_COMMERCIAL: + default: + return 95; + } +} + +static inline int k3_get_a53_max_frequency(void) +{ + switch (k3_get_speed_grade()) { + case 'K': + return 800000000; + case 'S': + return 1000000000; + case 'T': + return 1250000000; + case 'G': + default: + return 300000000; + } +} + static inline int k3_has_pru(void) { u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID); diff --git a/arch/arm/mach-k3/include/mach/am62p_hardware.h b/arch/arm/mach-k3/include/mach/am62p_hardware.h new file mode 100644 index 00000000000..923466c41f4 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/am62p_hardware.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K3: AM62Px SoC definitions, structures etc. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef __ASM_ARCH_AM62P_HARDWARE_H +#define __ASM_ARCH_AM62P_HARDWARE_H + +#include <config.h> +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#endif + +#define PADCFG_MMR0_BASE 0x04080000 +#define PADCFG_MMR1_BASE 0x000f0000 +#define CTRL_MMR0_BASE 0x00100000 +#define MCU_CTRL_MMR0_BASE 0x04500000 +#define WKUP_CTRL_MMR0_BASE 0x43000000 + +#define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7 +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10) +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10 +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13) +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13 + +/* Primary Bootmode MMC Config macros */ +#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4 +#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2 +#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1 +#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0 + +/* Primary Bootmode USB Config macros */ +#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1 +#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02 + +/* Backup Bootmode USB Config macros */ +#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01 + +/* + * The CTRL_MMR0 memory space is divided into several equally-spaced + * partitions, so defining the partition size allows us to determine + * register addresses common to those partitions. + */ +#define CTRL_MMR0_PARTITION_SIZE 0x4000 + +/* + * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism + * shared register definitions. The same registers are also used for + * PADCFG_MMR lock/kick-mechanism. + */ +#define CTRLMMR_LOCK_KICK0 0x1008 +#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 +#define CTRLMMR_LOCK_KICK1 0x100c +#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a + +#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038) +#define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c) +#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7) + +#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058) +#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3) + +#define ROM_EXTENDED_BOOT_DATA_INFO 0x43c4f1e0 + +#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290 + +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000 + +#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) + +static const u32 put_device_ids[] = {}; + +static const u32 put_core_ids[] = {}; + +#endif + +#endif /* __ASM_ARCH_AM62P_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am62p_spl.h b/arch/arm/mach-k3/include/mach/am62p_spl.h new file mode 100644 index 00000000000..db145a7bc83 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/am62p_spl.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef _ASM_ARCH_AM62P_SPL_H_ +#define _ASM_ARCH_AM62P_SPL_H_ + +/* Primary BootMode devices */ +#define BOOT_DEVICE_SPI_NAND 0x00 +#define BOOT_DEVICE_RAM 0xFF +#define BOOT_DEVICE_OSPI 0x01 +#define BOOT_DEVICE_QSPI 0x02 +#define BOOT_DEVICE_SPI 0x03 +#define BOOT_DEVICE_CPGMAC 0x04 +#define BOOT_DEVICE_ETHERNET_RGMII 0x04 +#define BOOT_DEVICE_ETHERNET_RMII 0x05 +#define BOOT_DEVICE_I2C 0x06 +#define BOOT_DEVICE_UART 0x07 +#define BOOT_DEVICE_MMC 0x08 +#define BOOT_DEVICE_EMMC 0x09 + +#define BOOT_DEVICE_USB 0x2A +#define BOOT_DEVICE_DFU 0x0A +#define BOOT_DEVICE_GPMC_NAND 0x0B +#define BOOT_DEVICE_GPMC_NOR 0x0C +#define BOOT_DEVICE_XSPI 0x0E +#define BOOT_DEVICE_NOBOOT 0x0F + +/* U-Boot used aliases */ +#define BOOT_DEVICE_ETHERNET 0x04 +#define BOOT_DEVICE_SPINAND 0x10 +#define BOOT_DEVICE_MMC2 0x08 +#define BOOT_DEVICE_MMC1 0x09 +/* Invalid */ +#define BOOT_DEVICE_MMC2_2 0x1F + +/* Backup BootMode devices */ +#define BACKUP_BOOT_DEVICE_DFU 0x01 +#define BACKUP_BOOT_DEVICE_UART 0x03 +#define BACKUP_BOOT_DEVICE_ETHERNET 0x04 +#define BACKUP_BOOT_DEVICE_MMC 0x05 +#define BACKUP_BOOT_DEVICE_SPI 0x06 +#define BACKUP_BOOT_DEVICE_I2C 0x07 +#define BACKUP_BOOT_DEVICE_USB 0x09 + +#define K3_PRIMARY_BOOTMODE 0x0 + +#endif /* _ASM_ARCH_AM62P_SPL_H_ */ diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 52ef82e70b0..c724450638c 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -32,19 +32,29 @@ #include "am62a_hardware.h" #endif +#ifdef CONFIG_SOC_K3_J784S4 +#include "j784s4_hardware.h" +#endif + +#ifdef CONFIG_SOC_K3_AM62P5 +#include "am62p_hardware.h" +#endif + /* Assuming these addresses and definitions stay common across K3 devices */ #define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14) #define JTAG_ID_VARIANT_SHIFT 28 #define JTAG_ID_VARIANT_MASK (0xf << 28) #define JTAG_ID_PARTNO_SHIFT 12 #define JTAG_ID_PARTNO_MASK (0xffff << 12) +#define JTAG_ID_PARTNO_AM62AX 0xbb8d +#define JTAG_ID_PARTNO_AM62PX 0xbb9d +#define JTAG_ID_PARTNO_AM62X 0xbb7e +#define JTAG_ID_PARTNO_AM64X 0xbb38 #define JTAG_ID_PARTNO_AM65X 0xbb5a -#define JTAG_ID_PARTNO_J721E 0xbb64 #define JTAG_ID_PARTNO_J7200 0xbb6d -#define JTAG_ID_PARTNO_AM64X 0xbb38 +#define JTAG_ID_PARTNO_J721E 0xbb64 #define JTAG_ID_PARTNO_J721S2 0xbb75 -#define JTAG_ID_PARTNO_AM62X 0xbb7e -#define JTAG_ID_PARTNO_AM62AX 0xbb8d +#define JTAG_ID_PARTNO_J784S4 0xbb80 #define K3_SOC_ID(id, ID) \ static inline bool soc_is_##id(void) \ @@ -60,6 +70,7 @@ K3_SOC_ID(am64x, AM64X) K3_SOC_ID(j721s2, J721S2) K3_SOC_ID(am62x, AM62X) K3_SOC_ID(am62ax, AM62AX) +K3_SOC_ID(am62px, AM62PX) #define K3_SEC_MGR_SYS_STATUS 0x44234100 #define SYS_STATUS_DEV_TYPE_SHIFT 0 @@ -96,4 +107,5 @@ struct rom_extended_boot_data { u32 num_components; }; +u32 get_boot_device(void); #endif /* _ASM_ARCH_HARDWARE_H_ */ diff --git a/arch/arm/mach-k3/include/mach/j721e_spl.h b/arch/arm/mach-k3/include/mach/j721e_spl.h index ed3d7333bd4..aaee6535376 100644 --- a/arch/arm/mach-k3/include/mach/j721e_spl.h +++ b/arch/arm/mach-k3/include/mach/j721e_spl.h @@ -24,8 +24,9 @@ #define BOOT_DEVICE_UFS 0x13 #define BOOT_DEVIE_GPMC 0x14 #define BOOT_DEVICE_PCIE 0x15 -#define BOOT_DEVICE_MMC2_2 0x16 -#define BOOT_DEVICE_RAM 0x17 +#define BOOT_DEVICE_XSPI 0x16 +#define BOOT_DEVICE_RAM 0x17 +#define BOOT_DEVICE_MMC2_2 0xFF /* Invalid value */ /* Backup boot modes with MCU Only = 0 */ #define BACKUP_BOOT_DEVICE_RAM 0x0 diff --git a/arch/arm/mach-k3/include/mach/j784s4_hardware.h b/arch/arm/mach-k3/include/mach/j784s4_hardware.h new file mode 100644 index 00000000000..0ffe238cdae --- /dev/null +++ b/arch/arm/mach-k3/include/mach/j784s4_hardware.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * K3: J784S4 SoC definitions, structures etc. + * + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ +#ifndef __ASM_ARCH_J784S4_HARDWARE_H +#define __ASM_ARCH_J784S4_HARDWARE_H + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#endif + +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x40f00000 +#define CTRL_MMR0_BASE 0x00100000 + +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) +#define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0) +#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0 +#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1) +#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1 +#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6) +#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6 +#define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7) +#define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7 + +#define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) +#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3) +#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 +#define WKUP_DEVSTAT_MCU_ONLY_MASK BIT(6) +#define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6 + +/* ROM HANDOFF Structure location */ +#define ROM_EXTENDED_BOOT_DATA_INFO 0x41cfdb00 + +/* MCU SCRATCHPAD usage */ +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE + +#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) + +#define J784S4_DEV_MCU_RTI0 367 +#define J784S4_DEV_MCU_RTI1 368 +#define J784S4_DEV_MCU_ARMSS0_CPU0 346 +#define J784S4_DEV_MCU_ARMSS0_CPU1 347 + +static const u32 put_device_ids[] = { + J784S4_DEV_MCU_RTI0, + J784S4_DEV_MCU_RTI1, +}; + +static const u32 put_core_ids[] = { + J784S4_DEV_MCU_ARMSS0_CPU1, + J784S4_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ +}; + +#endif + +#endif /* __ASM_ARCH_J784S4_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/j784s4_spl.h b/arch/arm/mach-k3/include/mach/j784s4_spl.h new file mode 100644 index 00000000000..d481a46c675 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/j784s4_spl.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef _ASM_ARCH_J784S4_SPL_H_ +#define _ASM_ARCH_J784S4_SPL_H_ + +/* With BootMode B = 0 */ +#include <linux/bitops.h> + +#define BOOT_DEVICE_HYPERFLASH 0x00 +#define BOOT_DEVICE_OSPI 0x01 +#define BOOT_DEVICE_QSPI 0x02 +#define BOOT_DEVICE_SPI 0x03 +#define BOOT_DEVICE_ETHERNET 0x04 +#define BOOT_DEVICE_I2C 0x06 +#define BOOT_DEVICE_UART 0x07 +#define BOOT_DEVICE_NOR BOOT_DEVICE_HYPERFLASH + +/* With BootMode B = 1 */ +#define BOOT_DEVICE_MMC2 0x10 +#define BOOT_DEVICE_MMC1 0x11 +#define BOOT_DEVICE_DFU 0x12 +#define BOOT_DEVICE_UFS 0x13 +#define BOOT_DEVIE_GPMC 0x14 +#define BOOT_DEVICE_PCIE 0x15 +#define BOOT_DEVICE_XSPI 0x16 +#define BOOT_DEVICE_RAM 0x17 +#define BOOT_DEVICE_MMC2_2 0xFF /* Invalid value */ + +/* Backup boot modes with MCU Only = 0 */ +#define BACKUP_BOOT_DEVICE_RAM 0x0 +#define BACKUP_BOOT_DEVICE_USB 0x1 +#define BACKUP_BOOT_DEVICE_UART 0x3 +#define BACKUP_BOOT_DEVICE_ETHERNET 0x4 +#define BACKUP_BOOT_DEVICE_MMC2 0x5 +#define BACKUP_BOOT_DEVICE_SPI 0x6 +#define BACKUP_BOOT_DEVICE_I2C 0x7 + +#define BOOT_MODE_B_SHIFT 4 +#define BOOT_MODE_B_MASK BIT(4) + +#define K3_PRIMARY_BOOTMODE 0x0 +#define K3_BACKUP_BOOTMODE 0x1 + +#endif diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h index 3ddc7eb6b63..83942779225 100644 --- a/arch/arm/mach-k3/include/mach/spl.h +++ b/arch/arm/mach-k3/include/mach/spl.h @@ -30,4 +30,12 @@ #include "am62a_spl.h" #endif +#ifdef CONFIG_SOC_K3_J784S4 +#include "j784s4_spl.h" +#endif + +#ifdef CONFIG_SOC_K3_AM62P5 +#include "am62p_spl.h" +#endif + #endif /* _ASM_ARCH_SPL_H_ */ diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index c2976c4ea0d..7ee9b75de4d 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -346,7 +346,8 @@ static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat) bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) << BOOT_MODE_B_SHIFT; - if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI) + if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI || + bootmode == BOOT_DEVICE_XSPI) bootmode = BOOT_DEVICE_SPI; if (bootmode == BOOT_DEVICE_MMC2) { diff --git a/arch/arm/mach-k3/j784s4/Kconfig b/arch/arm/mach-k3/j784s4/Kconfig new file mode 100644 index 00000000000..1eadfb346a3 --- /dev/null +++ b/arch/arm/mach-k3/j784s4/Kconfig @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ +# Hari Nagalla <hnagalla@ti.com> + +if SOC_K3_J784S4 + +choice + prompt "K3 J784S4 board" + optional + +config TARGET_J784S4_A72_EVM + bool "TI K3 based J784S4 EVM running on A72" + select ARM64 + select BOARD_LATE_INIT + select SYS_DISABLE_DCACHE_OPS + select BINMAN + +config TARGET_J784S4_R5_EVM + bool "TI K3 based J784S4 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + +endchoice + +source "board/ti/j784s4/Kconfig" + +endif diff --git a/arch/arm/mach-k3/j784s4_fdt.c b/arch/arm/mach-k3/j784s4_fdt.c new file mode 100644 index 00000000000..d05ed8b9911 --- /dev/null +++ b/arch/arm/mach-k3/j784s4_fdt.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * J784S4: SoC specific initialization + * + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Apurva Nandan <a-nandan@ti.com> + */ + +#include "common_fdt.h" +#include <fdt_support.h> + +int ft_system_setup(void *blob, struct bd_info *bd) +{ + return fdt_fixup_msmc_ram_k3(blob); +} diff --git a/arch/arm/mach-k3/j784s4_init.c b/arch/arm/mach-k3/j784s4_init.c new file mode 100644 index 00000000000..ae4420362d0 --- /dev/null +++ b/arch/arm/mach-k3/j784s4_init.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * J784S4: SoC specific initialization + * + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Hari Nagalla <hnagalla@ti.com> + */ + +#include <init.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/armv7_mpu.h> +#include <asm/arch/hardware.h> +#include "sysfw-loader.h" +#include "common.h" +#include <linux/soc/ti/ti_sci_protocol.h> +#include <dm.h> +#include <dm/uclass-internal.h> +#include <dm/pinctrl.h> +#include <mmc.h> +#include <remoteproc.h> + +#define J784S4_MAX_DDR_CONTROLLERS 4 + +struct fwl_data infra_cbass0_fwls[] = { + { "PSC0", 5, 1 }, + { "PLL_CTRL0", 6, 1 }, + { "PLL_MMR0", 8, 26 }, + { "CTRL_MMR0", 9, 16 }, + { "GPIO0", 16, 1 }, +}, wkup_cbass0_fwls[] = { + { "WKUP_PSC0", 129, 1 }, + { "WKUP_PLL_CTRL0", 130, 1 }, + { "WKUP_CTRL_MMR0", 131, 16 }, + { "WKUP_GPIO0", 132, 1 }, + { "WKUP_I2C0", 144, 1 }, + { "WKUP_USART0", 160, 1 }, +}, mcu_cbass0_fwls[] = { + { "MCU_R5FSS0_CORE0", 1024, 4 }, + { "MCU_R5FSS0_CORE0_CFG", 1025, 3 }, + { "MCU_R5FSS0_CORE1", 1028, 4 }, + { "MCU_R5FSS0_CORE1_CFG", 1029, 1 }, + { "MCU_FSS0_CFG", 1032, 12 }, + { "MCU_FSS0_S1", 1033, 8 }, + { "MCU_FSS0_S0", 1036, 8 }, + { "MCU_PSROM49152X32", 1048, 1 }, + { "MCU_MSRAM128KX64", 1050, 8 }, + { "MCU_MSRAM128KX64_CFG", 1051, 1 }, + { "MCU_TIMER0", 1056, 1 }, + { "MCU_TIMER9", 1065, 1 }, + { "MCU_USART0", 1120, 1 }, + { "MCU_I2C0", 1152, 1 }, + { "MCU_CTRL_MMR0", 1200, 8 }, + { "MCU_PLL_MMR0", 1201, 3 }, + { "MCU_CPSW0", 1220, 2 }, +}, cbass_rc_cfg0_fwls[] = { + { "EMMCSD4SS0_CFG", 2400, 4 }, +}, cbass_hc2_fwls[] = { + { "PCIE0", 2547, 24 }, +}, cbass_hc_cfg0_fwls[] = { + { "PCIE0_CFG", 2577, 7 }, + { "EMMC8SS0_CFG", 2579, 4 }, + { "USB3SS0_CORE", 2580, 4 }, + { "USB3SS1_CORE", 2581, 1 }, +}, navss_cbass0_fwls[] = { + { "NACSS_VIRT0", 6253, 1 }, +}; + +static void ctrl_mmr_unlock(void) +{ + /* Unlock all WKUP_CTRL_MMR0 module registers */ + mmr_unlock(WKUP_CTRL_MMR0_BASE, 0); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 1); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 2); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 3); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 4); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 6); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 7); + + /* Unlock all MCU_CTRL_MMR0 module registers */ + mmr_unlock(MCU_CTRL_MMR0_BASE, 0); + mmr_unlock(MCU_CTRL_MMR0_BASE, 1); + mmr_unlock(MCU_CTRL_MMR0_BASE, 2); + mmr_unlock(MCU_CTRL_MMR0_BASE, 3); + mmr_unlock(MCU_CTRL_MMR0_BASE, 4); + + /* Unlock all CTRL_MMR0 module registers */ + mmr_unlock(CTRL_MMR0_BASE, 0); + mmr_unlock(CTRL_MMR0_BASE, 1); + mmr_unlock(CTRL_MMR0_BASE, 2); + mmr_unlock(CTRL_MMR0_BASE, 3); + mmr_unlock(CTRL_MMR0_BASE, 5); + mmr_unlock(CTRL_MMR0_BASE, 7); +} + +/* + * This uninitialized global variable would normal end up in the .bss section, + * but the .bss is cleared between writing and reading this variable, so move + * it to the .data section. + */ +u32 bootindex __section(".data"); +static struct rom_extended_boot_data bootdata __section(".data"); + +static void store_boot_info_from_rom(void) +{ + bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); + memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO, + sizeof(struct rom_extended_boot_data)); +} + +void k3_spl_init(void) +{ + struct udevice *dev; + int ret; + + /* + * Cannot delay this further as there is a chance that + * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section. + */ + store_boot_info_from_rom(); + + /* Make all control module registers accessible */ + ctrl_mmr_unlock(); + + if (IS_ENABLED(CONFIG_CPU_V7R)) { + disable_linefill_optimization(); + setup_k3_mpu_regions(); + } + + /* Init DM early */ + ret = spl_early_init(); + + /* Prepare console output */ + preloader_console_init(); + + if (IS_ENABLED(CONFIG_CPU_V7R)) { + /* + * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue + * regardless of the result of pinctrl. Do this without probing the + * device, but instead by searching the device that would request the + * given sequence number if probed. The UART will be used by the system + * firmware (TIFS) image for various purposes and TIFS depends on us + * to initialize its pin settings. + */ + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev); + if (!ret) + pinctrl_select_state(dev, "default"); + + /* + * Load, start up, and configure system controller firmware. Provide + * the U-Boot console init function to the TIFS post-PM configuration + * callback hook, effectively switching on (or over) the console + * output. + */ + k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata), NULL, NULL); + + if (IS_ENABLED(CONFIG_SPL_CLK_K3)) { + /* + * Force probe of clk_k3 driver here to ensure basic default clock + * configuration is always done for enabling PM services. + */ + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(ti_clk), + &dev); + if (ret) + panic("Failed to initialize clk-k3!\n"); + } + + remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls)); + remove_fwl_configs(cbass_hc2_fwls, ARRAY_SIZE(cbass_hc2_fwls)); + remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls)); + remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls)); + remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls)); + remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls)); + remove_fwl_configs(navss_cbass0_fwls, ARRAY_SIZE(navss_cbass0_fwls)); + } + + /* Output System Firmware version info */ + k3_sysfw_print_ver(); +} + +void k3_mem_init(void) +{ + struct udevice *dev; + int ret, ctrl = 0; + + if (IS_ENABLED(CONFIG_K3_J721E_DDRSS)) { + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("DRAM 0 init failed: %d\n", ret); + ctrl++; + + while (ctrl < J784S4_MAX_DDR_CONTROLLERS) { + ret = uclass_next_device_err(&dev); + if (ret == -ENODEV) + break; + + if (ret) + panic("DRAM %d init failed: %d\n", ctrl, ret); + ctrl++; + } + printf("Initialized %d DRAM controllers\n", ctrl); + } + + spl_enable_cache(); +} + +void board_init_f(ulong dummy) +{ + k3_spl_init(); + k3_mem_init(); +} + +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) +{ + switch (boot_device) { + case BOOT_DEVICE_MMC1: + if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) + return MMCSD_MODE_EMMCBOOT; + if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4)) + return MMCSD_MODE_FS; + return MMCSD_MODE_EMMCBOOT; + case BOOT_DEVICE_MMC2: + return MMCSD_MODE_FS; + default: + return MMCSD_MODE_RAW; + } +} + +static u32 __get_backup_bootmedia(u32 main_devstat) +{ + u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >> + MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT; + + switch (bkup_boot) { + case BACKUP_BOOT_DEVICE_USB: + return BOOT_DEVICE_DFU; + case BACKUP_BOOT_DEVICE_UART: + return BOOT_DEVICE_UART; + case BACKUP_BOOT_DEVICE_ETHERNET: + return BOOT_DEVICE_ETHERNET; + case BACKUP_BOOT_DEVICE_MMC2: + { + u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >> + MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT; + if (port == 0x0) + return BOOT_DEVICE_MMC1; + return BOOT_DEVICE_MMC2; + } + case BACKUP_BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + case BACKUP_BOOT_DEVICE_I2C: + return BOOT_DEVICE_I2C; + } + + return BOOT_DEVICE_RAM; +} + +static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat) +{ + u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + + bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) << + BOOT_MODE_B_SHIFT; + + if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI || + bootmode == BOOT_DEVICE_XSPI) + bootmode = BOOT_DEVICE_SPI; + + if (bootmode == BOOT_DEVICE_MMC2) { + u32 port = (main_devstat & + MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >> + MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT; + if (port == 0x0) + bootmode = BOOT_DEVICE_MMC1; + } + + return bootmode; +} + +u32 spl_spi_boot_bus(void) +{ + u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT); + u32 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmode = ((wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT) | + ((main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) << BOOT_MODE_B_SHIFT); + + return (bootmode == BOOT_DEVICE_QSPI) ? 1 : 0; +} + +u32 spl_boot_device(void) +{ + u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT); + u32 main_devstat; + + if (wkup_devstat & WKUP_DEVSTAT_MCU_ONLY_MASK) { + printf("ERROR: MCU only boot is not yet supported\n"); + return BOOT_DEVICE_RAM; + } + + /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */ + main_devstat = readl(CTRLMMR_MAIN_DEVSTAT); + + if (bootindex == K3_PRIMARY_BOOTMODE) + return __get_primary_bootmedia(main_devstat, wkup_devstat); + else + return __get_backup_bootmedia(main_devstat); +} diff --git a/arch/arm/mach-k3/r5/Kconfig b/arch/arm/mach-k3/r5/Kconfig index 940a6dc4f4d..878087fbf56 100644 --- a/arch/arm/mach-k3/r5/Kconfig +++ b/arch/arm/mach-k3/r5/Kconfig @@ -51,3 +51,9 @@ config K3_SYSFW_IMAGE_SPI_OFFS help Offset of the combined System Firmware and configuration image tree blob to be loaded when booting from a SPI flash memory. + +config SYS_K3_SPL_ATF + bool "Start Cortex-A from SPL" + help + Enabling this will try to start Cortex-A (typically with ATF) + after SPL from R5. diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile index b99199d3374..1cfc8e3ade9 100644 --- a/arch/arm/mach-k3/r5/Makefile +++ b/arch/arm/mach-k3/r5/Makefile @@ -8,7 +8,10 @@ obj-$(CONFIG_SOC_K3_J721E) += j7200/ obj-$(CONFIG_SOC_K3_J721S2) += j721s2/ obj-$(CONFIG_SOC_K3_AM625) += am62x/ obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/ +obj-$(CONFIG_SOC_K3_J784S4) += j784s4/ +obj-$(CONFIG_SOC_K3_AM62P5) += am62px/ +obj-y += common.o obj-y += lowlevel_init.o obj-y += r5_mpu.o diff --git a/arch/arm/mach-k3/r5/am62ax/Makefile b/arch/arm/mach-k3/r5/am62ax/Makefile index e4e55ce5c7d..313ce5a05fd 100644 --- a/arch/arm/mach-k3/r5/am62ax/Makefile +++ b/arch/arm/mach-k3/r5/am62ax/Makefile @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0+ +# SPDX-License-Identifier: GPL-2.0+ # # Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ diff --git a/arch/arm/mach-k3/r5/am62px/Makefile b/arch/arm/mach-k3/r5/am62px/Makefile new file mode 100644 index 00000000000..091d4fa5b45 --- /dev/null +++ b/arch/arm/mach-k3/r5/am62px/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/r5/am62px/clk-data.c b/arch/arm/mach-k3/r5/am62px/clk-data.c new file mode 100644 index 00000000000..4b9892fe051 --- /dev/null +++ b/arch/arm/mach-k3/r5/am62px/clk-data.c @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62PX specific clock platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof <bb@ti.com>. + * + * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <linux/clk-provider.h> +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + NULL, + NULL, + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + NULL, +}; + +static const char * const clk_32k_rc_sel_out0_parents[] = { + "gluelogic_rcosc_clk_1p0v_97p65k", + "gluelogic_hfosc0_clkout", + "gluelogic_rcosc_clk_1p0v_97p65k", + "gluelogic_lfosc0_clkout", +}; + +static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = { + "board_0_mmc1_clklb_out", + "board_0_mmc1_clk_out", +}; + +static const char * const main_ospi_loopback_clk_sel_out0_parents[] = { + "board_0_ospi0_dqs_out", + "board_0_ospi0_lbclko_out", +}; + +static const char * const main_usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const main_usb1_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const clkout0_ctrl_out0_parents[] = { + "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", +}; + +static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_gtcclk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const main_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout1_clk", + "postdiv1_16fft_main_1_hsdivout5_clk", +}; + +static const char * const main_timerclkn_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "clk_32k_rc_sel_out0", + "postdiv4_16ff_main_0_hsdivout7_clk", + "gluelogic_rcosc_clkout", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + "board_0_cp_gemac_cpts0_rft_clk_out", + "hsdiv4_16fft_main_1_hsdivout3_clk", + "postdiv4_16ff_main_2_hsdivout6_clk", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +static const char * const wkup_clkout_sel_out0_parents[] = { + NULL, + "gluelogic_lfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "postdiv4_16ff_main_2_hsdivout9_clk", + "clk_32k_rc_sel_out0", + "gluelogic_rcosc_clkout", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clkout_sel_io_out0_parents[] = { + "wkup_clkout_sel_out0", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clksel_out0_parents[] = { + "hsdiv3_16fft_main_15_hsdivout0_clk", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const main_usart0_fclk_sel_out0_parents[] = { + "usart_programmable_clock_divider_out0", + "hsdiv4_16fft_main_1_hsdivout1_clk", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0), + CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0), + CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0, 1920000000), + CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0), + CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0), + CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x68009c, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682098, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0), + CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0), + CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0), + CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0), + CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0), + CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), + CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x68108c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), + CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), + CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), + CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), + CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0), + CLK_MUX("main_timerclkn_sel_out0", main_timerclkn_sel_out0_parents, 16, 0x1081b0, 0, 4, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000), + CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0), + CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0), + CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0), + CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 5, "board_0_ext_refclk1_out"), + DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"), + DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 9, "board_0_ext_refclk1_out"), + DEV_CLK(16, 10, "gluelogic_rcosc_clkout"), + DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(36, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(36, 2, "main_timerclkn_sel_out0"), + DEV_CLK(36, 3, "gluelogic_hfosc0_clkout"), + DEV_CLK(36, 4, "clk_32k_rc_sel_out0"), + DEV_CLK(36, 5, "postdiv4_16ff_main_0_hsdivout7_clk"), + DEV_CLK(36, 6, "gluelogic_rcosc_clkout"), + DEV_CLK(36, 7, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(36, 8, "board_0_ext_refclk1_out"), + DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"), + DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"), + DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"), + DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), + DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), + DEV_CLK(58, 2, "board_0_mmc1_clk_out"), + DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"), + DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(61, 0, "main_gtcclk_sel_out0"), + DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(61, 6, "board_0_ext_refclk1_out"), + DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 9, "wkup_clksel_out0"), + DEV_CLK(61, 10, "hsdiv3_16fft_main_15_hsdivout0_clk"), + DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(75, 0, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"), + DEV_CLK(75, 3, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"), + DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"), + DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"), + DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(102, 1, "board_0_i2c0_scl_out"), + DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"), + DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"), + DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"), + DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 36, "clkout0_ctrl_out0"), + DEV_CLK(157, 37, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 38, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 40, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 54, "mshsi2c_main_0_porscl"), + DEV_CLK(157, 91, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 101, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 103, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 143, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 145, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 161, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"), + DEV_CLK(157, 163, "dmtimer_dmc1ms_main_0_timer_pwm"), + DEV_CLK(157, 174, "wkup_clkout_sel_io_out0"), + DEV_CLK(157, 175, "wkup_clkout_sel_out0"), + DEV_CLK(157, 176, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"), + DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(161, 10, "board_0_tck_out"), + DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"), + DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(162, 10, "board_0_tck_out"), + DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(170, 2, "board_0_tck_out"), + DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), +}; + +const struct ti_k3_clk_platdata am62px_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = ARRAY_SIZE(clk_list), + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data), +}; diff --git a/arch/arm/mach-k3/r5/am62px/dev-data.c b/arch/arm/mach-k3/r5/am62px/dev-data.c new file mode 100644 index 00000000000..3cc211ea202 --- /dev/null +++ b/arch/arm/mach-k3/r5/am62px/dev-data.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62PX specific device platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof <bb@ti.com>. + * + * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x00400000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[0], NULL), + [1] = PSC_PD(3, &soc_psc_list[0], &soc_pd_list[0]), + [2] = PSC_PD(4, &soc_psc_list[0], &soc_pd_list[1]), + [3] = PSC_PD(13, &soc_psc_list[0], &soc_pd_list[0]), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]), + [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), + [4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), + [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), + [6] = PSC_LPSC(24, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), + [7] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), + [8] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), + [9] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]), + [10] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[9]), + [11] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]), + [12] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]), + [13] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(16, &soc_lpsc_list[0]), + PSC_DEV(77, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[0]), + PSC_DEV(178, &soc_lpsc_list[1]), + PSC_DEV(179, &soc_lpsc_list[2]), + PSC_DEV(57, &soc_lpsc_list[3]), + PSC_DEV(58, &soc_lpsc_list[4]), + PSC_DEV(161, &soc_lpsc_list[5]), + PSC_DEV(162, &soc_lpsc_list[6]), + PSC_DEV(75, &soc_lpsc_list[7]), + PSC_DEV(36, &soc_lpsc_list[8]), + PSC_DEV(102, &soc_lpsc_list[8]), + PSC_DEV(146, &soc_lpsc_list[8]), + PSC_DEV(166, &soc_lpsc_list[9]), + PSC_DEV(135, &soc_lpsc_list[10]), + PSC_DEV(170, &soc_lpsc_list[11]), + PSC_DEV(177, &soc_lpsc_list[12]), + PSC_DEV(55, &soc_lpsc_list[13]), +}; + +const struct ti_k3_pd_platdata am62px_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = ARRAY_SIZE(soc_psc_list), + .num_pd = ARRAY_SIZE(soc_pd_list), + .num_lpsc = ARRAY_SIZE(soc_lpsc_list), + .num_devs = ARRAY_SIZE(soc_dev_list), +}; diff --git a/arch/arm/mach-k3/r5/am62x/Makefile b/arch/arm/mach-k3/r5/am62x/Makefile index d6c876df66d..9ab0100ee17 100644 --- a/arch/arm/mach-k3/r5/am62x/Makefile +++ b/arch/arm/mach-k3/r5/am62x/Makefile @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0+ +# SPDX-License-Identifier: GPL-2.0+ # # Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c new file mode 100644 index 00000000000..0f6c294f1eb --- /dev/null +++ b/arch/arm/mach-k3/r5/common.c @@ -0,0 +1,352 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * K3: R5 Common Architecture initialization + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <linux/printk.h> +#include <linux/types.h> +#include <asm/hardware.h> +#include <asm/io.h> +#include <image.h> +#include <fs_loader.h> +#include <linux/soc/ti/ti_sci_protocol.h> +#include <spl.h> +#include <remoteproc.h> +#include <elf.h> + +#include "../common.h" + +#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF) +enum { + IMAGE_ID_ATF, + IMAGE_ID_OPTEE, + IMAGE_ID_SPL, + IMAGE_ID_DM_FW, + IMAGE_ID_TIFSSTUB_HS, + IMAGE_ID_TIFSSTUB_FS, + IMAGE_ID_T, + IMAGE_AMT, +}; + +#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS) +static const char *image_os_match[IMAGE_AMT] = { + "arm-trusted-firmware", + "tee", + "U-Boot", + "DM", + "tifsstub-hs", + "tifsstub-fs", + "tifsstub-gp", +}; +#endif + +static struct image_info fit_image_info[IMAGE_AMT]; + +void init_env(void) +{ +#ifdef CONFIG_SPL_ENV_SUPPORT + char *part; + + env_init(); + env_relocate(); + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC2: + part = env_get("bootpart"); + env_set("storage_interface", "mmc"); + env_set("fw_dev_part", part); + break; + case BOOT_DEVICE_SPI: + env_set("storage_interface", "ubi"); + env_set("fw_ubi_mtdpart", "UBI"); + env_set("fw_ubi_volume", "UBI0"); + break; + default: + printf("%s from device %u not supported!\n", + __func__, spl_boot_device()); + return; + } +#endif +} + +int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr) +{ + struct udevice *fsdev; + char *name = NULL; + int size = 0; + + if (!CONFIG_IS_ENABLED(FS_LOADER)) + return 0; + + *loadaddr = 0; +#ifdef CONFIG_SPL_ENV_SUPPORT + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC2: + name = env_get(name_fw); + *loadaddr = env_get_hex(name_loadaddr, *loadaddr); + break; + default: + printf("Loading rproc fw image from device %u not supported!\n", + spl_boot_device()); + return 0; + } +#endif + if (!*loadaddr) + return 0; + + if (!get_fs_loader(&fsdev)) { + size = request_firmware_into_buf(fsdev, name, (void *)*loadaddr, + 0, 0); + } + + return size; +} + +void release_resources_for_core_shutdown(void) +{ + struct ti_sci_handle *ti_sci = get_ti_sci_handle(); + struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops; + struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops; + int ret; + u32 i; + + /* Iterate through list of devices to put (shutdown) */ + for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) { + u32 id = put_device_ids[i]; + + ret = dev_ops->put_device(ti_sci, id); + if (ret) + panic("Failed to put device %u (%d)\n", id, ret); + } + + /* Iterate through list of cores to put (shutdown) */ + for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) { + u32 id = put_core_ids[i]; + + /* + * Queue up the core shutdown request. Note that this call + * needs to be followed up by an actual invocation of an WFE + * or WFI CPU instruction. + */ + ret = proc_ops->proc_shutdown_no_wait(ti_sci, id); + if (ret) + panic("Failed sending core %u shutdown message (%d)\n", + id, ret); + } +} + +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + typedef void __noreturn (*image_entry_noargs_t)(void); + struct ti_sci_handle *ti_sci = get_ti_sci_handle(); + u32 loadaddr = 0; + int ret, size = 0, shut_cpu = 0; + + /* Release all the exclusive devices held by SPL before starting ATF */ + ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci); + + ret = rproc_init(); + if (ret) + panic("rproc failed to be initialized (%d)\n", ret); + + init_env(); + + if (!fit_image_info[IMAGE_ID_DM_FW].image_start) { + size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load", + &loadaddr); + } + + /* + * It is assumed that remoteproc device 1 is the corresponding + * Cortex-A core which runs ATF. Make sure DT reflects the same. + */ + if (!fit_image_info[IMAGE_ID_ATF].image_start) + fit_image_info[IMAGE_ID_ATF].image_start = + spl_image->entry_point; + + ret = rproc_load(1, fit_image_info[IMAGE_ID_ATF].image_start, 0x200); + if (ret) + panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret); + +#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS) + /* Authenticate ATF */ + void *image_addr = (void *)fit_image_info[IMAGE_ID_ATF].image_start; + + debug("%s: Authenticating image: addr=%lx, size=%ld, os=%s\n", __func__, + fit_image_info[IMAGE_ID_ATF].image_start, + fit_image_info[IMAGE_ID_ATF].image_len, + image_os_match[IMAGE_ID_ATF]); + + ti_secure_image_post_process(&image_addr, + (size_t *)&fit_image_info[IMAGE_ID_ATF].image_len); + + /* Authenticate OPTEE */ + image_addr = (void *)fit_image_info[IMAGE_ID_OPTEE].image_start; + + debug("%s: Authenticating image: addr=%lx, size=%ld, os=%s\n", __func__, + fit_image_info[IMAGE_ID_OPTEE].image_start, + fit_image_info[IMAGE_ID_OPTEE].image_len, + image_os_match[IMAGE_ID_OPTEE]); + + ti_secure_image_post_process(&image_addr, + (size_t *)&fit_image_info[IMAGE_ID_OPTEE].image_len); +#endif + + if (!fit_image_info[IMAGE_ID_DM_FW].image_len && + !(size > 0 && valid_elf_image(loadaddr))) { + shut_cpu = 1; + goto start_arm64; + } + + if (!fit_image_info[IMAGE_ID_DM_FW].image_start) { + loadaddr = load_elf_image_phdr(loadaddr); + } else { + loadaddr = fit_image_info[IMAGE_ID_DM_FW].image_start; + if (valid_elf_image(loadaddr)) + loadaddr = load_elf_image_phdr(loadaddr); + } + + debug("%s: jumping to address %x\n", __func__, loadaddr); + +start_arm64: + /* Add an extra newline to differentiate the ATF logs from SPL */ + printf("Starting ATF on ARM64 core...\n\n"); + + ret = rproc_start(1); + if (ret) + panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret); + + if (shut_cpu) { + debug("Shutting down...\n"); + release_resources_for_core_shutdown(); + + while (1) + asm volatile("wfe"); + } + image_entry_noargs_t image_entry = (image_entry_noargs_t)loadaddr; + + image_entry(); +} +#endif + +void disable_linefill_optimization(void) +{ + u32 actlr; + + /* + * On K3 devices there are 2 conditions where R5F can deadlock: + * 1.When software is performing series of store operations to + * cacheable write back/write allocate memory region and later + * on software execute barrier operation (DSB or DMB). R5F may + * hang at the barrier instruction. + * 2.When software is performing a mix of load and store operations + * within a tight loop and store operations are all writing to + * cacheable write back/write allocates memory regions, R5F may + * hang at one of the load instruction. + * + * To avoid the above two conditions disable linefill optimization + * inside Cortex R5F. + */ + asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr)); + actlr |= (1 << 13); /* Set DLFO bit */ + asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr)); +} + +static void remove_fwl_regions(struct fwl_data fwl_data, size_t num_regions, + enum k3_firewall_region_type fwl_type) +{ + struct ti_sci_fwl_ops *fwl_ops; + struct ti_sci_handle *ti_sci; + struct ti_sci_msg_fwl_region region; + size_t j; + + ti_sci = get_ti_sci_handle(); + fwl_ops = &ti_sci->ops.fwl_ops; + + for (j = 0; j < fwl_data.regions; j++) { + region.fwl_id = fwl_data.fwl_id; + region.region = j; + region.n_permission_regs = 3; + + fwl_ops->get_fwl_region(ti_sci, ®ion); + + /* Don't disable the background regions */ + if (region.control != 0 && + ((region.control >> K3_FIREWALL_BACKGROUND_BIT) & 1) == fwl_type) { + pr_debug("Attempting to disable firewall %5d (%25s)\n", + region.fwl_id, fwl_data.name); + region.control = 0; + + if (fwl_ops->set_fwl_region(ti_sci, ®ion)) + pr_err("Could not disable firewall %5d (%25s)\n", + region.fwl_id, fwl_data.name); + } + } +} + +void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) +{ + size_t i; + + for (i = 0; i < fwl_data_size; i++) { + remove_fwl_regions(fwl_data[i], fwl_data[i].regions, + K3_FIREWALL_REGION_FOREGROUND); + remove_fwl_regions(fwl_data[i], fwl_data[i].regions, + K3_FIREWALL_REGION_BACKGROUND); + } +} + +#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS) +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) +{ + int len; + int i; + const char *os; + u32 addr; + + os = fdt_getprop(fit, node, "os", &len); + addr = fdt_getprop_u32_default_node(fit, node, 0, "entry", -1); + + debug("%s: processing image: addr=%x, size=%d, os=%s\n", __func__, + addr, *p_size, os); + + for (i = 0; i < IMAGE_AMT; i++) { + if (!strcmp(os, image_os_match[i])) { + fit_image_info[i].image_start = addr; + fit_image_info[i].image_len = *p_size; + debug("%s: matched image for ID %d\n", __func__, i); + break; + } + } + + if (i < IMAGE_AMT && i > IMAGE_ID_DM_FW) { + int device_type = get_device_type(); + + if ((device_type == K3_DEVICE_TYPE_HS_SE && + strcmp(os, "tifsstub-hs")) || + (device_type == K3_DEVICE_TYPE_HS_FS && + strcmp(os, "tifsstub-fs")) || + (device_type == K3_DEVICE_TYPE_GP && + strcmp(os, "tifsstub-gp"))) { + *p_size = 0; + } else { + debug("tifsstub-type: %s\n", os); + } + + return; + } + + /* + * Only DM and the DTBs are being authenticated here, + * rest will be authenticated when A72 cluster is up + */ + if ((i != IMAGE_ID_ATF) && (i != IMAGE_ID_OPTEE)) { + ti_secure_image_check_binary(p_image, p_size); + ti_secure_image_post_process(p_image, p_size); + } else { + ti_secure_image_check_binary(p_image, p_size); + } +} +#endif diff --git a/arch/arm/mach-k3/r5/j7200/Makefile b/arch/arm/mach-k3/r5/j7200/Makefile index 0f91cf4daea..78325db402c 100644 --- a/arch/arm/mach-k3/r5/j7200/Makefile +++ b/arch/arm/mach-k3/r5/j7200/Makefile @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0+ +# SPDX-License-Identifier: GPL-2.0+ # # Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ obj-y += clk-data.o diff --git a/arch/arm/mach-k3/r5/j721e/Makefile b/arch/arm/mach-k3/r5/j721e/Makefile index 0f91cf4daea..78325db402c 100644 --- a/arch/arm/mach-k3/r5/j721e/Makefile +++ b/arch/arm/mach-k3/r5/j721e/Makefile @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0+ +# SPDX-License-Identifier: GPL-2.0+ # # Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ obj-y += clk-data.o diff --git a/arch/arm/mach-k3/r5/j721s2/Makefile b/arch/arm/mach-k3/r5/j721s2/Makefile index e794bffb3af..8588c5e4c39 100644 --- a/arch/arm/mach-k3/r5/j721s2/Makefile +++ b/arch/arm/mach-k3/r5/j721s2/Makefile @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0+ +# SPDX-License-Identifier: GPL-2.0+ # # Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ obj-y += clk-data.o diff --git a/arch/arm/mach-k3/r5/j784s4/Makefile b/arch/arm/mach-k3/r5/j784s4/Makefile new file mode 100644 index 00000000000..9ce88305f57 --- /dev/null +++ b/arch/arm/mach-k3/r5/j784s4/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ +# + +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c new file mode 100644 index 00000000000..feaa13ee266 --- /dev/null +++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c @@ -0,0 +1,428 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * J784S4 specific clock platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof <bb@ti.com>. + * + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <linux/clk-provider.h> +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + "osc_19_2_mhz", + "osc_20_mhz", + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + "osc_27_mhz", +}; + +static const char * const mcu_ospi0_iclk_sel_out0_parents[] = { + "board_0_mcu_ospi0_dqs_out", + "fss_mcu_0_ospi_0_ospi_oclk_clk", +}; + +static const char * const mcu_ospi1_iclk_sel_out0_parents[] = { + "board_0_mcu_ospi1_dqs_out", + "fss_mcu_0_ospi_1_ospi_oclk_clk", +}; + +static const char * const wkup_fref_clksel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", +}; + +static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = { + "wkup_fref_clksel_out0", + "hsdiv1_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", +}; + +static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", +}; + +static const char * const wkup_gpio0_clksel_out0_parents[] = { + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", + "j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", + "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", +}; + +static const char * const mcu_usart_clksel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "postdiv3_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_i2c_mcupll_bypass_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out1_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out12_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out19_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out2_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out26_0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out27_0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out28_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out3_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out7_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out8_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const emmcsd1_lb_clksel_out0_parents[] = { + "board_0_mmc1_clklb_out", + "board_0_mmc1_clk_out", +}; + +static const char * const mcu_clkout_mux_out0_parents[] = { + "hsdiv4_16fft_mcu_2_hsdivout0_clk", + "hsdiv4_16fft_mcu_2_hsdivout0_clk", +}; + +static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "main_pll_hfosc_sel_out0", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const dpi0_ext_clksel_out0_parents[] = { + "hsdiv1_16fft_main_19_hsdivout0_clk", + "board_0_vout0_extpclkin_out", +}; + +static const char * const emmcsd_refclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const emmcsd_refclk_sel_out1_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const gtc_clk_mux_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv3_16fft_main_0_hsdivout6_clk", + "board_0_mcu_cpts0_rft_clk_out", + "board_0_cpts0_rft_clk_out", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_27_mhz", 27000000, 0), + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_FIXED_RATE("osc_20_mhz", 20000000, 0), + CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0), + CLK_FIXED_RATE("j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32000, 0), + CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0), + CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0), + CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0), + CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0), + CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0), + CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000), + CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000), + CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0), + CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), + CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0), + CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0), + CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0), + CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out26_0", main_pll_hfosc_sel_out26_0_parents, 2, 0x430080e8, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out27_0", main_pll_hfosc_sel_out27_0_parents, 2, 0x430080ec, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out28", main_pll_hfosc_sel_out28_parents, 2, 0x430080f0, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0), + CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0), + CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("board_0_vout0_extpclkin_out", 0, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0), + CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0, 2000000000), + CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000), + CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_26_foutvcop_clk", "main_pll_hfosc_sel_out26_0", 0x69a000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_27_foutvcop_clk", "main_pll_hfosc_sel_out27_0", 0x69b000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_28_foutvcop_clk", "main_pll_hfosc_sel_out28", 0x69c000, 0), + CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0, 2000000000), + CLK_PLL("pllfracf2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0), + CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), + CLK_DIV("postdiv3_16fft_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), + CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), + CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0), + CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0), + CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_27_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_27_foutvcop_clk", 0x69b080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_28_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_28_foutvcop_clk", 0x69c080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_MUX("dpi0_ext_clksel_out0", dpi0_ext_clksel_out0_parents, 2, 0x108300, 0, 1, 0), + CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0), + CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0), + CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), + CLK_DIV("usart_programmable_clock_divider_out5", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0), + CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(198, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(198, 3, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(198, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(202, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(61, 0, "gtc_clk_mux_out0"), + DEV_CLK(61, 1, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(61, 2, "postdiv3_16fft_main_0_hsdivout6_clk"), + DEV_CLK(61, 3, "board_0_mcu_cpts0_rft_clk_out"), + DEV_CLK(61, 4, "board_0_cpts0_rft_clk_out"), + DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(61, 6, "board_0_ext_refclk1_out"), + DEV_CLK(61, 15, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(61, 16, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(78, 0, "postdiv3_16fft_main_0_hsdivout8_clk"), + DEV_CLK(78, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(78, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(78, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(78, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(78, 5, "board_0_hfosc1_clk_out"), + DEV_CLK(78, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(78, 8, "gluelogic_hfosc0_clkout"), + DEV_CLK(78, 9, "board_0_hfosc1_clk_out"), + DEV_CLK(78, 10, "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(78, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(78, 12, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(140, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(140, 2, "emmcsd_refclk_sel_out0"), + DEV_CLK(140, 3, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(140, 4, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(140, 5, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(140, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(141, 0, "emmcsd1_lb_clksel_out0"), + DEV_CLK(141, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(141, 4, "emmcsd_refclk_sel_out1"), + DEV_CLK(141, 5, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(141, 6, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(141, 7, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(141, 8, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(146, 0, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(149, 0, "mcu_usart_clksel_out0"), + DEV_CLK(149, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), + DEV_CLK(149, 2, "postdiv3_16fft_main_1_hsdivout5_clk"), + DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(157, 174, "mcu_clkout_mux_out0"), + DEV_CLK(157, 175, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(157, 179, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), + DEV_CLK(157, 180, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), + DEV_CLK(157, 224, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 226, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 228, "fss_mcu_0_ospi_1_ospi_oclk_clk"), + DEV_CLK(157, 230, "fss_mcu_0_ospi_1_ospi_oclk_clk"), + DEV_CLK(157, 239, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(157, 243, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 245, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 354, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 359, "dpi0_ext_clksel_out0"), + DEV_CLK(157, 360, "mshsi2c_wkup_0_porscl"), + DEV_CLK(160, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(160, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(160, 4, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(160, 6, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(160, 8, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(161, 0, "board_0_mcu_ospi0_dqs_out"), + DEV_CLK(161, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(161, 2, "mcu_ospi0_iclk_sel_out0"), + DEV_CLK(161, 3, "board_0_mcu_ospi0_dqs_out"), + DEV_CLK(161, 4, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(161, 6, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(161, 7, "mcu_ospi_ref_clk_sel_out0"), + DEV_CLK(161, 8, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(161, 9, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(162, 0, "board_0_mcu_ospi1_dqs_out"), + DEV_CLK(162, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(162, 2, "mcu_ospi1_iclk_sel_out0"), + DEV_CLK(162, 3, "board_0_mcu_ospi1_dqs_out"), + DEV_CLK(162, 4, "fss_mcu_0_ospi_1_ospi_oclk_clk"), + DEV_CLK(162, 6, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(162, 7, "mcu_ospi_ref_clk_sel_out1"), + DEV_CLK(162, 8, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(162, 9, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(167, 0, "wkup_gpio0_clksel_out0"), + DEV_CLK(178, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(178, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(188, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(188, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(191, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(191, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(191, 4, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(191, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(192, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(192, 1, "hsdiv0_16fft_main_26_hsdivout0_clk"), + DEV_CLK(192, 4, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(192, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(193, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(193, 1, "hsdiv0_16fft_main_27_hsdivout0_clk"), + DEV_CLK(193, 4, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(193, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(194, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(194, 1, "hsdiv0_16fft_main_28_hsdivout0_clk"), + DEV_CLK(194, 4, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(194, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(201, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(201, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(243, 0, "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(243, 1, "gluelogic_hfosc0_clkout"), + DEV_CLK(243, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(279, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(279, 1, "board_0_wkup_i2c0_scl_out"), + DEV_CLK(279, 2, "wkup_i2c_mcupll_bypass_out0"), + DEV_CLK(279, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), + DEV_CLK(279, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(392, 0, "usart_programmable_clock_divider_out5"), + DEV_CLK(392, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(395, 0, "usart_programmable_clock_divider_out8"), + DEV_CLK(395, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(398, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(398, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(398, 2, "postdiv3_16fft_main_1_hsdivout7_clk"), + DEV_CLK(398, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(398, 20, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(398, 21, "usb0_refclk_sel_out0"), + DEV_CLK(398, 22, "gluelogic_hfosc0_clkout"), + DEV_CLK(398, 23, "board_0_hfosc1_clk_out"), + DEV_CLK(398, 28, "board_0_tck_out"), +}; + +const struct ti_k3_clk_platdata j784s4_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = ARRAY_SIZE(clk_list), + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data), +}; diff --git a/arch/arm/mach-k3/r5/j784s4/dev-data.c b/arch/arm/mach-k3/r5/j784s4/dev-data.c new file mode 100644 index 00000000000..d66ba8b16e0 --- /dev/null +++ b/arch/arm/mach-k3/r5/j784s4/dev-data.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * J784S4 specific device platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof <bb@ti.com>. + * + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x42000000), + [1] = PSC(1, 0x00420000), + [2] = PSC(2, 0x00400000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[0], NULL), + [1] = PSC_PD(3, &soc_psc_list[1], NULL), + [2] = PSC_PD(0, &soc_psc_list[2], NULL), + [3] = PSC_PD(1, &soc_psc_list[2], &soc_pd_list[2]), + [4] = PSC_PD(14, &soc_psc_list[2], NULL), + [5] = PSC_PD(15, &soc_psc_list[2], &soc_pd_list[4]), + [6] = PSC_PD(16, &soc_psc_list[2], &soc_pd_list[4]), + [7] = PSC_PD(38, &soc_psc_list[2], NULL), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(3, &soc_psc_list[0], &soc_pd_list[0], NULL), + [2] = PSC_LPSC(10, &soc_psc_list[0], &soc_pd_list[0], NULL), + [3] = PSC_LPSC(11, &soc_psc_list[0], &soc_pd_list[0], NULL), + [4] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], NULL), + [5] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[6]), + [6] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[1], NULL), + [7] = PSC_LPSC(0, &soc_psc_list[2], &soc_pd_list[2], NULL), + [8] = PSC_LPSC(9, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[2]), + [9] = PSC_LPSC(14, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[10]), + [10] = PSC_LPSC(15, &soc_psc_list[2], &soc_pd_list[2], NULL), + [11] = PSC_LPSC(16, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[12]), + [12] = PSC_LPSC(17, &soc_psc_list[2], &soc_pd_list[2], NULL), + [13] = PSC_LPSC(20, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]), + [14] = PSC_LPSC(23, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]), + [15] = PSC_LPSC(25, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]), + [16] = PSC_LPSC(43, &soc_psc_list[2], &soc_pd_list[3], NULL), + [17] = PSC_LPSC(45, &soc_psc_list[2], &soc_pd_list[3], NULL), + [18] = PSC_LPSC(78, &soc_psc_list[2], &soc_pd_list[4], NULL), + [19] = PSC_LPSC(80, &soc_psc_list[2], &soc_pd_list[5], &soc_lpsc_list[18]), + [20] = PSC_LPSC(81, &soc_psc_list[2], &soc_pd_list[6], &soc_lpsc_list[18]), + [21] = PSC_LPSC(120, &soc_psc_list[2], &soc_pd_list[7], &soc_lpsc_list[22]), + [22] = PSC_LPSC(121, &soc_psc_list[2], &soc_pd_list[7], NULL), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(35, &soc_lpsc_list[0]), + PSC_DEV(160, &soc_lpsc_list[0]), + PSC_DEV(161, &soc_lpsc_list[0]), + PSC_DEV(162, &soc_lpsc_list[0]), + PSC_DEV(243, &soc_lpsc_list[0]), + PSC_DEV(149, &soc_lpsc_list[0]), + PSC_DEV(167, &soc_lpsc_list[1]), + PSC_DEV(279, &soc_lpsc_list[1]), + PSC_DEV(161, &soc_lpsc_list[2]), + PSC_DEV(162, &soc_lpsc_list[3]), + PSC_DEV(160, &soc_lpsc_list[4]), + PSC_DEV(139, &soc_lpsc_list[5]), + PSC_DEV(194, &soc_lpsc_list[6]), + PSC_DEV(78, &soc_lpsc_list[7]), + PSC_DEV(61, &soc_lpsc_list[8]), + PSC_DEV(131, &soc_lpsc_list[9]), + PSC_DEV(191, &soc_lpsc_list[10]), + PSC_DEV(132, &soc_lpsc_list[11]), + PSC_DEV(192, &soc_lpsc_list[12]), + PSC_DEV(398, &soc_lpsc_list[13]), + PSC_DEV(141, &soc_lpsc_list[14]), + PSC_DEV(140, &soc_lpsc_list[15]), + PSC_DEV(146, &soc_lpsc_list[16]), + PSC_DEV(392, &soc_lpsc_list[17]), + PSC_DEV(395, &soc_lpsc_list[17]), + PSC_DEV(198, &soc_lpsc_list[18]), + PSC_DEV(202, &soc_lpsc_list[19]), + PSC_DEV(203, &soc_lpsc_list[20]), + PSC_DEV(133, &soc_lpsc_list[21]), + PSC_DEV(193, &soc_lpsc_list[22]), +}; + +const struct ti_k3_pd_platdata j784s4_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = ARRAY_SIZE(soc_psc_list), + .num_pd = ARRAY_SIZE(soc_pd_list), + .num_lpsc = ARRAY_SIZE(soc_lpsc_list), + .num_devs = ARRAY_SIZE(soc_dev_list), +}; diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c index 22697a263a8..7c46914d9dd 100644 --- a/arch/arm/mach-k3/security.c +++ b/arch/arm/mach-k3/security.c @@ -50,7 +50,7 @@ void ti_secure_image_check_binary(void **p_image, size_t *p_size) if (get_device_type() == K3_DEVICE_TYPE_GP) { if (ti_secure_cert_detected(*p_image)) { - printf("Warning: Detected image signing certificate on GP device. " + debug("Warning: Detected image signing certificate on GP device. " "Skipping certificate to prevent boot failure. " "This will fail if the image was also encrypted\n"); @@ -60,6 +60,7 @@ void ti_secure_image_check_binary(void **p_image, size_t *p_size) return; } + printf("Skipping authentication on GP device\n"); *p_image += cert_length; *p_size -= cert_length; } diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index c2fff84a686..031d4e5ecd3 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -6,10 +6,12 @@ config FEROCEON_88FR131 config KW88F6192 bool select ARCH_VERY_EARLY_INIT + imply OF_UPSTREAM config KW88F6281 bool select ARCH_VERY_EARLY_INIT + imply OF_UPSTREAM config SHEEVA_88SV131 bool diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index c3872f42869..82018bd9d3e 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -133,7 +133,6 @@ config SYS_BOARD be used. config SYS_CONFIG_NAME - string "Board configuration name" default "mt7622" if TARGET_MT7622 default "mt7623" if TARGET_MT7623 default "mt7629" if TARGET_MT7629 @@ -145,11 +144,6 @@ config SYS_CONFIG_NAME default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 default "mt8518" if TARGET_MT8518 - default "" - help - This option contains information about board configuration name. - Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header - will be used for board configuration. config MTK_BROM_HEADER_INFO string diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index d6c89058061..7570f48e25f 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -25,30 +25,35 @@ choice config MESON_GXBB bool "GXBB" select MESON_GX + imply OF_UPSTREAM help Select this if your SoC is an S905 config MESON_GXL bool "GXL" select MESON_GX + imply OF_UPSTREAM help Select this if your SoC is an S905X/D or S805X config MESON_GXM bool "GXM" select MESON_GX + imply OF_UPSTREAM help Select this if your SoC is an S912 config MESON_AXG bool "AXG" select MESON64_COMMON + imply OF_UPSTREAM help Select this if your SoC is an A113X/D config MESON_G12A bool "G12A" select MESON64_COMMON + imply OF_UPSTREAM help Select this if your SoC is an S905X/D2 @@ -88,12 +93,4 @@ config SYS_BOARD Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will be used. -config SYS_CONFIG_NAME - string "Board configuration name" - default "meson64" - help - This option contains information about board configuration name. - Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header - will be used for board configuration. - endif diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 2058c95ca2d..f15d3cc5edb 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -18,6 +18,8 @@ config ARMADA_32BIT select TOOLS_KWBIMAGE if SPL select SPL_SYS_NO_VECTOR_TABLE if SPL select ARCH_VERY_EARLY_INIT + select ARMADA_32BIT_SYSCON_RESET if DM_RESET && PCI_MVEBU + select ARMADA_32BIT_SYSCON_SYSRESET if SYSRESET # ARMv7 SoCs... config ARMADA_375 @@ -456,6 +458,29 @@ config SF_DEFAULT_MODE default 0x0 depends on MVEBU_SPL_BOOT_DEVICE_SPI +config ARMADA_32BIT_SYSCON + bool + depends on ARMADA_32BIT + select REGMAP + select SYSCON + +config ARMADA_32BIT_SYSCON_RESET + bool "Support Armada XP/375/38x/39x reset controller" + depends on ARMADA_32BIT + depends on DM_RESET + select ARMADA_32BIT_SYSCON + help + Build support for Armada XP/375/38x/39x reset controller. This is + needed for PCIe support. + +config ARMADA_32BIT_SYSCON_SYSRESET + bool "Support Armada XP/375/38x/39x sysreset via driver model" + depends on ARMADA_32BIT + depends on SYSRESET + select ARMADA_32BIT_SYSCON + help + Build support for Armada XP/375/38x/39x system reset via driver model. + source "board/solidrun/clearfog/Kconfig" source "board/kobol/helios4/Kconfig" diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 0584ed2be5b..329c2e49153 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -22,13 +22,14 @@ else # CONFIG_ARCH_KIRKWOOD obj-y = cpu.o obj-y += dram.o obj-y += lowlevel.o -obj-$(CONFIG_DM_RESET) += system-controller.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o obj-$(CONFIG_ARMADA_MSYS) += ../../../drivers/ddr/marvell/axp/xor.o +obj-$(CONFIG_ARMADA_32BIT_SYSCON) += system-controller.o + ifdef CONFIG_ARMADA_38X obj-$(CONFIG_MVEBU_EFUSE) += efuse.o endif diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 8e0de935385..7c62a5dbb6a 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -52,6 +52,7 @@ void lowlevel_init(void) */ } +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET) void reset_cpu(void) { struct mvebu_system_registers *reg = @@ -62,6 +63,7 @@ void reset_cpu(void) while (1) ; } +#endif u32 get_boot_device(void) { diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c index 7cdde11cbd2..682431ee11d 100644 --- a/arch/arm/mach-mvebu/system-controller.c +++ b/arch/arm/mach-mvebu/system-controller.c @@ -1,18 +1,33 @@ // SPDX-License-Identifier: GPL-2.0+ -// (C) 2021 Pali Rohár <pali@kernel.org> +/* + * Copyright (C) 2021 Pali Rohár <pali@kernel.org> + * Copyright (C) 2024 Marek Behún <kabel@kernel.org> + */ #include <common.h> #include <dm.h> +#include <dm/lists.h> +#include <regmap.h> #include <reset-uclass.h> +#include <syscon.h> +#include <sysreset.h> #include <asm/io.h> -#define MVEBU_SOC_CONTROL_1_REG 0x4 +#define MVEBU_SOC_CONTROL_1_REG 0x4 -#define MVEBU_PCIE_ID 0 +#if defined(CONFIG_ARMADA_375) +# define MVEBU_RSTOUTN_MASK_REG 0x54 +# define MVEBU_SYS_SOFT_RST_REG 0x58 +#else +# define MVEBU_RSTOUTN_MASK_REG 0x60 +# define MVEBU_SYS_SOFT_RST_REG 0x64 +#endif -struct mvebu_reset_data { - void *base; -}; +#define MVEBU_GLOBAL_SOFT_RST_BIT BIT(0) + +#define MVEBU_PCIE_ID 0 + +#if IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET) static int mvebu_reset_of_xlate(struct reset_ctl *rst, struct ofnode_phandle_args *args) @@ -46,46 +61,33 @@ static int mvebu_reset_free(struct reset_ctl *rst) static int mvebu_reset_assert(struct reset_ctl *rst) { - struct mvebu_reset_data *data = dev_get_priv(rst->dev); + struct regmap *regmap = syscon_get_regmap(rst->dev->parent); - clrbits_32(data->base + MVEBU_SOC_CONTROL_1_REG, BIT(rst->data)); - return 0; + return regmap_update_bits(regmap, MVEBU_SOC_CONTROL_1_REG, + BIT(rst->data), 0); } static int mvebu_reset_deassert(struct reset_ctl *rst) { - struct mvebu_reset_data *data = dev_get_priv(rst->dev); + struct regmap *regmap = syscon_get_regmap(rst->dev->parent); - setbits_32(data->base + MVEBU_SOC_CONTROL_1_REG, BIT(rst->data)); - return 0; + return regmap_update_bits(regmap, MVEBU_SOC_CONTROL_1_REG, + BIT(rst->data), BIT(rst->data)); } static int mvebu_reset_status(struct reset_ctl *rst) { - struct mvebu_reset_data *data = dev_get_priv(rst->dev); - - return !(readl(data->base + MVEBU_SOC_CONTROL_1_REG) & BIT(rst->data)); -} - -static int mvebu_reset_of_to_plat(struct udevice *dev) -{ - struct mvebu_reset_data *data = dev_get_priv(dev); + struct regmap *regmap = syscon_get_regmap(rst->dev->parent); + uint val; + int ret; - data->base = dev_read_addr_ptr(dev); - if (!data->base) - return -EINVAL; + ret = regmap_read(regmap, MVEBU_SOC_CONTROL_1_REG, &val); + if (ret < 0) + return ret; - return 0; + return !(val & BIT(rst->data)); } -static const struct udevice_id mvebu_reset_of_match[] = { - { .compatible = "marvell,armada-370-xp-system-controller" }, - { .compatible = "marvell,armada-375-system-controller" }, - { .compatible = "marvell,armada-380-system-controller" }, - { .compatible = "marvell,armada-390-system-controller" }, - { }, -}; - static const struct reset_ops mvebu_reset_ops = { .of_xlate = mvebu_reset_of_xlate, .request = mvebu_reset_request, @@ -98,8 +100,81 @@ static const struct reset_ops mvebu_reset_ops = { U_BOOT_DRIVER(mvebu_reset) = { .name = "mvebu-reset", .id = UCLASS_RESET, - .of_match = mvebu_reset_of_match, - .of_to_plat = mvebu_reset_of_to_plat, - .priv_auto = sizeof(struct mvebu_reset_data), .ops = &mvebu_reset_ops, }; + +#endif /* IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET) */ + +#if IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET) + +static int mvebu_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct regmap *regmap = syscon_get_regmap(dev->parent); + uint bit; + + if (type != SYSRESET_COLD) + return -EPROTONOSUPPORT; + + bit = MVEBU_GLOBAL_SOFT_RST_BIT; + + regmap_update_bits(regmap, MVEBU_RSTOUTN_MASK_REG, bit, bit); + regmap_update_bits(regmap, MVEBU_SYS_SOFT_RST_REG, bit, bit); + + /* Loop while waiting for the reset */ + while (1) + ; + + return 0; +} + +static struct sysreset_ops mvebu_sysreset_ops = { + .request = mvebu_sysreset_request, +}; + +U_BOOT_DRIVER(mvebu_sysreset) = { + .name = "mvebu-sysreset", + .id = UCLASS_SYSRESET, + .ops = &mvebu_sysreset_ops, +}; + +#endif /* IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET) */ + +static int mvebu_syscon_bind(struct udevice *dev) +{ + int ret = 0; + + /* bind also mvebu-reset, with the same ofnode */ + if (IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET)) { + ret = device_bind_driver_to_node(dev, "mvebu-reset", + "mvebu-reset", dev_ofnode(dev), + NULL); + if (ret < 0) + return ret; + } + + /* bind also mvebu-sysreset, with the same ofnode */ + if (IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)) { + ret = device_bind_driver_to_node(dev, "mvebu-sysreset", + "mvebu-sysreset", + dev_ofnode(dev), NULL); + if (ret < 0) + return ret; + } + + return ret; +} + +static const struct udevice_id mvebu_syscon_of_match[] = { + { .compatible = "marvell,armada-370-xp-system-controller" }, + { .compatible = "marvell,armada-375-system-controller" }, + { .compatible = "marvell,armada-380-system-controller" }, + { .compatible = "marvell,armada-390-system-controller" }, + { }, +}; + +U_BOOT_DRIVER(mvebu_syscon) = { + .name = "mvebu-system-controller", + .id = UCLASS_SYSCON, + .of_match = mvebu_syscon_of_match, + .bind = mvebu_syscon_bind, +}; diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index 57917da25cf..aa0ab13d5fb 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -190,7 +190,7 @@ int load_firmware(char *name_fw, u32 *loadaddr) struct udevice *fsdev; int size = 0; - if (!IS_ENABLED(CONFIG_FS_LOADER)) + if (!CONFIG_IS_ENABLED(FS_LOADER)) return 0; if (!*loadaddr) diff --git a/arch/arm/mach-omap2/omap5/fdt.c b/arch/arm/mach-omap2/omap5/fdt.c index a8c301c6c28..0ca02e664c4 100644 --- a/arch/arm/mach-omap2/omap5/fdt.c +++ b/arch/arm/mach-omap2/omap5/fdt.c @@ -206,9 +206,28 @@ u32 dra7_opp_gpu_clk_rates[NUM_OPPS][OPP_GPU_CLK_NUM] = { {1064000000, 532000000}, /* OPP_HIGH */ }; +static int fdt_clock_output_name_eq_(const void *fdt, int offset, + const char *s, int len) +{ + int olen; + const char *p = fdt_getprop(fdt, offset, "clock-output-names", &olen); + + if (!p) + /* short match */ + return 0; + + if (memcmp(p, s, len) != 0) + return 0; + + if (p[len] == '\0') + return 1; + else + return 0; +} + static int ft_fixup_clocks(void *fdt, const char **names, u32 *rates, int num) { - int offs, node_offs, ret, i; + int offs, node_offs, subnode, ret, i; uint32_t phandle; offs = fdt_path_offset(fdt, "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks"); @@ -223,9 +242,19 @@ static int ft_fixup_clocks(void *fdt, const char **names, u32 *rates, int num) for (i = 0; i < num; i++) { node_offs = fdt_subnode_offset(fdt, offs, names[i]); if (node_offs < 0) { - debug("Could not find clock sub-node %s: %s\n", - names[i], fdt_strerror(node_offs)); - return offs; + for (subnode = fdt_first_subnode(fdt, offs); + subnode >= 0; + subnode = fdt_next_subnode(fdt, subnode)) { + ret = fdt_clock_output_name_eq_(fdt, subnode, names[i], + strlen(names[i])); + if (ret) + node_offs = subnode; + } + if (node_offs < 0) { + debug("Could not find clock sub-node %s: %s\n", + names[i], fdt_strerror(node_offs)); + return offs; + } } phandle = fdt_get_phandle(fdt, node_offs); diff --git a/arch/arm/mach-renesas/Kconfig b/arch/arm/mach-renesas/Kconfig index 2ac867612bf..aeb55da609b 100644 --- a/arch/arm/mach-renesas/Kconfig +++ b/arch/arm/mach-renesas/Kconfig @@ -14,6 +14,7 @@ config RCAR_64 imply CMD_GPT imply CMD_MMC_SWRITE if MMC imply CMD_UUID + imply OF_UPSTREAM imply SUPPORT_EMMC_RPMB if MMC choice diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 1bc7ee90427..4f22d9bde9f 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -180,6 +180,7 @@ config ROCKCHIP_RK3328 select SUPPORT_TPL select TPL select TPL_NEEDS_SEPARATE_STACK if TPL + imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_SDRAM_COMMON imply SPL_ROCKCHIP_COMMON_BOARD @@ -189,6 +190,9 @@ config ROCKCHIP_RK3328 select ENABLE_ARM_SOC_BOOT0_HOOK select DEBUG_UART_BOARD_INIT select SYS_NS16550 + imply MISC + imply ROCKCHIP_EFUSE + imply MISC_INIT_R help The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two @@ -267,6 +271,9 @@ config ROCKCHIP_RK3399 imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT imply BOOTSTD_FULL imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT + imply MISC + imply ROCKCHIP_EFUSE + imply MISC_INIT_R help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. @@ -501,6 +508,30 @@ config SPL_ROCKCHIP_EARLYRETURN_TO_BROM This enables support code in the BOOT0 hook for the SPL stage to allow multiple entries. +config ROCKCHIP_DISABLE_FORCE_JTAG + bool "Disable force_jtag feature" + default y + depends on SPL + help + Rockchip SoCs can automatically switch between jtag and sdmmc based + on the following rules: + - all the SDMMC pins including SDMMC_DET set as SDMMC function in + GRF, + - force_jtag bit in GRF is 1, + - SDMMC_DET is low (no card detected), + + Some HW design may not route the SD card card detect to SDMMC_DET + pin, thus breaking the SD card support in some cases because JTAG + would be auto-enabled by mistake. + + Also, enabling JTAG at runtime may be an undesired feature, e.g. + because it could be a security vulnerability. + + This disables force_jtag feature, which you may want for debugging + purposes. + + If unsure, say Y. + config TPL_ROCKCHIP_EARLYRETURN_TO_BROM bool "TPL requires early-return (for RK3188-style BROM) to BROM" depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK @@ -528,6 +559,21 @@ config ROCKCHIP_SPI_IMAGE config LNX_KRNL_IMG_TEXT_OFFSET_BASE default TEXT_BASE +config ROCKCHIP_COMMON_STACK_ADDR + bool + depends on SPL_SHARES_INIT_SP_ADDR + select HAS_CUSTOM_SYS_INIT_SP_ADDR + imply SPL_LIBCOMMON_SUPPORT if SPL + imply SPL_LIBGENERIC_SUPPORT if SPL + imply SPL_ROCKCHIP_COMMON_BOARD if SPL + imply SPL_SYS_MALLOC_F if SPL + imply SPL_SYS_MALLOC_SIMPLE if SPL + imply TPL_LIBCOMMON_SUPPORT if TPL + imply TPL_LIBGENERIC_SUPPORT if TPL + imply TPL_ROCKCHIP_COMMON_BOARD if TPL + imply TPL_SYS_MALLOC_F if TPL + imply TPL_SYS_MALLOC_SIMPLE if TPL + source "arch/arm/mach-rockchip/px30/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3066/Kconfig" @@ -543,4 +589,44 @@ source "arch/arm/mach-rockchip/rk3568/Kconfig" source "arch/arm/mach-rockchip/rk3588/Kconfig" source "arch/arm/mach-rockchip/rv1108/Kconfig" source "arch/arm/mach-rockchip/rv1126/Kconfig" + +if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR + +config CUSTOM_SYS_INIT_SP_ADDR + default 0x3f00000 + +config SYS_MALLOC_F_LEN + default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + +config SPL_SYS_MALLOC_F_LEN + default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + +config TPL_SYS_MALLOC_F_LEN + default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + +config TEXT_BASE + default 0x00200000 if ARM64 + +config SPL_TEXT_BASE + default 0x0 if ARM64 + +config SPL_HAS_BSS_LINKER_SECTION + default y if ARM64 + +config SPL_BSS_START_ADDR + default 0x3f80000 + +config SPL_BSS_MAX_SIZE + default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000 + +config SPL_STACK_R + default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + +config SPL_STACK_R_ADDR + default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + +config SPL_STACK_R_MALLOC_SIMPLE_LEN + default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000 + +endif endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 1dc92066bbf..c07bdaee4c3 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -23,7 +23,6 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) # meaning "turn it off". obj-y += boot_mode.o obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o -obj-$(CONFIG_MISC_INIT_R) += misc.o endif ifeq ($(CONFIG_TPL_BUILD),) diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 2620530e03f..cd226844b63 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -1,29 +1,41 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2019 Rockchip Electronics Co., Ltd. + * + * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/ + * Rohan Garg <rohan.garg@collabora.com> + * + * Based on puma-rk3399.c: + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ #include <common.h> #include <clk.h> #include <cpu_func.h> +#include <env.h> #include <dm.h> +#include <dm/uclass-internal.h> #include <efi_loader.h> #include <fastboot.h> +#include <hash.h> #include <init.h> #include <log.h> #include <mmc.h> +#include <dm/uclass-internal.h> +#include <misc.h> #include <part.h> #include <ram.h> #include <syscon.h> #include <uuid.h> +#include <u-boot/crc.h> +#include <u-boot/sha256.h> #include <asm/cache.h> #include <asm/io.h> #include <asm/arch-rockchip/boot_mode.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/periph.h> -#include <asm/arch-rockchip/misc.h> #include <power/regulator.h> -#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION) +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION) #define DFU_ALT_BUF_LEN SZ_1K @@ -136,6 +148,10 @@ void set_dfu_alt_info(char *interface, char *devstr) env_set("dfu_alt_info", buf); } +__weak void rockchip_capsule_update_board_setup(void) +{ +} + static void gpt_capsule_update_setup(void) { int p, i, ret; @@ -170,10 +186,6 @@ static void gpt_capsule_update_setup(void) __weak int rk_board_late_init(void) { -#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION) - gpt_capsule_update_setup(); -#endif - return 0; } @@ -181,6 +193,10 @@ int board_late_init(void) { setup_boot_mode(); +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION) + gpt_capsule_update_setup(); +#endif + return rk_board_late_init(); } @@ -205,8 +221,24 @@ void enable_caches(void) } #endif -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#if IS_ENABLED(CONFIG_USB_GADGET) #include <usb.h> + +#if IS_ENABLED(CONFIG_USB_GADGET_DOWNLOAD) +#define ROCKCHIP_G_DNL_UMS_PRODUCT_NUM 0x0010 + +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + if (!strcmp(name, "usb_dnl_ums")) + put_unaligned(ROCKCHIP_G_DNL_UMS_PRODUCT_NUM, &dev->idProduct); + else + put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct); + + return 0; +} +#endif /* CONFIG_USB_GADGET_DOWNLOAD */ + +#if IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG) && !IS_ENABLED(CONFIG_DM_USB_GADGET) #include <linux/usb/otg.h> #include <usb/dwc2_udc.h> @@ -281,6 +313,7 @@ int board_usb_cleanup(int index, enum usb_init_type init) return 0; } #endif /* CONFIG_USB_GADGET_DWC2_OTG */ +#endif /* CONFIG_USB_GADGET */ #if IS_ENABLED(CONFIG_FASTBOOT) int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) @@ -297,6 +330,124 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) #endif #ifdef CONFIG_MISC_INIT_R +int rockchip_setup_macaddr(void) +{ +#if CONFIG_IS_ENABLED(HASH) && CONFIG_IS_ENABLED(SHA256) + int ret; + const char *cpuid = env_get("cpuid#"); + u8 hash[SHA256_SUM_LEN]; + int size = sizeof(hash); + u8 mac_addr[6]; + + /* Only generate a MAC address, if none is set in the environment */ + if (env_get("ethaddr")) + return 0; + + if (!cpuid) { + debug("%s: could not retrieve 'cpuid#'\n", __func__); + return -1; + } + + ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); + if (ret) { + debug("%s: failed to calculate SHA256\n", __func__); + return -1; + } + + /* Copy 6 bytes of the hash to base the MAC address on */ + memcpy(mac_addr, hash, 6); + + /* Make this a valid MAC address and set it */ + mac_addr[0] &= 0xfe; /* clear multicast bit */ + mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ + eth_env_set_enetaddr("ethaddr", mac_addr); + + /* Make a valid MAC address for ethernet1 */ + mac_addr[5] ^= 0x01; + eth_env_set_enetaddr("eth1addr", mac_addr); +#endif + return 0; +} + +int rockchip_cpuid_from_efuse(const u32 cpuid_offset, + const u32 cpuid_length, + u8 *cpuid) +{ +#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) || IS_ENABLED(CONFIG_ROCKCHIP_OTP) + struct udevice *dev; + int ret; + + /* retrieve the device */ +#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_efuse), &dev); +#elif IS_ENABLED(CONFIG_ROCKCHIP_OTP) + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); +#endif + if (ret) { + debug("%s: could not find efuse device\n", __func__); + return -1; + } + + /* read the cpu_id range from the efuses */ + ret = misc_read(dev, cpuid_offset, cpuid, cpuid_length); + if (ret < 0) { + debug("%s: reading cpuid from the efuses failed\n", + __func__); + return -1; + } +#endif + return 0; +} + +int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length) +{ + u8 low[cpuid_length / 2], high[cpuid_length / 2]; + char cpuid_str[cpuid_length * 2 + 1]; + u64 serialno; + char serialno_str[17]; + const char *oldid; + int i; + + memset(cpuid_str, 0, sizeof(cpuid_str)); + for (i = 0; i < cpuid_length; i++) + sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); + + debug("cpuid: %s\n", cpuid_str); + + /* + * Mix the cpuid bytes using the same rules as in + * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c + */ + for (i = 0; i < cpuid_length / 2; i++) { + low[i] = cpuid[1 + (i << 1)]; + high[i] = cpuid[i << 1]; + } + + serialno = crc32_no_comp(0, low, cpuid_length / 2); + serialno |= (u64)crc32_no_comp(serialno, high, cpuid_length / 2) << 32; + snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno); + + oldid = env_get("cpuid#"); + if (oldid && strcmp(oldid, cpuid_str) != 0) + printf("cpuid: value %s present in env does not match hardware %s\n", + oldid, cpuid_str); + + env_set("cpuid#", cpuid_str); + + /* Only generate serial# when none is set yet */ + if (!env_get("serial#")) + env_set("serial#", serialno_str); + + return 0; +} + +__weak int rockchip_early_misc_init_r(void) +{ + return 0; +} + __weak int misc_init_r(void) { const u32 cpuid_offset = CFG_CPUID_OFFSET; @@ -304,6 +455,10 @@ __weak int misc_init_r(void) u8 cpuid[cpuid_length]; int ret; + ret = rockchip_early_misc_init_r(); + if (ret) + return ret; + ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); if (ret) return ret; @@ -349,3 +504,33 @@ __weak int board_rng_seed(struct abuf *buf) return 0; } #endif + +int mmc_get_env_dev(void) +{ + int devnum; + const char *boot_device; + struct udevice *dev; + +#ifdef CONFIG_SYS_MMC_ENV_DEV + devnum = CONFIG_SYS_MMC_ENV_DEV; +#else + devnum = 0; +#endif + + boot_device = ofnode_read_chosen_string("u-boot,spl-boot-device"); + if (!boot_device) { + debug("%s: /chosen/u-boot,spl-boot-device not set\n", __func__); + return devnum; + } + + debug("%s: booted from %s\n", __func__, boot_device); + + if (uclass_find_device_by_ofnode(UCLASS_MMC, ofnode_path(boot_device), &dev)) { + debug("%s: no U-Boot device found for %s\n", __func__, boot_device); + return devnum; + } + + devnum = dev->seq_; + debug("%s: get MMC env from mmc%d\n", __func__, devnum); + return devnum; +} diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c index eb8f65ae4e9..f9be396aa55 100644 --- a/arch/arm/mach-rockchip/boot_mode.c +++ b/arch/arm/mach-rockchip/boot_mode.c @@ -40,6 +40,7 @@ void set_back_to_bootrom_dnl_flag(void) __weak int rockchip_dnl_key_pressed(void) { +#if CONFIG_IS_ENABLED(ADC) unsigned int val; struct udevice *dev; struct uclass *uc; @@ -69,6 +70,9 @@ __weak int rockchip_dnl_key_pressed(void) return true; else return false; +#else + return false; +#endif } void rockchip_dnl_mode_check(void) diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c index dac24910e0c..a62ff53c6a0 100644 --- a/arch/arm/mach-rockchip/cpu-info.c +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -7,7 +7,6 @@ #include <common.h> #include <env.h> #include <init.h> -#include <asm/io.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/cru.h> #include <asm/arch-rockchip/hardware.h> diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c deleted file mode 100644 index 7d03f0c2b67..00000000000 --- a/arch/arm/mach-rockchip/misc.c +++ /dev/null @@ -1,135 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * RK3399: Architecture common definitions - * - * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/ - * Rohan Garg <rohan.garg@collabora.com> - * - * Based on puma-rk3399.c: - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - */ - -#include <common.h> -#include <env.h> -#include <dm.h> -#include <hash.h> -#include <log.h> -#include <dm/uclass-internal.h> -#include <misc.h> -#include <u-boot/crc.h> -#include <u-boot/sha256.h> - -#include <asm/arch-rockchip/misc.h> - -int rockchip_setup_macaddr(void) -{ -#if CONFIG_IS_ENABLED(HASH) && CONFIG_IS_ENABLED(SHA256) - int ret; - const char *cpuid = env_get("cpuid#"); - u8 hash[SHA256_SUM_LEN]; - int size = sizeof(hash); - u8 mac_addr[6]; - - /* Only generate a MAC address, if none is set in the environment */ - if (env_get("ethaddr")) - return 0; - - if (!cpuid) { - debug("%s: could not retrieve 'cpuid#'\n", __func__); - return -1; - } - - ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); - if (ret) { - debug("%s: failed to calculate SHA256\n", __func__); - return -1; - } - - /* Copy 6 bytes of the hash to base the MAC address on */ - memcpy(mac_addr, hash, 6); - - /* Make this a valid MAC address and set it */ - mac_addr[0] &= 0xfe; /* clear multicast bit */ - mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ - eth_env_set_enetaddr("ethaddr", mac_addr); - - /* Make a valid MAC address for ethernet1 */ - mac_addr[5] ^= 0x01; - eth_env_set_enetaddr("eth1addr", mac_addr); -#endif - return 0; -} - -int rockchip_cpuid_from_efuse(const u32 cpuid_offset, - const u32 cpuid_length, - u8 *cpuid) -{ -#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) || IS_ENABLED(CONFIG_ROCKCHIP_OTP) - struct udevice *dev; - int ret; - - /* retrieve the device */ -#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(rockchip_efuse), &dev); -#elif IS_ENABLED(CONFIG_ROCKCHIP_OTP) - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(rockchip_otp), &dev); -#endif - if (ret) { - debug("%s: could not find efuse device\n", __func__); - return -1; - } - - /* read the cpu_id range from the efuses */ - ret = misc_read(dev, cpuid_offset, cpuid, cpuid_length); - if (ret < 0) { - debug("%s: reading cpuid from the efuses failed\n", - __func__); - return -1; - } -#endif - return 0; -} - -int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length) -{ - u8 low[cpuid_length / 2], high[cpuid_length / 2]; - char cpuid_str[cpuid_length * 2 + 1]; - u64 serialno; - char serialno_str[17]; - const char *oldid; - int i; - - memset(cpuid_str, 0, sizeof(cpuid_str)); - for (i = 0; i < 16; i++) - sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); - - debug("cpuid: %s\n", cpuid_str); - - /* - * Mix the cpuid bytes using the same rules as in - * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c - */ - for (i = 0; i < 8; i++) { - low[i] = cpuid[1 + (i << 1)]; - high[i] = cpuid[i << 1]; - } - - serialno = crc32_no_comp(0, low, 8); - serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; - snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno); - - oldid = env_get("cpuid#"); - if (oldid && strcmp(oldid, cpuid_str) != 0) - printf("cpuid: value %s present in env does not match hardware %s\n", - oldid, cpuid_str); - - env_set("cpuid#", cpuid_str); - - /* Only generate serial# when none is set yet */ - if (!env_get("serial#")) - env_set("serial#", serialno_str); - - return 0; -} diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 41893920cb4..23f8f430c4a 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -36,9 +36,9 @@ config TARGET_PX30_CORE 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. config TARGET_RINGNECK_PX30 - bool "Theobroma Systems PX30-µQ7 (Ringneck)" + bool "Theobroma Systems PX30-uQ7 (Ringneck)" help - The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm, + The PX30-uQ7 (Ringneck) SoM is a uQseven-compatible (40mmx70mm, MXM-230 connector) system-on-module from Theobroma Systems[1], featuring the Rockchip PX30. diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index fc7456e680c..b4f655fa4b3 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -9,7 +9,6 @@ #include <init.h> #include <spl.h> #include <asm/armv8/mmu.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/grf_px30.h> #include <asm/arch-rockchip/hardware.h> diff --git a/arch/arm/mach-rockchip/rk3036/rk3036.c b/arch/arm/mach-rockchip/rk3036/rk3036.c index 0a072cf03a8..e8130abdd77 100644 --- a/arch/arm/mach-rockchip/rk3036/rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/rk3036.c @@ -6,7 +6,6 @@ #include <common.h> #include <init.h> #include <asm/global_data.h> -#include <asm/io.h> #include <asm/arch-rockchip/grf_rk3036.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/sdram_rk3036.h> diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index fcae65b2e5a..07cd29a33e6 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -4,7 +4,6 @@ */ #include <common.h> #include <init.h> -#include <asm/io.h> #include <asm/types.h> #include <asm/arch-rockchip/cru_rk3036.h> #include <asm/arch-rockchip/grf_rk3036.h> diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c b/arch/arm/mach-rockchip/rk3066/rk3066.c index 78c7d894f90..9a95ff85041 100644 --- a/arch/arm/mach-rockchip/rk3066/rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/rk3066.c @@ -4,9 +4,9 @@ */ #include <common.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/grf_rk3066.h> +#include <asm/arch-rockchip/hardware.h> #define GRF_BASE 0x20008000 diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c index c807221f33f..ffdcaa49a1e 100644 --- a/arch/arm/mach-rockchip/rk3188/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -10,7 +10,6 @@ #include <log.h> #include <syscon.h> #include <asm/global_data.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/grf_rk3188.h> diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c index a304795fec6..712c0524266 100644 --- a/arch/arm/mach-rockchip/rk322x/rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/rk322x.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ #include <init.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/grf_rk322x.h> #include <asm/arch-rockchip/hardware.h> diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index d9f782e342b..c77c56c1dab 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -11,7 +11,6 @@ #include <malloc.h> #include <asm/armv7.h> #include <asm/global_data.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/cpu_rk3288.h> diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index 194353e4cd9..749e9995d91 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -17,8 +17,11 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3308" -config SYS_MALLOC_F_LEN - default 0x400 +config ROCKCHIP_COMMON_STACK_ADDR + default y + +config TEXT_BASE + default 0x00600000 config SPL_SERIAL default y diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index 6f121bf1304..27a748327e3 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -5,7 +5,6 @@ #include <common.h> #include <init.h> #include <malloc.h> -#include <asm/io.h> #include <asm/arch/grf_rk3308.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/hardware.h> diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index d5cb649ae6b..70770da5fdf 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -21,13 +21,7 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3328" -config SYS_MALLOC_F_LEN - default 0x2000 - -config SPL_LIBCOMMON_SUPPORT - default y - -config SPL_LIBGENERIC_SUPPORT +config ROCKCHIP_COMMON_STACK_ADDR default y config TPL_LDSCRIPT @@ -39,6 +33,9 @@ config TPL_TEXT_BASE config TPL_STACK default 0xff098000 +config TPL_SYS_MALLOC_F_LEN + default 0x800 + source "board/rockchip/evb_rk3328/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index b591d38fe41..ca3fa81e127 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -10,7 +10,6 @@ #include <asm/arch-rockchip/grf_rk3328.h> #include <asm/arch-rockchip/uart.h> #include <asm/armv8/mmu.h> -#include <asm/io.h> #define CRU_BASE 0xFF440000 #define GRF_BASE 0xFF100000 @@ -36,6 +35,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000", + [BROM_BOOTSOURCE_SPINOR] = "/spi@ff190000/flash@0", [BROM_BOOTSOURCE_SD] = "/mmc@ff500000", }; diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index d009b8758e5..651ba109020 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -8,7 +8,6 @@ #include <init.h> #include <syscon.h> #include <asm/armv8/mmu.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/cru_rk3368.h> diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index d01063ac98b..04a84e2f6a0 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -89,6 +89,11 @@ config TARGET_ROCK960_RK3399 * 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only), 1x USB 3.0 type C OTG +config TARGET_ROCKPI4_RK3399 + bool "Radxa ROCK Pi 4 board" + help + Support for ROCK Pi 4 board family by Radxa. + config TARGET_ROCKPRO64_RK3399 bool "Pine64 Rockpro64 board" help @@ -138,8 +143,11 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3399" +config ROCKCHIP_COMMON_STACK_ADDR + default y + config SYS_MALLOC_F_LEN - default 0x4000 + default 0x4000 if !SPL_SHARES_INIT_SP_ADDR config SPL_LIBCOMMON_SUPPORT default y @@ -157,7 +165,7 @@ config TPL_TEXT_BASE default 0xff8c2000 config SPL_STACK_R_ADDR - default 0x04000000 + default 0x04000000 if !SPL_SHARES_INIT_SP_ADDR if BOOTCOUNT_LIMIT @@ -174,6 +182,7 @@ source "board/google/gru/Kconfig" source "board/pine64/pinebook-pro-rk3399/Kconfig" source "board/pine64/pinephone-pro-rk3399/Kconfig" source "board/pine64/rockpro64_rk3399/Kconfig" +source "board/radxa/rockpi4-rk3399/Kconfig" source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" source "board/vamrs/rock960_rk3399/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index a1aa0e3e8b5..7fa1d7c7b7a 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -11,7 +11,6 @@ #include <spl_gpio.h> #include <syscon.h> #include <asm/armv8/mmu.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/cru.h> diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index baa51349f4b..af537d912a6 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -38,8 +38,11 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3568" -config SYS_MALLOC_F_LEN - default 0x20000 +config ROCKCHIP_COMMON_STACK_ADDR + default y + +config TEXT_BASE + default 0x00a00000 source "board/rockchip/evb_rk3568/Kconfig" source "board/anbernic/rgxx3_rk3566/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 69ef19cc85a..b30ea04f737 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -6,7 +6,6 @@ #include <common.h> #include <dm.h> #include <asm/armv8/mmu.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/grf_rk3568.h> #include <asm/arch-rockchip/hardware.h> diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index a2193fbd41f..39049ab35a9 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -6,6 +6,33 @@ config TARGET_EVB_RK3588 help RK3588 EVB is a evaluation board for Rockchp RK3588. +config TARGET_JAGUAR_RK3588 + bool "Theobroma Systems SBC-RK3588-AMR (Jaguar)" + select BOARD_LATE_INIT + help + The SBC-RK3588-AMR is a Single Board Computer designed by + Theobroma Systems for autonomous mobile robots. + + It provides the following features: + * up to 32GB LDDR4 + * up to 128GB on-module eMMC (with 8-bit 1.8V interface) + * SD card + * Gigabit Ethernet + * 1x USB-A 2.0 host + * PCIe M.2 2230 Key M (Gen 2 1-lane) for WiFi+BT + * PCIe M.2 2280 Key M (Gen 3 4-lane) for NVMe + * CAN + * RS485 UART + * 2x USB Type-C 3.1 host/device + * HDMI output + * 2x camera connectors (MIPI-CSI 2-lane + I2C/SPI for IMUs + GPIOs) + * EEPROM + * Secure Element + * ATtiny companion controller implementing: + - low-power RTC functionality (ISL1208 emulation) + - fan controller (AMC6821 emulation) + * 80-pin Mezzanine connector + config TARGET_NANOPCT6_RK3588 bool "FriendlyElec NanoPC-T6 RK3588 board" select BOARD_LATE_INIT @@ -39,7 +66,7 @@ config TARGET_NANOPCT6_RK3588 HDMI2.0, and HDMI1.4 2x 4-lane MIPI-DSI, compatible with MIPI DPHY 2.0 or CPHY 1.1 USB-A: USB 3.0, Type A - USB-C: Full function USB Type‑C port, DP display up to 4Kp60, USB 3.0 + USB-C: Full function USB Type-C port, DP display up to 4Kp60, USB 3.0 40-pin 2.54mm header connector: up to 2x SPIs, 6x UARTs, 1x I2Cs, 8x PWMs, 2x I2Ss, 28x GPIOs Debug UART: 3 Pin 2.54mm header, 3V level, 1500000bps @@ -90,7 +117,7 @@ config TARGET_ROCK5A_RK3588 Mali G610MC4 GPU MIPI CSI 2 multiple lanes connector 4-lane MIPI DSI connector - Audio – 3.5mm earphone jack + Audio - 3.5mm earphone jack eMMC module connector uSD slot (up to 128GB) 2x USB 2.0, 2x USB 3.0 @@ -155,6 +182,30 @@ config TARGET_TURINGRK1_RK3588 Gigabit Ethernet Size: 69.6mm x 45mm (260-pin SO-DIMM connector) +config TARGET_TOYBRICK_RK3588 + bool "Toybrick TB-RK3588X board" + select BOARD_LATE_INIT + help + Rockchip Toybrick TB-RK3588X is a Rockchip RK3588 based development board. + TB-RK3588X adopts core board and mainboard design. The core board is connected + with the mainboard through the MXM314Pin standard interface, which can form + a complete industry development board. + + Specifications: + + Rockchip RK3588 SoC + 4x ARM Cortex-A76, 4x ARM Cortex-A55 + 8/16GB Memory LPDDR4x + Mali G610MC4 GPU + 2x MIPI-CSI0 Connector + 1x 2Lanes PCIe3.0 Connector + 1x SATA3.0 Connector + 32GB eMMC Module + 2x USB2.0, 2x USB3.0 + 1x HDMI Output, 1x HDMI Input + 2x Ethernet Port + + config ROCKCHIP_BOOT_MODE_REG default 0xfd588080 @@ -164,15 +215,20 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3588" -config SYS_MALLOC_F_LEN - default 0x80000 - -source board/edgeble/neural-compute-module-6/Kconfig -source board/friendlyelec/nanopc-t6-rk3588/Kconfig -source board/pine64/quartzpro64-rk3588/Kconfig -source board/turing/turing-rk1-rk3588/Kconfig -source board/rockchip/evb_rk3588/Kconfig -source board/radxa/rock5a-rk3588s/Kconfig -source board/radxa/rock5b-rk3588/Kconfig +config ROCKCHIP_COMMON_STACK_ADDR + default y + +config TEXT_BASE + default 0x00a00000 + +source "board/edgeble/neural-compute-module-6/Kconfig" +source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" +source "board/pine64/quartzpro64-rk3588/Kconfig" +source "board/turing/turing-rk1-rk3588/Kconfig" +source "board/radxa/rock5a-rk3588s/Kconfig" +source "board/radxa/rock5b-rk3588/Kconfig" +source "board/rockchip/evb_rk3588/Kconfig" +source "board/rockchip/toybrick_rk3588/Kconfig" +source "board/theobroma-systems/jaguar_rk3588/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index 38e95a6e2b2..eb65dafe3a2 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -7,8 +7,8 @@ #include <common.h> #include <spl.h> #include <asm/armv8/mmu.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/grf_rk3588.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/ioc_rk3588.h> @@ -25,16 +25,14 @@ #define FW_SYSM_MST26_REG 0xa8 #define FW_SYSM_MST27_REG 0xac -#define PMU1_IOC_BASE 0xfd5f0000 -#define PMU2_IOC_BASE 0xfd5f4000 - -#define BUS_IOC_BASE 0xfd5f8000 #define BUS_IOC_GPIO2A_IOMUX_SEL_L 0x40 #define BUS_IOC_GPIO2B_IOMUX_SEL_L 0x48 #define BUS_IOC_GPIO2D_IOMUX_SEL_L 0x58 #define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c #define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60 +#define SYS_GRF_FORCE_JTAG BIT(14) + /** * Boot-device identifiers used by the BROM on RK3588 when device is booted * from SPI flash. IOMUX used for SPI flash affect the value used by the BROM @@ -134,6 +132,9 @@ void rockchip_stimer_init(void) int arch_cpu_init(void) { #ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG + static struct rk3588_sysgrf * const sys_grf = (void *)SYS_GRF_BASE; +#endif int secure_reg; /* Set the SDMMC eMMC crypto_ns FSPI access secure area */ @@ -168,6 +169,11 @@ int arch_cpu_init(void) secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG); secure_reg &= 0xffff0000; writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG); + +#ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG + /* Disable JTAG exposed on SDMMC */ + rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG); +#endif #endif return 0; diff --git a/arch/arm/mach-rockchip/rv1108/Kconfig b/arch/arm/mach-rockchip/rv1108/Kconfig index a12216dccf6..28ed0b24581 100644 --- a/arch/arm/mach-rockchip/rv1108/Kconfig +++ b/arch/arm/mach-rockchip/rv1108/Kconfig @@ -36,7 +36,7 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x400 -source board/rockchip/evb_rv1108/Kconfig -source board/elgin/elgin_rv1108/Kconfig +source "board/rockchip/evb_rv1108/Kconfig" +source "board/elgin/elgin_rv1108/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig b/arch/arm/mach-rockchip/rv1126/Kconfig index 55b11121203..330b7df2312 100644 --- a/arch/arm/mach-rockchip/rv1126/Kconfig +++ b/arch/arm/mach-rockchip/rv1126/Kconfig @@ -6,8 +6,8 @@ config TARGET_RV1126_NEU2 Neu2: Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module based on Rockchip RV1126 from Edgeble AI. - Neu2 powered with Consumer grade (0 to +80 °C) RV1126 SoC. - Neu2k powered with Industrial grade (-40 °C to +85 °C) RV1126K SoC. + Neu2 powered with Consumer grade (0 to +80 deg C) RV1126 SoC. + Neu2k powered with Industrial grade (-40 C to +85 deg C) RV1126K SoC. Neu2-IO: Neural Compute Module 2(Neu2) IO board is an industrial form factor @@ -64,7 +64,7 @@ config SYS_MALLOC_F_LEN config TEXT_BASE default 0x600000 -source board/edgeble/neural-compute-module-2/Kconfig -source board/itead/sonoff-ihost/Kconfig +source "board/edgeble/neural-compute-module-2/Kconfig" +source "board/itead/sonoff-ihost/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c b/arch/arm/mach-rockchip/rv1126/rv1126.c index b9b898756f7..8589c46f10a 100644 --- a/arch/arm/mach-rockchip/rv1126/rv1126.c +++ b/arch/arm/mach-rockchip/rv1126/rv1126.c @@ -5,7 +5,6 @@ */ #include <common.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/grf_rv1126.h> diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 2c39a215c10..79c856d2a0a 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -65,9 +65,6 @@ static int spl_node_to_boot_device(int node) default: return -ENOSYS; } - } else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, - &parent)) { - return BOOT_DEVICE_SPI; } /* diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index 87280e2ba7c..1586a093fc3 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -3,7 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include <common.h> +#include <cpu_func.h> #include <debug_uart.h> #include <dm.h> #include <hang.h> @@ -136,6 +136,20 @@ void board_init_f(ulong dummy) } gd->ram_top = gd->ram_base + get_effective_memsize(); gd->ram_top = board_get_usable_ram_top(gd->ram_size); + + if (IS_ENABLED(CONFIG_ARM64) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { + gd->relocaddr = gd->ram_top; + arch_reserve_mmu(); + enable_caches(); + } #endif preloader_console_init(); } + +void spl_board_prepare_for_boot(void) +{ + if (!IS_ENABLED(CONFIG_ARM64) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + return; + + cleanup_before_linux(); +} diff --git a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds index 74618eba591..ad32654085b 100644 --- a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds +++ b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds @@ -22,9 +22,9 @@ SECTIONS { . = 0x00000000; + __image_copy_start = ADDR(.text); .text : { . = ALIGN(8); - *(.__image_copy_start) CPUDIR/start.o (.text*) *(.text*) } @@ -44,10 +44,8 @@ SECTIONS KEEP(*(SORT(__u_boot_list*))); } - .image_copy_end : { - . = ALIGN(8); - *(.__image_copy_end) - } + . = ALIGN(8); + __image_copy_end = .; .end : { . = ALIGN(8); @@ -56,18 +54,11 @@ SECTIONS _image_binary_end = .; - .bss_start (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.__bss_start)); - } - - .bss (NOLOAD) : { + .bss ALIGN(8) : { + __bss_start = .; *(.bss*) - . = ALIGN(8); - } - - .bss_end (NOLOAD) : { - KEEP(*(.__bss_end)); + . = ALIGN(8); + __bss_end = .; } /DISCARD/ : { *(.dynsym) } diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index ad667108191..96e44e2c549 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -3,6 +3,9 @@ if ARCH_SNAPDRAGON config SYS_SOC default "snapdragon" +config SYS_VENDOR + default "qualcomm" + config SYS_MALLOC_F_LEN default 0x2000 @@ -12,90 +15,24 @@ config SPL_SYS_MALLOC_F config SPL_SYS_MALLOC_F_LEN default 0x2000 -config SDM845 - bool "Qualcomm Snapdragon 845 SoC" - select LINUX_KERNEL_IMAGE_HEADER - imply CLK_QCOM_SDM845 - imply PINCTRL_QCOM_SDM845 - imply BUTTON_QCOM_PMIC - config LNX_KRNL_IMG_TEXT_OFFSET_BASE default 0x80000000 -choice - prompt "Snapdragon board select" - -config TARGET_DRAGONBOARD410C - bool "96Boards Dragonboard 410C" - select BOARD_LATE_INIT - select ENABLE_ARM_SOC_BOOT0_HOOK - imply CLK_QCOM_APQ8016 - imply PINCTRL_QCOM_APQ8016 - imply BUTTON_QCOM_PMIC - help - Support for 96Boards Dragonboard 410C. This board complies with - 96Board Open Platform Specifications. Features: - - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) - - 1GiB RAM - - 8GiB eMMC, uSD slot - - WiFi, Bluetooth and GPS module - - 2x Host, 1x Device USB port - - HDMI - - 20-pin low speed and 40-pin high speed expanders, 4 LED, 3 buttons - -config TARGET_DRAGONBOARD820C - bool "96Boards Dragonboard 820C" - imply CLK_QCOM_APQ8096 - imply PINCTRL_QCOM_APQ8096 - imply BUTTON_QCOM_PMIC - help - Support for 96Boards Dragonboard 820C. This board complies with - 96Board Open Platform Specifications. Features: - - Qualcomm Snapdragon 820C SoC - APQ8096 (4xKyro CPU) - - 3GiB RAM - - 32GiB UFS drive - -config TARGET_DRAGONBOARD845C - bool "96Boards Dragonboard 845C" - help - Support for 96Boards Dragonboard 845C aka Robotics RB3 Development - Platform. This board complies with 96Boards Open Platform - Specifications. Features: - - Qualcomm Snapdragon SDA845 SoC - - 4GiB RAM - - 64GiB UFS drive - select MISC_INIT_R - select SDM845 - -config TARGET_STARQLTECHN - bool "Samsung S9 SM-G9600(starqltechn)" +config SYS_BOARD + string "Qualcomm custom board" help - Support for Samsung S9 SM-G9600(starqltechn) board. - Features: - - Qualcomm Snapdragon SDM845 SoC - - 4GiB RAM - - 64GiB UFS drive - select MISC_INIT_R - select SDM845 - -config TARGET_QCS404EVB - bool "Qualcomm Technologies, Inc. QCS404 EVB" - select LINUX_KERNEL_IMAGE_HEADER - imply CLK_QCOM_QCS404 - imply PINCTRL_QCOM_QCS404 + The Dragonboard 410c and 820c have additional board init + code that isn't shared with other Qualcomm boards. + Based on this option board/qualcomm/<CONFIG_SYS_BOARD> will + be used. + +config SYS_CONFIG_NAME + string "Board configuration name" + default SYS_BOARD if SYS_BOARD != "" + default "qcom" help - Support for Qualcomm Technologies, Inc. QCS404 evaluation board. - Features: - - Qualcomm Snapdragon QCS404 SoC - - 1GiB RAM - - 8GiB eMMC, uSD slot - -endchoice - -source "board/qualcomm/dragonboard410c/Kconfig" -source "board/qualcomm/dragonboard820c/Kconfig" -source "board/qualcomm/dragonboard845c/Kconfig" -source "board/samsung/starqltechn/Kconfig" -source "board/qualcomm/qcs404-evb/Kconfig" + This option contains information about board configuration name. + Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header + will be used for board configuration. endif diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 3a3a297c176..7a4495c8108 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -2,10 +2,5 @@ # # (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> -obj-$(CONFIG_SDM845) += sysmap-sdm845.o -obj-$(CONFIG_SDM845) += init_sdm845.o -obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o -obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o -obj-y += misc.o -obj-y += dram.o -obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o +obj-y += board.o +obj-$(CONFIG_OF_LIVE) += of_fixup.o diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c new file mode 100644 index 00000000000..3d5994c8788 --- /dev/null +++ b/arch/arm/mach-snapdragon/board.c @@ -0,0 +1,476 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Common initialisation for Qualcomm Snapdragon boards. + * + * Copyright (c) 2024 Linaro Ltd. + * Author: Caleb Connolly <caleb.connolly@linaro.org> + */ + +#include "time.h" +#include <asm/armv8/mmu.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/psci.h> +#include <asm/system.h> +#include <dm/device.h> +#include <dm/pinctrl.h> +#include <dm/uclass-internal.h> +#include <dm/read.h> +#include <power/regulator.h> +#include <env.h> +#include <init.h> +#include <linux/arm-smccc.h> +#include <linux/bug.h> +#include <linux/psci.h> +#include <linux/sizes.h> +#include <lmb.h> +#include <malloc.h> +#include <fdt_support.h> +#include <usb.h> +#include <sort.h> + +#include "qcom-priv.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } }; + +struct mm_region *mem_map = rbx_mem_map; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +static int ddr_bank_cmp(const void *v1, const void *v2) +{ + const struct { + phys_addr_t start; + phys_size_t size; + } *res1 = v1, *res2 = v2; + + if (!res1->size) + return 1; + if (!res2->size) + return -1; + + return (res1->start >> 24) - (res2->start >> 24); +} + +int dram_init_banksize(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret < 0) + return ret; + + if (CONFIG_NR_DRAM_BANKS < 2) + return 0; + + /* Sort our RAM banks -_- */ + qsort(gd->bd->bi_dram, CONFIG_NR_DRAM_BANKS, sizeof(gd->bd->bi_dram[0]), ddr_bank_cmp); + + return 0; +} + +static void show_psci_version(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res); + + debug("PSCI: v%ld.%ld\n", + PSCI_VERSION_MAJOR(res.a0), + PSCI_VERSION_MINOR(res.a0)); +} + +void *board_fdt_blob_setup(int *err) +{ + phys_addr_t fdt; + /* Return DTB pointer passed by ABL */ + *err = 0; + fdt = get_prev_bl_fdt_addr(); + + /* + * If we bail then the board will simply not boot, instead let's + * try and use the FDT built into U-Boot if there is one... + * This avoids having a hard dependency on the previous stage bootloader + */ + + if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K) || + fdt_check_header((void *)fdt))) { + debug("%s: Using built in FDT, bootloader gave us %#llx\n", __func__, fdt); + return (void *)gd->fdt_blob; + } + + return (void *)fdt; +} + +void reset_cpu(void) +{ + psci_system_reset(); +} + +/* + * Some Qualcomm boards require GPIO configuration when switching USB modes. + * Support setting this configuration via pinctrl state. + */ +int board_usb_init(int index, enum usb_init_type init) +{ + struct udevice *usb; + int ret = 0; + + /* USB device */ + ret = uclass_find_device_by_seq(UCLASS_USB, index, &usb); + if (ret) { + printf("Cannot find USB device\n"); + return ret; + } + + ret = dev_read_stringlist_search(usb, "pinctrl-names", + "device"); + /* No "device" pinctrl state, so just bail */ + if (ret < 0) + return 0; + + /* Select "default" or "device" pinctrl */ + switch (init) { + case USB_INIT_HOST: + pinctrl_select_state(usb, "default"); + break; + case USB_INIT_DEVICE: + pinctrl_select_state(usb, "device"); + break; + default: + debug("Unknown usb_init_type %d\n", init); + break; + } + + return 0; +} + +/* + * Some boards still need board specific init code, they can implement that by + * overriding this function. + * + * FIXME: get rid of board specific init code + */ +void __weak qcom_board_init(void) +{ +} + +int board_init(void) +{ + regulators_enable_boot_on(false); + show_psci_version(); + qcom_of_fixup_nodes(); + qcom_board_init(); + return 0; +} + +/* Sets up the "board", and "soc" environment variables as well as constructing the devicetree + * path, with a few quirks to handle non-standard dtb filenames. This is not meant to be a + * comprehensive solution to automatically picking the DTB, but aims to be correct for the + * majority case. For most devices it should be possible to make this algorithm work by + * adjusting the root compatible property in the U-Boot DTS. Handling devices with multiple + * variants that are all supported by a single U-Boot image will require implementing device- + * specific detection. + */ +static void configure_env(void) +{ + const char *first_compat, *last_compat; + char *tmp; + char buf[32] = { 0 }; + /* + * Most DTB filenames follow the scheme: qcom/<soc>-[vendor]-<board>.dtb + * The vendor is skipped when it's a Qualcomm reference board, or the + * db845c. + */ + char dt_path[64] = { 0 }; + int compat_count, ret; + ofnode root; + + root = ofnode_root(); + /* This is almost always 2, but be explicit that we want the first and last compatibles + * not the first and second. + */ + compat_count = ofnode_read_string_count(root, "compatible"); + if (compat_count < 2) { + log_warning("%s: only one root compatible bailing!\n", __func__); + return; + } + + /* The most specific device compatible (e.g. "thundercomm,db845c") */ + ret = ofnode_read_string_index(root, "compatible", 0, &first_compat); + if (ret < 0) { + log_warning("Can't read first compatible\n"); + return; + } + + /* The last compatible is always the SoC compatible */ + ret = ofnode_read_string_index(root, "compatible", compat_count - 1, &last_compat); + if (ret < 0) { + log_warning("Can't read second compatible\n"); + return; + } + + /* Copy the second compat (e.g. "qcom,sdm845") into buf */ + strlcpy(buf, last_compat, sizeof(buf) - 1); + tmp = buf; + + /* strsep() is destructive, it replaces the comma with a \0 */ + if (!strsep(&tmp, ",")) { + log_warning("second compatible '%s' has no ','\n", buf); + return; + } + + /* tmp now points to just the "sdm845" part of the string */ + env_set("soc", tmp); + + /* Now figure out the "board" part from the first compatible */ + memset(buf, 0, sizeof(buf)); + strlcpy(buf, first_compat, sizeof(buf) - 1); + tmp = buf; + + /* The Qualcomm reference boards (RBx, HDK, etc) */ + if (!strncmp("qcom", buf, strlen("qcom"))) { + /* + * They all have the first compatible as "qcom,<soc>-<board>" + * (e.g. "qcom,qrb5165-rb5"). We extract just the part after + * the dash. + */ + if (!strsep(&tmp, "-")) { + log_warning("compatible '%s' has no '-'\n", buf); + return; + } + /* tmp is now "rb5" */ + env_set("board", tmp); + } else { + if (!strsep(&tmp, ",")) { + log_warning("compatible '%s' has no ','\n", buf); + return; + } + /* for thundercomm we just want the bit after the comma (e.g. "db845c"), + * for all other boards we replace the comma with a '-' and take both + * (e.g. "oneplus-enchilada") + */ + if (!strncmp("thundercomm", buf, strlen("thundercomm"))) { + env_set("board", tmp); + } else { + *(tmp - 1) = '-'; + env_set("board", buf); + } + } + + /* Now build the full path name */ + snprintf(dt_path, sizeof(dt_path), "qcom/%s-%s.dtb", + env_get("soc"), env_get("board")); + env_set("fdtfile", dt_path); +} + +void __weak qcom_late_init(void) +{ +} + +#define KERNEL_COMP_SIZE SZ_64M + +#define addr_alloc(lmb, size) lmb_alloc(lmb, size, SZ_2M) + +/* Stolen from arch/arm/mach-apple/board.c */ +int board_late_init(void) +{ + struct lmb lmb; + u32 status = 0; + + lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); + + /* We need to be fairly conservative here as we support boards with just 1G of TOTAL RAM */ + status |= env_set_hex("kernel_addr_r", addr_alloc(&lmb, SZ_128M)); + status |= env_set_hex("ramdisk_addr_r", addr_alloc(&lmb, SZ_128M)); + status |= env_set_hex("kernel_comp_addr_r", addr_alloc(&lmb, KERNEL_COMP_SIZE)); + status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE); + status |= env_set_hex("scriptaddr", addr_alloc(&lmb, SZ_4M)); + status |= env_set_hex("pxefile_addr_r", addr_alloc(&lmb, SZ_4M)); + status |= env_set_hex("fdt_addr_r", addr_alloc(&lmb, SZ_2M)); + + if (status) + log_warning("%s: Failed to set run time variables\n", __func__); + + configure_env(); + qcom_late_init(); + + return 0; +} + +static void build_mem_map(void) +{ + int i, j; + + /* + * Ensure the peripheral block is sized to correctly cover the address range + * up to the first memory bank. + * Don't map the first page to ensure that we actually trigger an abort on a + * null pointer access rather than just hanging. + * FIXME: we should probably split this into more precise regions + */ + mem_map[0].phys = 0x1000; + mem_map[0].virt = mem_map[0].phys; + mem_map[0].size = gd->bd->bi_dram[0].start - mem_map[0].phys; + mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN; + + for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->bd->bi_dram[j].size; i++, j++) { + mem_map[i].phys = gd->bd->bi_dram[j].start; + mem_map[i].virt = mem_map[i].phys; + mem_map[i].size = gd->bd->bi_dram[j].size; + mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \ + PTE_BLOCK_INNER_SHARE; + } + + mem_map[i].phys = UINT64_MAX; + mem_map[i].size = 0; + +#ifdef DEBUG + debug("Configured memory map:\n"); + for (i = 0; mem_map[i].size; i++) + debug(" 0x%016llx - 0x%016llx: entry %d\n", + mem_map[i].phys, mem_map[i].phys + mem_map[i].size, i); +#endif +} + +u64 get_page_table_size(void) +{ + return SZ_64K; +} + +static int fdt_cmp_res(const void *v1, const void *v2) +{ + const struct fdt_resource *res1 = v1, *res2 = v2; + + return res1->start - res2->start; +} + +#define N_RESERVED_REGIONS 32 + +/* Mark all no-map regions as PTE_TYPE_FAULT to prevent speculative access. + * On some platforms this is enough to trigger a security violation and trap + * to EL3. + */ +static void carve_out_reserved_memory(void) +{ + static struct fdt_resource res[N_RESERVED_REGIONS] = { 0 }; + int parent, rmem, count, i = 0; + phys_addr_t start; + size_t size; + + /* Some reserved nodes must be carved out, as the cache-prefetcher may otherwise + * attempt to access them, causing a security exception. + */ + parent = fdt_path_offset(gd->fdt_blob, "/reserved-memory"); + if (parent <= 0) { + log_err("No reserved memory regions found\n"); + return; + } + + /* Collect the reserved memory regions */ + fdt_for_each_subnode(rmem, gd->fdt_blob, parent) { + const fdt32_t *ptr; + int len; + if (!fdt_getprop(gd->fdt_blob, rmem, "no-map", NULL)) + continue; + + if (i == N_RESERVED_REGIONS) { + log_err("Too many reserved regions!\n"); + break; + } + + /* Read the address and size out from the reg property. Doing this "properly" with + * fdt_get_resource() takes ~70ms on SDM845, but open-coding the happy path here + * takes <1ms... Oh the woes of no dcache. + */ + ptr = fdt_getprop(gd->fdt_blob, rmem, "reg", &len); + if (ptr) { + /* Qualcomm devices use #address/size-cells = <2> but all reserved regions are within + * the 32-bit address space. So we can cheat here for speed. + */ + res[i].start = fdt32_to_cpu(ptr[1]); + res[i].end = res[i].start + fdt32_to_cpu(ptr[3]); + i++; + } + } + + /* Sort the reserved memory regions by address */ + count = i; + qsort(res, count, sizeof(struct fdt_resource), fdt_cmp_res); + + /* Now set the right attributes for them. Often a lot of the regions are tightly packed together + * so we can optimise the number of calls to mmu_change_region_attr() by combining adjacent + * regions. + */ + start = ALIGN_DOWN(res[0].start, SZ_2M); + size = ALIGN(res[0].end - start, SZ_2M); + for (i = 1; i <= count; i++) { + /* We ideally want to 2M align everything for more efficient pagetables, but we must avoid + * overwriting reserved memory regions which shouldn't be mapped as FAULT (like those with + * compatible properties). + * If within 2M of the previous region, bump the size to include this region. Otherwise + * start a new region. + */ + if (i == count || start + size < res[i].start - SZ_2M) { + debug(" 0x%016llx - 0x%016llx: reserved\n", + start, start + size); + mmu_change_region_attr(start, size, PTE_TYPE_FAULT); + /* If this is the final region then quit here before we index + * out of bounds... + */ + if (i == count) + break; + start = ALIGN_DOWN(res[i].start, SZ_2M); + size = ALIGN(res[i].end - start, SZ_2M); + } else { + /* Bump size if this region is immediately after the previous one */ + size = ALIGN(res[i].end - start, SZ_2M); + } + } +} + +/* This function open-codes setup_all_pgtables() so that we can + * insert additional mappings *before* turning on the MMU. + */ +void enable_caches(void) +{ + u64 tlb_addr = gd->arch.tlb_addr; + u64 tlb_size = gd->arch.tlb_size; + u64 pt_size; + ulong carveout_start; + + gd->arch.tlb_fillptr = tlb_addr; + + build_mem_map(); + + icache_enable(); + + /* Create normal system page tables */ + setup_pgtables(); + + pt_size = (uintptr_t)gd->arch.tlb_fillptr - + (uintptr_t)gd->arch.tlb_addr; + debug("Primary pagetable size: %lluKiB\n", pt_size / 1024); + + /* Create emergency page tables */ + gd->arch.tlb_size -= pt_size; + gd->arch.tlb_addr = gd->arch.tlb_fillptr; + setup_pgtables(); + gd->arch.tlb_emerg = gd->arch.tlb_addr; + gd->arch.tlb_addr = tlb_addr; + gd->arch.tlb_size = tlb_size; + + carveout_start = get_timer(0); + /* Takes ~20-50ms on SDM845 */ + carve_out_reserved_memory(); + debug("carveout time: %lums\n", get_timer(carveout_start)); + + dcache_enable(); +} diff --git a/arch/arm/mach-snapdragon/dram.c b/arch/arm/mach-snapdragon/dram.c deleted file mode 100644 index 499dfdf0da6..00000000000 --- a/arch/arm/mach-snapdragon/dram.c +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Onboard memory detection for Snapdragon boards - * - * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com> - * - */ - -#include <common.h> -#include <dm.h> -#include <log.h> -#include <part.h> -#include <smem.h> -#include <fdt_support.h> -#include <asm/arch/dram.h> - -#define SMEM_USABLE_RAM_PARTITION_TABLE 402 -#define RAM_PART_NAME_LENGTH 16 -#define RAM_NUM_PART_ENTRIES 32 -#define CATEGORY_SDRAM 0x0E -#define TYPE_SYSMEM 0x01 - -struct smem_ram_ptable_hdr { - u32 magic[2]; - u32 version; - u32 reserved; - u32 len; -} __attribute__ ((__packed__)); - -struct smem_ram_ptn { - char name[RAM_PART_NAME_LENGTH]; - u64 start; - u64 size; - u32 attr; - u32 category; - u32 domain; - u32 type; - u32 num_partitions; - u32 reserved[3]; -} __attribute__ ((__packed__)); - -struct smem_ram_ptable { - struct smem_ram_ptable_hdr hdr; - u32 reserved; /* Added for 8 bytes alignment of header */ - struct smem_ram_ptn parts[RAM_NUM_PART_ENTRIES]; -} __attribute__ ((__packed__)); - -#ifndef MEMORY_BANKS_MAX -#define MEMORY_BANKS_MAX 4 -#endif - -int msm_fixup_memory(void *blob) -{ - u64 bank_start[MEMORY_BANKS_MAX]; - u64 bank_size[MEMORY_BANKS_MAX]; - size_t size; - int i; - int count = 0; - struct udevice *smem; - int ret; - struct smem_ram_ptable *ram_ptable; - struct smem_ram_ptn *p; - - ret = uclass_get_device_by_name(UCLASS_SMEM, "smem", &smem); - if (ret < 0) { - printf("Failed to find SMEM node. Check device tree\n"); - return 0; - } - - ram_ptable = smem_get(smem, -1, SMEM_USABLE_RAM_PARTITION_TABLE, &size); - - if (!ram_ptable) { - printf("Failed to find SMEM partition.\n"); - return -ENODEV; - } - - /* Check validy of RAM */ - for (i = 0; i < RAM_NUM_PART_ENTRIES; i++) { - p = &ram_ptable->parts[i]; - if (p->category == CATEGORY_SDRAM && p->type == TYPE_SYSMEM) { - bank_start[count] = p->start; - bank_size[count] = p->size; - debug("Detected memory bank %u: start: 0x%llx size: 0x%llx\n", - count, p->start, p->size); - count++; - } - } - - if (!count) { - printf("Failed to detect any memory bank\n"); - return -ENODEV; - } - - ret = fdt_fixup_memory_banks(blob, bank_start, bank_size, count); - if (ret) - return ret; - - return 0; -} diff --git a/arch/arm/mach-snapdragon/include/mach/dram.h b/arch/arm/mach-snapdragon/include/mach/dram.h deleted file mode 100644 index 0a9eedda414..00000000000 --- a/arch/arm/mach-snapdragon/include/mach/dram.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Snapdragon DRAM - * Copyright (C) 2018 Ramon Fried <ramon.fried@gmail.com> - */ - -#ifndef DRAM_H -#define DRAM_H - -int msm_fixup_memory(void *blob); - -#endif diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h b/arch/arm/mach-snapdragon/include/mach/gpio.h index 8dac62f870b..53c6ae06490 100644 --- a/arch/arm/mach-snapdragon/include/mach/gpio.h +++ b/arch/arm/mach-snapdragon/include/mach/gpio.h @@ -13,6 +13,8 @@ struct msm_pin_data { int pin_count; const unsigned int *pin_offsets; + /* Index of first special pin, these are ignored for now */ + unsigned int special_pins_start; }; static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector) @@ -25,4 +27,9 @@ static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selecto return out; } +static inline bool qcom_is_special_pin(const struct msm_pin_data *pindata, unsigned int pin) +{ + return pindata->special_pins_start && pin >= pindata->special_pins_start; +} + #endif /* _QCOM_GPIO_H_ */ diff --git a/arch/arm/mach-snapdragon/include/mach/misc.h b/arch/arm/mach-snapdragon/include/mach/misc.h deleted file mode 100644 index c60e3e47247..00000000000 --- a/arch/arm/mach-snapdragon/include/mach/misc.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Snapdragon DRAM - * Copyright (C) 2018 Ramon Fried <ramon.fried@gmail.com> - */ - -#ifndef MISC_H -#define MISC_H - -u32 msm_board_serial(void); -void msm_generate_mac_addr(u8 *mac); - -#endif diff --git a/arch/arm/mach-snapdragon/init_sdm845.c b/arch/arm/mach-snapdragon/init_sdm845.c deleted file mode 100644 index 067acc9a6f4..00000000000 --- a/arch/arm/mach-snapdragon/init_sdm845.c +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Common init part for boards based on SDM845 - * - * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> - */ - -#include <button.h> -#include <init.h> -#include <env.h> -#include <common.h> -#include <asm/system.h> -#include <asm/gpio.h> -#include <dm.h> - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - return fdtdec_setup_mem_size_base(); -} - -void reset_cpu(void) -{ - psci_system_reset(); -} - -__weak int board_init(void) -{ - return 0; -} - -/* Check for vol- and power buttons */ -__weak int misc_init_r(void) -{ - struct udevice *btn; - int ret; - enum button_state_t state; - - ret = button_get_by_label("pwrkey", &btn); - if (ret < 0) { - printf("Couldn't find power button!\n"); - return ret; - } - - state = button_get_state(btn); - if (state == BUTTON_ON) { - env_set("key_power", "1"); - printf("Power button pressed\n"); - } else { - env_set("key_power", "0"); - } - - /* - * search for kaslr address, set by primary bootloader by searching first - * 0x100 relocated bytes at u-boot's initial load address range - */ - uintptr_t start = gd->ram_base; - uintptr_t end = start + 0x800000; - u8 *addr = (u8 *)start; - phys_addr_t *relocaddr = (phys_addr_t *)gd->relocaddr; - u32 block_size = 0x1000; - - while (memcmp(addr, relocaddr, 0x100) && (uintptr_t)addr < end) - addr += block_size; - - if ((uintptr_t)addr >= end) - printf("KASLR not found in range 0x%lx - 0x%lx", start, end); - else - env_set_addr("KASLR", addr); - - return 0; -} diff --git a/arch/arm/mach-snapdragon/misc.c b/arch/arm/mach-snapdragon/misc.c deleted file mode 100644 index 7d452f4529b..00000000000 --- a/arch/arm/mach-snapdragon/misc.c +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Miscellaneous Snapdragon functionality - * - * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com> - * - */ - -#include <common.h> -#include <mmc.h> -#include <asm/arch/misc.h> -#include <asm/unaligned.h> - -/* UNSTUFF_BITS macro taken from Linux Kernel: drivers/mmc/core/sd.c */ -#define UNSTUFF_BITS(resp, start, size) \ - ({ \ - const int __size = size; \ - const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \ - const int __off = 3 - ((start) / 32); \ - const int __shft = (start) & 31; \ - u32 __res; \ - \ - __res = resp[__off] >> __shft; \ - if (__size + __shft > 32) \ - __res |= resp[__off - 1] << ((32 - __shft) % 32); \ - __res & __mask; \ - }) - -u32 msm_board_serial(void) -{ - struct mmc *mmc_dev; - - mmc_dev = find_mmc_device(0); - if (!mmc_dev) - return 0; - - if (mmc_init(mmc_dev)) - return 0; - - return UNSTUFF_BITS(mmc_dev->cid, 16, 32); -} - -void msm_generate_mac_addr(u8 *mac) -{ - /* use locally adminstrated pool */ - mac[0] = 0x02; - mac[1] = 0x00; - - /* - * Put the 32-bit serial number in the last 32-bit of the MAC address. - * Use big endian order so it is consistent with the serial number - * written as a hexadecimal string, e.g. 0x1234abcd -> 02:00:12:34:ab:cd - */ - put_unaligned_be32(msm_board_serial(), &mac[2]); -} diff --git a/arch/arm/mach-snapdragon/of_fixup.c b/arch/arm/mach-snapdragon/of_fixup.c new file mode 100644 index 00000000000..3f7ac227bd0 --- /dev/null +++ b/arch/arm/mach-snapdragon/of_fixup.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * OF_LIVE devicetree fixup. + * + * This file implements runtime fixups for Qualcomm DT to improve + * compatibility with U-Boot. This includes adjusting the USB nodes + * to only use USB high-speed, as well as remapping volume buttons + * to behave as up/down for navigating U-Boot. + * + * We use OF_LIVE for this rather than early FDT fixup for a couple + * of reasons: it has a much nicer API, is most likely more efficient, + * and our changes are only applied to U-Boot. This allows us to use a + * DT designed for Linux, run U-Boot with a modified version, and then + * boot Linux with the original FDT. + * + * Copyright (c) 2024 Linaro Ltd. + * Author: Caleb Connolly <caleb.connolly@linaro.org> + */ + +#include <dt-bindings/input/linux-event-codes.h> +#include <dm/of_access.h> +#include <dm/of.h> +#include <fdt_support.h> +#include <linux/errno.h> +#include <stdlib.h> +#include <time.h> + +/* U-Boot only supports USB high-speed mode on Qualcomm platforms with DWC3 + * USB controllers. Rather than requiring source level DT changes, we fix up + * DT here. This improves compatibility with upstream DT and simplifies the + * porting process for new devices. + */ +static int fixup_qcom_dwc3(struct device_node *glue_np) +{ + struct device_node *dwc3; + int ret, len, hsphy_idx = 1; + const __be32 *phandles; + const char *second_phy_name; + + debug("Fixing up %s\n", glue_np->name); + + /* Tell the glue driver to configure the wrapper for high-speed only operation */ + ret = of_write_prop(glue_np, "qcom,select-utmi-as-pipe-clk", 0, NULL); + if (ret) { + log_err("Failed to add property 'qcom,select-utmi-as-pipe-clk': %d\n", ret); + return ret; + } + + /* Find the DWC3 node itself */ + dwc3 = of_find_compatible_node(glue_np, NULL, "snps,dwc3"); + if (!dwc3) { + log_err("Failed to find dwc3 node\n"); + return -ENOENT; + } + + phandles = of_get_property(dwc3, "phys", &len); + len /= sizeof(*phandles); + if (len == 1) { + log_debug("Only one phy, not a superspeed controller\n"); + return 0; + } + + /* Figure out if the superspeed phy is present and if so then which phy is it? */ + ret = of_property_read_string_index(dwc3, "phy-names", 1, &second_phy_name); + if (ret == -ENODATA) { + log_debug("Only one phy, not a super-speed controller\n"); + return 0; + } else if (ret) { + log_err("Failed to read second phy name: %d\n", ret); + return ret; + } + + if (!strncmp("usb3-phy", second_phy_name, strlen("usb3-phy"))) { + log_debug("Second phy isn't superspeed (is '%s') assuming first phy is SS\n", + second_phy_name); + hsphy_idx = 0; + } + + /* Overwrite the "phys" property to only contain the high-speed phy */ + ret = of_write_prop(dwc3, "phys", sizeof(*phandles), phandles + hsphy_idx); + if (ret) { + log_err("Failed to overwrite 'phys' property: %d\n", ret); + return ret; + } + + /* Overwrite "phy-names" to only contain a single entry */ + ret = of_write_prop(dwc3, "phy-names", strlen("usb2-phy"), "usb2-phy"); + if (ret) { + log_err("Failed to overwrite 'phy-names' property: %d\n", ret); + return ret; + } + + ret = of_write_prop(dwc3, "maximum-speed", strlen("high-speed"), "high-speed"); + if (ret) { + log_err("Failed to set 'maximum-speed' property: %d\n", ret); + return ret; + } + + return 0; +} + +static void fixup_usb_nodes(void) +{ + struct device_node *glue_np = NULL; + int ret; + + while ((glue_np = of_find_compatible_node(glue_np, NULL, "qcom,dwc3"))) { + ret = fixup_qcom_dwc3(glue_np); + if (ret) + log_warning("Failed to fixup node %s: %d\n", glue_np->name, ret); + } +} + +/* Remove all references to the rpmhpd device */ +static void fixup_power_domains(void) +{ + struct device_node *pd = NULL, *np = NULL; + struct property *prop; + const __be32 *val; + + /* All Qualcomm platforms name the rpm(h)pd "power-controller" */ + for_each_of_allnodes(pd) { + if (pd->name && !strcmp("power-controller", pd->name)) + break; + } + + /* Sanity check that this is indeed a power domain controller */ + if (!of_find_property(pd, "#power-domain-cells", NULL)) { + log_err("Found power-controller but it doesn't have #power-domain-cells\n"); + return; + } + + /* Remove all references to the power domain controller */ + for_each_of_allnodes(np) { + if (!(prop = of_find_property(np, "power-domains", NULL))) + continue; + + val = prop->value; + if (val[0] == cpu_to_fdt32(pd->phandle)) + of_remove_property(np, prop); + } +} + +#define time_call(func, ...) \ + do { \ + u64 start = timer_get_us(); \ + func(__VA_ARGS__); \ + debug(#func " took %lluus\n", timer_get_us() - start); \ + } while (0) + +void qcom_of_fixup_nodes(void) +{ + time_call(fixup_usb_nodes); + time_call(fixup_power_domains); +} diff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h new file mode 100644 index 00000000000..0a7ed5eff8b --- /dev/null +++ b/arch/arm/mach-snapdragon/qcom-priv.h @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 + +#ifndef __QCOM_PRIV_H__ +#define __QCOM_PRIV_H__ + +#if CONFIG_IS_ENABLED(OF_LIVE) +/** + * qcom_of_fixup_nodes() - Fixup Qualcomm DT nodes + * + * Adjusts nodes in the live tree to improve compatibility with U-Boot. + */ +void qcom_of_fixup_nodes(void); +#else +static inline void qcom_of_fixup_nodes(void) +{ + log_debug("Unable to dynamically fixup USB nodes, please enable CONFIG_OF_LIVE\n"); +} +#endif /* OF_LIVE */ + +#endif /* __QCOM_PRIV_H__ */ diff --git a/arch/arm/mach-snapdragon/sysmap-apq8016.c b/arch/arm/mach-snapdragon/sysmap-apq8016.c deleted file mode 100644 index ffa3f9aa353..00000000000 --- a/arch/arm/mach-snapdragon/sysmap-apq8016.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Qualcomm APQ8016 memory map - * - * (C) Copyright 2016 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> - */ - -#include <common.h> -#include <asm/armv8/mmu.h> - -static struct mm_region apq8016_mem_map[] = { - { - .virt = 0x0UL, /* Peripheral block */ - .phys = 0x0UL, /* Peripheral block */ - .size = 0x8000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, /* DDR */ - .phys = 0x80000000UL, /* DDR */ - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = apq8016_mem_map; diff --git a/arch/arm/mach-snapdragon/sysmap-apq8096.c b/arch/arm/mach-snapdragon/sysmap-apq8096.c deleted file mode 100644 index 0614f8308d0..00000000000 --- a/arch/arm/mach-snapdragon/sysmap-apq8096.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Qualcomm APQ8096 memory map - * - * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org> - */ - -#include <common.h> -#include <asm/armv8/mmu.h> - -static struct mm_region apq8096_mem_map[] = { - { - .virt = 0x0UL, /* Peripheral block */ - .phys = 0x0UL, /* Peripheral block */ - .size = 0x10000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, /* DDR */ - .phys = 0x80000000UL, /* DDR */ - .size = 0xC0000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = apq8096_mem_map; diff --git a/arch/arm/mach-snapdragon/sysmap-qcs404.c b/arch/arm/mach-snapdragon/sysmap-qcs404.c deleted file mode 100644 index 64ca4adf1bd..00000000000 --- a/arch/arm/mach-snapdragon/sysmap-qcs404.c +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Qualcomm QCS404 memory map - * - * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org> - */ - -#include <common.h> -#include <asm/armv8/mmu.h> - -static struct mm_region qcs404_mem_map[] = { - { - .virt = 0x0UL, /* Peripheral block */ - .phys = 0x0UL, /* Peripheral block */ - .size = 0x8000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, /* DDR */ - .phys = 0x80000000UL, /* DDR */ - .size = 0x05900000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x89600000UL, /* DDR */ - .phys = 0x89600000UL, /* DDR */ - .size = 0x162000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa0000000UL, /* DDR */ - .phys = 0xa0000000UL, /* DDR */ - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = qcs404_mem_map; diff --git a/arch/arm/mach-snapdragon/sysmap-sdm845.c b/arch/arm/mach-snapdragon/sysmap-sdm845.c deleted file mode 100644 index 721ac411665..00000000000 --- a/arch/arm/mach-snapdragon/sysmap-sdm845.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Qualcomm SDM845 memory map - * - * (C) Copyright 2021 Dzmitry Sankouski <dsankousk@gmail.com> - */ - -#include <common.h> -#include <asm/armv8/mmu.h> - -static struct mm_region sdm845_mem_map[] = { - { - .virt = 0x0UL, /* Peripheral block */ - .phys = 0x0UL, /* Peripheral block */ - .size = 0x10000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, /* DDR */ - .phys = 0x80000000UL, /* DDR */ - .size = 0x200000000UL, /* 8GiB - maximum allowed memory */ - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = sdm845_mem_map; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 114d2438129..6b6a162f568 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -8,7 +8,8 @@ config NR_DRAM_BANKS config SOCFPGA_SECURE_VAB_AUTH bool "Enable boot image authentication with Secure Device Manager" - depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X + depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X || \ + TARGET_SOCFPGA_AGILEX5 select FIT_IMAGE_POST_PROCESS select SHA384 select SHA512 @@ -58,6 +59,15 @@ config TARGET_SOCFPGA_AGILEX select SPL_CLK if SPL select TARGET_SOCFPGA_SOC64 +config TARGET_SOCFPGA_AGILEX5 + bool + select BINMAN if SPL_ATF + select CLK + select FPGA_INTEL_SDM_MAILBOX + select GICV3 + select SPL_CLK if SPL + select TARGET_SOCFPGA_SOC64 + config TARGET_SOCFPGA_ARRIA5 bool select TARGET_SOCFPGA_GEN5 @@ -80,6 +90,14 @@ config TARGET_SOCFPGA_ARRIA10 imply FPGA_SOCFPGA imply SPL_USE_TINY_PRINTF +config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM + bool "Always reprogram Arria 10 FPGA" + depends on TARGET_SOCFPGA_ARRIA10 + help + Arria 10 FPGA is only programmed during the cold boot. + This option forces the FPGA to be reprogrammed every reboot, + allowing to change the bitstream and apply it with warm reboot. + config TARGET_SOCFPGA_CYCLONE5 bool select TARGET_SOCFPGA_GEN5 @@ -129,6 +147,10 @@ config TARGET_SOCFPGA_AGILEX_SOCDK bool "Intel SOCFPGA SoCDK (Agilex)" select TARGET_SOCFPGA_AGILEX +config TARGET_SOCFPGA_AGILEX5_SOCDK + bool "Intel SOCFPGA SoCDK (Agilex5)" + select TARGET_SOCFPGA_AGILEX5 + config TARGET_SOCFPGA_ARIES_MCVEVK bool "Aries MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -202,6 +224,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT endchoice config SYS_BOARD + default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK @@ -223,6 +246,7 @@ config SYS_BOARD default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA config SYS_VENDOR + default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK default "intel" if TARGET_SOCFPGA_N5X_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -245,6 +269,7 @@ config SYS_SOC default "socfpga" config SYS_CONFIG_NAME + default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index ec38b64dd4d..67c6a8dfec5 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -4,7 +4,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # Copyright (C) 2012-2017 Altera Corporation <www.altera.com> -# Copyright (C) 2017-2021 Intel Corporation <www.intel.com> +# Copyright (C) 2017-2024 Intel Corporation <www.intel.com> obj-y += board.o obj-y += clock_manager.o @@ -56,6 +56,15 @@ obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 +obj-y += clock_manager_agilex5.o +obj-y += mailbox_s10.o +obj-y += misc_soc64.o +obj-y += mmu-arm64_s10.o +obj-y += reset_manager_s10.o +obj-y += wrap_pll_config_soc64.o +endif + ifdef CONFIG_TARGET_SOCFPGA_N5X obj-y += clock_manager_n5x.o obj-y += lowlevel_init_soc64.o @@ -95,6 +104,9 @@ endif ifdef CONFIG_TARGET_SOCFPGA_N5X obj-y += spl_n5x.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 +obj-y += spl_soc64.o +endif else obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o obj-$(CONFIG_SPL_ATF) += smc_api.o diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 09e09192fba..616e1afe5de 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -7,9 +7,11 @@ #include <common.h> #include <asm/arch/clock_manager.h> +#include <asm/arch/mailbox_s10.h> #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/secure_vab.h> +#include <asm/arch/smc_api.h> #include <asm/global_data.h> #include <asm/io.h> #include <errno.h> @@ -23,6 +25,8 @@ DECLARE_GLOBAL_DATA_PTR; +#define DEFAULT_JTAG_USERCODE 0xFFFFFFFF + void s_init(void) { #ifndef CONFIG_ARM64 /* @@ -92,13 +96,50 @@ int g_dnl_board_usb_cable_connected(void) } #endif -#ifdef CONFIG_SPL_BUILD -__weak int board_fit_config_name_match(const char *name) +u8 socfpga_get_board_id(void) { - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); + u8 board_id = 0; + u32 jtag_usercode; + int err; - return 0; +#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF) + err = smc_get_usercode(&jtag_usercode); +#else + u32 resp_len = 1; + + err = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_GET_USERCODE, MBOX_CMD_DIRECT, 0, + NULL, 0, &resp_len, &jtag_usercode); +#endif + + if (err) { + puts("Fail to read JTAG Usercode. Default Board ID to 0\n"); + return board_id; + } + + debug("Valid JTAG Usercode: %u\n", jtag_usercode); + + if (jtag_usercode == DEFAULT_JTAG_USERCODE) { + debug("JTAG Usercode is not set. Default Board ID to 0\n"); + } else if (jtag_usercode >= 0 && jtag_usercode <= 255) { + board_id = jtag_usercode; + debug("Valid JTAG Usercode. Set Board ID to %u\n", board_id); + } else { + puts("Board ID is not in range 0 to 255\n"); + } + + return board_id; +} + +#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +int board_fit_config_name_match(const char *name) +{ + char board_name[10]; + + sprintf(board_name, "board_%u", socfpga_get_board_id()); + + debug("Board name: %s\n", board_name); + + return strcmp(name, board_name); } #endif @@ -116,6 +157,8 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image, #if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT) void board_prep_linux(struct bootm_headers *images) { + bool use_fit = false; + if (!images->fit_uname_cfg) { if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) && !IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) { @@ -127,12 +170,13 @@ void board_prep_linux(struct bootm_headers *images) hang(); } } else { + use_fit = true; /* Update fdt_addr in enviroment variable */ env_set_hex("fdt_addr", (ulong)images->ft_addr); debug("images->ft_addr = 0x%08lx\n", (ulong)images->ft_addr); } - if (IS_ENABLED(CONFIG_CADENCE_QSPI)) { + if (use_fit && IS_ENABLED(CONFIG_CADENCE_QSPI)) { if (env_get("linux_qspi_enable")) run_command(env_get("linux_qspi_enable"), 0); } diff --git a/arch/arm/mach-socfpga/clock_manager_agilex5.c b/arch/arm/mach-socfpga/clock_manager_agilex5.c new file mode 100644 index 00000000000..b92f0b3af80 --- /dev/null +++ b/arch/arm/mach-socfpga/clock_manager_agilex5.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + * + */ + +#include <clk.h> +#include <config.h> +#include <dm.h> +#include <errno.h> +#include <log.h> +#include <malloc.h> +#include <stdarg.h> +#include <stdio.h> +#include <time.h> +#include <vsprintf.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/u-boot.h> +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/types.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/system_manager.h> +#include <dt-bindings/clock/agilex5-clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +static ulong cm_get_rate_dm(u32 id) +{ + struct udevice *dev; + struct clk clk; + ulong rate; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(socfpga_agilex5_clk), + &dev); + if (ret) + return 0; + + clk.id = id; + ret = clk_request(dev, &clk); + if (ret < 0) + return 0; + + rate = clk_get_rate(&clk); + + if ((rate == (unsigned long)-ENOSYS) || + (rate == (unsigned long)-ENXIO) || + (rate == (unsigned long)-EIO)) { + debug("%s id %u: clk_get_rate err: %ld\n", + __func__, id, rate); + return 0; + } + + return rate; +} + +static u32 cm_get_rate_dm_khz(u32 id) +{ + return cm_get_rate_dm(id) / 1000; +} + +unsigned long cm_get_mpu_clk_hz(void) +{ + return cm_get_rate_dm(AGILEX5_MPU_CLK); +} + +unsigned int cm_get_l4_sys_free_clk_hz(void) +{ + return cm_get_rate_dm(AGILEX5_L4_SYS_FREE_CLK); +} + +void cm_print_clock_quick_summary(void) +{ + printf("MPU %10d kHz\n", + cm_get_rate_dm_khz(AGILEX5_MPU_CLK)); + printf("L4 Main %8d kHz\n", + cm_get_rate_dm_khz(AGILEX5_L4_MAIN_CLK)); + printf("L4 sys free %8d kHz\n", + cm_get_rate_dm_khz(AGILEX5_L4_SYS_FREE_CLK)); + printf("L4 MP %8d kHz\n", + cm_get_rate_dm_khz(AGILEX5_L4_MP_CLK)); + printf("L4 SP %8d kHz\n", + cm_get_rate_dm_khz(AGILEX5_L4_SP_CLK)); + printf("SDMMC %8d kHz\n", + cm_get_rate_dm_khz(AGILEX5_SDMMC_CLK)); +} diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 3f899fcfa3a..65721098b2b 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -1,11 +1,46 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2016-2021 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2024 Intel Corporation <www.intel.com> */ #ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_ #define _SOCFPGA_SOC64_BASE_HARDWARE_H_ +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOCFPGA_CCU_ADDRESS 0x1c000000 +#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0x18001000 +#define SOCFPGA_SMMU_ADDRESS 0x16000000 +#define SOCFPGA_OCRAM_FIREWALL_ADDRESS 0x108cc400 +#define SOCFPGA_MAILBOX_ADDRESS 0x10a30000 +#define SOCFPGA_UART0_ADDRESS 0x10c02000 +#define SOCFPGA_UART1_ADDRESS 0x10c02100 +#define SOCFPGA_SPTIMER0_ADDRESS 0x10c03000 +#define SOCFPGA_SPTIMER1_ADDRESS 0x10c03100 +#define SOCFPGA_SYSTIMER0_ADDRESS 0x10d00000 +#define SOCFPGA_SYSTIMER1_ADDRESS 0x10d00100 +#define SOCFPGA_L4WD0_ADDRESS 0x10d00200 +#define SOCFPGA_L4WD1_ADDRESS 0x10d00300 +#define SOCFPGA_L4WD2_ADDRESS 0x10d00400 +#define SOCFPGA_L4WD3_ADDRESS 0x10d00500 +#define SOCFPGA_L4WD4_ADDRESS 0x10d00600 +#define SOCFPGA_GTIMER_SEC_ADDRESS 0x10d01000 +#define SOCFPGA_GTIMER_NSEC_ADDRESS 0x10d02000 +#define SOCFPGA_CLKMGR_ADDRESS 0x10d10000 +#define SOCFPGA_RSTMGR_ADDRESS 0x10d11000 +#define SOCFPGA_SYSMGR_ADDRESS 0x10d12000 +#define SOCFPGA_OCRAM_ADDRESS 0x00000000 +#define SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS 0x18000800 +#define SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS 0x18000A00 +#define SOCFPGA_FW_TBU2NOC_ADDRESS 0x18000C00 +#define SOCFPGA_FIREWALL_L4_PER 0x10d21000 +#define SOCFPGA_FIREWALL_L4_SYS 0x10d21100 +#define SOCFPGA_FIREWALL_SOC2FPGA 0x10d21200 +#define SOCFPGA_FIREWALL_LWSOC2FPGA 0x10d21300 +#define SOCFPGA_FIREWALL_TCU 0x10d21400 +#define SOCFPGA_FIREWALL_PRIV_MEMORYMAP_PRIV 0x10d24800 +#define GICD_BASE 0x1d000000 +#define GICR_BASE 0x1d060000 +#else #define SOCFPGA_CCU_ADDRESS 0xf7000000 #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 @@ -44,5 +79,6 @@ #define SOCFPGA_OCRAM_ADDRESS 0xffe00000 #define GICD_BASE 0xfffc1000 #define GICC_BASE 0xfffc2000 +#endif /* IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) */ #endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index a8cb07a1c47..6c9d32b9dd8 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> + * Copyright (C) 2013-2024 Altera Corporation <www.altera.com> */ #ifndef _CLOCK_MANAGER_H_ @@ -28,6 +28,8 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz); #include <asm/arch/clock_manager_s10.h> #elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) #include <asm/arch/clock_manager_agilex.h> +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#include <asm/arch/clock_manager_agilex5.h> #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #include <asm/arch/clock_manager_n5x.h> #endif diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h new file mode 100644 index 00000000000..1ae0a926032 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */ + +#ifndef _CLOCK_MANAGER_AGILEX5_ +#define _CLOCK_MANAGER_AGILEX5_ + +#include <asm/arch/clock_manager_soc64.h> +#include "../../../../../drivers/clk/altera/clk-agilex5.h" + +#endif /* _CLOCK_MANAGER_AGILEX5_ */ diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index 9b85e5865ba..d839f288411 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2016-2021 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2024 Intel Corporation <www.intel.com> * */ @@ -17,7 +17,12 @@ #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 #define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 #define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOC64_HANDOFF_MAGIC_PERI 0x50455249 +#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524d +#else #define SOC64_HANDOFF_MAGIC_MISC 0x4D495343 +#endif #define SOC64_HANDOFF_OFFSET_LENGTH 0x4 #define SOC64_HANDOFF_OFFSET_DATA 0x10 @@ -27,6 +32,8 @@ IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) #define SOC64_HANDOFF_BASE 0xFFE3F000 #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOC64_HANDOFF_BASE 0x0007F000 #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #define SOC64_HANDOFF_BASE 0xFFE5F000 #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630) @@ -58,13 +65,21 @@ #define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) #define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0) #define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580) +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOC64_HANDOFF_PERI (SOC64_HANDOFF_BASE + 0x620) +#define SOC64_HANDOFF_SDRAM (SOC64_HANDOFF_BASE + 0x634) +#define SOC64_HANDOFF_SDRAM_LEN 1 +#endif #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) -#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608) -#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C) +#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608) +#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C) +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x60c) +#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x610) #else -#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x5fc) -#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600) +#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x5fc) +#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600) #endif #define SOC64_HANDOFF_MUX_LEN 96 diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index fbaf11597ed..2cc7c890449 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -119,6 +119,7 @@ enum ALT_SDM_MBOX_RESP_CODE { #define MBOX_RECONFIG_DATA 8 #define MBOX_RECONFIG_STATUS 9 #define MBOX_VAB_SRC_CERT 11 +#define MBOX_GET_USERCODE 19 #define MBOX_QSPI_OPEN 50 #define MBOX_QSPI_CLOSE 51 #define MBOX_QSPI_DIRECT 59 diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c index a55b7b7cf3b..91c6d7c55f1 100644 --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2024 Intel Corporation <www.intel.com> * */ @@ -10,6 +10,62 @@ DECLARE_GLOBAL_DATA_PTR; +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +static struct mm_region socfpga_agilex5_mem_map[] = { + { + /* OCRAM 512KB */ + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x00080000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE, + }, { + /* DEVICE */ + .virt = 0x10808000UL, + .phys = 0x10808000UL, + .size = 0x0F7F8000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* FPGA 1.5GB */ + .virt = 0x20000000UL, + .phys = 0x20000000UL, + .size = 0x60000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* FPGA 15GB */ + .virt = 0x440000000UL, + .phys = 0x440000000UL, + .size = 0x3C0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* FPGA 240GB */ + .virt = 0x4400000000UL, + .phys = 0x4400000000UL, + .size = 0x3C00000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* MEM 2GB */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { + /* List terminator */ + }, +}; + +struct mm_region *mem_map = socfpga_agilex5_mem_map; + +#else static struct mm_region socfpga_stratix10_mem_map[] = { { /* MEM 2GB*/ @@ -70,3 +126,4 @@ static struct mm_region socfpga_stratix10_mem_map[] = { }; struct mm_region *mem_map = socfpga_stratix10_mem_map; +#endif diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 9edbbf4a29c..3981d2d4f14 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -122,7 +122,10 @@ void spl_board_init(void) arch_early_init_r(); /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */ - if (is_fpgamgr_user_mode()) { + if ((IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) && + is_regular_boot_valid()) || + (!IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) && + is_fpgamgr_user_mode())) { ret = config_pins(gd->fdt_blob, "shared"); if (ret) return; @@ -130,7 +133,8 @@ void spl_board_init(void) ret = config_pins(gd->fdt_blob, "fpga"); if (ret) return; - } else if (!is_fpgamgr_early_user_mode()) { + } else if (IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) || + !is_fpgamgr_early_user_mode()) { /* Program IOSSM(early IO release) or full FPGA */ fpgamgr_program(buf, FPGA_BUFSIZ, 0); diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c index df0701ec85e..6aa9bb26b4e 100644 --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -11,7 +11,6 @@ #include "log.h" #ifndef __ASSEMBLY__ -#include <asm/types.h> enum endianness { LITTLE_ENDIAN = 0, BIG_ENDIAN, diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig index 8f91db4b46b..589276282e4 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig @@ -17,6 +17,7 @@ config CMD_STM32PROG config CMD_STM32PROG_USB bool "support stm32prog over USB" depends on CMD_STM32PROG + depends on USB_GADGET_DOWNLOAD default y help activate the command "stm32prog usb" for STM32MP soc family diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile index 857148747ef..ebae50f66c9 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/Makefile +++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile @@ -8,7 +8,6 @@ obj-y += cpu.o obj-$(CONFIG_STM32MP13X) += stm32mp13x.o obj-$(CONFIG_STM32MP15X) += stm32mp15x.o -obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o ifdef CONFIG_SPL_BUILD obj-y += spl.o obj-y += tzc400.o diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c index 8cdeb0ab3f2..4f2379df45f 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c @@ -703,6 +703,8 @@ void __secure psci_system_suspend(u32 __always_unused function_id, { u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr; u32 gicd_addr = stm32mp_get_gicd_base_address(); + u32 cpu = psci_get_cpu_id(); + u32 sp = (u32)__secure_stack_end - (cpu << ARM_PSCI_STACK_SHIFT); bool iwdg1_wake = false; bool iwdg2_wake = false; bool other_wake = false; @@ -805,4 +807,16 @@ void __secure psci_system_suspend(u32 __always_unused function_id, writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR); clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); + + /* + * The system has resumed successfully. Rewrite LR register stored + * on stack with 'ep' value, so that on return from this PSCI call, + * the code would jump to that 'ep' resume entry point code path + * instead of the previous 'lr' register content which (e.g. with + * Linux) points to resume failure code path. + * + * See arch/arm/cpu/armv7/psci.S _smc_psci: for the stack layout + * used here, SP-4 is PC, SP-8 is LR, SP-12 is R7, and so on. + */ + writel(ep, sp - 8); } diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index afc56b02eea..d75ec99d6a1 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -14,6 +14,7 @@ #include <asm/arch/sys_proto.h> #include <dm/device.h> #include <dm/uclass.h> +#include <linux/bitfield.h> /* RCC register */ #define RCC_TZCR (STM32_RCC_BASE + 0x00) @@ -41,6 +42,9 @@ #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) +#define TAMP_SMCR (STM32_TAMP_BASE + 0x20) +#define TAMP_SMCR_BKPRWDPROT GENMASK(7, 0) +#define TAMP_SMCR_BKPWDPROT GENMASK(23, 16) #define PWR_CR1 (STM32_PWR_BASE + 0x00) #define PWR_MCUCR (STM32_PWR_BASE + 0x14) @@ -136,6 +140,18 @@ static void security_init(void) */ writel(0x0, TAMP_CR1); + /* + * TAMP: Configure non-zero secure protection settings. This is + * checked by BootROM function 35ac on OTP-CLOSED device during + * CPU core 1 release from endless loop. If secure protection + * fields are zero, the core 1 is not released from endless + * loop on second SGI0. + */ + clrsetbits_le32(TAMP_SMCR, + TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT, + FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x20) | + FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x20)); + /* GPIOZ: deactivate the security */ writel(BIT(0), RCC_MP_AHB5ENSETR); writel(0x0, GPIOZ_SECCFGR); @@ -322,8 +338,23 @@ void get_soc_name(char name[SOC_NAME_SIZE]) get_cpu_string_offsets(&type, &pkg, &rev); - snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", - soc_type[type], soc_pkg[pkg], soc_rev[rev]); + if (bsec_dbgswenable()) { + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", + soc_type[type], soc_pkg[pkg], soc_rev[rev]); + } else { + /* + * SoC revision is only accessible via DBUMCU IDC register, + * which requires BSEC.DENABLE DBGSWENABLE bit to be set to + * make the register accessible, otherwise an access to the + * register triggers bus fault. As BSEC.DBGSWENABLE is zero + * in case of an OTP-CLOSED system, do NOT set DBGSWENABLE + * bit as this might open a brief window for timing attacks. + * Instead, report that this system is OTP-CLOSED and do not + * report any SoC revision to avoid confusing users. + */ + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s SEC/C", + soc_type[type], soc_pkg[pkg]); + } } static void setup_soc_type_pkg_rev(void) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index fe89aec6b9a..ddf9414b08e 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1078,7 +1078,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2 help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 1d4c70ec352..3f83c0280ef 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -7,7 +7,6 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-y += board.o -obj-y += clock.o obj-y += cpu_info.o obj-y += dram_helpers.o obj-$(CONFIG_SUN6I_PRCM) += prcm.o @@ -31,6 +30,7 @@ obj-y += timer.o endif ifdef CONFIG_SPL_BUILD +obj-y += clock.o obj-$(CONFIG_MACH_SUNIV) += dram_suniv.o obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o obj-$(CONFIG_DRAM_SUN6I) += dram_sun6i.o diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index f4dbb2a740b..0140b07d32a 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -458,10 +458,8 @@ void board_init_f(ulong dummy) { sunxi_sram_init(); -#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 /* Enable non-secure access to some peripherals */ tzpc_init(); -#endif clock_init(); timer_init(); diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c index b6c68c94f67..5e9fa0d0748 100644 --- a/arch/arm/mach-sunxi/clock.c +++ b/arch/arm/mach-sunxi/clock.c @@ -23,10 +23,8 @@ __weak void gtbus_init(void) int clock_init(void) { -#ifdef CONFIG_SPL_BUILD clock_init_safe(); gtbus_init(); -#endif clock_init_uart(); clock_init_sec(); diff --git a/arch/arm/mach-sunxi/clock_sun4i.c b/arch/arm/mach-sunxi/clock_sun4i.c index ac3b7a801f4..6458d066f7e 100644 --- a/arch/arm/mach-sunxi/clock_sun4i.c +++ b/arch/arm/mach-sunxi/clock_sun4i.c @@ -43,7 +43,6 @@ void clock_init_safe(void) setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); #endif } -#endif void clock_init_uart(void) { @@ -77,7 +76,6 @@ int clock_twi_onoff(int port, int state) return 0; } -#ifdef CONFIG_SPL_BUILD #define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \ 0 << CCM_PLL1_CFG_VCO_RST_SHIFT | \ 8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \ @@ -177,8 +175,9 @@ void clock_set_pll1(unsigned int hz) &ccm->cpu_ahb_apb0_cfg); sdelay(20); } -#endif +#endif /* CONFIG_SPL_BUILD */ +/* video, DRAM, PLL_PERIPH clocks */ void clock_set_pll3(unsigned int clk) { struct sunxi_ccm_reg * const ccm = diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index dac3663e1be..cc2ee336416 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -51,7 +51,6 @@ void clock_init_safe(void) */ writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg); } -#endif void clock_init_uart(void) { @@ -73,7 +72,6 @@ void clock_init_uart(void) 1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1)); } -#ifdef CONFIG_SPL_BUILD void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -105,33 +103,6 @@ void clock_set_pll1(unsigned int clk) val |= CCM_CPU_AXI_MUX_PLL_CPUX; writel(val, &ccm->cpu_axi_cfg); } -#endif - -unsigned int clock_get_pll6(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - uint32_t rval = readl(&ccm->pll6_cfg); - int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; - int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> - CCM_PLL6_CTRL_DIV2_SHIFT) + 1; - int div1, m; - - if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) { - div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >> - CCM_PLL6_CTRL_P0_SHIFT) + 1; - m = 1; - } else { - div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> - CCM_PLL6_CTRL_DIV1_SHIFT) + 1; - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) - m = 4; - else - m = 2; - } - - return 24000000U * n / m / div1 / div2; -} int clock_twi_onoff(int port, int state) { @@ -160,3 +131,31 @@ int clock_twi_onoff(int port, int state) return 0; } +#endif /* CONFIG_SPL_BUILD */ + +/* PLL_PERIPH0 clock, used by the MMC driver */ +unsigned int clock_get_pll6(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll6_cfg); + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; + int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> + CCM_PLL6_CTRL_DIV2_SHIFT) + 1; + int div1, m; + + if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) { + div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >> + CCM_PLL6_CTRL_P0_SHIFT) + 1; + m = 1; + } else { + div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> + CCM_PLL6_CTRL_DIV1_SHIFT) + 1; + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + m = 4; + else + m = 2; + } + + return 24000000U * n / m / div1 / div2; +} diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index aad9df282ec..59f7e15ffe8 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -62,7 +62,6 @@ void clock_init_safe(void) setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE); #endif } -#endif /* CONFIG_SPL_BUILD */ void clock_init_sec(void) { @@ -124,7 +123,6 @@ void clock_init_uart(void) #endif } -#ifdef CONFIG_SPL_BUILD void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -173,6 +171,7 @@ void clock_set_pll1(unsigned int clk) } #endif /* CONFIG_SPL_BUILD */ +/* video, DRAM, PLL_PERIPH clocks */ void clock_set_pll3(unsigned int clk) { struct sunxi_ccm_reg * const ccm = diff --git a/arch/arm/mach-sunxi/clock_sun8i_a83t.c b/arch/arm/mach-sunxi/clock_sun8i_a83t.c index 198fe9dbd73..9eeba084f95 100644 --- a/arch/arm/mach-sunxi/clock_sun8i_a83t.c +++ b/arch/arm/mach-sunxi/clock_sun8i_a83t.c @@ -46,7 +46,6 @@ void clock_init_safe(void) /* timestamp */ writel(1, 0x01720000); } -#endif void clock_init_uart(void) { @@ -70,7 +69,6 @@ void clock_init_uart(void) CONFIG_CONS_INDEX - 1)); } -#ifdef CONFIG_SPL_BUILD void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -102,8 +100,9 @@ void clock_set_pll1(unsigned int clk) CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT, &ccm->cpu_axi_cfg); } -#endif +#endif /* CONFIG_SPL_BUILD */ +/* DRAM and PLL_PERIPH0 clock (used by the MMC driver) */ void clock_set_pll5(unsigned int clk) { struct sunxi_ccm_reg * const ccm = diff --git a/arch/arm/mach-sunxi/clock_sun9i.c b/arch/arm/mach-sunxi/clock_sun9i.c index edaff9a28ce..5913e40cb65 100644 --- a/arch/arm/mach-sunxi/clock_sun9i.c +++ b/arch/arm/mach-sunxi/clock_sun9i.c @@ -17,6 +17,52 @@ #ifdef CONFIG_SPL_BUILD +static void clock_set_pll2(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int p = 0; + + /* Switch cluster 1 to 24MHz clock while changing PLL2 */ + clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, + C1_CPUX_CLK_SRC_OSC24M); + + writel(CCM_PLL2_CTRL_EN | CCM_PLL2_CTRL_P(p) | + CCM_PLL2_CLOCK_TIME_2 | CCM_PLL2_CTRL_N(clk / 24000000), + &ccm->pll2_c1_cfg); + + sdelay(2000); + + /* Switch cluster 1 back to PLL2 */ + clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, + C1_CPUX_CLK_SRC_PLL2); +} + +static void clock_set_pll4(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + writel(CCM_PLL4_CTRL_EN | CCM_PLL4_CTRL_N(clk / 24000000), + &ccm->pll4_periph0_cfg); + + sdelay(2000); +} + +static void clock_set_pll12(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN) + return; + + writel(CCM_PLL12_CTRL_EN | CCM_PLL12_CTRL_N(clk / 24000000), + &ccm->pll12_periph1_cfg); + + sdelay(2000); +} + void clock_init_safe(void) { struct sunxi_ccm_reg * const ccm = @@ -63,7 +109,6 @@ void clock_init_safe(void) /* set enable-bit in TSTAMP_CTRL_REG */ writel(1, 0x01720000); } -#endif void clock_init_uart(void) { @@ -80,7 +125,6 @@ void clock_init_uart(void) CONFIG_CONS_INDEX - 1)); } -#ifdef CONFIG_SPL_BUILD void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -108,27 +152,6 @@ void clock_set_pll1(unsigned int clk) C0_CPUX_CLK_SRC_PLL1); } -void clock_set_pll2(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - const int p = 0; - - /* Switch cluster 1 to 24MHz clock while changing PLL2 */ - clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, - C1_CPUX_CLK_SRC_OSC24M); - - writel(CCM_PLL2_CTRL_EN | CCM_PLL2_CTRL_P(p) | - CCM_PLL2_CLOCK_TIME_2 | CCM_PLL2_CTRL_N(clk / 24000000), - &ccm->pll2_c1_cfg); - - sdelay(2000); - - /* Switch cluster 1 back to PLL2 */ - clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, - C1_CPUX_CLK_SRC_PLL2); -} - void clock_set_pll6(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -143,32 +166,6 @@ void clock_set_pll6(unsigned int clk) sdelay(2000); } -void clock_set_pll12(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN) - return; - - writel(CCM_PLL12_CTRL_EN | CCM_PLL12_CTRL_N(clk / 24000000), - &ccm->pll12_periph1_cfg); - - sdelay(2000); -} - - -void clock_set_pll4(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - writel(CCM_PLL4_CTRL_EN | CCM_PLL4_CTRL_N(clk / 24000000), - &ccm->pll4_periph0_cfg); - - sdelay(2000); -} -#endif int clock_twi_onoff(int port, int state) { @@ -193,7 +190,9 @@ int clock_twi_onoff(int port, int state) return 0; } +#endif /* CONFIG_SPL_BUILD */ +/* PLL_PERIPH0 clock (used by the MMC driver) */ unsigned int clock_get_pll4_periph0(void) { struct sunxi_ccm_reg *const ccm = diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 72faa7171c1..7acb44f52ae 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -72,18 +72,27 @@ #define SUN6I_CTL_ENABLE BIT(0) #define SUN6I_CTL_MASTER BIT(1) #define SUN6I_CTL_SRST BIT(31) +#define SUN6I_TCR_SDM BIT(13) #define SUN6I_TCR_XCH BIT(31) /*****************************************************************************/ -#define CCM_AHB_GATING0 (0x01C20000 + 0x60) -#define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c) -#ifdef CONFIG_SUN50I_GEN_H6 -#define CCM_SPI0_CLK (0x03001000 + 0x940) +#if IS_ENABLED(CONFIG_SUN50I_GEN_H6) +#define CCM_BASE 0x03001000 +#elif IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) +#define CCM_BASE 0x02001000 #else -#define CCM_SPI0_CLK (0x01C20000 + 0xA0) +#define CCM_BASE 0x01C20000 #endif -#define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0) + +#define CCM_AHB_GATING0 (CCM_BASE + 0x60) +#define CCM_H6_SPI_BGR_REG (CCM_BASE + 0x96c) +#if IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) +#define CCM_SPI0_CLK (CCM_BASE + 0x940) +#else +#define CCM_SPI0_CLK (CCM_BASE + 0xA0) +#endif +#define SUN6I_BUS_SOFT_RST_REG0 (CCM_BASE + 0x2C0) #define AHB_RESET_SPI0_SHIFT 20 #define AHB_GATE_OFFSET_SPI0 20 @@ -101,17 +110,22 @@ */ static void spi0_pinmux_setup(unsigned int pin_function) { - /* All chips use PC0 and PC2. */ - sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); + /* All chips use PC2. And all chips use PC0, except R528/T113 */ + if (!IS_ENABLED(CONFIG_MACH_SUN8I_R528)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); + sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function); - /* All chips except H6 and H616 use PC1. */ - if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + /* All chips except H6/H616/R528/T113 use PC1. */ + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && + !IS_ENABLED(CONFIG_MACH_SUN8I_R528)) sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function); - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6) || + IS_ENABLED(CONFIG_MACH_SUN8I_R528)) sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function); - if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || + IS_ENABLED(CONFIG_MACH_SUN8I_R528)) sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function); /* Older generations use PC23 for CS, newer ones use PC3. */ @@ -125,7 +139,8 @@ static void spi0_pinmux_setup(unsigned int pin_function) static bool is_sun6i_gen_spi(void) { return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || - IS_ENABLED(CONFIG_SUN50I_GEN_H6); + IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2); } static uintptr_t spi0_base_address(void) @@ -136,6 +151,9 @@ static uintptr_t spi0_base_address(void) if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) return 0x05010000; + if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) + return 0x04025000; + if (!is_sun6i_gen_spi() || IS_ENABLED(CONFIG_MACH_SUNIV)) return 0x01C05000; @@ -151,23 +169,30 @@ static void spi0_enable_clock(void) uintptr_t base = spi0_base_address(); /* Deassert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); else if (is_sun6i_gen_spi()) setbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); /* Open the SPI0 gate */ - if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && + !IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); if (IS_ENABLED(CONFIG_MACH_SUNIV)) { /* Divide by 32, clock source is AHB clock 200MHz */ writel(SPI0_CLK_DIV_BY_32, base + SUN6I_SPI0_CCTL); } else { - /* Divide by 4 */ - writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ? - SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL)); + /* New SoCs do not have a clock divider inside */ + if (!IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) { + /* Divide by 4 */ + writel(SPI0_CLK_DIV_BY_4, + base + (is_sun6i_gen_spi() ? SUN6I_SPI0_CCTL : + SUN4I_SPI0_CCTL)); + } + /* 24MHz from OSC24M */ writel((1 << 31), CCM_SPI0_CLK); } @@ -179,6 +204,14 @@ static void spi0_enable_clock(void) /* Wait for completion */ while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) ; + + /* + * For new SoCs we should configure sample mode depending on + * input clock. As 24MHz from OSC24M is used, we could use + * normal sample mode by setting SDM bit in the TCR register + */ + if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) + setbits_le32(base + SUN6I_SPI0_TCR, SUN6I_TCR_SDM); } else { /* Enable SPI in the master mode and reset FIFO */ setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | @@ -205,11 +238,13 @@ static void spi0_disable_clock(void) writel(0, CCM_SPI0_CLK); /* Close the SPI0 gate */ - if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && + !IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Assert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); else if (is_sun6i_gen_spi()) clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, @@ -223,7 +258,8 @@ static void spi0_init(void) if (IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_SUN50I_GEN_H6)) pin_function = SUN50I_GPC_SPI0; - else if (IS_ENABLED(CONFIG_MACH_SUNIV)) + else if (IS_ENABLED(CONFIG_MACH_SUNIV) || + IS_ENABLED(CONFIG_MACH_SUN8I_R528)) pin_function = SUNIV_GPC_SPI0; spi0_pinmux_setup(pin_function); diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 05e194de082..04612895576 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -219,6 +219,10 @@ config TEGRA_ENABLE_UARTC config TEGRA_ENABLE_UARTD bool "Use UARTD" +config TEGRA_ENABLE_UARTE + bool "Use UARTE" + depends on TEGRA20 || TEGRA30 + endchoice config TEGRA_GPU diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 7f2753190c2..e6f1286e71f 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -265,14 +265,15 @@ int dram_init(void) if (uniphier_get_soc_id() == UNIPHIER_LD20_ID) gd->ram_size -= 64; + /* map all the DRAM regions */ + uniphier_mem_map_init(gd->ram_base, prev_top - gd->ram_base); + return 0; } int dram_init_banksize(void) { struct uniphier_dram_map dram_map[3] = {}; - unsigned long base, top; - bool valid_bank_found = false; int ret, i; ret = uniphier_dram_map_get(dram_map); @@ -287,18 +288,7 @@ int dram_init_banksize(void) if (!dram_map[i].size) continue; - - if (!valid_bank_found) - base = dram_map[i].base; - top = dram_map[i].base + dram_map[i].size; - valid_bank_found = true; } - if (!valid_bank_found) - return -EINVAL; - - /* map all the DRAM regions */ - uniphier_mem_map_init(base, top - base); - return 0; } diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig index edff5b039e9..54fb93aeb53 100644 --- a/arch/arm/mach-versal-net/Kconfig +++ b/arch/arm/mach-versal-net/Kconfig @@ -13,14 +13,6 @@ config SYS_VENDOR config SYS_SOC default "versal-net" -config SYS_CONFIG_NAME - string "Board configuration name" - default "xilinx_versal_net" - help - This option contains information about board configuration name. - Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header - will be used for board configuration. - config COUNTER_FREQUENCY int "Timer clock frequency" default 0 @@ -43,6 +35,9 @@ config SYS_MEM_RSVD_FOR_MMU config GICV3 def_bool y +config GICV3_SUPPORT_GIC600 + def_bool y + config SYS_MALLOC_LEN default 0x2000000 diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig index 645f06add44..629a14129d5 100644 --- a/arch/arm/mach-versal/Kconfig +++ b/arch/arm/mach-versal/Kconfig @@ -13,14 +13,6 @@ config SYS_VENDOR config SYS_SOC default "versal" -config SYS_CONFIG_NAME - string "Board configuration name" - default "xilinx_versal" - help - This option contains information about board configuration name. - Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header - will be used for board configuration. - config SYS_MALLOC_LEN default 0x2000000 diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index b4c439b4cd6..265e9ce588a 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -43,14 +43,6 @@ config SYS_VENDOR config SYS_SOC default "zynq" -config SYS_CONFIG_NAME - string "Board configuration name" - default "zynq-common" - help - This option contains information about board configuration name. - Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header - will be used for board configuration. - config SYS_MALLOC_F_LEN default 0x800 diff --git a/arch/arm/mach-zynq/u-boot-spl.lds b/arch/arm/mach-zynq/u-boot-spl.lds index 8c18d3f91f4..d96a5770288 100644 --- a/arch/arm/mach-zynq/u-boot-spl.lds +++ b/arch/arm/mach-zynq/u-boot-spl.lds @@ -18,9 +18,9 @@ ENTRY(_start) SECTIONS { . = ALIGN(4); + __image_copy_start = ADDR(.text); .text : { - __image_copy_start = .; *(.vectors) CPUDIR/start.o (.text*) *(.text*) diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds index 3b7c9d515f8..3e0c96c5055 100644 --- a/arch/arm/mach-zynq/u-boot.lds +++ b/arch/arm/mach-zynq/u-boot.lds @@ -14,26 +14,20 @@ SECTIONS . = 0x00000000; . = ALIGN(4); + __image_copy_start = ADDR(.text); .text : { - *(.__image_copy_start) *(.vectors) CPUDIR/start.o (.text*) } /* This needs to come before *(.text*) */ - .__efi_runtime_start : { - *(.__efi_runtime_start) - } - .efi_runtime : { + __efi_runtime_start = .; *(.text.efi_runtime*) *(.rodata.efi_runtime*) *(.data.efi_runtime*) - } - - .__efi_runtime_stop : { - *(.__efi_runtime_stop) + __efi_runtime_stop = .; } .text_rest : @@ -58,41 +52,20 @@ SECTIONS KEEP(*(SORT(__u_boot_list*))); } - . = ALIGN(4); - - .efi_runtime_rel_start : - { - *(.__efi_runtime_rel_start) - } - .efi_runtime_rel : { + __efi_runtime_rel_start = .; *(.rel*.efi_runtime) *(.rel*.efi_runtime.*) - } - - .efi_runtime_rel_stop : - { - *(.__efi_runtime_rel_stop) + __efi_runtime_rel_stop = .; } . = ALIGN(8); - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } + __image_copy_end = .; - .rel.dyn : { + .rel.dyn ALIGN(8) : { + __rel_dyn_start = .; *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) + __rel_dyn_end = .; } .end : @@ -103,23 +76,15 @@ SECTIONS _image_binary_end = .; /* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) + * These sections occupy the same memory, but their lifetimes do + * not overlap: U-Boot initializes .bss only after applying dynamic + * relocations and therefore after it doesn't need .rel.dyn any more. */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { + .bss ADDR(.rel.dyn) (OVERLAY): { + __bss_start = .; *(.bss*) - . = ALIGN(8); - __bss_limit = .; - } - - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); + . = ALIGN(8); + __bss_end = .; } /* diff --git a/arch/arm/mach-zynqmp-r5/Kconfig b/arch/arm/mach-zynqmp-r5/Kconfig index f14514b3c7c..b2ba896e9b4 100644 --- a/arch/arm/mach-zynqmp-r5/Kconfig +++ b/arch/arm/mach-zynqmp-r5/Kconfig @@ -13,14 +13,6 @@ config SYS_VENDOR config SYS_SOC default "zynqmp-r5" -config SYS_CONFIG_NAME - string "Board configuration name" - default "xilinx_zynqmp_r5" - help - This option contains information about board configuration name. - Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header - will be used for board configuration. - config CPU_FREQ_HZ int "CPU frequency" default 800000000 diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 7e7c87d16fa..0d2238ace1e 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -1,29 +1,5 @@ if ARCH_ZYNQMP -config SPL_FS_FAT - default y - -config SPL_LIBCOMMON_SUPPORT - default y - -config SPL_LIBDISK_SUPPORT - default y - -config SPL_LIBGENERIC_SUPPORT - default y - -config SPL_MMC - default y if MMC_SDHCI_ZYNQ - -config SPL_SERIAL - default y - -config SPL_SPI_FLASH_SUPPORT - default y if ZYNQ_QSPI - -config SPL_SPI - default y if ZYNQ_QSPI - config SYS_BOARD string "Board name" default "zynqmp" @@ -35,14 +11,6 @@ config SYS_VENDOR config SYS_SOC default "zynqmp" -config SYS_CONFIG_NAME - string "Board configuration name" - default "xilinx_zynqmp" - help - This option contains information about board configuration name. - Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header - will be used for board configuration. - config SYS_MEM_RSVD_FOR_MMU bool "Reserve memory for MMU Table" help @@ -143,7 +111,8 @@ config ZYNQMP_PSU_INIT_ENABLED config SPL_ZYNQMP_PSU_INIT_ENABLED bool "Include psu_init in SPL" - default y if SPL + depends on SPL + default y select BOARD_EARLY_INIT_F help Include psu_init by default in SPL. diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index a0f35f36faa..979ff3aef6c 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -9,6 +9,7 @@ #include <image.h> #include <init.h> #include <log.h> +#include <semihosting.h> #include <spl.h> #include <linux/delay.h> @@ -66,6 +67,11 @@ void spl_board_init(void) } #endif +static u32 jtag_boot_device(void) +{ + return semihosting_enabled() ? BOOT_DEVICE_SMH : BOOT_DEVICE_RAM; +} + void board_boot_order(u32 *spl_boot_list) { spl_boot_list[0] = spl_boot_device(); @@ -75,7 +81,7 @@ void board_boot_order(u32 *spl_boot_list) if (spl_boot_list[0] == BOOT_DEVICE_MMC2) spl_boot_list[1] = BOOT_DEVICE_MMC1; - spl_boot_list[2] = BOOT_DEVICE_RAM; + spl_boot_list[2] = jtag_boot_device(); } u32 spl_boot_device(void) @@ -85,19 +91,20 @@ u32 spl_boot_device(void) #if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED) /* Change default boot mode at run-time */ + reg = CONFIG_SPL_ZYNQMP_ALT_BOOTMODE; writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT, &crlapb_base->boot_mode); -#endif - +#else reg = readl(&crlapb_base->boot_mode); if (reg >> BOOT_MODE_ALT_SHIFT) reg >>= BOOT_MODE_ALT_SHIFT; +#endif bootmode = reg & BOOT_MODES_MASK; switch (bootmode) { case JTAG_MODE: - return BOOT_DEVICE_RAM; + return jtag_boot_device(); #ifdef CONFIG_SPL_MMC case SD_MODE1: case SD1_LSHFT_MODE: /* not working on silicon v1 */ diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f0704d97f79..eb7f3ad2376 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -473,12 +473,6 @@ config MIPS_TUNE_74KC config MIPS_TUNE_OCTEON3 bool -config 32BIT - bool - -config 64BIT - bool - config SWAP_IO_SPACE bool diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h index 3ba33d27c17..58c89d5e645 100644 --- a/arch/mips/mach-mscc/include/mach/ddr.h +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -225,7 +225,7 @@ #define VC3_MPAR_FAW VC3_MPAR_tFAW #define VC3_MPAR_BL 4 #define MSCC_MEMPARM_MR0 ((VC3_MPAR_RL - 4) << 4) | ((VC3_MPAR_tWR - 4) << 9) -/* ODT_RTT: “0x0040” for 120ohm, and “0x0004” for 60ohm. */ +/* ODT_RTT: "0x0040" for 120ohm, and "0x0004" for 60ohm. */ #define MSCC_MEMPARM_MR1 0x0040 #define MSCC_MEMPARM_MR2 ((VC3_MPAR_WL - 5) << 3) #define MSCC_MEMPARM_MR3 0 diff --git a/arch/mips/mach-mtmips/mt7620/Kconfig b/arch/mips/mach-mtmips/mt7620/Kconfig index 3ca711ad0f3..398c7c6a948 100644 --- a/arch/mips/mach-mtmips/mt7620/Kconfig +++ b/arch/mips/mach-mtmips/mt7620/Kconfig @@ -67,7 +67,6 @@ config CPU_FREQ_MULTI default 7 if CPU_FREQ_620MHZ config SYS_CONFIG_NAME - string "Board configuration name" default "mt7620" if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB config SYS_BOARD diff --git a/arch/mips/mach-mtmips/mt7621/Kconfig b/arch/mips/mach-mtmips/mt7621/Kconfig index 008a28f991c..8fe6e0a2d9a 100644 --- a/arch/mips/mach-mtmips/mt7621/Kconfig +++ b/arch/mips/mach-mtmips/mt7621/Kconfig @@ -102,7 +102,6 @@ config BOARD_MT7621_NAND_RFB endchoice config SYS_CONFIG_NAME - string "Board configuration name" default "mt7621" if BOARD_MT7621_RFB || BOARD_MT7621_NAND_RFB config SYS_BOARD diff --git a/arch/mips/mach-mtmips/mt7628/Kconfig b/arch/mips/mach-mtmips/mt7628/Kconfig index e7273591bca..79b2ddc6692 100644 --- a/arch/mips/mach-mtmips/mt7628/Kconfig +++ b/arch/mips/mach-mtmips/mt7628/Kconfig @@ -49,7 +49,6 @@ config SYS_BOARD default "mt7628" if BOARD_MT7628_RFB config SYS_CONFIG_NAME - string "Board configuration name" default "mt7628" if BOARD_MT7628_RFB source "board/gardena/smart-gateway-mt7688/Kconfig" diff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-pki.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-pki.h index ff32dab67b5..25e2877469a 100644 --- a/arch/mips/mach-octeon/include/mach/cvmx-helper-pki.h +++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-pki.h @@ -267,7 +267,7 @@ void cvmx_helper_pki_set_fcs_op(int node, int interface, int nports, int has_fcs * buffer separate from the work queue entry. Words following the * WQE in the same cache line will be zeroed, other lines in the * buffer will not be modified and will retain stale data (from the - * buffer’s previous use). This setting may decrease the peak PKI + * buffer's previous use). This setting may decrease the peak PKI * performance by up to half on small packets. */ void cvmx_helper_pki_set_wqe_mode(int node, bool pkt_outside_wqe); diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pki.h b/arch/mips/mach-octeon/include/mach/cvmx-pki.h index c1feb55a1f0..d918f792eee 100644 --- a/arch/mips/mach-octeon/include/mach/cvmx-pki.h +++ b/arch/mips/mach-octeon/include/mach/cvmx-pki.h @@ -110,8 +110,8 @@ enum cvmx_pki_wqe_vlan { CVMX_PKI_USE_FIRST_VLAN = 0, CVMX_PKI_USE_SECOND_VLAN } * Controls how the PKI statistics counters are handled * The PKI_STAT*_X registers can be indexed either by port kind (pkind), or * final style. (Does not apply to the PKI_STAT_INB* registers.) - * 0 = X represents the packet’s pkind - * 1 = X represents the low 6-bits of packet’s final style + * 0 = X represents the packet's pkind + * 1 = X represents the low 6-bits of packet's final style */ enum cvmx_pki_stats_mode { CVMX_PKI_STAT_MODE_PKIND, CVMX_PKI_STAT_MODE_STYLE }; @@ -880,7 +880,7 @@ int cvmx_pki_get_pkind_style(int node, int pkind); * buffer separate from the work queue entry. Words following the * WQE in the same cache line will be zeroed, other lines in the * buffer will not be modified and will retain stale data (from the - * buffer’s previous use). This setting may decrease the peak PKI + * buffer's previous use). This setting may decrease the peak PKI * performance by up to half on small packets. */ void cvmx_pki_set_wqe_mode(int node, u64 style, bool pkt_outside_wqe); diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pko3.h b/arch/mips/mach-octeon/include/mach/cvmx-pko3.h index 86f89be855f..bda607203f3 100644 --- a/arch/mips/mach-octeon/include/mach/cvmx-pko3.h +++ b/arch/mips/mach-octeon/include/mach/cvmx-pko3.h @@ -366,7 +366,7 @@ enum cvmx_pko_memalg_e { */ MEMALG_SETRSLT = 2, /* [DSZ] = B64; mem = PKO_MEM_RESULT_S. */ MEMALG_ADD = 8, /* mem = mem + PKO_SEND_MEM_S[OFFSET] */ - MEMALG_SUB = 9, /* mem = mem – PKO_SEND_MEM_S[OFFSET] */ + MEMALG_SUB = 9, /* mem = mem - PKO_SEND_MEM_S[OFFSET] */ MEMALG_ADDLEN = 0xA, /* mem += [OFFSET] + PKO_SEND_HDR_S[TOTAL] */ MEMALG_SUBLEN = 0xB, /* mem -= [OFFSET] + PKO_SEND_HDR_S[TOTAL] */ MEMALG_ADDMBUF = 0xC, /* mem += [OFFSET] + mbufs_freed */ diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig index bb4fb2ac3a5..b06b3efcf56 100644 --- a/arch/nios2/Kconfig +++ b/arch/nios2/Kconfig @@ -4,11 +4,4 @@ menu "Nios II architecture" config SYS_ARCH default "nios2" -config SYS_CONFIG_NAME - string "Board header file" - help - This option should contain the base name of board header file. - The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h - should be included from include/config.h. - endmenu diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index aac4203a6e4..d1abe8f00bf 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -92,6 +92,12 @@ void cpu_init_f(immap_t __iomem *immr) CONFIG_SYS_PLPRCR); #endif + /* Set SDMA configuration register */ + if (IS_ENABLED(CONFIG_MPC885)) + out_be32(&immr->im_siu_conf.sc_sdcr, 0x0040); + else + out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001); + /* * Memory Controller: */ diff --git a/arch/powerpc/dts/cmpc885.dts b/arch/powerpc/dts/cmpc885.dts index 7b9566a0fa4..454ceb91ca0 100644 --- a/arch/powerpc/dts/cmpc885.dts +++ b/arch/powerpc/dts/cmpc885.dts @@ -83,13 +83,23 @@ spi: spi@aa0 { status = "okay"; #address-cells = <1>; - #size-cells = <1>; - cell-index = <0>; + #size-cells = <0>; compatible = "fsl,mpc8xx-spi"; - gpios = <&CPM1_PIO_B 21 1>; /* /EEPROM_CS ACTIVE_LOW */ + gpios = <&CPM1_PIO_B 21 1 /* /EEPROM_CS ACTIVE_LOW */ + &CPM1_PIO_B 23 1 /* Temperature mother board */ + &CPM1_PIO_B 14 1>; /* Temperature CPU board */ eeprom@0 { - cell-index = <1>; + reg = <0>; + compatible = "atmel,at25", "cs,eeprom"; + }; + temp@1 { + reg = <1>; + compatible = "ti,lm74"; + }; + temp@2 { + reg = <2>; + compatible = "ti,lm74"; }; }; }; diff --git a/arch/powerpc/dts/cmpcpro.dts b/arch/powerpc/dts/cmpcpro.dts index c27d9dba335..1dfa864ebba 100644 --- a/arch/powerpc/dts/cmpcpro.dts +++ b/arch/powerpc/dts/cmpcpro.dts @@ -140,11 +140,21 @@ compatible = "fsl,mpc832x-spi"; reg = <0x4c0 0x40>; mode = "cpu"; - gpios = <&qe_pio_d 3 1>; + gpios = <&qe_pio_d 3 1 + &qe_pio_c 5 1 /* TEMP mother board */ + &qe_pio_c 3 1>; /* TEMP CPU board */ clock-frequency = <0>; - eeprom@3 { + eeprom@0 { + reg = <0>; compatible = "atmel,at25", "cs,eeprom"; - cell-index = <1>; + }; + temp@1 { + reg = <1>; + compatible = "ti,lm74"; + }; + temp@2 { + reg = <2>; + compatible = "ti,lm74"; }; }; eth0: ucc@3000 { diff --git a/arch/powerpc/dts/mcr3000.dts b/arch/powerpc/dts/mcr3000.dts index c4d7737bc67..aa46007b8d9 100644 --- a/arch/powerpc/dts/mcr3000.dts +++ b/arch/powerpc/dts/mcr3000.dts @@ -26,6 +26,47 @@ timeout-sec = <2>; hw_margin_ms = <1000>; }; + + spi: spi@aa0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,mpc8xx-spi"; + gpios = <&csspi 2 0 + &csspi 0 0>; + + temp@0 { + reg = <0>; + compatible = "ti,lm74"; + }; + fpga@1 { + reg = <1>; + }; + }; + }; + + localbus@ff000100 { + compatible = "s3k,mcr3000-localbus", "fsl,pq1-localbus", "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xff000100 0x40>; // ORx and BRx register + + ranges = <0 0 0x04000000 0x04000000 // BOOT + 1 0 0x00000000 0x04000000 // SDRAM + 2 0 0x08000000 0x04000000 // RAMDP + 3 0 0x0C000000 0x04000000 // NAND + 4 0 0x10000000 0x04000000 // Periphs + 5 0 0x14000000 0x04000000 // FPGA + 6 0 0x18000000 0x04000000 // mezzanine + 7 0 0x1c000000 0x04000000>; // DSP + + csspi: gpio-controller@2 { + #gpio-cells = <2>; + compatible = "s3k,mcr3000-cpld-csspi"; + reg = <4 0x802 2>; + gpio-controller; + }; }; SERIAL: smc@0 { diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ac52c5e6daf..7e20ef63bba 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -22,6 +22,7 @@ config TARGET_OPENPITON_RISCV64 config TARGET_QEMU_VIRT bool "Support QEMU Virt Board" + select BOARD_LATE_INIT config TARGET_SIFIVE_UNLEASHED bool "Support SiFive Unleashed Board" @@ -93,6 +94,7 @@ source "board/xilinx/mbv/Kconfig" # platform-specific options below source "arch/riscv/cpu/andesv5/Kconfig" +source "arch/riscv/cpu/cv1800b/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" @@ -119,6 +121,26 @@ config ARCH_RV64I endchoice +config FRAMEPOINTER + bool "Build with frame pointer for stack unwinding" + help + Choose this option to use the frame pointer so the stack can be + unwound if needed. This is useful for tracing where faults came + from as the source may be several functions back + + If you say Y here, then the code size will be increased due to + having to store the fp. + +config SPL_FRAMEPOINTER + bool "Build SPL with frame pointer for stack unwinding" + help + Choose this option to use the frame pointer so the stack can be + unwound if needed. This is useful for tracing where faults came + from as the source may be several functions back + + If you say Y here, then the code size will be increased due to + having to store the fp. + choice prompt "Code Model" default CMODEL_MEDLOW @@ -288,12 +310,6 @@ endmenu config RISCV_ISA_A def_bool y -config 32BIT - bool - -config 64BIT - bool - config DMA_ADDR_T_64BIT bool default y if 64BIT diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index b3ef87078b5..c36a8533e0f 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -48,6 +48,10 @@ endif ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ -mcmodel=$(CMODEL) +ifeq ($(CONFIG_$(SPL_)FRAMEPOINTER),y) + ARCH_FLAGS += -fno-omit-frame-pointer +endif + PLATFORM_CPPFLAGS += $(ARCH_FLAGS) CFLAGS_EFI += $(ARCH_FLAGS) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index ecfefa1a025..affe70081b5 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -38,35 +38,51 @@ static inline bool supports_extension(char ext) #if CONFIG_IS_ENABLED(RISCV_MMODE) return csr_read(CSR_MISA) & (1 << (ext - 'a')); #elif CONFIG_CPU + char sext[2] = {ext}; struct udevice *dev; - char desc[32]; - int i; + const char *isa; + int ret, i; uclass_find_first_device(UCLASS_CPU, &dev); if (!dev) { debug("unable to find the RISC-V cpu device\n"); return false; } - if (!cpu_get_desc(dev, desc, sizeof(desc))) { - /* - * skip the first 4 characters (rv32|rv64) - */ - for (i = 4; i < sizeof(desc); i++) { - switch (desc[i]) { - case 's': - case 'x': - case 'z': - case '_': - case '\0': - /* - * Any of these characters mean the single - * letter extensions have all been consumed. - */ - return false; - default: - if (desc[i] == ext) - return true; - } + + ret = dev_read_stringlist_search(dev, "riscv,isa-extensions", sext); + if (ret >= 0) + return true; + + /* + * Only if the property is not found (ENODATA) is the fallback to + * riscv,isa used, otherwise the extension is not present in this + * CPU. + */ + if (ret != -ENODATA) + return false; + + isa = dev_read_string(dev, "riscv,isa"); + if (!isa) + return false; + + /* + * Skip the first 4 characters (rv32|rv64). + */ + for (i = 4; i < sizeof(isa); i++) { + switch (isa[i]) { + case 's': + case 'x': + case 'z': + case '_': + case '\0': + /* + * Any of these characters mean the single + * letter extensions have all been consumed. + */ + return false; + default: + if (isa[i] == ext) + return true; } } diff --git a/arch/riscv/cpu/cv1800b/Kconfig b/arch/riscv/cpu/cv1800b/Kconfig new file mode 100644 index 00000000000..7225b1210c5 --- /dev/null +++ b/arch/riscv/cpu/cv1800b/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + +config SOPHGO_CV1800B + bool + select ARCH_EARLY_INIT_R + select SYS_CACHE_SHIFT_6 + imply CPU + imply CPU_RISCV + imply RISCV_TIMER + imply CMD_CPU diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile new file mode 100644 index 00000000000..95beb34b51a --- /dev/null +++ b/arch/riscv/cpu/cv1800b/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + +obj-y += dram.o +obj-y += cpu.o +obj-y += cache.o diff --git a/arch/riscv/cpu/cv1800b/cache.c b/arch/riscv/cpu/cv1800b/cache.c new file mode 100644 index 00000000000..b8051e29e02 --- /dev/null +++ b/arch/riscv/cpu/cv1800b/cache.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + */ + +#include <cpu_func.h> + +/* + * dcache.ipa rs1 (invalidate) + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000001 01010 rs1 000 00000 0001011 + * + * dcache.cpa rs1 (clean) + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000001 01001 rs1 000 00000 0001011 + * + * dcache.cipa rs1 (clean then invalidate) + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000001 01011 rs1 000 00000 0001011 + * + * sync.s + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000000 11001 00000 000 00000 0001011 + */ +#define DCACHE_IPA_A0 ".long 0x02a5000b" +#define DCACHE_CPA_A0 ".long 0x0295000b" +#define DCACHE_CIPA_A0 ".long 0x02b5000b" + +#define SYNC_S ".long 0x0190000b" + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1); + for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE) + __asm__ __volatile__(DCACHE_IPA_A0); + __asm__ __volatile__(SYNC_S); +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1); + for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE) + __asm__ __volatile__(DCACHE_CPA_A0); + __asm__ __volatile__(SYNC_S); +} diff --git a/arch/riscv/cpu/cv1800b/cpu.c b/arch/riscv/cpu/cv1800b/cpu.c new file mode 100644 index 00000000000..233a6a3d64e --- /dev/null +++ b/arch/riscv/cpu/cv1800b/cpu.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + */ + +int cleanup_before_linux(void) +{ + return 0; +} diff --git a/arch/riscv/cpu/cv1800b/dram.c b/arch/riscv/cpu/cv1800b/dram.c new file mode 100644 index 00000000000..91007c0a3d3 --- /dev/null +++ b/arch/riscv/cpu/cv1800b/dram.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <fdtdec.h> +#include <init.h> +#include <asm/global_data.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 6cecadfac56..a9e19356928 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -418,6 +418,7 @@ call_board_init_r: */ mv a0, s3 /* gd_t */ mv a1, s4 /* dest_addr */ + mv s0, zero /* fp == NULL */ /* * jump to it ... diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts b/arch/riscv/dts/cv1800b-milkv-duo.dts index 3af9e34b3bc..94e64ddce8f 100644 --- a/arch/riscv/dts/cv1800b-milkv-duo.dts +++ b/arch/riscv/dts/cv1800b-milkv-duo.dts @@ -33,6 +33,14 @@ clock-frequency = <25000000>; }; +&sdhci0 { + status = "okay"; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sdio; +}; + &uart0 { status = "okay"; }; diff --git a/arch/riscv/dts/cv1800b.dtsi b/arch/riscv/dts/cv1800b.dtsi index 165e9e320a8..baf641829e7 100644 --- a/arch/riscv/dts/cv1800b.dtsi +++ b/arch/riscv/dts/cv1800b.dtsi @@ -16,3 +16,7 @@ &clint { compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; }; + +&clk { + compatible = "sophgo,cv1800-clk"; +}; diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi index 2d6f4a4b1e5..ec99c4deeb6 100644 --- a/arch/riscv/dts/cv18xx.dtsi +++ b/arch/riscv/dts/cv18xx.dtsi @@ -45,6 +45,13 @@ #clock-cells = <0>; }; + sdhci_clk: sdhci-clock { + compatible = "fixed-clock"; + clock-frequency = <375000000>; + clock-output-names = "sdhci_clk"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -53,6 +60,12 @@ dma-noncoherent; ranges; + clk: clock-controller@3002000 { + reg = <0x03002000 0x1000>; + clocks = <&osc>; + #clock-cells = <1>; + }; + gpio0: gpio@3020000 { compatible = "snps,dw-apb-gpio"; reg = <0x3020000 0x1000>; @@ -175,6 +188,15 @@ status = "disabled"; }; + sdhci0: mmc@4310000 { + compatible = "sophgo,cv1800b-dwcmshc"; + reg = <0x4310000 0x1000>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sdhci_clk>; + clock-names = "core"; + status = "disabled"; + }; + plic: interrupt-controller@70000000 { reg = <0x70000000 0x4000000>; interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi index f2c6bec9298..e11babc1cde 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi @@ -298,7 +298,7 @@ pinctrl-0 = <&mmc1_pins>; no-sdio; no-mmc; - broken-cd; + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; cap-sd-highspeed; post-power-on-delay-ms = <200>; status = "okay"; diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts index 94e42c26811..48ee1154956 100644 --- a/arch/riscv/dts/xilinx-mbv32.dts +++ b/arch/riscv/dts/xilinx-mbv32.dts @@ -8,6 +8,9 @@ */ /dts-v1/; + +#include "binman.dtsi" + / { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h b/arch/riscv/include/asm/arch-jh7110/eeprom.h index d2776d5b6cb..62d184aeb57 100644 --- a/arch/riscv/include/asm/arch-jh7110/eeprom.h +++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h @@ -12,4 +12,13 @@ u8 get_pcb_revision_from_eeprom(void); u32 get_ddr_size_from_eeprom(void); +/** + * get_product_id_from_eeprom - get product ID string + * + * A string like "VF7110A1-2228-D008E000-00000001" is returned. + * + * Return: product ID string + */ +const char *get_product_id_from_eeprom(void); + #endif /* _ASM_RISCV_EEPROM_H */ diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S index 46b08552371..c7a4559eac8 100644 --- a/arch/riscv/lib/crt0_riscv_efi.S +++ b/arch/riscv/lib/crt0_riscv_efi.S @@ -96,7 +96,11 @@ extra_header_fields: .long _start - ImageBase /* SizeOfHeaders */ .long 0 /* CheckSum */ .short IMAGE_SUBSYSTEM_EFI_APPLICATION /* Subsystem */ +#if CONFIG_VENDOR_EFI .short 0 /* DllCharacteristics */ +#else + .short IMAGE_DLLCHARACTERISTICS_NX_COMPAT +#endif #if __riscv_xlen == 32 .long 0 /* SizeOfStackReserve */ .long 0 /* SizeOfStackCommit */ diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index a26ccc721fd..7350e2ced85 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -60,6 +60,40 @@ static void show_regs(struct pt_regs *regs) #endif } +#if defined(CONFIG_FRAMEPOINTER) || defined(CONFIG_SPL_FRAMEPOINTER) +static void show_backtrace(struct pt_regs *regs) +{ + uintptr_t *fp = (uintptr_t *)regs->s0; + unsigned count = 0; + ulong ra; + + printf("backtrace:\n"); + + /* there are a few entry points where the s0 register is + * set to gd, so to avoid changing those, just abort if + * the value is the same */ + while (fp != NULL && fp != (uintptr_t *)gd) { + ra = fp[-1]; + printf("backtrace %2d: FP: " REG_FMT " RA: " REG_FMT, + count, (ulong)fp, ra); + + if (gd && gd->flags & GD_FLG_RELOC) + printf(" - RA: " REG_FMT " reloc adjusted\n", + ra - gd->reloc_off); + else + printf("\n"); + + fp = (uintptr_t *)fp[-2]; + count++; + } +} +#else +static void show_backtrace(struct pt_regs *regs) +{ + printf("No backtrace support enabled\n"); +} +#endif + /** * instr_len() - get instruction length * @@ -131,6 +165,7 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) epc - gd->reloc_off, regs->ra - gd->reloc_off); show_regs(regs); + show_backtrace(regs); show_code(epc); show_efi_loaded_images(epc); panic("\n"); diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 0ce77de2fcb..1c8353d6156 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -58,10 +58,15 @@ config SANDBOX_CRASH_RESET bool "Reset on crash" help If an illegal instruction or an illegal memory access occurs, the - sandbox by default writes a crash dump and exits. If you set this - flag, the sandbox is reset instead. This may be useful when running - test suites like the UEFI self certification test which continue - with the next test after a crash. + sandbox exits with an error by default. + + If the u-boot binary is invoked with --signals (or -S), U-Boot will + handle the signal writing a crash dump before exiting. + + If you additionally set the CONFIG_SANDBOX_CRASH_RESET flag, the + sandbox is reset after writing the crash dump. This may be useful + when running test suites like the UEFI self certification test which + continue with the next test after a crash. config SANDBOX_BITS_PER_LONG int diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index 1d50991f8d2..405843800e9 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -69,5 +69,3 @@ EFI_LDS := ${SRCDIR}/../../../arch/riscv/lib/elf_riscv64_efi.lds endif EFI_CRT0 := crt0_sandbox_efi.o EFI_RELOC := reloc_sandbox_efi.o -AFLAGS_crt0_sandbox_efi.o += -DHOST_ARCH="$(HOST_ARCH)" -CFLAGS_reloc_sandbox_efi.o += -DHOST_ARCH="$(HOST_ARCH)" diff --git a/arch/sandbox/cpu/eth-raw-os.c b/arch/sandbox/cpu/eth-raw-os.c index 92c35aed95d..39ea3b3f012 100644 --- a/arch/sandbox/cpu/eth-raw-os.c +++ b/arch/sandbox/cpu/eth-raw-os.c @@ -105,7 +105,12 @@ static int _raw_packet_start(struct eth_sandbox_raw_priv *priv, /* Make the socket non-blocking */ flags = fcntl(priv->sd, F_GETFL, 0); - fcntl(priv->sd, F_SETFL, flags | O_NONBLOCK); + ret = fcntl(priv->sd, F_SETFL, flags | O_NONBLOCK); + if (ret == -1) { + printf("Failed to make socket non-blocking: %d %s\n", errno, + strerror(errno)); + return -errno; + } /* Enable promiscuous mode to receive responses meant for us */ mr.mr_ifindex = device->sll_ifindex; @@ -172,7 +177,12 @@ static int _local_inet_start(struct eth_sandbox_raw_priv *priv) /* Make the socket non-blocking */ flags = fcntl(priv->sd, F_GETFL, 0); - fcntl(priv->sd, F_SETFL, flags | O_NONBLOCK); + ret = fcntl(priv->sd, F_SETFL, flags | O_NONBLOCK); + if (ret == -1) { + printf("Failed to make socket non-blocking: %d %s\n", errno, + strerror(errno)); + return -errno; + } /* Include the UDP/IP headers on send and receive */ ret = setsockopt(priv->sd, IPPROTO_IP, IP_HDRINCL, &one, diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index cbae5109e85..154a5d77490 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -188,7 +188,7 @@ int os_read_file(const char *fname, void **bufp, int *sizep) fd = os_open(fname, OS_O_RDONLY); if (fd < 0) { printf("Cannot open file '%s'\n", fname); - goto err; + return -EIO; } size = os_filesize(fd); if (size < 0) { diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 12d3eff5fa7..8392206eea6 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -106,3 +106,7 @@ #if IS_ENABLED(CONFIG_SUPPORT_VPL) #include "sandbox_vpl.dtsi" #endif + +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) +#include "sandbox_capsule.dtsi" +#endif diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi index 241f397ba6e..c93ce712894 100644 --- a/arch/sandbox/dts/sandbox.dtsi +++ b/arch/sandbox/dts/sandbox.dtsi @@ -419,17 +419,16 @@ #size-cells = <0x1>; pm8916@0 { compatible = "qcom,spmi-pmic"; - reg = <0x0 0x1>; + reg = <0x0 0x0>; #address-cells = <0x1>; - #size-cells = <0x1>; + #size-cells = <0x0>; spmi_gpios: gpios@c000 { compatible = "qcom,pm8916-gpio"; - reg = <0xc000 0x400>; + reg = <0xc000>; gpio-controller; - gpio-count = <4>; + gpio-ranges = <&spmi_gpios 0 0 4>; #gpio-cells = <2>; - gpio-bank-name="spmi"; }; }; }; diff --git a/arch/sandbox/dts/sandbox_capsule.dtsi b/arch/sandbox/dts/sandbox_capsule.dtsi new file mode 100644 index 00000000000..34d29916b30 --- /dev/null +++ b/arch/sandbox/dts/sandbox_capsule.dtsi @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Devicetree file with binman nodes needed for generating EFI + * capsules. + * + */ + +#include <sandbox_efi_capsule.h> + +/ { + binman: binman { + multiple-images; + }; +}; + +&binman { + capsule1 { + filename = "Test01"; + efi-capsule { + image-index = <0x1>; + image-guid = SANDBOX_UBOOT_IMAGE_GUID; + + text { + text = "u-boot:New"; + }; + }; + }; + + capsule2 { + filename = "Test02"; + efi-capsule { + image-index = <0x2>; + image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID; + + text { + text = "u-boot-env:New"; + }; + }; + }; + + capsule3 { + filename = "Test03"; + efi-capsule { + image-index = <0x1>; + image-guid = SANDBOX_INCORRECT_GUID; + + text { + text = "u-boot:New"; + }; + }; + }; + + capsule4 { + filename = "Test101"; + efi-capsule { + image-index = <0x1>; + fw-version = <0x5>; + image-guid = SANDBOX_UBOOT_IMAGE_GUID; + + text { + text = "u-boot:New"; + }; + }; + }; + + capsule5 { + filename = "Test102"; + efi-capsule { + image-index = <0x2>; + fw-version = <0xa>; + image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID; + + text { + text = "u-boot-env:New"; + }; + }; + }; + + capsule6 { + filename = "Test103"; + efi-capsule { + image-index = <0x1>; + fw-version = <0x2>; + image-guid = SANDBOX_UBOOT_IMAGE_GUID; + + text { + text = "u-boot:New"; + }; + }; + }; + + capsule7 { + filename = "Test11"; + efi-capsule { + image-index = <0x1>; + image-guid = SANDBOX_UBOOT_IMAGE_GUID; + private-key = CAPSULE_PRIV_KEY; + public-key-cert = CAPSULE_PUB_KEY; + monotonic-count = <0x1>; + + text { + text = "u-boot:New"; + }; + }; + }; + + capsule8 { + filename = "Test12"; + efi-capsule { + image-index = <0x1>; + image-guid = SANDBOX_UBOOT_IMAGE_GUID; + private-key = CAPSULE_INVAL_KEY; + public-key-cert = CAPSULE_INVAL_PUB_KEY; + monotonic-count = <0x1>; + + text { + text = "u-boot:New"; + }; + }; + }; + + capsule9 { + filename = "Test111"; + efi-capsule { + image-index = <0x1>; + fw-version = <0x5>; + image-guid = SANDBOX_UBOOT_IMAGE_GUID; + private-key = CAPSULE_PRIV_KEY; + public-key-cert = CAPSULE_PUB_KEY; + monotonic-count = <0x1>; + + text { + text = "u-boot:New"; + }; + }; + }; + + capsule10 { + filename = "Test112"; + efi-capsule { + image-index = <0x2>; + fw-version = <0xa>; + image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID; + private-key = CAPSULE_PRIV_KEY; + public-key-cert = CAPSULE_PUB_KEY; + monotonic-count = <0x1>; + + text { + text = "u-boot-env:New"; + }; + }; + }; + + capsule11 { + filename = "Test113"; + efi-capsule { + image-index = <0x1>; + fw-version = <0x2>; + image-guid = SANDBOX_UBOOT_IMAGE_GUID; + private-key = CAPSULE_PRIV_KEY; + public-key-cert = CAPSULE_PUB_KEY; + monotonic-count = <0x1>; + + text { + text = "u-boot:New"; + }; + }; + }; +}; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index e264b29554c..a012f5c4c9b 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -1990,4 +1990,8 @@ #include "sandbox_vpl.dtsi" #endif +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) +#include "sandbox_capsule.dtsi" +#endif + #include "cedit.dtsi" diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c index 8dbcd9ff7dd..44ba8b52e13 100644 --- a/arch/sandbox/lib/bootm.c +++ b/arch/sandbox/lib/bootm.c @@ -85,5 +85,7 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) int booti_setup(ulong image, ulong *relocated_addr, ulong *size, bool force_reloc) { - return 0; + log_err("Booting is not supported on the sandbox.\n"); + + return 1; } diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 99e59d94c60..23a1e21b29e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -723,6 +723,14 @@ config ROM_TABLE_SIZE hex default 0x10000 +config X86_HARDFP + bool "Support hardware floating point" + help + U-Boot generally does not make use of floating point. Where this is + needed, it can be enabled using this option. This adjusts the + start-up code for 64-bit mode and changes the compiler options for + 64-bit to enable SSE. + config HAVE_ITSS bool "Enable ITSS" help @@ -1053,4 +1061,12 @@ config SPL_COREBOOT_SYSINFO display, memory and build information. It is stored in struct sysinfo_t after parsing by get_coreboot_info(). +config ZBOOT + bool "Support the zImage format" + default y + help + Enable this to support booting the x86-specific zImage format. This + uses a special, binary format containing information about the Linux + format to boot. + endmenu diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 26ec1af2f0b..2e3a7119e79 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -27,9 +27,13 @@ ifeq ($(IS_32BIT),y) PLATFORM_CPPFLAGS += -march=i386 -m32 else PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common -march=core2 -m64 + +ifndef CONFIG_X86_HARDFP PLATFORM_CPPFLAGS += -mno-mmx -mno-sse endif +endif # IS_32BIT + PLATFORM_RELFLAGS += -fdata-sections -ffunction-sections -fvisibility=hidden KBUILD_LDFLAGS += -Bsymbolic -Bsymbolic-functions diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 2647bff891f..5ea746ecce4 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -10,6 +10,7 @@ #include <init.h> #include <asm/cpu.h> #include <asm/global_data.h> +#include <asm/processor-flags.h> DECLARE_GLOBAL_DATA_PTR; @@ -39,11 +40,22 @@ int x86_mp_init(void) return 0; } +/* enable SSE features for hardware floating point */ +static void setup_sse_features(void) +{ + asm ("mov %%cr4, %%rax\n" \ + "or %0, %%rax\n" \ + "mov %%rax, %%cr4\n" \ + : : "i" (X86_CR4_OSFXSR | X86_CR4_OSXMMEXCPT) : "eax"); +} + int x86_cpu_reinit_f(void) { /* set the vendor to Intel so that native_calibrate_tsc() works */ gd->arch.x86_vendor = X86_VENDOR_INTEL; gd->arch.has_mtrr = true; + if (IS_ENABLED(CONFIG_X86_HARDFP)) + setup_sse_features(); return 0; } diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts index dfce7c2d591..b867468e16c 100644 --- a/arch/x86/dts/coreboot.dts +++ b/arch/x86/dts/coreboot.dts @@ -46,6 +46,16 @@ compatible = "coreboot-fb"; }; + bootstd { + compatible = "u-boot,boot-std"; + + theme { + font-size = <30>; + menu-inset = <3>; + menuitem-gap-y = <1>; + }; + }; + sysinfo { compatible = "coreboot,sysinfo"; }; diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h index 655675b6661..8b542605170 100644 --- a/arch/x86/include/asm/zimage.h +++ b/arch/x86/include/asm/zimage.h @@ -30,6 +30,78 @@ #define BZIMAGE_LOAD_ADDR 0x100000 #define ZIMAGE_LOAD_ADDR 0x10000 +enum { + ZBOOT_STATE_START = BIT(0), + ZBOOT_STATE_LOAD = BIT(1), + ZBOOT_STATE_SETUP = BIT(2), + ZBOOT_STATE_INFO = BIT(3), + ZBOOT_STATE_GO = BIT(4), + + /* This one doesn't execute automatically, so stop the count before 5 */ + ZBOOT_STATE_DUMP = BIT(5), + ZBOOT_STATE_COUNT = 5, +}; + +/** + * struct zboot_state - Current state of the boot + * + * @bzimage_addr: Address of the bzImage to boot, or 0 if the image has already + * been loaded and does not exist (as a cohesive whole) in memory + * @bzimage_size: Size of the bzImage, or 0 to detect this + * @initrd_addr: Address of the initial ramdisk, or 0 if none + * @initrd_size: Size of the initial ramdisk, or 0 if none + * @load_address: Address where the bzImage is moved before booting, either + * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR + * This is set up when loading the zimage + * @base_ptr: Pointer to the boot parameters, typically at address + * DEFAULT_SETUP_BASE + * This is set up when loading the zimage + * @cmdline: Environment variable containing the 'override' command line, or + * NULL to use the one in the setup block + */ +struct zboot_state { + ulong bzimage_addr; + ulong bzimage_size; + ulong initrd_addr; + ulong initrd_size; + ulong load_address; + struct boot_params *base_ptr; + const char *cmdline; +}; + +extern struct zboot_state state; + +/** + * zimage_dump() - Dump information about a zimage + * + * @base_ptr: Pointer to the boot parameters + * @show_cmdline: true to show the kernel command line + */ +void zimage_dump(struct boot_params *base_ptr, bool show_cmdline); + +/** + * zboot_load() - Load a zimage + * + * Load the zimage into the correct place + * + * Return: 0 if OK, -ve on error + */ +int zboot_load(void); + +/** + * zboot_setup() - Set up the zboot image reeady for booting + * + * Return: 0 if OK, -ve on error + */ +int zboot_setup(void); + +/** + * zboot_go() - Start the image + * + * Return: 0 if OK, -ve on error + */ +int zboot_go(void); + /** * load_zimage() - Load a zImage or bzImage * @@ -62,4 +134,29 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size, int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, ulong initrd_addr, ulong initrd_size, ulong cmdline_force); +/** + * zboot_start() - Prepare to boot a zimage + * + * Record information about a zimage so it can be booted + * + * @bzimage_addr: Address of the bzImage to boot + * @bzimage_size: Size of the bzImage, or 0 to detect this + * @initrd_addr: Address of the initial ramdisk, or 0 if none + * @initrd_size: Size of the initial ramdisk, or 0 if none + * @base_addr: If non-zero, this indicates that the boot parameters have already + * been loaded by the caller to this address, so the load_zimage() call + * in zboot_load() will be skipped when booting + * @cmdline: Environment variable containing the 'override' command line, or + * NULL to use the one in the setup block + */ +void zboot_start(ulong bzimage_addr, ulong bzimage_size, ulong initrd_addr, + ulong initrd_size, ulong base_addr, const char *cmdline); + +/** + * zboot_info() - Show simple info about a zimage + * + * Shows wherer the kernel was loaded and also the setup base + */ +void zboot_info(void); + #endif diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 90a7618ecfd..8fc35e1b51e 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -48,7 +48,7 @@ obj-$(CONFIG_$(SPL_TPL_)GENERATE_ACPI_TABLE) += acpi_table.o endif obj-y += tables.o ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_CMD_ZBOOT) += zimage.o +obj-$(CONFIG_ZBOOT) += zimage.o endif obj-$(CONFIG_USE_HOB) += hob.o ifndef CONFIG_TPL_BUILD diff --git a/arch/x86/lib/acpi_nhlt.c b/arch/x86/lib/acpi_nhlt.c index 6c8cd83e12d..08e13fdea67 100644 --- a/arch/x86/lib/acpi_nhlt.c +++ b/arch/x86/lib/acpi_nhlt.c @@ -409,7 +409,7 @@ int nhlt_serialise_oem_overrides(struct acpi_ctx *ctx, struct nhlt *nhlt, memcpy(header->oem_table_id, oem_table_id, oem_table_id_len); } header->oem_revision = oem_revision; - memcpy(header->aslc_id, ASLC_ID, 4); + memcpy(header->creator_id, ASLC_ID, 4); cur.buf = (void *)(header + 1); cur.start = (void *)header; diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 5ecd3d4b651..a5683132b01 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -253,7 +253,7 @@ static int acpi_write_tpm2(struct acpi_ctx *ctx, /* Fill out header fields. */ acpi_fill_header(header, "TPM2"); - memcpy(header->aslc_id, ASLC_ID, 4); + memcpy(header->creator_id, ASLC_ID, 4); header->length = sizeof(struct acpi_tpm2); header->revision = acpi_get_table_revision(ACPITAB_TPM2); @@ -479,7 +479,7 @@ static int acpi_create_hpet(struct acpi_hpet *hpet) /* Fill out header fields. */ acpi_fill_header(header, "HPET"); - header->aslc_revision = ASL_REVISION; + header->creator_revision = ASL_REVISION; header->length = sizeof(struct acpi_hpet); header->revision = acpi_get_table_revision(ACPITAB_HPET); @@ -569,8 +569,8 @@ void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs, header->revision = 4; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, OEM_TABLE_ID, 8); - memcpy(header->aslc_id, ASLC_ID, 4); - header->aslc_revision = 1; + memcpy(header->creator_id, ASLC_ID, 4); + header->creator_revision = 1; fadt->x_firmware_ctrl = map_to_sysmem(facs); fadt->x_dsdt = map_to_sysmem(dsdt); diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 12eae17c396..1095dc92c5a 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -98,6 +98,8 @@ int write_tables(void) int size = table->size ? : CONFIG_ROM_TABLE_SIZE; u32 rom_table_end; + rom_addr = ALIGN(rom_addr, 16); + if (!strcmp("smbios", table->name)) gd->arch.smbios_start = rom_addr; diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index a41e1ccf8a6..d7403876c13 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -56,41 +56,8 @@ DECLARE_GLOBAL_DATA_PTR; #define COMMAND_LINE_SIZE 2048 -/** - * struct zboot_state - Current state of the boot - * - * @bzimage_addr: Address of the bzImage to boot - * @bzimage_size: Size of the bzImage, or 0 to detect this - * @initrd_addr: Address of the initial ramdisk, or 0 if none - * @initrd_size: Size of the initial ramdisk, or 0 if none - * @load_address: Address where the bzImage is moved before booting, either - * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR - * @base_ptr: Pointer to the boot parameters, typically at address - * DEFAULT_SETUP_BASE - * @cmdline: Environment variable containing the 'override' command line, or - * NULL to use the one in the setup block - */ -struct zboot_state { - ulong bzimage_addr; - ulong bzimage_size; - ulong initrd_addr; - ulong initrd_size; - ulong load_address; - struct boot_params *base_ptr; - char *cmdline; -} state; - -enum { - ZBOOT_STATE_START = BIT(0), - ZBOOT_STATE_LOAD = BIT(1), - ZBOOT_STATE_SETUP = BIT(2), - ZBOOT_STATE_INFO = BIT(3), - ZBOOT_STATE_GO = BIT(4), - - /* This one doesn't execute automatically, so stop the count before 5 */ - ZBOOT_STATE_DUMP = BIT(5), - ZBOOT_STATE_COUNT = 5, -}; +/* Current state of the boot */ +struct zboot_state state; static void build_command_line(char *command_line, int auto_boot) { @@ -400,56 +367,10 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, return 0; } -static int do_zboot_start(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - const char *s; - - memset(&state, '\0', sizeof(state)); - if (argc >= 2) { - /* argv[1] holds the address of the bzImage */ - s = argv[1]; - } else { - s = env_get("fileaddr"); - } - - if (s) - state.bzimage_addr = hextoul(s, NULL); - - if (argc >= 3) { - /* argv[2] holds the size of the bzImage */ - state.bzimage_size = hextoul(argv[2], NULL); - } - - if (argc >= 4) - state.initrd_addr = hextoul(argv[3], NULL); - if (argc >= 5) - state.initrd_size = hextoul(argv[4], NULL); - if (argc >= 6) { - /* - * When the base_ptr is passed in, we assume that the image is - * already loaded at the address given by argv[1] and therefore - * the original bzImage is somewhere else, or not accessible. - * In any case, we don't need access to the bzImage since all - * the processing is assumed to be done. - * - * So set the base_ptr to the given address, use this arg as the - * load address and set bzimage_addr to 0 so we know that it - * cannot be proceesed (or processed again). - */ - state.base_ptr = (void *)hextoul(argv[5], NULL); - state.load_address = state.bzimage_addr; - state.bzimage_addr = 0; - } - if (argc >= 7) - state.cmdline = env_get(argv[6]); - - return 0; -} - -static int zboot_load(void) +int zboot_load(void) { struct boot_params *base_ptr; + int ret; if (state.base_ptr) { struct boot_params *from = (struct boot_params *)state.base_ptr; @@ -469,23 +390,16 @@ static int zboot_load(void) } state.base_ptr = base_ptr; - return 0; -} - -static int do_zboot_load(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - if (zboot_load()) - return CMD_RET_FAILURE; - - if (env_set_hex("zbootbase", map_to_sysmem(state.base_ptr)) || - env_set_hex("zbootaddr", state.load_address)) - return CMD_RET_FAILURE; + ret = env_set_hex("zbootbase", map_to_sysmem(state.base_ptr)); + if (!ret) + ret = env_set_hex("zbootaddr", state.load_address); + if (ret) + return ret; return 0; } -static int zboot_setup(void) +int zboot_setup(void) { struct boot_params *base_ptr = state.base_ptr; int ret; @@ -499,33 +413,7 @@ static int zboot_setup(void) return 0; } -static int do_zboot_setup(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - struct boot_params *base_ptr = state.base_ptr; - - if (!base_ptr) { - printf("base is not set: use 'zboot load' first\n"); - return CMD_RET_FAILURE; - } - if (zboot_setup()) { - puts("Setting up boot parameters failed ...\n"); - return CMD_RET_FAILURE; - } - - return 0; -} - -static int do_zboot_info(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - printf("Kernel loaded at %08lx, setup_base=%p\n", - state.load_address, state.base_ptr); - - return 0; -} - -static int zboot_go(void) +int zboot_go(void) { struct boot_params *params = state.base_ptr; struct setup_header *hdr = ¶ms->hdr; @@ -549,35 +437,12 @@ static int zboot_go(void) return ret; } -static int do_zboot_go(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) +int zboot_run(ulong addr, ulong size, ulong initrd, ulong initrd_size, + ulong base, char *cmdline) { int ret; - ret = zboot_go(); - printf("Kernel returned! (err=%d)\n", ret); - - return CMD_RET_FAILURE; -} - -int zboot_start(ulong addr, ulong size, ulong initrd, ulong initrd_size, - ulong base, char *cmdline) -{ - int ret; - - memset(&state, '\0', sizeof(state)); - - if (base) { - state.base_ptr = map_sysmem(base, 0); - state.load_address = addr; - } else { - state.bzimage_addr = addr; - } - state.bzimage_size = size; - state.initrd_addr = initrd; - state.initrd_size = initrd_size; - state.cmdline = cmdline; - + zboot_start(addr, size, initrd, initrd_size, base, cmdline); ret = zboot_load(); if (ret) return log_msg_ret("ld", ret); @@ -586,7 +451,7 @@ int zboot_start(ulong addr, ulong size, ulong initrd, ulong initrd_size, return log_msg_ret("set", ret); ret = zboot_go(); if (ret) - return log_msg_ret("set", ret); + return log_msg_ret("go", ret); return -EFAULT; } @@ -776,97 +641,25 @@ void zimage_dump(struct boot_params *base_ptr, bool show_cmdline) print_num("Kernel info offset", hdr->kernel_info_offset); } -static int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) +void zboot_start(ulong bzimage_addr, ulong bzimage_size, ulong initrd_addr, + ulong initrd_size, ulong base_addr, const char *cmdline) { - struct boot_params *base_ptr = state.base_ptr; - - if (argc > 1) - base_ptr = (void *)hextoul(argv[1], NULL); - if (!base_ptr) { - printf("No zboot setup_base\n"); - return CMD_RET_FAILURE; - } - zimage_dump(base_ptr, true); - - return 0; -} - -/* Note: This defines the complete_zboot() function */ -U_BOOT_SUBCMDS(zboot, - U_BOOT_CMD_MKENT(start, 8, 1, do_zboot_start, "", ""), - U_BOOT_CMD_MKENT(load, 1, 1, do_zboot_load, "", ""), - U_BOOT_CMD_MKENT(setup, 1, 1, do_zboot_setup, "", ""), - U_BOOT_CMD_MKENT(info, 1, 1, do_zboot_info, "", ""), - U_BOOT_CMD_MKENT(go, 1, 1, do_zboot_go, "", ""), - U_BOOT_CMD_MKENT(dump, 2, 1, do_zboot_dump, "", ""), -) - -int do_zboot_states(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[], int state_mask) -{ - int i; - - for (i = 0; i < ZBOOT_STATE_COUNT; i++) { - struct cmd_tbl *cmd = &zboot_subcmds[i]; - int mask = 1 << i; - int ret; + memset(&state, '\0', sizeof(state)); - if (mask & state_mask) { - ret = cmd->cmd(cmd, flag, argc, argv); - if (ret) - return ret; - } + state.bzimage_size = bzimage_size; + state.initrd_addr = initrd_addr; + state.initrd_size = initrd_size; + if (base_addr) { + state.base_ptr = map_sysmem(base_addr, 0); + state.load_address = bzimage_addr; + } else { + state.bzimage_addr = bzimage_addr; } - - return 0; + state.cmdline = cmdline; } -int do_zboot_parent(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[], int *repeatable) +void zboot_info(void) { - /* determine if we have a sub command */ - if (argc > 1) { - char *endp; - - hextoul(argv[1], &endp); - /* - * endp pointing to nul means that argv[1] was just a valid - * number, so pass it along to the normal processing - */ - if (*endp) - return do_zboot(cmdtp, flag, argc, argv, repeatable); - } - - do_zboot_states(cmdtp, flag, argc, argv, ZBOOT_STATE_START | - ZBOOT_STATE_LOAD | ZBOOT_STATE_SETUP | - ZBOOT_STATE_INFO | ZBOOT_STATE_GO); - - return CMD_RET_FAILURE; + printf("Kernel loaded at %08lx, setup_base=%p\n", + state.load_address, state.base_ptr); } - -U_BOOT_CMDREP_COMPLETE( - zboot, 8, do_zboot_parent, "Boot bzImage", - "[addr] [size] [initrd addr] [initrd size] [setup] [cmdline]\n" - " addr - The optional starting address of the bzimage.\n" - " If not set it defaults to the environment\n" - " variable \"fileaddr\".\n" - " size - The optional size of the bzimage. Defaults to\n" - " zero.\n" - " initrd addr - The address of the initrd image to use, if any.\n" - " initrd size - The size of the initrd image to use, if any.\n" - " setup - The address of the kernel setup region, if this\n" - " is not at addr\n" - " cmdline - Environment variable containing the kernel\n" - " command line, to override U-Boot's normal\n" - " cmdline generation\n" - "\n" - "Sub-commands to do part of the zboot sequence:\n" - "\tstart [addr [arg ...]] - specify arguments\n" - "\tload - load OS image\n" - "\tsetup - set up table\n" - "\tinfo - show summary info\n" - "\tgo - start OS\n" - "\tdump [addr] - dump info (optional address of boot params)", - complete_zboot -); |