diff options
Diffstat (limited to 'arch')
37 files changed, 140 insertions, 180 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index dab785efad5..ef79fc3a0a7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -609,6 +609,9 @@ config ARM64_SUPPORT_AARCH32 help This ARM64 system supports AArch32 execution state. +config S5P + def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX + choice prompt "Target select" default TARGET_HIKEY @@ -996,11 +999,6 @@ config ARCH_MX6 imply SYS_THUMB_BUILD imply SPL_SEPARATE_BSS -if ARCH_MX6 -config SPL_LDSCRIPT - default "arch/arm/mach-omap2/u-boot-spl.lds" -endif - config ARCH_MX5 bool "Freescale MX5" select BOARD_EARLY_INIT_F @@ -2354,6 +2352,7 @@ source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" +source "board/siemens/common/Kconfig" source "board/seeed/npi_imx6ull/Kconfig" source "board/socionext/developerbox/Kconfig" source "board/st/stv0991/Kconfig" @@ -2368,8 +2367,3 @@ source "board/xen/xenguest_arm64/Kconfig" source "arch/arm/Kconfig.debug" endmenu - -config SPL_LDSCRIPT - default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK - default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136 - default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 80a1642447d..5a809b46118 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -701,9 +701,6 @@ config SYS_FSL_HAS_RGMII bool depends on SYS_FSL_EC1 || SYS_FSL_EC2 -config SPL_LDSCRIPT - default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A - config HAS_FSL_XHCI_USB bool help diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a9f4cccf8db..87b210dbb01 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -5,9 +5,9 @@ dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb -dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb -dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb -dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ +dtb-$(CONFIG_TARGET_SMDKC100) += s5pc1xx-smdkc100.dtb +dtb-$(CONFIG_TARGET_S5P_GONI) += s5pc1xx-goni.dtb +dtb-$(CONFIG_ARCH_EXYNOS4) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-universal_c210.dtb \ exynos4210-trats.dtb \ @@ -19,7 +19,7 @@ dtb-$(CONFIG_TARGET_HIKEY960) += hi3660-hikey960.dtb dtb-$(CONFIG_TARGET_POPLAR) += hi3798cv200-poplar.dtb -dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ +dtb-$(CONFIG_ARCH_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-snow.dtb \ exynos5250-spring.dtb \ exynos5250-smdk5250.dtb \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 61db1738f33..4b0f554e336 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -37,7 +37,6 @@ #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 3b1d9a3f0c4..aa790ab54c3 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -34,7 +34,6 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) #define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) #define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 #define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000 @@ -96,7 +95,6 @@ #define DCU_LAYER_MAX_NUM 16 #ifdef CONFIG_ARCH_LS1021A -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else #error SoC not defined diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index b5790bd0bc4..0ece4b09060 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -6,9 +6,8 @@ #ifndef _ASM_SPL_H_ #define _ASM_SPL_H_ -#if defined(CONFIG_ARCH_OMAP2PLUS) \ - || defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \ - || defined(CONFIG_EXYNOS4210) || defined(CONFIG_ARCH_K3) +#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) || \ + defined(CONFIG_ARCH_K3) || defined(CONFIG_ARCH_OMAP2PLUS) /* Platform-specific defines */ #include <asm/arch/spl.h> diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds index 22b4e16d35c..95a509ba3f3 100644 --- a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds +++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds @@ -40,8 +40,8 @@ SECTIONS } > .nor . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } > .nor . = ALIGN(4); @@ -68,7 +68,7 @@ SECTIONS _image_binary_end = .; - .bss : { + .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; *(.bss*) . = ALIGN(4); diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index b87639f8c07..11bfd5afe74 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -327,6 +327,13 @@ config AT91_EFLASH Enable the driver for the embedded flash used in the Atmel AT91SAM9XE devices. +config EFLASH_PROTSECTORS + int "Number of flash sectors to protect from erasing" + depends on AT91_EFLASH + help + If non-zero, this will be the number of sectors of the flash to disallow + U-Boot to ease, starting from the beginning of flash. + config AT91_GPIO_PULLUP bool "Keep pullups on peripheral pins" depends on CPU_ARM926EJS @@ -370,8 +377,4 @@ source "board/siemens/corvus/Kconfig" source "board/siemens/taurus/Kconfig" source "board/siemens/smartweb/Kconfig" -config SPL_LDSCRIPT - default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS - default "arch/arm/mach-at91/armv7/u-boot-spl.lds" if CPU_V7A - endif diff --git a/arch/arm/mach-at91/arm926ejs/eflash.c b/arch/arm/mach-at91/arm926ejs/eflash.c index 23c24936edf..043f06a8271 100644 --- a/arch/arm/mach-at91/arm926ejs/eflash.c +++ b/arch/arm/mach-at91/arm926ejs/eflash.c @@ -120,7 +120,7 @@ unsigned long flash_init(void) if (i%32 == 0) tmp = readl(&eefc->frr); flash_info[0].protect[i] = (tmp >> (i%32)) & 1; -#if defined(CONFIG_EFLASH_PROTSECTORS) +#if CONFIG_VAL(EFLASH_PROTSECTORS) if (i < CONFIG_EFLASH_PROTSECTORS) flash_info[0].protect[i] = 1; #endif @@ -158,7 +158,7 @@ int flash_real_protect (flash_info_t *info, long sector, int prot) debug("protect sector=%ld prot=%d\n", sector, prot); -#if defined(CONFIG_EFLASH_PROTSECTORS) +#if CONFIG_VAL(EFLASH_PROTSECTORS) if (sector < CONFIG_EFLASH_PROTSECTORS) { if (!prot) { printf("eflash: sector %lu cannot be unprotected\n", diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 6eca8db6d5f..25c5db49915 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -134,7 +134,4 @@ endif source "board/davinci/da8xxevm/Kconfig" source "board/lego/ev3/Kconfig" -config SPL_LDSCRIPT - default "board/davinci/da8xxevm/u-boot-spl-da850evm.lds" - endif diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index f73dbbb507d..84102908561 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -54,11 +54,15 @@ endchoice if ARCH_EXYNOS4 +config EXYNOS4210 + bool + choice prompt "EXYNOS4 board select" config TARGET_SMDKV310 bool "Exynos4210 SMDKV310 board" + select EXYNOS4210 select OF_CONTROL select SUPPORT_SPL @@ -70,6 +74,7 @@ config TARGET_S5PC210_UNIVERSAL config TARGET_ORIGEN bool "Exynos4412 Origen board" + select EXYNOS4210 select SUPPORT_SPL config TARGET_TRATS2 @@ -83,6 +88,15 @@ endif if ARCH_EXYNOS5 +config EXYNOS5250 + bool + +config EXYNOS5420 + bool + +config EXYNOS5_DT + bool + config SPL_GPIO default y @@ -97,6 +111,8 @@ choice config TARGET_ODROID_XU3 bool "Exynos5422 Odroid board" + select EXYNOS5_DT + select EXYNOS5420 select OF_CONTROL config TARGET_ARNDALE @@ -105,36 +121,49 @@ config TARGET_ARNDALE select ARM_ERRATA_774769 select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT + select EXYNOS5250 select OF_CONTROL select SUPPORT_SPL config TARGET_SMDK5250 bool "SMDK5250 board" + select EXYNOS5_DT + select EXYNOS5250 select OF_CONTROL select SUPPORT_SPL config TARGET_SNOW bool "Snow board" + select EXYNOS5_DT + select EXYNOS5250 select OF_CONTROL select SUPPORT_SPL config TARGET_SPRING bool "Spring board" + select EXYNOS5_DT + select EXYNOS5250 select OF_CONTROL select SUPPORT_SPL config TARGET_SMDK5420 bool "SMDK5420 board" + select EXYNOS5_DT + select EXYNOS5420 select OF_CONTROL select SUPPORT_SPL config TARGET_PEACH_PI bool "Peach Pi board" + select EXYNOS5_DT + select EXYNOS5420 select OF_CONTROL select SUPPORT_SPL config TARGET_PEACH_PIT bool "Peach Pit board" + select EXYNOS5_DT + select EXYNOS5420 select OF_CONTROL select SUPPORT_SPL @@ -189,6 +218,16 @@ endif config SYS_SOC default "exynos" +config EXYNOS_ACE_SHA + bool "Advanced Crypto Engine SHA support" + depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && (LIB_HW_RAND || SHA_HW_ACCEL) + default y if ARCH_EXYNOS5 + +config EXYNOS_TMU + bool "Exynos5 thermal management unit support" + depends on ARCH_EXYNOS5 + default y + source "board/samsung/smdkv310/Kconfig" source "board/samsung/trats/Kconfig" source "board/samsung/universal_c210/Kconfig" @@ -201,7 +240,4 @@ source "board/samsung/smdk5420/Kconfig" source "board/samsung/espresso7420/Kconfig" source "board/samsung/axy17lte/Kconfig" -config SPL_LDSCRIPT - default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4 - endif diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index e895c13157f..dd097cf5418 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -10,8 +10,8 @@ obj-$(CONFIG_ARM64) += mmu-arm64.o obj-$(CONFIG_EXYNOS5420) += sec_boot.o ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o -obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o +obj-$(CONFIG_ARCH_EXYNOS5) += clock_init_exynos5.o +obj-$(CONFIG_ARCH_EXYNOS5) += dmc_common.o dmc_init_ddr3.o obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o obj-y += spl_boot.o tzpc.o obj-y += lowlevel_init.o diff --git a/arch/arm/mach-exynos/dmc_init_exynos4.c b/arch/arm/mach-exynos/dmc_init_exynos4.c index ecddc726849..58a3c82f681 100644 --- a/arch/arm/mach-exynos/dmc_init_exynos4.c +++ b/arch/arm/mach-exynos/dmc_init_exynos4.c @@ -175,7 +175,7 @@ void mem_ctrl_init(int reset) * 0: full_sync */ writel(1, ASYNC_CONFIG); -#ifdef CONFIG_ORIGEN +#ifdef CONFIG_TARGET_ORIGEN /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */ writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE + APB_SFR_INTERLEAVE_CONF_OFFSET); diff --git a/arch/arm/mach-exynos/exynos4_setup.h b/arch/arm/mach-exynos/exynos4_setup.h index a08d64a8e23..fbb45eb897e 100644 --- a/arch/arm/mach-exynos/exynos4_setup.h +++ b/arch/arm/mach-exynos/exynos4_setup.h @@ -420,7 +420,7 @@ struct mem_timings { #define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET 0x828 #define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830 -#ifdef CONFIG_ORIGEN +#ifdef CONFIG_TARGET_ORIGEN /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */ #define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507 #define APB_SFR_ARBRITATION_CONF_VAL 0x00000001 @@ -542,7 +542,7 @@ struct mem_timings { #define CONTROL2_VAL 0x00000000 -#ifdef CONFIG_ORIGEN +#ifdef CONFIG_TARGET_ORIGEN #define TIMINGREF_VAL 0x000000BB #define TIMINGROW_VAL 0x4046654f #define TIMINGDATA_VAL 0x46400506 diff --git a/arch/arm/mach-exynos/include/mach/pwm_backlight.h b/arch/arm/mach-exynos/include/mach/pwm_backlight.h deleted file mode 100644 index c7d3a91e318..00000000000 --- a/arch/arm/mach-exynos/include/mach/pwm_backlight.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Samsung Electronics - * - * Author: Donghwa Lee <dh09.lee@samsung.com> - */ - -#ifndef _PWM_BACKLIGHT_H_ -#define _PWM_BACKLIGHT_H_ - -struct pwm_backlight_data { - int pwm_id; - int period; - int max_brightness; - int brightness; -}; - -extern int exynos_pwm_backlight_init(struct pwm_backlight_data *pd); - -#endif /* _PWM_BACKLIGHT_H_ */ diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h index 48f13c76481..5d0bebac573 100644 --- a/arch/arm/mach-exynos/include/mach/system.h +++ b/arch/arm/mach-exynos/include/mach/system.h @@ -116,6 +116,5 @@ struct exynos5_sysreg { void set_usbhost_mode(unsigned int mode); void set_system_display_ctrl(void); -int exynos_lcd_early_init(const void *blob); #endif /* _EXYNOS4_SYSTEM_H */ diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 2645a8ff492..1ff5fcac1b3 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -49,6 +49,10 @@ enum { }; #ifdef CONFIG_EXYNOS5420 + +/* Address for relocating helper code (Last 4 KB of IRAM) */ +#define EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000) + /* * Power up secondary CPUs. */ @@ -56,7 +60,7 @@ static void secondary_cpu_start(void) { v7_enable_smp(EXYNOS5420_INFORM_BASE); svc32_mode_en(); - branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE); + branch_bx(EXYNOS_RELOCATE_CODE_BASE); } /* @@ -153,7 +157,7 @@ static void power_down_core(void) static void secondary_cores_configure(void) { /* Clear secondary boot iRAM base */ - writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C)); + writel(0x0, (EXYNOS_RELOCATE_CODE_BASE + 0x1C)); /* set lowpower flag and address */ writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG); diff --git a/arch/arm/mach-exynos/sec_boot.S b/arch/arm/mach-exynos/sec_boot.S index 59d05e6c01d..40c07209e47 100644 --- a/arch/arm/mach-exynos/sec_boot.S +++ b/arch/arm/mach-exynos/sec_boot.S @@ -21,7 +21,7 @@ relocate_wait_code: .ltorg /* * Secondary core waits here until Primary wake it up. - * Below code is copied to CONFIG_EXYNOS_RELOCATE_CODE_BASE. + * Below code is copied to (CONFIG_IRAM_TOP - 0x1000) * This is a workaround code which is supposed to act as a * substitute/supplement to the iROM code. * diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 5e1b20a4229..8f185c192d5 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -57,11 +57,13 @@ config TARGET_COLIBRI_IMX8X config TARGET_DENEB bool "Support i.MX8QXP Capricorn Deneb board" select BOARD_LATE_INIT + select FACTORYSET select IMX8QXP config TARGET_GIEDI bool "Support i.MX8QXP Capricorn Giedi board" select BOARD_LATE_INIT + select FACTORYSET select IMX8QXP config TARGET_IMX8QM_MEK diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index 45ee0272f77..ca341570544 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -49,8 +49,6 @@ #define __io /* Data, registers and alternate blocks are at the same offset */ /* Each 8-bit ATA register is aligned to a 4-bytes address */ -/* Controller supports 48-bits LBA addressing */ -#define CONFIG_LBA48 /* CONFIG_IDE requires some #defines for ATA registers */ /* ATA registers base is at SATA controller base */ #endif /* CONFIG_IDE */ diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index e1b9180a3bb..51d1db4a87b 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -190,7 +190,4 @@ source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_t43/Kconfig" source "board/phytec/phycore_am335x_r2/Kconfig" -config SPL_LDSCRIPT - default "arch/arm/mach-omap2/u-boot-spl.lds" - endif diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 23865d4c070..bd6b0865526 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -138,6 +138,7 @@ config TARGET_DRACO select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_ETAMIN @@ -146,6 +147,7 @@ config TARGET_ETAMIN select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_PCM051 @@ -168,6 +170,7 @@ config TARGET_PXM2 select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_RASTABAN @@ -176,6 +179,7 @@ config TARGET_RASTABAN select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_RUT @@ -184,6 +188,7 @@ config TARGET_RUT select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_THUBAN @@ -192,6 +197,7 @@ config TARGET_THUBAN select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_PDU001 diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 25afd3cb607..c3249a7be45 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -65,9 +65,6 @@ source "board/rockchip/sheep_rk3368/Kconfig" source "board/geekbuying/geekbox/Kconfig" source "board/rockchip/evb_px5/Kconfig" -config SPL_LDSCRIPT - default "arch/arm/cpu/armv8/u-boot-spl.lds" - config SPL_STACK_R_ADDR default 0x04000000 diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index e712a895340..71a7f8dcee0 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1,9 +1,5 @@ if ARCH_SUNXI -config SPL_LDSCRIPT - default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV - default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 - config IDENT_STRING default " Allwinner Technology" diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 5309be9cc21..09ad2d6f5ae 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -178,6 +178,10 @@ source "arch/arm/mach-tegra/tegra124/Kconfig" source "arch/arm/mach-tegra/tegra210/Kconfig" source "arch/arm/mach-tegra/tegra186/Kconfig" +config TEGRA_GPU + bool "Enable setting up the GPU" + depends on TEGRA124 || TEGRA210 + config CMD_ENTERRCM bool "Enable 'enterrcm' command" default y diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h index 7b728ac1101..000af974e86 100644 --- a/arch/arm/mach-versal/include/mach/hardware.h +++ b/arch/arm/mach-versal/include/mach/hardware.h @@ -58,6 +58,10 @@ struct rpu_regs { #define VERSAL_CRP_BASEADDR 0xF1260000 +#define VERSAL_SLCR_BASEADDR 0xF1060000 +#define VERSAL_AXI_MUX_SEL (VERSAL_SLCR_BASEADDR + 0x504) +#define VERSAL_OSPI_LINEAR_MODE BIT(1) + struct crp_regs { u32 reserved0[128]; u32 boot_mode_usr; @@ -82,3 +86,14 @@ struct crp_regs { #define JTAG_MODE 0x00000000 #define BOOT_MODE_USE_ALT 0x100 #define BOOT_MODE_ALT_SHIFT 12 + +#define FLASH_RESET_GPIO 0xc +#define WPROT_CRP 0xF126001C +#define RST_GPIO 0xF1260318 +#define WPROT_LPD_MIO 0xFF080728 +#define WPROT_PMC_MIO 0xF1060828 +#define BOOT_MODE_DIR 0xF1020204 +#define BOOT_MODE_OUT 0xF1020208 +#define MIO_PIN_12 0xF1060030 +#define BANK0_OUTPUT 0xF1020040 +#define BANK0_TRI 0xF1060200 diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index cf2e727916b..b4c439b4cd6 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -1,8 +1,5 @@ if ARCH_ZYNQ -config SPL_LDSCRIPT - default "arch/arm/mach-zynq/u-boot-spl.lds" - config SPL_FS_FAT default y diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index e3e1bfd65a5..33835eeec2a 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -251,19 +251,6 @@ void cpu_init_f (volatile immap_t * im) im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT; im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR; #endif -#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X) - uint32_t temp; - struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; - - /* Configure interface. */ - setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN); - - /* Wait for clock to stabilize */ - do { - temp = __raw_readl(&ehci->control); - udelay(1000); - } while (!(temp & PHY_CLK_VALID)); -#endif } int cpu_init_r (void) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index c1b4e94d919..02efa1c6030 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1185,6 +1185,29 @@ config SYS_FSL_LBC_CLK_DIV Defines divider of platform clock(clock input to eLBC controller). +config SYS_MPC85XX_NO_RESETVEC + bool "Discard resetvec section and move bootpg section up" + depends on MPC85xx + help + If this variable is specified, the section .resetvec is not kept and + the section .bootpg is placed in the previous 4k of the .text section. + +config SPL_SYS_MPC85XX_NO_RESETVEC + bool "Discard resetvec section and move bootpg section up, in SPL" + depends on MPC85xx && SPL + help + If this variable is specified, the section .resetvec is not kept and + the section .bootpg is placed in the previous 4k of the .text section, + of the SPL portion of the binary. + +config TPL_SYS_MPC85XX_NO_RESETVEC + bool "Discard resetvec section and move bootpg section up, in TPL" + depends on MPC85xx && TPL + help + If this variable is specified, the section .resetvec is not kept and + the section .bootpg is placed in the previous 4k of the .text section, + of the SPL portion of the binary. + config FSL_VIA bool diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 9a28269020d..5009cbef54a 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1128,7 +1128,7 @@ switch_as: /*--------------------------------------------------------------*/ lis r3,CONFIG_VAL(SYS_MONITOR_BASE)@h ori r3,r3,CONFIG_VAL(SYS_MONITOR_BASE)@l - addi r3,r3,_start_cont - _start_cont + addi r3,r3,_start_cont - CONFIG_VAL(SYS_MONITOR_BASE) mtlr r3 blr #endif @@ -1600,7 +1600,7 @@ relocate_code: * initialization, now running from RAM. */ - addi r0,r10,in_ram - _start_cont + addi r0,r10,in_ram - CONFIG_VAL(SYS_MONITOR_BASE) /* * As IVPR is going to point RAM address, diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 06a70ff2af9..62c3c51dea2 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -9,24 +9,15 @@ #include "config.h" OUTPUT_ARCH(powerpc) -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC -PHDRS -{ - text PT_LOAD; - bss PT_LOAD; -} -#endif + SECTIONS { + . = IMAGE_TEXT_BASE; + .text : { /* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC - .bootpg IMAGE_TEXT_BASE - 0x1000 : - { +#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) KEEP(*(.bootpg)) - } :text = 0xffff #endif - . = IMAGE_TEXT_BASE; - .text : { *(.text*) } _etext = .; @@ -75,7 +66,7 @@ SECTIONS #endif /* For nor and nand is needed the SPL with section .resetvec */ -#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC +#if !CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ #ifndef BOOT_PAGE_OFFSET #define BOOT_PAGE_OFFSET 0x1000 diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 8bbe319b3e7..8fba7126555 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -14,32 +14,22 @@ OUTPUT_ARCH(powerpc) ENTRY(_start) -PHDRS -{ - text PT_LOAD; - bss PT_LOAD; -} - SECTIONS { /* Read-only sections, merged into text segment: */ -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC - .bootpg CONFIG_SYS_TEXT_BASE - 0x1000 : + .text : { +#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) - } :text = 0xffff - . = CONFIG_SYS_TEXT_BASE; #endif - .text : - { *(.text*) - } :text + } _etext = .; PROVIDE (etext = .); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } :text + } /* Read-write section, merged into data segment: */ . = (. + 0x00FF) & 0xFFFFFF00; @@ -84,16 +74,16 @@ SECTIONS __init_end = .; _end = .; -#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC +#if !CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) .bootpg RESET_VECTOR_ADDRESS - 0xffc : { arch/powerpc/cpu/mpc85xx/start.o (.bootpg) - } :text = 0xffff + } = 0xffff .resetvec RESET_VECTOR_ADDRESS : { KEEP(*(.resetvec)) - } :text = 0xffff + } = 0xffff . = RESET_VECTOR_ADDRESS + 0x4; @@ -115,7 +105,7 @@ SECTIONS *(.sbss*) *(.bss*) *(COMMON) - } :bss + } . = ALIGN(4); __bss_end = . ; diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 67f8b100018..871554a7f48 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -17,10 +17,6 @@ #include <phy.h> #include <hwconfig.h> -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) { diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 47bfcc72444..06f66d02de2 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -31,7 +31,6 @@ #elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -41,25 +40,19 @@ /* P1011 is single core version of P1020 */ #elif defined(CONFIG_ARCH_P1011) #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #elif defined(CONFIG_ARCH_P1020) #define CONFIG_TSECV2 -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif #elif defined(CONFIG_ARCH_P1021) #define CONFIG_TSECV2 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_ARCH_P1023) #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 @@ -68,11 +61,9 @@ /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_ARCH_P1024) #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* P1025 is lower end variant of P1021 */ #elif defined(CONFIG_ARCH_P1025) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_TSECV2 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -84,7 +75,6 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -92,9 +82,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" @@ -118,7 +105,6 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -132,7 +118,6 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" @@ -151,7 +136,6 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_DTSEC 5 #define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" @@ -163,7 +147,6 @@ #elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 @@ -172,7 +155,6 @@ #elif defined(CONFIG_ARCH_BSC9132) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 @@ -204,7 +186,6 @@ #define CONFIG_SYS_FSL_SRDS_3 #define CONFIG_SYS_FSL_SRDS_4 #define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 @@ -234,7 +215,6 @@ #define CONFIG_SYS_CPRI #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FM1_CLK 0 #define CONFIG_SYS_CPRI_CLK 3 #define CONFIG_SYS_ULB_CLK 4 @@ -255,7 +235,6 @@ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -278,7 +257,6 @@ #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_PME_PLAT_CLK_DIV 2 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 @@ -309,7 +287,6 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM1_CLK 0 #define CONFIG_QBMAN_CLK_DIV 1 @@ -343,7 +320,6 @@ #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #endif -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_PME_PLAT_CLK_DIV 1 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FM1_CLK 0 diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index d2443dc90d5..6d1ddbcd27b 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -666,19 +666,6 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; -#ifndef CONFIG_ARCH_MPC834X -#ifdef CONFIG_HAS_FSL_MPH_USB -#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */ -#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0 -#else -#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0 -#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */ -#endif -#else -#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 -#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 -#endif - #elif defined(CONFIG_ARCH_MPC8313) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ @@ -944,15 +931,6 @@ struct ccsr_gpio { #define CONFIG_SYS_MPC83xx_ESDHC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) -#ifndef CONFIG_SYS_MPC83xx_USB1_OFFSET -#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x23000 -#endif -#define CONFIG_SYS_MPC83xx_USB1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET) -#if defined(CONFIG_ARCH_MPC834X) -#define CONFIG_SYS_MPC83xx_USB2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET) -#endif #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) #define CONFIG_SYS_TSEC1_OFFSET 0x24000 diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 7cbfd6c9720..1ac43e98bb6 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -956,6 +956,7 @@ config SPL_ACPI_GPE config TPL_ACPI_GPE bool "Support ACPI general-purpose events in TPL" + depends on TPL help Enable a driver for ACPI GPEs to allow peripherals to send interrupts via ACPI to the OS. In U-Boot this is only used when U-Boot itself diff --git a/arch/xtensa/dts/Makefile b/arch/xtensa/dts/Makefile index fbbdefaf2cf..c22c50ac4e5 100644 --- a/arch/xtensa/dts/Makefile +++ b/arch/xtensa/dts/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_XTFPGA) += ml605.dtb ml605_nommu.dtb kc705.dtb kc705_nommu.dtb +dtb-$(CONFIG_XTENSA) += ml605.dtb ml605_nommu.dtb kc705.dtb kc705_nommu.dtb include $(srctree)/scripts/Makefile.dts |