diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-snapdragon/clock-qcs404.c | 58 | ||||
| -rw-r--r-- | arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h | 17 |
2 files changed, 75 insertions, 0 deletions
diff --git a/arch/arm/mach-snapdragon/clock-qcs404.c b/arch/arm/mach-snapdragon/clock-qcs404.c index b8f5691aae2..3357b54c30c 100644 --- a/arch/arm/mach-snapdragon/clock-qcs404.c +++ b/arch/arm/mach-snapdragon/clock-qcs404.c @@ -81,6 +81,36 @@ static const struct bcr_regs emac_ptp_regs = { .D = EMAC_D, }; +static const struct bcr_regs blsp1_qup0_i2c_apps_regs = { + .cmd_rcgr = BLSP1_QUP0_I2C_APPS_CMD_RCGR, + .cfg_rcgr = BLSP1_QUP0_I2C_APPS_CFG_RCGR, + /* mnd_width = 0 */ +}; + +static const struct bcr_regs blsp1_qup1_i2c_apps_regs = { + .cmd_rcgr = BLSP1_QUP1_I2C_APPS_CMD_RCGR, + .cfg_rcgr = BLSP1_QUP1_I2C_APPS_CFG_RCGR, + /* mnd_width = 0 */ +}; + +static const struct bcr_regs blsp1_qup2_i2c_apps_regs = { + .cmd_rcgr = BLSP1_QUP2_I2C_APPS_CMD_RCGR, + .cfg_rcgr = BLSP1_QUP2_I2C_APPS_CFG_RCGR, + /* mnd_width = 0 */ +}; + +static const struct bcr_regs blsp1_qup3_i2c_apps_regs = { + .cmd_rcgr = BLSP1_QUP3_I2C_APPS_CMD_RCGR, + .cfg_rcgr = BLSP1_QUP3_I2C_APPS_CFG_RCGR, + /* mnd_width = 0 */ +}; + +static const struct bcr_regs blsp1_qup4_i2c_apps_regs = { + .cmd_rcgr = BLSP1_QUP4_I2C_APPS_CMD_RCGR, + .cfg_rcgr = BLSP1_QUP4_I2C_APPS_CFG_RCGR, + /* mnd_width = 0 */ +}; + ulong msm_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -171,6 +201,34 @@ int msm_enable(struct clk *clk) case GCC_ETH_AXI_CLK: clk_enable_cbc(priv->base + ETH_AXI_CBCR); break; + case GCC_BLSP1_AHB_CLK: + clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk); + break; + case GCC_BLSP1_QUP0_I2C_APPS_CLK: + clk_enable_cbc(priv->base + BLSP1_QUP0_I2C_APPS_CBCR); + clk_rcg_set_rate(priv->base, &blsp1_qup0_i2c_apps_regs, 0, + CFG_CLK_SRC_CXO); + break; + case GCC_BLSP1_QUP1_I2C_APPS_CLK: + clk_enable_cbc(priv->base + BLSP1_QUP1_I2C_APPS_CBCR); + clk_rcg_set_rate(priv->base, &blsp1_qup1_i2c_apps_regs, 0, + CFG_CLK_SRC_CXO); + break; + case GCC_BLSP1_QUP2_I2C_APPS_CLK: + clk_enable_cbc(priv->base + BLSP1_QUP2_I2C_APPS_CBCR); + clk_rcg_set_rate(priv->base, &blsp1_qup2_i2c_apps_regs, 0, + CFG_CLK_SRC_CXO); + break; + case GCC_BLSP1_QUP3_I2C_APPS_CLK: + clk_enable_cbc(priv->base + BLSP1_QUP3_I2C_APPS_CBCR); + clk_rcg_set_rate(priv->base, &blsp1_qup3_i2c_apps_regs, 0, + CFG_CLK_SRC_CXO); + break; + case GCC_BLSP1_QUP4_I2C_APPS_CLK: + clk_enable_cbc(priv->base + BLSP1_QUP4_I2C_APPS_CBCR); + clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0, + CFG_CLK_SRC_CXO); + break; default: return 0; } diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h index 8920c4ee8ff..5768fb13775 100644 --- a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h @@ -28,6 +28,23 @@ #define BLSP1_UART2_APPS_N (0x3040) #define BLSP1_UART2_APPS_D (0x3044) +/* I2C controller clock control registerss */ +#define BLSP1_QUP0_I2C_APPS_CBCR (0x6028) +#define BLSP1_QUP0_I2C_APPS_CMD_RCGR (0x602C) +#define BLSP1_QUP0_I2C_APPS_CFG_RCGR (0x6030) +#define BLSP1_QUP1_I2C_APPS_CBCR (0x2008) +#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C) +#define BLSP1_QUP1_I2C_APPS_CFG_RCGR (0x2010) +#define BLSP1_QUP2_I2C_APPS_CBCR (0x3010) +#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000) +#define BLSP1_QUP2_I2C_APPS_CFG_RCGR (0x3004) +#define BLSP1_QUP3_I2C_APPS_CBCR (0x4020) +#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x4000) +#define BLSP1_QUP3_I2C_APPS_CFG_RCGR (0x4004) +#define BLSP1_QUP4_I2C_APPS_CBCR (0x5020) +#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x5000) +#define BLSP1_QUP4_I2C_APPS_CFG_RCGR (0x5004) + /* SD controller clock control registers */ #define SDCC_BCR(n) (((n) * 0x1000) + 0x41000) #define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x41004) |