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-rw-r--r--board/MigoR/Makefile48
-rw-r--r--board/MigoR/config.mk32
-rw-r--r--board/MigoR/lowlevel_init.S269
-rw-r--r--board/MigoR/migo_r.c54
-rw-r--r--board/MigoR/u-boot.lds106
-rw-r--r--board/mpr2/Makefile54
-rw-r--r--board/mpr2/config.mk37
-rw-r--r--board/mpr2/lowlevel_init.S148
-rw-r--r--board/mpr2/mpr2.c162
-rw-r--r--board/mpr2/u-boot.lds109
-rw-r--r--board/r2dplus/Makefile43
-rw-r--r--board/r2dplus/config.mk23
-rw-r--r--board/r2dplus/lowlevel_init.S154
-rw-r--r--board/r2dplus/r2dplus.c76
-rw-r--r--board/r2dplus/u-boot.lds105
-rw-r--r--board/r7780mp/Makefile44
-rw-r--r--board/r7780mp/config.mk27
-rw-r--r--board/r7780mp/lowlevel_init.S428
-rw-r--r--board/r7780mp/r7780mp.c81
-rw-r--r--board/r7780mp/r7780mp.h54
-rw-r--r--board/r7780mp/u-boot.lds105
21 files changed, 2159 insertions, 0 deletions
diff --git a/board/MigoR/Makefile b/board/MigoR/Makefile
new file mode 100644
index 00000000000..5a9d651afb5
--- /dev/null
+++ b/board/MigoR/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/MigoR/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := migo_r.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/MigoR/config.mk b/board/MigoR/config.mk
new file mode 100644
index 00000000000..c68cb723df2
--- /dev/null
+++ b/board/MigoR/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/MigoR/config.mk
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# TEXT_BASE refers to image _after_ relocation.
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+
+TEXT_BASE = 0x8FFC0000
+
diff --git a/board/MigoR/lowlevel_init.S b/board/MigoR/lowlevel_init.S
new file mode 100644
index 00000000000..7fd771d6937
--- /dev/null
+++ b/board/MigoR/lowlevel_init.S
@@ -0,0 +1,269 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/MigoR/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+/*
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
+ *
+ * (Note: As no stack is available, no subroutines can be called...).
+ */
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ mov.l CCR_A, r1 ! Address of Cache Control Register
+ mov.l CCR_D, r0 ! Instruction Cache Invalidate
+ mov.l r0, @r1
+
+ mov.l MMUCR_A, r1 ! Address of MMU Control Register
+ mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit
+ mov.l r0, @r1
+
+ mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0
+ mov.l MSTPCR0_D, r0 !
+ mov.l r0, @r1
+
+ mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2
+ mov.l MSTPCR2_D, r0 !
+ mov.l r0, @r1
+
+ mov.l PFC_PULCR_A, r1
+ mov.w PFC_PULCR_D, r0
+ mov.w r0,@r1
+
+ mov.l PFC_DRVCR_A, r1
+ mov.w PFC_DRVCR_D, r0
+ mov.w r0, @r1
+
+ mov.l SBSCR_A, r1 !
+ mov.w SBSCR_D, r0 !
+ mov.w r0, @r1
+
+ mov.l PSCR_A, r1 !
+ mov.w PSCR_D, r0 !
+ mov.w r0, @r1
+
+ mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
+ mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max
+ mov.w r0, @r1
+
+ mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register)
+ mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear
+ mov.w r0, @r1
+
+ mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
+ mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms
+ mov.w r0, @r1
+
+ mov.l DLLFRQ_A, r1 ! 20080115
+ mov.l DLLFRQ_D, r0 ! 20080115
+ mov.l r0, @r1
+
+ mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register
+ mov.l FRQCR_D, r0 ! 20080115
+ mov.l r0, @r1
+
+ mov.l CCR_A, r1 ! Address of Cache Control Register
+ mov.l CCR_D_2, r0 ! ??
+ mov.l r0, @r1
+
+bsc_init:
+
+ mov.l CMNCR_A, r1 ! CMNCR address -> R1
+ mov.l CMNCR_D, r0 ! CMNCR data -> R0
+ mov.l r0, @r1 ! CMNCR set
+
+ mov.l CS0BCR_A, r1 ! CS0BCR address -> R1
+ mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
+ mov.l r0, @r1 ! CS0BCR set
+
+ mov.l CS4BCR_A, r1 ! CS4BCR address -> R1
+ mov.l CS4BCR_D, r0 ! CS4BCR data -> R0
+ mov.l r0, @r1 ! CS4BCR set
+
+ mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1
+ mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
+ mov.l r0, @r1 ! CS5ABCR set
+
+ mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1
+ mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
+ mov.l r0, @r1 ! CS5BBCR set
+
+ mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1
+ mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
+ mov.l r0, @r1 ! CS6ABCR set
+
+ mov.l CS0WCR_A, r1 ! CS0WCR address -> R1
+ mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
+ mov.l r0, @r1 ! CS0WCR set
+
+ mov.l CS4WCR_A, r1 ! CS4WCR address -> R1
+ mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
+ mov.l r0, @r1 ! CS4WCR set
+
+ mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1
+ mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
+ mov.l r0, @r1 ! CS5AWCR set
+
+ mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1
+ mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
+ mov.l r0, @r1 ! CS5BWCR set
+
+ mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1
+ mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
+ mov.l r0, @r1 ! CS6AWCR set
+
+ ! SDRAM initialization
+ mov.l SDCR_A, r1 ! SB_SDCR address -> R1
+ mov.l SDCR_D, r0 ! SB_SDCR data -> R0
+ mov.l r0, @r1 ! SB_SDCR set
+
+ mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1
+ mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0
+ mov.l r0, @r1 ! SB_SDWCR set
+
+ mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1
+ mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0
+ mov.l r0, @r1 ! SB_SDPCR set
+
+ mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1
+ mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0
+ mov.l r0, @r1 ! SB_RTCOR set
+
+ mov.l RTCNT_A, r1 ! SB_RTCNT address -> R1
+ mov.l RTCNT_D, r0 ! SB_RTCNT data -> R0
+ mov.l r0, @r1
+
+ mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1
+ mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0
+ mov.l r0, @r1 ! SB_RTCSR set
+
+ mov.l RFCR_A, r1 ! SB_RFCR address -> R1
+ mov.l RFCR_D, r0 ! SB_RFCR data -> R0
+ mov.l r0, @r1
+
+ mov.l SDMR3_A, r1 ! SDMR3 address -> R1
+ mov #0x00, r0 ! SDMR3 data -> R0
+ mov.b r0, @r1 ! SDMR3 set
+
+ ! BL bit off (init = ON) (?!?)
+
+ stc sr, r0 ! BL bit off(init=ON)
+ mov.l SR_MASK_D, r1
+ and r1, r0
+ ldc r0, sr
+
+ rts
+ mov #0, r0
+
+
+
+ .align 4
+
+CCR_A: .long CCR
+MMUCR_A: .long MMUCR
+MSTPCR0_A: .long MSTPCR0
+MSTPCR2_A: .long MSTPCR2
+PFC_PULCR_A: .long PULCR
+PFC_DRVCR_A: .long DRVCR
+SBSCR_A: .long SBSCR
+PSCR_A: .long PSCR
+RWTCSR_A: .long RWTCSR
+RWTCNT_A: .long RWTCNT
+FRQCR_A: .long FRQCR
+PLLCR_A: .long PLLCR
+DLLFRQ_A: .long DLLFRQ
+
+CCR_D: .long 0x00000800
+CCR_D_2: .long 0x00000103
+MMUCR_D: .long 0x00000004
+MSTPCR0_D: .long 0x00001001
+MSTPCR2_D: .long 0xffffffff
+PFC_PULCR_D: .long 0x6000
+PFC_DRVCR_D: .long 0x0464
+FRQCR_D: .long 0x07033639
+PLLCR_D: .long 0x00005000
+DLLFRQ_D: .long 0x000004F6 ! 20080115
+
+CMNCR_A: .long CMNCR
+CMNCR_D: .long 0x0000001B ! 20080115
+CS0BCR_A: .long CS0BCR ! Flash bank 1
+CS0BCR_D: .long 0x24920400
+CS4BCR_A: .long CS4BCR !
+CS4BCR_D: .long 0x10003400 ! 20080115
+CS5ABCR_A: .long CS5ABCR !
+CS5ABCR_D: .long 0x24920400
+CS5BBCR_A: .long CS5BBCR !
+CS5BBCR_D: .long 0x24920400
+CS6ABCR_A: .long CS6ABCR !
+CS6ABCR_D: .long 0x24920400
+
+CS0WCR_A: .long CS0WCR
+CS0WCR_D: .long 0x00000380
+CS4WCR_A: .long CS4WCR
+CS4WCR_D: .long 0x00100A81 ! 20080115
+CS5AWCR_A: .long CS5AWCR
+CS5AWCR_D: .long 0x00000300
+CS5BWCR_A: .long CS5BWCR
+CS5BWCR_D: .long 0x00000300
+CS6AWCR_A: .long CS6AWCR
+CS6AWCR_D: .long 0x00000300
+
+SDCR_A: .long SBSC_SDCR
+SDCR_D: .long 0x80160809 ! 20080115
+SDWCR_A: .long SBSC_SDWCR
+SDWCR_D: .long 0x0014450C ! 20080115
+SDPCR_A: .long SBSC_SDPCR
+SDPCR_D: .long 0x00000087
+RTCOR_A: .long SBSC_RTCOR
+RTCNT_A: .long SBSC_RTCNT
+RTCNT_D: .long 0xA55A0012
+RTCOR_D: .long 0xA55A001C ! 20080115
+RTCSR_A: .long SBSC_RTCSR
+RFCR_A: .long SBSC_RFCR
+RFCR_D: .long 0xA55A0221
+RTCSR_D: .long 0xA55A009a ! 20080115
+SDMR3_A: .long 0xFE581180 ! 20080115
+
+SR_MASK_D: .long 0xEFFFFF0F
+
+ .align 2
+
+SBSCR_D: .word 0x0044
+PSCR_D: .word 0x0000
+RWTCSR_D_1: .word 0xA507
+RWTCSR_D_2: .word 0xA504 ! 20080115
+RWTCNT_D: .word 0x5A00
+
diff --git a/board/MigoR/migo_r.c b/board/MigoR/migo_r.c
new file mode 100644
index 00000000000..53f4bb229f0
--- /dev/null
+++ b/board/MigoR/migo_r.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/MigoR/migo_r.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+ puts("BOARD: Renesas MigoR\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state (unsigned short value)
+{
+}
+
diff --git a/board/MigoR/u-boot.lds b/board/MigoR/u-boot.lds
new file mode 100644
index 00000000000..1877b812fec
--- /dev/null
+++ b/board/MigoR/u-boot.lds
@@ -0,0 +1,106 @@
+/*
+ * Copyrigth (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ Base address of internal SDRAM is 0x0C000000.
+ Although size of SDRAM can be either 16 or 32 MBytes,
+ we assume 16 MBytes (ie ignore upper half if the full
+ 32 MBytes is present).
+
+ NOTE: This address must match with the definition of
+ TEXT_BASE in config.mk (in this directory).
+
+ */
+ . = 0x8C000000 + (64*1024*1024) - (256*1024);
+
+ PROVIDE (reloc_dst = .);
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh4/start.o (.text)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenv)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(.rodata)
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
+
diff --git a/board/mpr2/Makefile b/board/mpr2/Makefile
new file mode 100644
index 00000000000..17ca17ec5b2
--- /dev/null
+++ b/board/mpr2/Makefile
@@ -0,0 +1,54 @@
+#
+# Copyright (C) 2007
+# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# (C) Copyright 2008
+# Mark Jonas <mark.jonas@de.bosch.com>
+#
+# board/mpr2/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := mpr2.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mpr2/config.mk b/board/mpr2/config.mk
new file mode 100644
index 00000000000..6d41d97cb7a
--- /dev/null
+++ b/board/mpr2/config.mk
@@ -0,0 +1,37 @@
+#
+# Copyright (C) 2007
+# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# Copyright (C) 2008
+# Mark Jonas <mark.jonas@de.bosch.com>
+#
+# board/mpr2/config.mk
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# TEXT_BASE refers to image _after_ relocation.
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+
+TEXT_BASE = 0x8FFC0000
diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S
new file mode 100644
index 00000000000..060957ad063
--- /dev/null
+++ b/board/mpr2/lowlevel_init.S
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * (C) Copyright 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * board/mpr2/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+/*
+ * Set frequency multipliers and dividers in FRQCR.
+ */
+ mov.l WTCSR_A,r1
+ mov.l WTCSR_D,r0
+ mov.w r0,@r1
+
+ mov.l WTCNT_A,r1
+ mov.l WTCNT_D,r0
+ mov.w r0,@r1
+
+ mov.l FRQCR_A,r1
+ mov.l FRQCR_D,r0
+ mov.w r0,@r1
+
+/*
+ * Setup CS0 (Flash).
+ */
+ mov.l CS0BCR_A, r1
+ mov.l CS0BCR_D, r0
+ mov.l r0, @r1
+
+ mov.l CS0WCR_A, r1
+ mov.l CS0WCR_D, r0
+ mov.l r0, @r1
+
+/*
+ * Setup CS3 (SDRAM).
+ */
+ mov.l CS3BCR_A, r1
+ mov.l CS3BCR_D, r0
+ mov.l r0, @r1
+
+ mov.l CS3WCR_A, r1
+ mov.l CS3WCR_D, r0
+ mov.l r0, @r1
+
+ mov.l SDCR_A, r1
+ mov.l SDCR_D1, r0
+ mov.l r0, @r1
+
+ mov.l RTCSR_A, r1
+ mov.l RTCSR_D, r0
+ mov.l r0, @r1
+
+ mov.l RTCNT_A, r1
+ mov.l RTCNT_D, r0
+ mov.l r0, @r1
+
+ mov.l RTCOR_A, r1
+ mov.l RTCOR_D, r0
+ mov.l r0, @r1
+
+ mov.l SDCR_A, r1
+ mov.l SDCR_D2, r0
+ mov.l r0, @r1
+
+ mov.l SDMR3_A, r1
+ mov.l SDMR3_D, r0
+ add r0, r1
+ mov #0, r0
+ mov.w r0, @r1
+
+ rts
+ nop
+
+ .align 4
+
+/*
+ * Configuration for MPR2 A.3 through A.7
+ */
+
+/*
+ * PLL Settings
+ */
+FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */
+WTCNT_D: .long 0x5A00 /* start counting at zero */
+WTCSR_D: .long 0xA507 /* divide by 4096 */
+
+/*
+ * Spansion S29GL256N11 @ 48 MHz
+ */
+CS0BCR_D: .long 0x12490400 /* 1 idle cycle inserted, normal space, 16 bit */
+CS0WCR_D: .long 0x00000340 /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
+
+/*
+ * Samsung K4S511632B-UL75 @ 48 MHz
+ * Micron MT48LC32M16A2-75 @ 48 MHz
+ */
+CS3BCR_D: .long 0x10004400 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
+CS3WCR_D: .long 0x00000091 /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
+SDCR_D1: .long 0x00000012 /* no refresh, 13 rows, 10 cols, NO bank active mode */
+SDCR_D2: .long 0x00000812 /* refresh */
+RTCSR_D: .long 0xA55A0008 /* 1/4, once */
+RTCNT_D: .long 0xA55A005D /* count 93 */
+RTCOR_D: .long 0xa55a005d /* count 93 */
+SDMR3_D: .long 0x440 /* mode register CL2, burst read and SINGLE WRITE */
+
+/*
+ * Registers
+ */
+
+FRQCR_A: .long 0xA415FF80
+WTCNT_A: .long 0xA415FF84
+WTCSR_A: .long 0xA415FF86
+
+#define BSC_BASE 0xA4FD0000
+CS0BCR_A: .long BSC_BASE + 0x04
+CS3BCR_A: .long BSC_BASE + 0x0C
+CS0WCR_A: .long BSC_BASE + 0x24
+CS3WCR_A: .long BSC_BASE + 0x2C
+SDCR_A: .long BSC_BASE + 0x44
+RTCSR_A: .long BSC_BASE + 0x48
+RTCNT_A: .long BSC_BASE + 0x4C
+RTCOR_A: .long BSC_BASE + 0x50
+SDMR3_A: .long BSC_BASE + 0x5000
diff --git a/board/mpr2/mpr2.c b/board/mpr2/mpr2.c
new file mode 100644
index 00000000000..2ddb0c10c19
--- /dev/null
+++ b/board/mpr2/mpr2.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * board/mpr2/mpr2.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+ puts("BOARD: MPR2\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * For MPR2 A.3 through A.7
+ */
+
+ /* CS2: Ethernet (0xA8000000 - 0xABFFFFFF) */
+ __raw_writel(0x36db0400, CS2BCR); /* 4 idle cycles, normal space, 16 bit data bus */
+ __raw_writel(0x000003c0, CS2WCR); /* (WR:8), no ext. wait */
+
+ /* CS4: CAN1 (0xB0000000 - 0xB3FFFFFF) */
+ __raw_writel(0x00000200, CS4BCR); /* no idle cycles, normal space, 8 bit data bus */
+ __raw_writel(0x00100981, CS4WCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+
+ /* CS5a: CAN2 (0xB4000000 - 0xB5FFFFFF) */
+ __raw_writel(0x00000200, CS5ABCR); /* no idle cycles, normal space, 8 bit data bus */
+ __raw_writel(0x00100981, CS5AWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+
+ /* CS5b: CAN3 (0xB6000000 - 0xB7FFFFFF) */
+ __raw_writel(0x00000200, CS5BBCR); /* no idle cycles, normal space, 8 bit data bus */
+ __raw_writel(0x00100981, CS5BWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+
+ /* CS6a: Rotary (0xB8000000 - 0xB9FFFFFF) */
+ __raw_writel(0x00000200, CS6ABCR); /* no idle cycles, normal space, 8 bit data bus */
+ __raw_writel(0x001009C1, CS6AWCR); /* (SW:1.5 WR:3 HW:1.5), no ext. wait */
+
+ /* set Pin Select Register A: /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND */
+ __raw_writew(0xAABC, PSELA); /* 10 10 10 10 10 11 11 00 */
+
+ /* set Pin Select Register B: /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved */
+ __raw_writew(0x3C00, PSELB); /* 0 0 11 11 0 0 00000000 */
+
+ /* set Pin Select Register C: SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved */
+ __raw_writew(0x0000, PSELC); /* 00 00 00 00 00000000 */
+
+ /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved */
+ __raw_writew(0x0000, PSELD); /* 0 00 00 00 00 00 00 00 0 */
+
+ /* OTH: (00) Other fuction
+ * GPO: (01) General Purpose Output
+ * GPI: (11) General Purpose Input
+ * GPI+: (10) General Purpose Input with internal pull-up
+ *-------------------------------------------------------
+ * A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5);
+ * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); */
+ __raw_writew(0x5555, PACR); /* 01 01 01 01 01 01 01 01 */
+
+ /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1);
+ * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); */
+ __raw_writew(0x5555, PBCR); /* 01 01 01 01 01 01 01 01 */
+
+ /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4);
+ * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; */
+ __raw_writew(0x5500, PCCR); /* 01 01 01 01 00 00 00 00 */
+
+ /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4);
+ * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); */
+ __raw_writew(0x5555, PDCR); /* 01 01 01 01 01 01 01 01 */
+
+ /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP;
+ * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; */
+ __raw_writew(0x2800, PECR); /* 00 10 10 00 00 00 00 00 */
+
+ /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3;
+ * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); */
+ __raw_writew(0x0002, PFCR); /* 00 00 00 00 00 00 00 10 */
+
+ /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ);G4 GPI(KEY2);
+ * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); */
+ __raw_writew(0x03D5, PGCR); /* 00 00 00 11 11 01 01 01 */
+
+ /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE);
+ * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; */
+ __raw_writew(0x0050, PHCR); /* 00 00 00 00 01 01 00 00 */
+
+ /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3;
+ * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; */
+ __raw_writew(0x0000, PJCR); /* 00 00 00 00 00 00 00 00 */
+
+ /* K7 (x); K6 (x); K5 (x); K4 (x)
+ * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nc); K0 PINT4(FLASH_READY); */
+ __raw_writew(0x00FB, PKCR); /* 00 00 00 00 11 11 10 11 */
+
+ /* L7 TRST; L6 TMS; L5 TDO; L4 TDI;
+ * L3 TCK; L2 (x); L1 (x); L0 (x); */
+ __raw_writew(0x0000, PLCR); /* 00 00 00 00 00 00 00 00 */
+
+ /* M7 GPO(CURRENT_SINK);M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); M4 GPO(LAN_RESET);
+ * M3 GPO(BUZZER); M2 GPO(LCD_BL); M1 CS5B(CAN3_CS); M0 GPI+(nc); */
+ __raw_writew(0x5552, PMCR); /* 01 01 01 01 01 01 00 10 */
+ __raw_writeb(0xF0, PMDR); /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, LAN_RESET=off, BUZZER=off, LCD_BL=off */
+
+ /* P7 (x); P6 (x); P5 (x); P4 GPO(on pullup);
+ * P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ); */
+ __raw_writew(0x0100, PPCR); /* 00 00 00 01 00 00 00 00 */
+ __raw_writeb(0x10, PPDR); /* no current flow through pullup */
+
+ /* R7 A25; R6 A24; R5 A23; R4 A22;
+ * R3 A21; R2 A20; R1 A19; R0 A0; */
+ __raw_writew(0x0000, PRCR); /* 00 00 00 00 00 00 00 00 */
+
+ /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2);
+ * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; */
+ __raw_writew(0x0140, PSCR); /* 00 00 00 01 01 00 00 00 */
+
+ /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS;
+ * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG); */
+ __raw_writew(0x0001, PTCR); /* 00 00 00 00 00 00 00 01 */
+
+ /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT);
+ * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; */
+ __raw_writew(0x0240, PUCR); /* 00 00 00 10 01 00 00 00 */
+
+ /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2);
+ * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); */
+ __raw_writew(0x0142, PVCR); /* 00 00 00 01 01 00 00 10 */
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+ printf("SDRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
diff --git a/board/mpr2/u-boot.lds b/board/mpr2/u-boot.lds
new file mode 100644
index 00000000000..6fee7f25422
--- /dev/null
+++ b/board/mpr2/u-boot.lds
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ Base address of internal SDRAM is 0x8C000000.
+ U-Boot resides in the last 256 kB of the 64 MB.
+
+ NOTE: This address must match with the definition of
+ TEXT_BASE in config.mk (in this directory).
+
+ */
+ . = 0x8C000000 + (64*1024*1024) - (256*1024);
+
+ PROVIDE (reloc_dst = .);
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh3/start.o (.text)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenv)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(.rodata)
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
diff --git a/board/r2dplus/Makefile b/board/r2dplus/Makefile
new file mode 100644
index 00000000000..ed609ea67e3
--- /dev/null
+++ b/board/r2dplus/Makefile
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2007,2008
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := r2dplus.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#################################################################
diff --git a/board/r2dplus/config.mk b/board/r2dplus/config.mk
new file mode 100644
index 00000000000..1ec7dcc605a
--- /dev/null
+++ b/board/r2dplus/config.mk
@@ -0,0 +1,23 @@
+#
+# Copyright (C) 2007,2008
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+TEXT_BASE = 0x0FFC0000
diff --git a/board/r2dplus/lowlevel_init.S b/board/r2dplus/lowlevel_init.S
new file mode 100644
index 00000000000..5755de87b9a
--- /dev/null
+++ b/board/r2dplus/lowlevel_init.S
@@ -0,0 +1,154 @@
+/*
+ * modified from SH-IPL+g (init-r0p751rlc0011rl.S)
+ * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz)
+ * Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+*/
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+ .global lowlevel_init
+ .text
+ .align 2
+
+lowlevel_init:
+
+ mov.l CCR_A, r1
+ mov.l CCR_D_D, r0
+ mov.l r0,@r1
+
+ mov.l MMUCR_A,r1
+ mov.l MMUCR_D,r0
+ mov.w r0,@r1
+
+ mov.l BCR1_A,r1
+ mov.l BCR1_D,r0
+ mov.l r0,@r1
+
+ mov.l BCR2_A,r1
+ mov.l BCR2_D,r0
+ mov.w r0,@r1
+
+ mov.l BCR3_A,r1
+ mov.l BCR3_D,r0
+ mov.w r0,@r1
+
+ mov.l BCR4_A,r1
+ mov.l BCR4_D,r0
+ mov.l r0,@r1
+
+ mov.l WCR1_A,r1
+ mov.l WCR1_D,r0
+ mov.l r0,@r1
+
+ mov.l WCR2_A,r1
+ mov.l WCR2_D,r0
+ mov.l r0,@r1
+
+ mov.l WCR3_A,r1
+ mov.l WCR3_D,r0
+ mov.l r0,@r1
+
+ mov.l PCR_A,r1
+ mov.l PCR_D,r0
+ mov.w r0,@r1
+
+ mov.l LED_A,r1
+ mov #0xff,r0
+ mov.w r0,@r1
+
+ mov.l MCR_A,r1
+ mov.l MCR_D1,r0
+ mov.l r0,@r1
+
+ mov.l RTCNT_A,r1
+ mov.l RTCNT_D,r0
+ mov.w r0,@r1
+
+ mov.l RTCOR_A,r1
+ mov.l RTCOR_D,r0
+ mov.w r0,@r1
+
+ mov.l RFCR_A,r1
+ mov.l RFCR_D,r0
+ mov.w r0,@r1
+
+ mov.l RTCSR_A,r1
+ mov.l RTCSR_D,r0
+ mov.w r0,@r1
+
+ mov.l SDMR3_A,r1
+ mov #0x55,r0
+ mov.b r0,@r1
+
+ /* Wait DRAM refresh 30 times */
+ mov.l RFCR_A,r1
+ mov #30,r3
+1:
+ mov.w @r1,r0
+ extu.w r0,r2
+ cmp/hi r3,r2
+ bf 1b
+
+ mov.l MCR_A,r1
+ mov.l MCR_D2,r0
+ mov.l r0,@r1
+
+ mov.l SDMR3_A,r1
+ mov #0,r0
+ mov.b r0,@r1
+
+ mov.l IRLMASK_A,r1
+ mov.l IRLMASK_D,r0
+ mov.l r0,@r1
+
+ mov.l CCR_A, r1
+ mov.l CCR_D_E, r0
+ mov.l r0, @r1
+
+ rts
+ nop
+
+ .align 2
+CCR_A: .long CCR /* Cache Control Register */
+CCR_D_D: .long 0x0808 /* Flush the cache, disable */
+CCR_D_E: .long 0x8000090B
+
+FRQCR_A: .long FRQCR /* FRQCR Address */
+FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */
+BCR1_A: .long BCR1 /* BCR1 Address */
+BCR1_D: .long 0x00180008
+BCR2_A: .long BCR2 /* BCR2 Address */
+BCR2_D: .long 0xabe8
+BCR3_A: .long BCR3 /* BCR3 Address */
+BCR3_D: .long 0x0000
+BCR4_A: .long BCR4 /* BCR4 Address */
+BCR4_D: .long 0x00000010
+WCR1_A: .long WCR1 /* WCR1 Address */
+WCR1_D: .long 0x33343333
+WCR2_A: .long WCR2 /* WCR2 Address */
+WCR2_D: .long 0xcff86fbf
+WCR3_A: .long WCR3 /* WCR3 Address */
+WCR3_D: .long 0x07777707
+LED_A: .long 0x04000036 /* LED Address */
+RTCNT_A: .long RTCNT /* RTCNT Address */
+RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */
+RTCOR_A: .long RTCOR /* RTCOR Address */
+RTCOR_D: .long 0xA534 /* RTCOR Write Code */
+RTCSR_A: .long RTCSR /* RTCSR Address */
+RTCSR_D: .long 0xA510 /* RTCSR Write Code */
+SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */
+SDMR3_D: .long 0x55
+MCR_A: .long MCR /* MCR Address */
+MCR_D1: .long 0x081901F4 /* MRSET:'0' */
+MCR_D2: .long 0x481901F4 /* MRSET:'1' */
+RFCR_A: .long RFCR /* RFCR Address */
+RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
+PCR_A: .long PCR /* PCR Address */
+PCR_D: .long 0x0000
+MMUCR_A: .long MMUCR /* MMUCCR Address */
+MMUCR_D: .long 0x00000000 /* MMUCCR Data */
+IRLMASK_A: .long 0xA4000000 /* IRLMASK Address */
+IRLMASK_D: .long 0x00000000 /* IRLMASK Data */
diff --git a/board/r2dplus/r2dplus.c b/board/r2dplus/r2dplus.c
new file mode 100644
index 00000000000..2ee3ea2f3fc
--- /dev/null
+++ b/board/r2dplus/r2dplus.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <asm/processor.h>
+#include <asm/pci.h>
+
+int checkboard(void)
+{
+ puts("BOARD: Renesas Solutions R2D Plus\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+#define FPGA_BASE 0xA4000000
+#define FPGA_CFCTL (FPGA_BASE + 0x04)
+#define FPGA_CFPOW (FPGA_BASE + 0x06)
+#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A)
+
+void ide_set_reset (int idereset)
+{
+ /* if reset = 1 IDE reset will be asserted */
+ if (idereset){
+ (*(vu_short *)FPGA_CFCTL) = 0x432;
+ (*(vu_short *)FPGA_CFPOW) |= 0x02;
+ (*(vu_short *)FPGA_CFCDINTCLR) = 0x01;
+ }
+}
+
+#if defined(CONFIG_PCI)
+static struct pci_controller hose;
+void pci_init_board(void)
+{
+ pci_sh7751_init( &hose );
+}
+#endif /* CONFIG_PCI */
diff --git a/board/r2dplus/u-boot.lds b/board/r2dplus/u-boot.lds
new file mode 100644
index 00000000000..96d8d81acf8
--- /dev/null
+++ b/board/r2dplus/u-boot.lds
@@ -0,0 +1,105 @@
+/*
+ * Copyrigth (c) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ Base address of internal SDRAM is 0x0C000000.
+ Although size of SDRAM can be either 16 or 32 MBytes,
+ we assume 16 MBytes (ie ignore upper half if the full
+ 32 MBytes is present).
+
+ NOTE: This address must match with the definition of
+ TEXT_BASE in config.mk (in this directory).
+
+ */
+ . = 0x0C000000 + (64*1024*1024) - (256*1024);
+
+ PROVIDE (reloc_dst = .);
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh4/start.o (.text)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenv)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(.rodata)
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
diff --git a/board/r7780mp/Makefile b/board/r7780mp/Makefile
new file mode 100644
index 00000000000..554dca1d5fe
--- /dev/null
+++ b/board/r7780mp/Makefile
@@ -0,0 +1,44 @@
+#
+# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
+#
+# board/r7780mp/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := r7780mp.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/r7780mp/config.mk b/board/r7780mp/config.mk
new file mode 100644
index 00000000000..6a045a15c22
--- /dev/null
+++ b/board/r7780mp/config.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
+#
+# board/r77870mp/config.mk
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# TEXT_BASE refers to image _after_ relocation.
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+
+TEXT_BASE = 0x0FFC0000
diff --git a/board/r7780mp/lowlevel_init.S b/board/r7780mp/lowlevel_init.S
new file mode 100644
index 00000000000..eb5d8b721d1
--- /dev/null
+++ b/board/r7780mp/lowlevel_init.S
@@ -0,0 +1,428 @@
+/*
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
+ *
+ * u-boot/board/r7780mp/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+
+/*
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
+ *
+ * (Note: As no stack is available, no subroutines can be called...).
+ */
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ mov.l CCR_A, r1 /* Address of Cache Control Register */
+ mov.l CCR_D, r0 /* Instruction Cache Invalidate */
+ mov.l r0, @r1
+
+ mov.l FRQCR_A, r1 /* Frequency control register */
+ mov.l FRQCR_D, r0
+ mov.l r0, @r1
+
+ /* pin_multi_setting */
+ mov.l BBG_PMMR_A,r1
+ mov.l BBG_PMMR_D_PMSR1,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMSR1_A,r1
+ mov.l BBG_PMSR1_D,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMMR_A,r1
+ mov.l BBG_PMMR_D_PMSR2,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMSR2_A,r1
+ mov.l BBG_PMSR2_D,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMMR_A,r1
+ mov.l BBG_PMMR_D_PMSR3,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMSR3_A,r1
+ mov.l BBG_PMSR3_D,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMMR_A,r1
+ mov.l BBG_PMMR_D_PMSR4,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMSR4_A,r1
+ mov.l BBG_PMSR4_D,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMMR_A,r1
+ mov.l BBG_PMMR_D_PMSRG,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMSRG_A,r1
+ mov.l BBG_PMSRG_D,r0
+ mov.l r0,@r1
+
+ /* cpg_setting */
+ mov.l FRQCR_A,r1
+ mov.l FRQCR_D,r0
+ mov.l r0,@r1
+
+ mov.l DLLCSR_A,r1
+ mov.l DLLCSR_D,r0
+ mov.l r0,@r1
+
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ /* wait 200us */
+ mov.l REPEAT0_R3,r3
+ mov #0,r2
+repeat0:
+ add #1,r2
+ cmp/hs r3,r2
+ bf repeat0
+ nop
+
+ /* bsc_setting */
+ mov.l MMSELR_A,r1
+ mov.l MMSELR_D,r0
+ mov.l r0,@r1
+
+ mov.l BCR_A,r1
+ mov.l BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS0BCR_A,r1
+ mov.l CS0BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS1BCR_A,r1
+ mov.l CS1BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS2BCR_A,r1
+ mov.l CS2BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS4BCR_A,r1
+ mov.l CS4BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS5BCR_A,r1
+ mov.l CS5BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS6BCR_A,r1
+ mov.l CS6BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS0WCR_A,r1
+ mov.l CS0WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS1WCR_A,r1
+ mov.l CS1WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS2WCR_A,r1
+ mov.l CS2WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS4WCR_A,r1
+ mov.l CS4WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS5WCR_A,r1
+ mov.l CS5WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS6WCR_A,r1
+ mov.l CS6WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS5PCR_A,r1
+ mov.l CS5PCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS6PCR_A,r1
+ mov.l CS6PCR_D,r0
+ mov.l r0,@r1
+
+ /* ddr_setting */
+ /* wait 200us */
+ mov.l REPEAT0_R3,r3
+ mov #0,r2
+repeat1:
+ add #1,r2
+ cmp/hs r3,r2
+ bf repeat1
+ nop
+
+ mov.l MIM_U_A,r0
+ mov.l MIM_U_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ mov.l MIM_L_A,r0
+ mov.l MIM_L_D0,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ mov.l STR_L_A,r0
+ mov.l STR_L_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ mov.l SDR_L_A,r0
+ mov.l SDR_L_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D0,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D1,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l EMRS_A,r0
+ mov.l EMRS_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l MRS1_A,r0
+ mov.l MRS1_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D2,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D3,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D4,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l MRS2_A,r0
+ mov.l MRS2_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D5,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ /* wait 200us */
+ mov.l REPEAT0_R1,r3
+ mov #0,r2
+repeat2:
+ add #1,r2
+ cmp/hs r3,r2
+ bf repeat2
+
+ synco
+
+ mov.l MIM_L_A,r0
+ mov.l MIM_L_D1,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ rts
+ nop
+ .align 4
+
+RWTCSR_D_1: .word 0xA507
+RWTCSR_D_2: .word 0xA507
+RWTCNT_D: .word 0x5A00
+
+BBG_PMMR_A: .long 0xFF800010
+BBG_PMSR1_A: .long 0xFF800014
+BBG_PMSR2_A: .long 0xFF800018
+BBG_PMSR3_A: .long 0xFF80001C
+BBG_PMSR4_A: .long 0xFF800020
+BBG_PMSRG_A: .long 0xFF800024
+
+BBG_PMMR_D_PMSR1: .long 0xffffbffd
+BBG_PMSR1_D: .long 0x00004002
+BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
+BBG_PMSR2_D: .long 0x03de5800
+BBG_PMMR_D_PMSR3: .long 0xfffffff8
+BBG_PMSR3_D: .long 0x00000007
+BBG_PMMR_D_PMSR4: .long 0xdffdfff9
+BBG_PMSR4_D: .long 0x20020006
+BBG_PMMR_D_PMSRG: .long 0xffffffff
+BBG_PMSRG_D: .long 0x00000000
+
+FRQCR_A: .long FRQCR
+DLLCSR_A: .long 0xffc40010
+FRQCR_D: .long 0x40233035
+DLLCSR_D: .long 0x00000000
+
+/* for DDR-SDRAM */
+MIM_U_A: .long MIM_1
+MIM_L_A: .long MIM_2
+SCR_U_A: .long SCR_1
+SCR_L_A: .long SCR_2
+STR_U_A: .long STR_1
+STR_L_A: .long STR_2
+SDR_U_A: .long SDR_1
+SDR_L_A: .long SDR_2
+
+EMRS_A: .long 0xFEC02000
+MRS1_A: .long 0xFEC00B08
+MRS2_A: .long 0xFEC00308
+
+MIM_U_D: .long 0x00004000
+MIM_L_D0: .long 0x03e80009
+MIM_L_D1: .long 0x03e80209
+SCR_L_D0: .long 0x3
+SCR_L_D1: .long 0x2
+SCR_L_D2: .long 0x2
+SCR_L_D3: .long 0x4
+SCR_L_D4: .long 0x4
+SCR_L_D5: .long 0x0
+STR_L_D: .long 0x000f0000
+SDR_L_D: .long 0x00000400
+EMRS_D: .long 0x0
+MRS1_D: .long 0x0
+MRS2_D: .long 0x0
+
+/* Cache Controller */
+CCR_A: .long CCR
+MMUCR_A: .long MMUCR
+RWTCNT_A: .long WTCNT
+
+CCR_D: .long 0x0000090b
+CCR_D_2: .long 0x00000103
+MMUCR_D: .long 0x00000004
+MSTPCR0_D: .long 0x00001001
+MSTPCR2_D: .long 0xffffffff
+
+/* local Bus State Controller */
+MMSELR_A: .long MMSELR
+BCR_A: .long BCR
+CS0BCR_A: .long CS0BCR
+CS1BCR_A: .long CS1BCR
+CS2BCR_A: .long CS2BCR
+CS4BCR_A: .long CS4BCR
+CS5BCR_A: .long CS5BCR
+CS6BCR_A: .long CS6BCR
+CS0WCR_A: .long CS0WCR
+CS1WCR_A: .long CS1WCR
+CS2WCR_A: .long CS2WCR
+CS4WCR_A: .long CS4WCR
+CS5WCR_A: .long CS5WCR
+CS6WCR_A: .long CS6WCR
+CS5PCR_A: .long CS5PCR
+CS6PCR_A: .long CS6PCR
+
+MMSELR_D: .long 0xA5A50003
+BCR_D: .long 0x00000000
+CS0BCR_D: .long 0x77777770
+CS1BCR_D: .long 0x77777670
+CS2BCR_D: .long 0x77777770
+CS4BCR_D: .long 0x77777770
+CS5BCR_D: .long 0x77777670
+CS6BCR_D: .long 0x77777770
+CS0WCR_D: .long 0x00020006
+CS1WCR_D: .long 0x00232304
+CS2WCR_D: .long 0x7777770F
+CS4WCR_D: .long 0x7777770F
+CS5WCR_D: .long 0x00101006
+CS6WCR_D: .long 0x77777703
+CS5PCR_D: .long 0x77000000
+CS6PCR_D: .long 0x77000000
+
+REPEAT0_R3: .long 0x00002000
+REPEAT0_R1: .long 0x0000200
diff --git a/board/r7780mp/r7780mp.c b/board/r7780mp/r7780mp.c
new file mode 100644
index 00000000000..1a37711d6fa
--- /dev/null
+++ b/board/r7780mp/r7780mp.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include "r7780mp.h"
+
+int checkboard(void)
+{
+#if defined(CONFIG_R7780MP)
+ puts("BOARD: Renesas Solutions R7780MP\n");
+#else
+ puts("BOARD: Renesas Solutions R7780RP\n");
+#endif
+ return 0;
+}
+
+int board_init(void)
+{
+ /* SCIF Enable */
+ *(vu_short*)PHCR = 0x0000;
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state (unsigned short value)
+{
+
+}
+
+void ide_set_reset (int idereset)
+{
+ /* if reset = 1 IDE reset will be asserted */
+ if (idereset){
+ (*(vu_short *)FPGA_CFCTL) = 0x432;
+#if defined(CONFIG_R7780MP)
+ (*(vu_short *)FPGA_CFPOW) |= 0x01;
+#else
+ (*(vu_short *)FPGA_CFPOW) |= 0x02;
+#endif
+ (*(vu_short *)FPGA_CFCDINTCLR) = 0x01;
+ }
+}
+
+#if defined(CONFIG_PCI)
+static struct pci_controller hose;
+void pci_init_board(void)
+{
+ pci_sh7780_init( &hose );
+}
+#endif
diff --git a/board/r7780mp/r7780mp.h b/board/r7780mp/r7780mp.h
new file mode 100644
index 00000000000..476a41354ff
--- /dev/null
+++ b/board/r7780mp/r7780mp.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2007 Nobuhiro Iwamatsu
+ * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * u-boot/board/r7780mp/r7780mp.h
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BOARD_R7780MP_R7780MP_H_
+#define _BOARD_R7780MP_R7780MP_H_
+
+/* R7780MP's FPGA register map */
+#define FPGA_BASE 0xa4000000
+#define FPGA_IRLMSK (FPGA_BASE + 0x00)
+#define FPGA_IRLMON (FPGA_BASE + 0x02)
+#define FPGA_IRLPRI1 (FPGA_BASE + 0x04)
+#define FPGA_IRLPRI2 (FPGA_BASE + 0x06)
+#define FPGA_IRLPRI3 (FPGA_BASE + 0x08)
+#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A)
+#define FPGA_RSTCTL (FPGA_BASE + 0x0C)
+#define FPGA_PCIBD (FPGA_BASE + 0x0E)
+#define FPGA_PCICD (FPGA_BASE + 0x10)
+#define FPGA_EXTGIO (FPGA_BASE + 0x16)
+#define FPGA_IVDRMON (FPGA_BASE + 0x18)
+#define FPGA_IVDRCR (FPGA_BASE + 0x1A)
+#define FPGA_OBLED (FPGA_BASE + 0x1C)
+#define FPGA_OBSW (FPGA_BASE + 0x1E)
+#define FPGA_TPCTL (FPGA_BASE + 0x100)
+#define FPGA_TPDCKCTL (FPGA_BASE + 0x102)
+#define FPGA_TPCLR (FPGA_BASE + 0x104)
+#define FPGA_TPXPOS (FPGA_BASE + 0x106)
+#define FPGA_TPYPOS (FPGA_BASE + 0x108)
+#define FPGA_DBSW (FPGA_BASE + 0x200)
+#define FPGA_VERSION (FPGA_BASE + 0x700)
+#define FPGA_CFCTL (FPGA_BASE + 0x300)
+#define FPGA_CFPOW (FPGA_BASE + 0x302)
+#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304)
+#define FPGA_PMR (FPGA_BASE + 0x900)
+
+#endif /* _BOARD_R7780RP_R7780RP_H_ */
diff --git a/board/r7780mp/u-boot.lds b/board/r7780mp/u-boot.lds
new file mode 100644
index 00000000000..e7499e5cd98
--- /dev/null
+++ b/board/r7780mp/u-boot.lds
@@ -0,0 +1,105 @@
+/*
+ * Copyrigth (c) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ Base address of internal SDRAM is 0x0C000000.
+ Although size of SDRAM can be either 16 or 32 MBytes,
+ we assume 16 MBytes (ie ignore upper half if the full
+ 32 MBytes is present).
+
+ NOTE: This address must match with the definition of
+ TEXT_BASE in config.mk (in this directory).
+
+ */
+ . = 0x08000000 + (128*1024*1024) - (256*1024);
+
+ PROVIDE (reloc_dst = .);
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh4/start.o (.text)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenv)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(.rodata)
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-17 14:43:54 +0000