diff options
Diffstat (limited to 'board')
157 files changed, 6172 insertions, 885 deletions
diff --git a/board/CZ.NIC/turris_1x/Kconfig b/board/CZ.NIC/turris_1x/Kconfig index f55dfa14bc6..baea4d80d1c 100644 --- a/board/CZ.NIC/turris_1x/Kconfig +++ b/board/CZ.NIC/turris_1x/Kconfig @@ -128,8 +128,6 @@ config SYS_FLASH_CFI default y config NAND_ECC_BCH default y -endif - config SYS_LOAD_ADDR default 0x1000000 @@ -153,3 +151,5 @@ config SPL_SYS_I2C_LEGACY default y endif + +endif diff --git a/board/CZ.NIC/turris_omnia/Makefile b/board/CZ.NIC/turris_omnia/Makefile index 341378b4e54..d1ef5cb8600 100644 --- a/board/CZ.NIC/turris_omnia/Makefile +++ b/board/CZ.NIC/turris_omnia/Makefile @@ -3,3 +3,5 @@ # Copyright (C) 2017 Marek Behún <kabel@kernel.org> obj-y := turris_omnia.o ../turris_atsha_otp.o ../turris_common.o +obj-$(CONFIG_CMD_EEPROM_LAYOUT) += eeprom.o +obj-$(CONFIG_SPL_BUILD) += old_ddr3_training.o diff --git a/board/CZ.NIC/turris_omnia/eeprom.c b/board/CZ.NIC/turris_omnia/eeprom.c new file mode 100644 index 00000000000..6e2640ad2a7 --- /dev/null +++ b/board/CZ.NIC/turris_omnia/eeprom.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Marek Behún <kabel@kernel.org> + */ + +#include <asm/unaligned.h> +#include <ctype.h> +#include <linux/compiler.h> +#include <linux/kernel.h> +#include <eeprom_field.h> +#include <eeprom_layout.h> +#include <u-boot/crc.h> + +#define _DEF_FIELD(_n, _s, _t) \ + { _n, _s, NULL, eeprom_field_print_ ## _t, eeprom_field_update_ ## _t } + +static void eeprom_field_print_ramsz(const struct eeprom_field *field) +{ + printf(PRINT_FIELD_SEGMENT, field->name); + printf("%u\n", get_unaligned_le32(field->buf)); +} + +static int eeprom_field_update_ramsz(struct eeprom_field *field, char *value) +{ + u32 sz; + + if (value[0] == '1' || value[0] == '2' || value[0] == '4') + sz = value[0] - '0'; + else + return -1; + + if (value[1] != '\0') + return -1; + + put_unaligned_le32(sz, field->buf); + + return 0; +} + +static void eeprom_field_print_region(const struct eeprom_field *field) +{ + eeprom_field_print_ascii(field); +} + +static int eeprom_field_update_region(struct eeprom_field *field, char *value) +{ + if (strlen(value) != 2) { + printf("%s: has to be 2 characters\n", field->name); + return -1; + } + + memcpy(field->buf, value, 2); + memset(&field->buf[2], '\0', 2); + + return 0; +} + +static void eeprom_field_print_ddr_speed(const struct eeprom_field *field) +{ + printf(PRINT_FIELD_SEGMENT, field->name); + + if (field->buf[0] == '\0' || field->buf[0] == 0xff) + puts("(empty, defaults to 1600K)\n"); + else + printf("%.5s\n", field->buf); +} + +bool omnia_valid_ddr_speed(const char *name); +void omnia_print_ddr_speeds(void); + +static int eeprom_field_update_ddr_speed(struct eeprom_field *field, + char *value) +{ + if (value[0] == '\0') { + /* setting default value */ + memset(field->buf, 0xff, field->size); + + return 0; + } + + if (!omnia_valid_ddr_speed(value)) { + printf("%s: invalid setting, supported values are:\n ", + field->name); + omnia_print_ddr_speeds(); + + return -1; + } + + strncpy(field->buf, value, field->size); + + return 0; +} + +static void eeprom_field_print_bool(const struct eeprom_field *field) +{ + unsigned char val = field->buf[0]; + + printf(PRINT_FIELD_SEGMENT, field->name); + + if (val == 0xff) + puts("(empty, defaults to 0)\n"); + else + printf("%u\n", val); +} + +static int eeprom_field_update_bool(struct eeprom_field *field, char *value) +{ + unsigned char *val = &field->buf[0]; + + if (value[0] == '\0') { + /* setting default value */ + *val = 0xff; + + return 0; + } + + if (value[1] != '\0') + return -1; + + if (value[0] == '1' || value[0] == '0') + *val = value[0] - '0'; + else + return -1; + + return 0; +} + +static struct eeprom_field omnia_layout[] = { + _DEF_FIELD("Magic constant", 4, bin), + _DEF_FIELD("RAM size in GB", 4, ramsz), + _DEF_FIELD("Wi-Fi Region", 4, region), + _DEF_FIELD("CRC32 checksum", 4, bin), + _DEF_FIELD("DDR speed", 5, ddr_speed), + _DEF_FIELD("Use old DDR training", 1, bool), + _DEF_FIELD("Extended reserved fields", 38, reserved), + _DEF_FIELD("Extended CRC32 checksum", 4, bin), +}; + +static struct eeprom_field *crc_field = &omnia_layout[3]; +static struct eeprom_field *ext_crc_field = + &omnia_layout[ARRAY_SIZE(omnia_layout) - 1]; + +static int omnia_update_field(struct eeprom_layout *layout, char *field_name, + char *new_data) +{ + struct eeprom_field *field; + int err; + + if (!new_data) + return 0; + + if (!field_name) + return -1; + + field = eeprom_layout_find_field(layout, field_name, true); + if (!field) + return -1; + + err = field->update(field, new_data); + if (err) { + printf("Invalid data for field %s\n", field_name); + return err; + } + + if (field < crc_field) { + u32 crc = crc32(0, layout->data, 12); + put_unaligned_le32(crc, crc_field->buf); + } + + if (field < ext_crc_field) { + u32 crc = crc32(0, layout->data, 60); + put_unaligned_le32(crc, ext_crc_field->buf); + } + + return 0; +} + +void eeprom_layout_assign(struct eeprom_layout *layout, int) +{ + layout->fields = omnia_layout; + layout->num_of_fields = ARRAY_SIZE(omnia_layout); + layout->update = omnia_update_field; + layout->data_size = 64; +} + +int eeprom_layout_detect(unsigned char *) +{ + /* Turris Omnia has only one version of EEPROM layout */ + return 0; +} diff --git a/board/CZ.NIC/turris_omnia/old_ddr3_training.c b/board/CZ.NIC/turris_omnia/old_ddr3_training.c new file mode 100644 index 00000000000..cdb3487ad9e --- /dev/null +++ b/board/CZ.NIC/turris_omnia/old_ddr3_training.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Marek Behún <kabel@kernel.org> + */ + +#include <asm/arch/soc.h> +#include <asm/io.h> + +#include "../drivers/ddr/marvell/a38x/old/ddr3_init.h" + +static struct hws_topology_map board_topology_map_1g = { + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ + { { { {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0} }, + SPEED_BIN_DDR_1600K, /* speed_bin */ + BUS_WIDTH_16, /* memory_width */ + MEM_4G, /* mem_size */ + DDR_FREQ_800, /* frequency */ + 0, 0, /* cas_l cas_wl */ + HWS_TEMP_NORMAL, /* temperature */ + HWS_TIM_2T} }, /* timing (force 2t) */ + 5, /* Num Of Bus Per Interface*/ + BUS_MASK_32BIT /* Busses mask */ +}; + +static struct hws_topology_map board_topology_map_2g = { + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ + { { { {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0} }, + SPEED_BIN_DDR_1600K, /* speed_bin */ + BUS_WIDTH_16, /* memory_width */ + MEM_8G, /* mem_size */ + DDR_FREQ_800, /* frequency */ + 0, 0, /* cas_l cas_wl */ + HWS_TEMP_NORMAL, /* temperature */ + HWS_TIM_2T} }, /* timing (force 2t) */ + 5, /* Num Of Bus Per Interface*/ + BUS_MASK_32BIT /* Busses mask */ +}; + +/* defined in turris_omnia.c */ +extern int omnia_get_ram_size_gb(void); + +struct hws_topology_map *ddr3_get_topology_map(void) +{ + if (omnia_get_ram_size_gb() == 2) + return &board_topology_map_2g; + else + return &board_topology_map_1g; +} + +__weak u32 sys_env_get_topology_update_info(struct topology_update_info *tui) +{ + return MV_OK; +} diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 4ee1a394b02..2f29d26edf8 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -429,12 +429,42 @@ struct omnia_eeprom { u32 ramsize; char region[4]; u32 crc; + + /* second part (only considered if crc2 is not all-ones) */ + char ddr_speed[5]; + u8 old_ddr_training; + u8 reserved[38]; + u32 crc2; }; +static bool is_omnia_eeprom_second_part_valid(const struct omnia_eeprom *oep) +{ + return oep->crc2 != 0xffffffff; +} + +static void make_omnia_eeprom_second_part_invalid(struct omnia_eeprom *oep) +{ + oep->crc2 = 0xffffffff; +} + +static bool check_eeprom_crc(const void *buf, size_t size, u32 expected, + const char *name) +{ + u32 crc; + + crc = crc32(0, buf, size); + if (crc != expected) { + printf("bad %s EEPROM CRC (stored %08x, computed %08x)\n", + name, expected, crc); + return false; + } + + return true; +} + static bool omnia_read_eeprom(struct omnia_eeprom *oep) { struct udevice *chip; - u32 crc; int ret; chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR, @@ -455,17 +485,19 @@ static bool omnia_read_eeprom(struct omnia_eeprom *oep) return false; } - crc = crc32(0, (void *)oep, sizeof(*oep) - 4); - if (crc != oep->crc) { - printf("bad EEPROM CRC (stored %08x, computed %08x)\n", - oep->crc, crc); + if (!check_eeprom_crc(oep, offsetof(struct omnia_eeprom, crc), oep->crc, + "first")) return false; - } + + if (is_omnia_eeprom_second_part_valid(oep) && + !check_eeprom_crc(oep, offsetof(struct omnia_eeprom, crc2), + oep->crc2, "second")) + make_omnia_eeprom_second_part_invalid(oep); return true; } -static int omnia_get_ram_size_gb(void) +int omnia_get_ram_size_gb(void) { static int ram_size; struct omnia_eeprom oep; @@ -490,6 +522,39 @@ static int omnia_get_ram_size_gb(void) return ram_size; } +bool board_use_old_ddr3_training(void) +{ + struct omnia_eeprom oep; + + if (!omnia_read_eeprom(&oep)) + return false; + + if (!is_omnia_eeprom_second_part_valid(&oep)) + return false; + + return oep.old_ddr_training == 1; +} + +static const char *omnia_get_ddr_speed(void) +{ + struct omnia_eeprom oep; + static char speed[sizeof(oep.ddr_speed) + 1]; + + if (!omnia_read_eeprom(&oep)) + return NULL; + + if (!is_omnia_eeprom_second_part_valid(&oep)) + return NULL; + + if (!oep.ddr_speed[0] || oep.ddr_speed[0] == 0xff) + return NULL; + + memcpy(&speed, &oep.ddr_speed, sizeof(oep.ddr_speed)); + speed[sizeof(speed) - 1] = '\0'; + + return speed; +} + static const char * const omnia_get_mcu_type(void) { static char result[] = "xxxxxxx (with peripheral resets)"; @@ -604,12 +669,84 @@ static struct mv_ddr_topology_map board_topology_map_2g = { {0} /* timing parameters */ }; +static const struct omnia_ddr_speed { + char name[5]; + u8 speed_bin; + u8 freq; +} omnia_ddr_speeds[] = { + { "1066F", SPEED_BIN_DDR_1066F, MV_DDR_FREQ_533 }, + { "1333H", SPEED_BIN_DDR_1333H, MV_DDR_FREQ_667 }, + { "1600K", SPEED_BIN_DDR_1600K, MV_DDR_FREQ_800 }, +}; + +static const struct omnia_ddr_speed *find_ddr_speed_setting(const char *name) +{ + for (int i = 0; i < ARRAY_SIZE(omnia_ddr_speeds); ++i) + if (!strncmp(name, omnia_ddr_speeds[i].name, 5)) + return &omnia_ddr_speeds[i]; + + return NULL; +} + +bool omnia_valid_ddr_speed(const char *name) +{ + return find_ddr_speed_setting(name) != NULL; +} + +void omnia_print_ddr_speeds(void) +{ + for (int i = 0; i < ARRAY_SIZE(omnia_ddr_speeds); ++i) + printf("%.5s%s", omnia_ddr_speeds[i].name, + i == ARRAY_SIZE(omnia_ddr_speeds) - 1 ? "\n" : ", "); +} + +static void fixup_speed_in_ddr_topology(struct mv_ddr_topology_map *topology) +{ + typeof(topology->interface_params[0]) *params; + const struct omnia_ddr_speed *setting; + const char *speed; + static bool done; + + if (done) + return; + + done = true; + + speed = omnia_get_ddr_speed(); + if (!speed) + return; + + setting = find_ddr_speed_setting(speed); + if (!setting) { + printf("Unsupported value %s for DDR3 speed in EEPROM!\n", + speed); + return; + } + + params = &topology->interface_params[0]; + + /* don't inform if we are not changing the speed from the default one */ + if (params->speed_bin_index == setting->speed_bin) + return; + + printf("Fixing up DDR3 speed (EEPROM defines %s)\n", speed); + + params->speed_bin_index = setting->speed_bin; + params->memory_freq = setting->freq; +} + struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) { + struct mv_ddr_topology_map *topology; + if (omnia_get_ram_size_gb() == 2) - return &board_topology_map_2g; + topology = &board_topology_map_2g; else - return &board_topology_map_1g; + topology = &board_topology_map_1g; + + fixup_speed_in_ddr_topology(topology); + + return topology; } static int set_regdomain(void) @@ -978,11 +1115,21 @@ static int fixup_mcu_gpio_in_pcie_nodes(void *blob) return 0; } -static int fixup_mcu_gpio_in_eth_wan_node(void *blob) +static int get_phy_wan_node_offset(const void *blob) +{ + u32 phy_wan_phandle; + + phy_wan_phandle = fdt_getprop_u32_default(blob, "ethernet2", "phy-handle", 0); + if (!phy_wan_phandle) + return -FDT_ERR_NOTFOUND; + + return fdt_node_offset_by_phandle(blob, phy_wan_phandle); +} + +static int fixup_mcu_gpio_in_phy_wan_node(void *blob) { unsigned int mcu_phandle; - int eth_wan_node; - int ret; + int phy_wan_node, ret; ret = fdt_increase_size(blob, 64); if (ret < 0) { @@ -990,21 +1137,17 @@ static int fixup_mcu_gpio_in_eth_wan_node(void *blob) return ret; } - eth_wan_node = fdt_path_offset(blob, "ethernet2"); - if (eth_wan_node < 0) - return eth_wan_node; + phy_wan_node = get_phy_wan_node_offset(blob); + if (phy_wan_node < 0) + return phy_wan_node; mcu_phandle = fdt_create_phandle_by_compatible(blob, "cznic,turris-omnia-mcu"); if (!mcu_phandle) return -FDT_ERR_NOPHANDLES; - /* insert: phy-reset-gpios = <&mcu 2 gpio GPIO_ACTIVE_LOW>; */ - ret = insert_mcu_gpio_prop(blob, eth_wan_node, "phy-reset-gpios", - mcu_phandle, 2, ilog2(EXT_CTL_nRES_PHY), GPIO_ACTIVE_LOW); - if (ret < 0) - return ret; - - return 0; + /* insert: reset-gpios = <&mcu 2 gpio GPIO_ACTIVE_LOW>; */ + return insert_mcu_gpio_prop(blob, phy_wan_node, "reset-gpios", + mcu_phandle, 2, ilog2(EXT_CTL_nRES_PHY), GPIO_ACTIVE_LOW); } static void fixup_atsha_node(void *blob) @@ -1033,7 +1176,7 @@ int board_fix_fdt(void *blob) { if (omnia_mcu_has_feature(FEAT_PERIPH_MCU)) { fixup_mcu_gpio_in_pcie_nodes(blob); - fixup_mcu_gpio_in_eth_wan_node(blob); + fixup_mcu_gpio_in_phy_wan_node(blob); } fixup_msata_port_nodes(blob); @@ -1218,14 +1361,14 @@ int ft_board_setup(void *blob, struct bd_info *bd) int node; /* - * U-Boot's FDT blob contains phy-reset-gpios in ethernet2 - * node when MCU controls all peripherals resets. + * U-Boot's FDT blob contains reset-gpios in ethernet2 PHY node when MCU + * controls all peripherals resets. * Fixup MCU GPIO nodes in PCIe and eth wan nodes in this case. */ - node = fdt_path_offset(gd->fdt_blob, "ethernet2"); - if (node >= 0 && fdt_getprop(gd->fdt_blob, node, "phy-reset-gpios", NULL)) { + node = get_phy_wan_node_offset(gd->fdt_blob); + if (node >= 0 && fdt_getprop(gd->fdt_blob, node, "reset-gpios", NULL)) { fixup_mcu_gpio_in_pcie_nodes(blob); - fixup_mcu_gpio_in_eth_wan_node(blob); + fixup_mcu_gpio_in_phy_wan_node(blob); } fixup_spi_nor_partitions(blob); diff --git a/board/Marvell/mvebu_armada-37xx/MAINTAINERS b/board/Marvell/mvebu_armada-37xx/MAINTAINERS index 9b0afeef106..e96499e1612 100644 --- a/board/Marvell/mvebu_armada-37xx/MAINTAINERS +++ b/board/Marvell/mvebu_armada-37xx/MAINTAINERS @@ -9,3 +9,8 @@ ESPRESSOBin BOARD M: Konstantin Porotchkin <kostap@marvell.com> S: Maintained F: configs/mvebu_espressobin-88f3720_defconfig + +ESPRESSOBin Ultra BOARD +M: Ben Schneider <ben@bens.haus> +S: Maintained +F: configs/mvebu_espressobin_ultra-88f3720_defconfig diff --git a/board/Marvell/octeon_nic23/board.c b/board/Marvell/octeon_nic23/board.c index bc9332cb74a..cf20c97684a 100644 --- a/board/Marvell/octeon_nic23/board.c +++ b/board/Marvell/octeon_nic23/board.c @@ -249,7 +249,7 @@ void board_configure_qlms(void) * read the incorrect device ID 0x9700 (reset value) instead of 0x9702 * (restored value). */ -static void octeon_board_restore_pf(void *ctx) +static void octeon_board_restore_pf(struct cyclic_info *c) { union cvmx_spemx_flr_pf_stopreq stopreq; static bool start_initialized[2] = {false, false}; @@ -357,10 +357,13 @@ int board_late_init(void) board_configure_qlms(); /* Register cyclic function for PCIe FLR fixup */ - cyclic = cyclic_register(octeon_board_restore_pf, 100, - "pcie_flr_fix", NULL); - if (!cyclic) + cyclic = calloc(1, sizeof(*cyclic)); + if (cyclic) { + cyclic_register(cyclic, octeon_board_restore_pf, 100, + "pcie_flr_fix"); + } else { printf("Registering of cyclic function failed\n"); + } return 0; } diff --git a/board/Synology/common/legacy.c b/board/Synology/common/legacy.c index a0bace7b46c..2e3aa660eaa 100644 --- a/board/Synology/common/legacy.c +++ b/board/Synology/common/legacy.c @@ -6,6 +6,7 @@ */ #include <config.h> +#include <stdio.h> #include <vsprintf.h> #include <env.h> #include <net.h> diff --git a/board/amd/common b/board/amd/common new file mode 120000 index 00000000000..cd4d172974b --- /dev/null +++ b/board/amd/common @@ -0,0 +1 @@ +../xilinx/common/
\ No newline at end of file diff --git a/board/amd/versal2/Kconfig b/board/amd/versal2/Kconfig new file mode 100644 index 00000000000..ab46af6935e --- /dev/null +++ b/board/amd/versal2/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2020 - 2022, Xilinx, Inc. +# Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. +# +if ARCH_VERSAL2 + +config CMD_VERSAL2 + bool "Enable Versal Gen 2 specific commands" + default y + depends on ZYNQMP_FIRMWARE + help + Select this to enable AMD Versal Gen 2 specific commands. + Commands like versal2 loadpdi are enabled by this. + +endif diff --git a/board/amd/versal2/MAINTAINERS b/board/amd/versal2/MAINTAINERS new file mode 100644 index 00000000000..af7913d8db3 --- /dev/null +++ b/board/amd/versal2/MAINTAINERS @@ -0,0 +1,7 @@ +XILINX_VERSAL2 BOARDS +M: Michal Simek <michal.simek@amd.com> +S: Maintained +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git +F: arch/arm/dts/versal2* +F: board/amd/ +F: configs/amd* diff --git a/board/amd/versal2/Makefile b/board/amd/versal2/Makefile new file mode 100644 index 00000000000..3a044517f0c --- /dev/null +++ b/board/amd/versal2/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2021 - 2022, Xilinx, Inc. +# Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. +# +# Michal Simek <michal.simek@amd.com> +# + +obj-y := board.o + +obj-$(CONFIG_CMD_VERSAL2) += cmds.o diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c new file mode 100644 index 00000000000..5651d516a9e --- /dev/null +++ b/board/amd/versal2/board.c @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <cpu_func.h> +#include <fdtdec.h> +#include <init.h> +#include <env_internal.h> +#include <log.h> +#include <malloc.h> +#include <time.h> +#include <asm/cache.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include "../../xilinx/common/board.h" + +#include <linux/bitfield.h> +#include <debug_uart.h> +#include <generated/dt.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + printf("EL Level:\tEL%d\n", current_el()); + + return 0; +} + +static u32 platform_id, platform_version; + +char *soc_name_decode(void) +{ + char *name, *platform_name; + + switch (platform_id) { + case VERSAL2_SPP: + platform_name = "spp"; + break; + case VERSAL2_EMU: + platform_name = "emu"; + break; + case VERSAL2_SPP_MMD: + platform_name = "spp-mmd"; + break; + case VERSAL2_EMU_MMD: + platform_name = "emu-mmd"; + break; + case VERSAL2_QEMU: + platform_name = "qemu"; + break; + default: + return NULL; + } + + /* + * --rev. are 6 chars + * max platform name is qemu which is 4 chars + * platform version number are 1+1 + * Plus 1 char for \n + */ + name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13); + if (!name) + return NULL; + + sprintf(name, "%s-%s-rev%d.%d-el%d", CONFIG_SYS_BOARD, + platform_name, platform_version / 10, + platform_version % 10, current_el()); + + return name; +} + +bool soc_detection(void) +{ + u32 version, ps_version; + + version = readl(PMC_TAP_VERSION); + platform_id = FIELD_GET(PLATFORM_MASK, version); + ps_version = FIELD_GET(PS_VERSION_MASK, version); + + debug("idcode %x, version %x, usercode %x\n", + readl(PMC_TAP_IDCODE), version, + readl(PMC_TAP_USERCODE)); + + debug("pmc_ver %lx, ps version %x, rtl version %lx\n", + FIELD_GET(PMC_VERSION_MASK, version), + ps_version, + FIELD_GET(RTL_VERSION_MASK, version)); + + platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); + + debug("Platform id: %d version: %d.%d\n", platform_id, + platform_version / 10, platform_version % 10); + + return true; +} + +int board_early_init_r(void) +{ + u32 val; + + if (current_el() != 3) + return 0; + + debug("iou_switch ctrl div0 %x\n", + readl(&crlapb_base->iou_switch_ctrl)); + + writel(IOU_SWITCH_CTRL_CLKACT_BIT | + (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), + &crlapb_base->iou_switch_ctrl); + + /* Global timer init - Program time stamp reference clk */ + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + debug("ref ctrl 0x%x\n", + readl(&crlapb_base->timestamp_ref_ctrl)); + + /* Clear reset of timestamp reg */ + writel(0, &crlapb_base->rst_timestamp); + + /* + * Program freq register in System counter and + * enable system counter. + */ + writel(CONFIG_COUNTER_FREQUENCY, + &iou_scntr_secure->base_frequency_id_register); + + debug("counter val 0x%x\n", + readl(&iou_scntr_secure->base_frequency_id_register)); + + writel(IOU_SCNTRS_CONTROL_EN, + &iou_scntr_secure->counter_control_register); + + debug("scntrs control 0x%x\n", + readl(&iou_scntr_secure->counter_control_register)); + debug("timer 0x%llx\n", get_ticks()); + debug("timer 0x%llx\n", get_ticks()); + + return 0; +} + +static u8 versal_net_get_bootmode(void) +{ + u8 bootmode; + u32 reg = 0; + + reg = readl(&crp_base->boot_mode_usr); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + bootmode = reg & BOOT_MODES_MASK; + + return bootmode; +} + +static int boot_targets_setup(void) +{ + u8 bootmode; + struct udevice *dev; + int bootseq = -1; + int bootseq_len = 0; + int env_targets_len = 0; + const char *mode = NULL; + char *new_targets; + char *env_targets; + + bootmode = versal_net_get_bootmode(); + + puts("Bootmode: "); + switch (bootmode) { + case USB_MODE: + puts("USB_MODE\n"); + mode = "usb_dfu0 usb_dfu1"; + break; + case JTAG_MODE: + puts("JTAG_MODE\n"); + mode = "jtag pxe dhcp"; + break; + case QSPI_MODE_24BIT: + puts("QSPI_MODE_24\n"); + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1030000", &dev)) { + debug("QSPI driver for QSPI device is not present\n"); + break; + } + mode = "xspi"; + bootseq = dev_seq(dev); + break; + case QSPI_MODE_32BIT: + puts("QSPI_MODE_32\n"); + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1030000", &dev)) { + debug("QSPI driver for QSPI device is not present\n"); + break; + } + mode = "xspi"; + bootseq = dev_seq(dev); + break; + case OSPI_MODE: + puts("OSPI_MODE\n"); + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1010000", &dev)) { + debug("OSPI driver for OSPI device is not present\n"); + break; + } + mode = "xspi"; + bootseq = dev_seq(dev); + break; + case EMMC_MODE: + puts("EMMC_MODE\n"); + mode = "mmc"; + bootseq = dev_seq(dev); + break; + case SELECTMAP_MODE: + puts("SELECTMAP_MODE\n"); + break; + case SD_MODE: + puts("SD_MODE\n"); + if (uclass_get_device_by_name(UCLASS_MMC, + "mmc@f1040000", &dev)) { + debug("SD0 driver for SD0 device is not present\n"); + break; + } + debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev)); + + mode = "mmc"; + bootseq = dev_seq(dev); + break; + case SD1_LSHFT_MODE: + puts("LVL_SHFT_"); + fallthrough; + case SD_MODE1: + puts("SD_MODE1\n"); + if (uclass_get_device_by_name(UCLASS_MMC, + "mmc@f1050000", &dev)) { + debug("SD1 driver for SD1 device is not present\n"); + break; + } + debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev)); + + mode = "mmc"; + bootseq = dev_seq(dev); + break; + default: + printf("Invalid Boot Mode:0x%x\n", bootmode); + break; + } + + if (mode) { + if (bootseq >= 0) { + bootseq_len = snprintf(NULL, 0, "%i", bootseq); + debug("Bootseq len: %x\n", bootseq_len); + } + + /* + * One terminating char + one byte for space between mode + * and default boot_targets + */ + env_targets = env_get("boot_targets"); + if (env_targets) + env_targets_len = strlen(env_targets); + + new_targets = calloc(1, strlen(mode) + env_targets_len + 2 + + bootseq_len); + if (!new_targets) + return -ENOMEM; + + if (bootseq >= 0) + sprintf(new_targets, "%s%x %s", mode, bootseq, + env_targets ? env_targets : ""); + else + sprintf(new_targets, "%s %s", mode, + env_targets ? env_targets : ""); + + env_set("boot_targets", new_targets); + } + + return 0; +} + +int board_late_init(void) +{ + int ret; + + if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { + debug("Saved variables - Skipping\n"); + return 0; + } + + if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) + return 0; + + if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) { + ret = boot_targets_setup(); + if (ret) + return ret; + } + + return board_late_init_xilinx(); +} + +int dram_init_banksize(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + + mem_map_fill(); + + return 0; +} + +int dram_init(void) +{ + int ret; + + if (IS_ENABLED(CONFIG_SYS_MEM_RSVD_FOR_MMU)) + ret = fdtdec_setup_mem_size_base(); + else + ret = fdtdec_setup_mem_size_base_lowest(); + + if (ret) + return -EINVAL; + + return 0; +} + +void reset_cpu(void) +{ +} diff --git a/board/amd/versal2/cmds.c b/board/amd/versal2/cmds.c new file mode 100644 index 00000000000..56ae39bc6a1 --- /dev/null +++ b/board/amd/versal2/cmds.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <cpu_func.h> +#include <command.h> +#include <log.h> +#include <memalign.h> +#include <versalpl.h> +#include <vsprintf.h> +#include <zynqmp_firmware.h> + +/** + * do_versal2_load_pdi - Handle the "versal2 load pdi" command-line command + * @cmdtp: Command data struct pointer + * @flag: Command flag + * @argc: Command-line argument count + * @argv: Array of command-line arguments + * + * Processes the versal2 load pdi command + * + * Return: return 0 on success, Error value if command fails. + * CMD_RET_USAGE incase of incorrect/missing parameters. + */ +static int do_versal2_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + u32 buf_lo, buf_hi; + u32 ret_payload[PAYLOAD_ARG_CNT]; + ulong addr, *pdi_buf; + size_t len; + int ret; + + if (argc != cmdtp->maxargs) { + debug("pdi_load: incorrect parameters passed\n"); + return CMD_RET_USAGE; + } + + addr = simple_strtol(argv[1], NULL, 16); + if (!addr) { + debug("pdi_load: zero pdi_data address\n"); + return CMD_RET_USAGE; + } + + len = hextoul(argv[2], NULL); + if (!len) { + debug("pdi_load: zero size\n"); + return CMD_RET_USAGE; + } + + pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN); + if ((ulong)addr != (ulong)pdi_buf) { + memcpy((void *)pdi_buf, (void *)addr, len); + debug("Pdi addr:0x%lx aligned to 0x%lx\n", + addr, (ulong)pdi_buf); + } + + flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len); + + buf_lo = lower_32_bits((ulong)pdi_buf); + buf_hi = upper_32_bits((ulong)pdi_buf); + + ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, + buf_hi, 0, ret_payload); + if (ret) + printf("PDI load failed with err: 0x%08x\n", ret); + + return cmd_process_error(cmdtp, ret); +} + +U_BOOT_LONGHELP(versal2, + "loadpdi addr len - Load pdi image\n" + "load pdi image at ddr address 'addr' with pdi image size 'len'\n"); + +U_BOOT_CMD_WITH_SUBCMDS(versal2, "Versal Gen 2 sub-system", versal2_help_text, + U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1, + do_versal2_load_pdi)); diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c index 099eea60c39..5c57b902d14 100644 --- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c +++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c @@ -6,14 +6,12 @@ #include <abuf.h> #include <adc.h> #include <asm/io.h> -#include <command.h> #include <display.h> #include <dm.h> #include <dm/lists.h> #include <env.h> #include <fdt_support.h> #include <linux/delay.h> -#include <linux/iopoll.h> #include <mipi_dsi.h> #include <mmc.h> #include <panel.h> @@ -21,8 +19,6 @@ #include <stdlib.h> #include <video_bridge.h> -#define BOOT_BROM_DOWNLOAD 0xef08a53c - #define GPIO0_BASE 0xfdd60000 #define GPIO4_BASE 0xfe770000 #define GPIO_SWPORT_DR_L 0x0000 @@ -36,14 +32,6 @@ #define GPIO_WRITEMASK(bits) ((bits) << 16) -#define SARADC_BASE 0xfe720000 -#define SARADC_DATA 0x0000 -#define SARADC_STAS 0x0004 -#define SARADC_ADC_STATUS BIT(0) -#define SARADC_CTRL 0x0008 -#define SARADC_INPUT_SRC_MSK 0x7 -#define SARADC_POWER_CTRL BIT(3) - #define DTB_DIR "rockchip/" struct rg3xx_model { @@ -170,63 +158,11 @@ static const struct rg353_panel rg353_panel_details[] = { }; /* - * The device has internal eMMC, and while some devices have an exposed - * clk pin you can ground to force a bypass not all devices do. As a - * result it may be possible for some devices to become a perma-brick - * if a corrupted TPL or SPL stage with a valid header is flashed to - * the internal eMMC. Add functionality to read ADC channel 0 (the func - * button) as early as possible in the boot process to provide some - * protection against this. If we ever get an open TPL stage, we should - * consider moving this function there. - */ -void read_func_button(void) -{ - int ret; - u32 reg; - - /* Turn off SARADC to reset it. */ - writel(0, (SARADC_BASE + SARADC_CTRL)); - - /* Enable channel 0 and power on SARADC. */ - writel(((0 & SARADC_INPUT_SRC_MSK) | SARADC_POWER_CTRL), - (SARADC_BASE + SARADC_CTRL)); - - /* - * Wait for data to be ready. Use timeout of 20000us from - * rockchip_saradc driver. - */ - ret = readl_poll_timeout((SARADC_BASE + SARADC_STAS), reg, - !(reg & SARADC_ADC_STATUS), 20000); - if (ret) { - printf("ADC Timeout"); - return; - } - - /* Read the data from the SARADC. */ - reg = readl((SARADC_BASE + SARADC_DATA)); - - /* Turn the SARADC back off so it's ready to be used again. */ - writel(0, (SARADC_BASE + SARADC_CTRL)); - - /* - * If the value is less than 30 the button is being pressed. - * Reset the device back into Rockchip download mode. - */ - if (reg <= 30) { - printf("download key pressed, entering download mode..."); - writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); - do_reset(NULL, 0, 0, NULL); - } -}; - -/* * Start LED very early so user knows device is on. Set color * to red. */ void spl_board_init(void) { - read_func_button(); - /* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */ writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \ (GPIO_C7 | GPIO_C6 | GPIO_C5), diff --git a/board/armltd/vexpress/MAINTAINERS b/board/armltd/vexpress/MAINTAINERS index 2b3e4916a5d..7a54c6b560b 100644 --- a/board/armltd/vexpress/MAINTAINERS +++ b/board/armltd/vexpress/MAINTAINERS @@ -1,5 +1,5 @@ VERSATILE EXPRESS BOARDS -M: Kristian Amlie <kristian.amlie@northern.tech> +M: Josef Holzmayr <josef.holzmayr@northern.tech> S: Maintained F: board/armltd/vexpress/ F: include/configs/vexpress_ca9x4.h diff --git a/board/armsom/sige7-rk3588/Kconfig b/board/armsom/sige7-rk3588/Kconfig new file mode 100644 index 00000000000..793985f531b --- /dev/null +++ b/board/armsom/sige7-rk3588/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SIGE7_RK3588 + +config SYS_BOARD + default "sige7-rk3588" + +config SYS_VENDOR + default "armsom" + +config SYS_CONFIG_NAME + default "sige7-rk3588" + +endif diff --git a/board/armsom/sige7-rk3588/MAINTAINERS b/board/armsom/sige7-rk3588/MAINTAINERS new file mode 100644 index 00000000000..0fba39b76c2 --- /dev/null +++ b/board/armsom/sige7-rk3588/MAINTAINERS @@ -0,0 +1,7 @@ +SIGE7-RK3588 +M: Jianfeng Liu <liujianfeng1994@gmail.com> +S: Maintained +F: board/armsom/sige7-rk3588 +F: include/configs/sige7-rk3588.h +F: configs/sige7-rk3588_defconfig +F: arch/arm/dts/rk3588-armsom-sige7* diff --git a/board/asus/transformer-t20/Kconfig b/board/asus/transformer-t20/Kconfig new file mode 100644 index 00000000000..d5fe4128289 --- /dev/null +++ b/board/asus/transformer-t20/Kconfig @@ -0,0 +1,12 @@ +if TARGET_TRANSFORMER_T20 + +config SYS_BOARD + default "transformer-t20" + +config SYS_VENDOR + default "asus" + +config SYS_CONFIG_NAME + default "transformer-t20" + +endif diff --git a/board/asus/transformer-t20/MAINTAINERS b/board/asus/transformer-t20/MAINTAINERS new file mode 100644 index 00000000000..7bf93570985 --- /dev/null +++ b/board/asus/transformer-t20/MAINTAINERS @@ -0,0 +1,8 @@ +TRANSFORMER T20 BOARD +M: Svyatoslav Ryhel <clamor95@gmail.com> +S: Maintained +F: arch/arm/dts/tegra20-asus-* +F: board/asus/transformer-t20/ +F: configs/transformer_t20_defconfig +F: doc/board/asus/transformer_t20.rst +F: include/configs/transformer-t20.h diff --git a/board/asus/transformer-t20/Makefile b/board/asus/transformer-t20/Makefile new file mode 100644 index 00000000000..8522f82c2bd --- /dev/null +++ b/board/asus/transformer-t20/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation <www.nvidia.com> +# +# (C) Copyright 2021 +# Svyatoslav Ryhel <clamor95@gmail.com> + +obj-y += transformer-t20.o diff --git a/board/asus/transformer-t20/configs/sl101.config b/board/asus/transformer-t20/configs/sl101.config new file mode 100644 index 00000000000..4f639e1b412 --- /dev/null +++ b/board/asus/transformer-t20/configs/sl101.config @@ -0,0 +1 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-sl101" diff --git a/board/asus/transformer-t20/configs/tf101.config b/board/asus/transformer-t20/configs/tf101.config new file mode 100644 index 00000000000..44a1d1a3c10 --- /dev/null +++ b/board/asus/transformer-t20/configs/tf101.config @@ -0,0 +1 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-tf101" diff --git a/board/asus/transformer-t20/configs/tf101g.config b/board/asus/transformer-t20/configs/tf101g.config new file mode 100644 index 00000000000..0ccf2498ccd --- /dev/null +++ b/board/asus/transformer-t20/configs/tf101g.config @@ -0,0 +1 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-tf101g" diff --git a/board/asus/transformer-t20/transformer-t20.c b/board/asus/transformer-t20/transformer-t20.c new file mode 100644 index 00000000000..42fc563a0bf --- /dev/null +++ b/board/asus/transformer-t20/transformer-t20.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2021 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +/* T20 Transformers derive from Ventana board */ + +#include <dm.h> +#include <i2c.h> +#include <log.h> +#include <linux/delay.h> + +#define TPS6586X_I2C_ADDRESS 0x34 +#define TPS6586X_SUPPLYENE 0x14 +#define EXITSLREQ_BIT BIT(1) +#define SLEEP_MODE_BIT BIT(3) + +#ifdef CONFIG_CMD_POWEROFF +int do_poweroff(struct cmd_tbl *cmdtp, + int flag, int argc, char *const argv[]) +{ + struct udevice *dev; + uchar data_buffer[1]; + int ret; + + ret = i2c_get_chip_for_busnum(0, TPS6586X_I2C_ADDRESS, 1, &dev); + if (ret) { + log_debug("cannot find PMIC I2C chip\n"); + return 0; + } + + ret = dm_i2c_read(dev, TPS6586X_SUPPLYENE, data_buffer, 1); + if (ret) + return ret; + + data_buffer[0] &= ~EXITSLREQ_BIT; + + ret = dm_i2c_write(dev, TPS6586X_SUPPLYENE, data_buffer, 1); + if (ret) + return ret; + + data_buffer[0] |= SLEEP_MODE_BIT; + + ret = dm_i2c_write(dev, TPS6586X_SUPPLYENE, data_buffer, 1); + if (ret) + return ret; + + // wait some time and then print error + mdelay(5000); + printf("Failed to power off!!!\n"); + return 1; +} +#endif diff --git a/board/beacon/beacon-rzg2m/MAINTAINERS b/board/beacon/beacon-rzg2m/MAINTAINERS index f8042bb2c44..a4a920a017b 100644 --- a/board/beacon/beacon-rzg2m/MAINTAINERS +++ b/board/beacon/beacon-rzg2m/MAINTAINERS @@ -1,5 +1,6 @@ BEACON_RZG2M BOARD M: Adam Ford <aford173@gmail.com> +M: Marek Vasut <marek.vasut+renesas@mailbox.org> S: Maintained F: board/beacon/beacon-rzg2m/ F: include/configs/beacon-rzg2m.h diff --git a/board/beagle/beagleboneai64/Kconfig b/board/beagle/beagleboneai64/Kconfig index 7cfccf9baf0..0f21582614d 100644 --- a/board/beagle/beagleboneai64/Kconfig +++ b/board/beagle/beagleboneai64/Kconfig @@ -37,7 +37,7 @@ config SYS_VENDOR default "beagle" config SYS_CONFIG_NAME - default "j721e_evm" + default "beagleboneai64" source "board/ti/common/Kconfig" @@ -52,7 +52,7 @@ config SYS_VENDOR default "beagle" config SYS_CONFIG_NAME - default "j721e_evm" + default "beagleboneai64" source "board/ti/common/Kconfig" diff --git a/board/beagle/beagleboneai64/beagleboneai64.c b/board/beagle/beagleboneai64/beagleboneai64.c index c5b4ff7df47..1e43d1c1bd2 100644 --- a/board/beagle/beagleboneai64/beagleboneai64.c +++ b/board/beagle/beagleboneai64/beagleboneai64.c @@ -7,6 +7,7 @@ * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation */ +#include <efi_loader.h> #include <cpu_func.h> #include <env.h> #include <fdt_support.h> @@ -14,6 +15,44 @@ DECLARE_GLOBAL_DATA_PTR; +struct efi_fw_image fw_images[] = { + { + .image_type_id = BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID, + .fw_name = u"BEAGLEBONEAI64_TIBOOT3", + .image_index = 1, + }, + { + .image_type_id = BEAGLEBONEAI64_SPL_IMAGE_GUID, + .fw_name = u"BEAGLEBONEAI64_SPL", + .image_index = 2, + }, + { + .image_type_id = BEAGLEBONEAI64_UBOOT_IMAGE_GUID, + .fw_name = u"BEAGLEBONEAI64_UBOOT", + .image_index = 3, + }, + { + .image_type_id = BEAGLEBONEAI64_SYSFW_IMAGE_GUID, + .fw_name = u"BEAGLEBONEAI64_SYSFW", + .image_index = 4, + } +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=tiboot3.bin raw 0 2000 mmcpart 1;" + "tispl.bin fat 0 1;u-boot.img fat 0 1; sysfw.itb fat 0 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; + +#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO) +void set_dfu_alt_info(char *interface, char *devstr) +{ + if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)) + env_set("dfu_alt_info", update_info.dfu_string); +} +#endif + int board_init(void) { return 0; diff --git a/board/beagle/beagleplay/Kconfig b/board/beagle/beagleplay/Kconfig index 7dbd833acb4..592b53e493c 100644 --- a/board/beagle/beagleplay/Kconfig +++ b/board/beagle/beagleplay/Kconfig @@ -12,6 +12,7 @@ config TARGET_AM625_A53_BEAGLEPLAY bool "BeagleBoard.org AM625 BeaglePlay running on A53" select ARM64 select BINMAN + select OF_SYSTEM_SETUP config TARGET_AM625_R5_BEAGLEPLAY bool "BeagleBoard.org AM625 BeaglePlay running on R5" @@ -35,7 +36,7 @@ config SYS_VENDOR default "beagle" config SYS_CONFIG_NAME - default "am62x_evm" + default "beagleplay" source "board/ti/common/Kconfig" @@ -50,7 +51,7 @@ config SYS_VENDOR default "beagle" config SYS_CONFIG_NAME - default "am62x_evm" + default "beagleplay" config SPL_LDSCRIPT default "arch/arm/mach-omap2/u-boot-spl.lds" diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c index af36439e2e2..a21f09e3122 100644 --- a/board/beagle/beagleplay/beagleplay.c +++ b/board/beagle/beagleplay/beagleplay.c @@ -6,6 +6,7 @@ * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation */ +#include <efi_loader.h> #include <cpu_func.h> #include <env.h> #include <fdt_support.h> @@ -15,6 +16,39 @@ DECLARE_GLOBAL_DATA_PTR; +struct efi_fw_image fw_images[] = { + { + .image_type_id = BEAGLEPLAY_TIBOOT3_IMAGE_GUID, + .fw_name = u"BEAGLEPLAY_TIBOOT3", + .image_index = 1, + }, + { + .image_type_id = BEAGLEPLAY_SPL_IMAGE_GUID, + .fw_name = u"BEAGLEPLAY_SPL", + .image_index = 2, + }, + { + .image_type_id = BEAGLEPLAY_UBOOT_IMAGE_GUID, + .fw_name = u"BEAGLEPLAY_UBOOT", + .image_index = 3, + } +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=tiboot3.bin raw 0 2000 mmcpart 1;" + "tispl.bin fat 0 1;u-boot.img fat 0 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; + +#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO) +void set_dfu_alt_info(char *interface, char *devstr) +{ + if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)) + env_set("dfu_alt_info", update_info.dfu_string); +} +#endif + int board_init(void) { return 0; diff --git a/board/beagle/beagleplay/beagleplay.env b/board/beagle/beagleplay/beagleplay.env index 8dbfc2f7d24..354bc987d12 100644 --- a/board/beagle/beagleplay/beagleplay.env +++ b/board/beagle/beagleplay/beagleplay.env @@ -12,7 +12,7 @@ set_led_state_start_load=led led-0 on; led led-1 off; led led-2 on; led led-3 off; led led-4 on boot=mmc mmcdev=1 -bootpart=1:1 +bootpart=1:2 bootdir=/boot boot_targets=mmc1 mmc0 bootmeths=script extlinux efi pxe diff --git a/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c b/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c index 0da641834d4..33452d2ad5b 100644 --- a/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c +++ b/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c @@ -18,15 +18,15 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x20 }, { 0x3d400000, 0xa1040001 }, - { 0x3d400064, 0x610040 }, + { 0x3d400064, 0x300040 }, { 0x3d4000d0, 0xc00200c5 }, { 0x3d4000d4, 0x1000b }, { 0x3d4000dc, 0x1d700004 }, - { 0x3d4000e0, 0x180000 }, + { 0x3d4000e0, 0x580000 }, { 0x3d4000e4, 0x90000 }, - { 0x3d4000f0, 0x0 }, + { 0x3d4000f0, 0x2 }, { 0x3d4000f4, 0xee5 }, - { 0x3d400100, 0xc101b0e }, + { 0x3d400100, 0xc100d0e }, { 0x3d400104, 0x30314 }, { 0x3d400108, 0x4060509 }, { 0x3d40010c, 0x2006 }, @@ -67,10 +67,10 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400498, 0x7ff }, { 0x3d40049c, 0xe00 }, { 0x3d4004a0, 0x7ff }, - { 0x3d402064, 0x28001b }, + { 0x3d402064, 0x14001b }, { 0x3d4020dc, 0x12200004 }, - { 0x3d4020e0, 0x0 }, - { 0x3d402100, 0x7090b07 }, + { 0x3d4020e0, 0x400000 }, + { 0x3d402100, 0x7090507 }, { 0x3d402104, 0x20209 }, { 0x3d402108, 0x3030407 }, { 0x3d40210c, 0x2006 }, @@ -680,12 +680,13 @@ struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x54006, 0x140 }, { 0x54007, 0x1000 }, { 0x54008, 0x101 }, + { 0x54009, 0x200 }, { 0x5400b, 0x31f }, { 0x5400c, 0xc8 }, { 0x54012, 0x1 }, { 0x5402f, 0x1d70 }, { 0x54030, 0x4 }, - { 0x54031, 0x18 }, + { 0x54031, 0x58 }, { 0x5403a, 0x1323 }, { 0xd0000, 0x1 }, }; @@ -700,11 +701,13 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x54006, 0x140 }, { 0x54007, 0x1000 }, { 0x54008, 0x101 }, + { 0x54009, 0x200 }, { 0x5400b, 0x21f }, { 0x5400c, 0xc8 }, { 0x54012, 0x1 }, { 0x5402f, 0x1220 }, { 0x54030, 0x4 }, + { 0x54031, 0x40 }, { 0x5403a, 0x1323 }, { 0xd0000, 0x1 }, }; @@ -886,11 +889,11 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, { 0x90026, 0x2b }, - { 0x2000b, 0x32 }, + { 0x2000b, 0x1c2 }, { 0x2000c, 0x64 }, { 0x2000d, 0x3e8 }, { 0x2000e, 0x2c }, - { 0x12000b, 0x14 }, + { 0x12000b, 0xbb }, { 0x12000c, 0x26 }, { 0x12000d, 0x1a1 }, { 0x12000e, 0x10 }, diff --git a/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c b/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c index f845395ad97..ca14a474429 100644 --- a/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c +++ b/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c @@ -18,15 +18,15 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x20 }, { 0x3d400000, 0xa1040001 }, - { 0x3d400064, 0x610068 }, + { 0x3d400064, 0x300068 }, { 0x3d4000d0, 0xc00200c5 }, { 0x3d4000d4, 0x1000b }, { 0x3d4000dc, 0x1d700004 }, - { 0x3d4000e0, 0x180000 }, + { 0x3d4000e0, 0x580000 }, { 0x3d4000e4, 0x90000 }, - { 0x3d4000f0, 0x0 }, + { 0x3d4000f0, 0x2 }, { 0x3d4000f4, 0xee5 }, - { 0x3d400100, 0xc101b0e }, + { 0x3d400100, 0xc100d0e }, { 0x3d400104, 0x30314 }, { 0x3d400108, 0x4060509 }, { 0x3d40010c, 0x2006 }, @@ -700,11 +700,13 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x54006, 0x140 }, { 0x54007, 0x1000 }, { 0x54008, 0x101 }, + { 0x54009, 0x200 }, { 0x5400b, 0x21f }, { 0x5400c, 0xc8 }, { 0x54012, 0x1 }, { 0x5402f, 0x1220 }, { 0x54030, 0x4 }, + { 0x54031, 0x40 }, { 0x5403a, 0x1323 }, { 0xd0000, 0x1 }, }; @@ -886,11 +888,11 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, { 0x90026, 0x2b }, - { 0x2000b, 0x32 }, + { 0x2000b, 0x1c2 }, { 0x2000c, 0x64 }, { 0x2000d, 0x3e8 }, { 0x2000e, 0x2c }, - { 0x12000b, 0x14 }, + { 0x12000b, 0xbb }, { 0x12000c, 0x26 }, { 0x12000d, 0x1a1 }, { 0x12000e, 0x10 }, diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c index 5110fed3119..6b92fe31c0e 100644 --- a/board/cadence/xtfpga/xtfpga.c +++ b/board/cadence/xtfpga/xtfpga.c @@ -66,6 +66,11 @@ unsigned long get_board_sys_clk(void) #endif } +int dram_init(void) +{ + return 0; +} + int board_postclk_init(void) { gd->cpu_clk = get_board_sys_clk(); diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c index 99d3bf3af3b..6a3d816a48a 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c @@ -46,7 +46,9 @@ struct lpddr4_desc { static const struct lpddr4_desc lpddr4_array[] = { { .name = "Nanya", .id = 0x05000010, .subind = 0xff, .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010}, - { .name = "Samsung", .id = 0x01061010, .subind = 0xff, + { .name = "Samsung", .id = 0x01061010, .subind = 0x04, + .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110}, + { .name = "Samsung", .id = 0x01061010, .subind = 0x02, .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010}, { .name = "Kingston", .id = 0xff000010, .subind = 0x04, .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110}, diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c index ba158734142..bda7aac5be4 100644 --- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c +++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c @@ -8,6 +8,7 @@ #include <efi_loader.h> #include <env.h> #include <extension_board.h> +#include <fdt_support.h> #include <hang.h> #include <i2c.h> #include <init.h> @@ -30,6 +31,8 @@ DECLARE_GLOBAL_DATA_PTR; +static int fec_phyaddr = -1; + #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) struct efi_fw_image fw_images[] = { #if defined(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) @@ -109,10 +112,72 @@ static int setup_fec(void) return 0; } +#define FDT_PHYADDR "/soc@0/bus@30800000/ethernet@30be0000/mdio/ethernet-phy@0" +#define FLIP_32B(val) (((val >> 24) & 0xff) | ((val << 8) & 0xff0000) | ((val >> 8) & 0xff00) | ((val << 24) & 0xff000000)) +static int fdt_set_fec_phy_addr(void *blob) +{ + u32 val; + + if (fec_phyaddr < 0) + return -EINVAL; + + val = FLIP_32B(fec_phyaddr); + return fdt_find_and_setprop(blob, FDT_PHYADDR, "reg", (const void *)&val, + sizeof(val), 0); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + fdt_set_fec_phy_addr(blob); + return 0; +} + +/* + * These are specific ID, purposed to distiguish between PHY vendors. + * These values are not equal to real vendors' OUI (half of MAC address) + */ +#define OUI_PHY_ATHEROS 0x1374 +#define OUI_PHY_REALTEK 0x0732 + int board_phy_config(struct phy_device *phydev) { - if (IS_ENABLED(CONFIG_FEC_MXC)) { + unsigned int model, rev, oui; + int phyid1, phyid2; + unsigned int reg; + + if (!IS_ENABLED(CONFIG_FEC_MXC)) + return 0; + + phyid1 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID1); + if (phyid1 < 0) { + printf("%s: PHYID1 registry read fail %i\n", __func__, phyid1); + return phyid1; + } + + phyid2 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID2); + if (phyid2 < 0) { + printf("%s: PHYID2 registry read fail %i\n", __func__, phyid2); + return phyid2; + } + + reg = phyid2 | phyid1 << 16; + if (reg == 0xffff) { + printf("%s: There is no device @%i\n", __func__, phydev->addr); + return -ENODEV; + } + + rev = reg & 0xf; + reg >>= 4; + model = reg & 0x3f; + reg >>= 6; + oui = reg; + debug("%s: PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n", + __func__, phydev->addr, oui, model, rev); + + switch (oui) { + case OUI_PHY_ATHEROS: /* enable rgmii rxc skew and phy mode select to RGMII copper */ + printf("phy: AR803x@%x\t", phydev->addr); phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); @@ -120,10 +185,45 @@ int board_phy_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + break; + case OUI_PHY_REALTEK: + printf("phy: RTL8211E@%x\t", phydev->addr); + /* RTL8211E-VB-CG - add TX and RX delay */ + unsigned short val; + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x07); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0xa4); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1c); + val |= (0x1 << 13) | (0x1 << 12) | (0x1 << 11); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, val); + /* LEDs: set to extension page */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0007); + /* extension Page44 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x002c); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, 0x0430);//LCR + phy_write(phydev, MDIO_DEVAD_NONE, 0x1a, 0x0010);//LACR + /* + * To disable EEE LED mode (blinking .4s/2s) + * Extension Page5 + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0005); + phy_write(phydev, MDIO_DEVAD_NONE, 0x05, 0x8b82);//magic const + phy_write(phydev, MDIO_DEVAD_NONE, 0x06, 0x052b);//magic const + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x00);// Back to Page0 - if (phydev->drv->config) - phydev->drv->config(phydev); + break; + default: + printf("%s: ERROR: unknown PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n", + __func__, phydev->addr, oui, model, rev); + return -ENOSYS; } + + fec_phyaddr = phydev->addr; + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; } diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds index 7e0f09f3b5b..56d6f4f114b 100644 --- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds +++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds @@ -46,12 +46,7 @@ SECTIONS } >.sram __image_copy_end = .; - - .end : - { - *(.__end) - } - + _end = .; _image_binary_end = .; .bss : diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 20c9d70737e..4f4f537fee5 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -37,6 +37,7 @@ #include <power/regulator.h> #include <remoteproc.h> #include <reset.h> +#include <spl.h> #include <syscon.h> #include <usb.h> #include <usb/dwc2_udc.h> @@ -75,14 +76,25 @@ static bool dh_stm32_mac_is_in_ks8851(void) { - ofnode node; + struct udevice *udev; u32 reg, cider, ccr; + char path[256]; + ofnode node; + int ret; node = ofnode_path("ethernet1"); if (!ofnode_valid(node)) return false; - if (ofnode_device_is_compatible(node, "micrel,ks8851-mll")) + ret = ofnode_get_path(node, path, sizeof(path)); + if (ret) + return false; + + ret = uclass_get_device_by_of_path(UCLASS_ETH, path, &udev); + if (ret) + return false; + + if (!ofnode_device_is_compatible(node, "micrel,ks8851-mll")) return false; /* @@ -672,12 +684,69 @@ void board_quiesce_devices(void) #endif } +static void dh_stm32_ks8851_fixup(void *blob) +{ + struct gpio_desc ks8851intrn; + bool compatible = false; + int ks8851intrn_value; + const char *prop; + ofnode node; + int idx = 0; + int offset; + int ret; + + /* Do nothing if not STM32MP15xx DHCOM SoM */ + while ((prop = fdt_stringlist_get(blob, 0, "compatible", idx++, NULL))) { + if (!strstr(prop, "dhcom-som")) + continue; + compatible = true; + break; + } + + if (!compatible) + return; + + /* + * Read state of INTRN pull up resistor, if this pull up is populated, + * KS8851-16MLL is populated as well and should be enabled, otherwise + * it should be disabled. + */ + node = ofnode_path("/config"); + if (!ofnode_valid(node)) + return; + + ret = gpio_request_by_name_nodev(node, "dh,mac-coding-gpios", 0, + &ks8851intrn, GPIOD_IS_IN); + if (ret) + return; + + ks8851intrn_value = dm_gpio_get_value(&ks8851intrn); + + dm_gpio_free(NULL, &ks8851intrn); + + /* Set the 'status' property into KS8851-16MLL DT node. */ + offset = fdt_path_offset(blob, "ethernet1"); + ret = fdt_node_check_compatible(blob, offset, "micrel,ks8851-mll"); + if (ret) /* Not compatible */ + return; + + /* Add a bit of extra space for new 'status' property */ + ret = fdt_shrink_to_minimum(blob, 4096); + if (!ret) + return; + + fdt_setprop_string(blob, offset, "status", + ks8851intrn_value ? "okay" : "disabled"); +} + #if defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { const char *buck3path = "/soc/i2c@5c002000/stpmic@33/regulators/buck3"; int buck3off, ret, uv; + dh_stm32_ks8851_fixup(blob); + ret = board_get_regulator_buck3_nvm_uv_av96(&uv); if (ret) /* Not Avenger96 board, do not patch Buck3 in DT. */ return 0; @@ -698,6 +767,13 @@ int ft_board_setup(void *blob, struct bd_info *bd) } #endif +#if defined(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + dh_stm32_ks8851_fixup(spl_image_fdt_addr(spl_image)); +} +#endif + static void board_copro_image_process(ulong fw_image, size_t fw_size) { int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */ diff --git a/board/emulation/qemu-xtensa/Kconfig b/board/emulation/qemu-xtensa/Kconfig new file mode 100644 index 00000000000..8767b6fabbd --- /dev/null +++ b/board/emulation/qemu-xtensa/Kconfig @@ -0,0 +1,43 @@ +if TARGET_QEMU_XTENSA + +config SYS_BOARD + default "qemu-xtensa" + +config SYS_VENDOR + default "emulation" + +config SYS_CONFIG_NAME + default "qemu-xtensa" + +config TEXT_BASE + default 0x50000000 if (SYS_CPU = de212) + default 0xfe000000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_EARLY_INIT_F + select DM + select CPU + select CPU_XTENSA + select CLK + select DM_SERIAL + select XTENSA_SEMIHOSTING + select XTENSA_SEMIHOSTING_SERIAL + imply BLK + imply VIRTIO + imply VIRTIO_PCI + imply VIRTIO_NET + imply VIRTIO_BLK + imply E1000 + imply PCI + imply PCI_INIT_R + imply NVME_PCI + imply PCIE_ECAM_GENERIC + imply SCSI + imply REMAKE_ELF + select OF_CONTROL + select OF_UPSTREAM + imply CMD_DM + imply CMD_PCI + +endif diff --git a/board/emulation/qemu-xtensa/MAINTAINERS b/board/emulation/qemu-xtensa/MAINTAINERS new file mode 100644 index 00000000000..6ffdfe85dee --- /dev/null +++ b/board/emulation/qemu-xtensa/MAINTAINERS @@ -0,0 +1,8 @@ +QEMU XTENSA 'VIRT' BOARD +M: Jiaxun Yang <jiaxun.yang@flygoat.com> +M: Max Filippov <jcmvbkbc@gmail.com> +S: Maintained +F: board/emulation/qemu-xtensa/ +F: board/emulation/common/ +F: include/configs/qemu-xtensa.h +F: configs/qemu-xtensa-dc233c_defconfig diff --git a/board/emulation/qemu-xtensa/Makefile b/board/emulation/qemu-xtensa/Makefile new file mode 100644 index 00000000000..0f33a65f6c6 --- /dev/null +++ b/board/emulation/qemu-xtensa/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024, Jiaxun Yang <jiaxun.yang@flygoat.com> + +obj-y += qemu-xtensa.o diff --git a/board/emulation/qemu-xtensa/qemu-xtensa.c b/board/emulation/qemu-xtensa/qemu-xtensa.c new file mode 100644 index 00000000000..0ca83341c25 --- /dev/null +++ b/board/emulation/qemu-xtensa/qemu-xtensa.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <dm.h> +#include <cpu.h> +#include <log.h> +#include <init.h> +#include <usb.h> +#include <virtio_types.h> +#include <virtio.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + return gd->cpu_clk ? gd->cpu_clk : 40000000; +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int board_early_init_f(void) +{ + struct cpu_plat *cpu_plat; + struct udevice *cpu = cpu_get_current_dev(); + + if (!cpu) + return -ENODEV; + + cpu_plat = dev_get_parent_plat(cpu); + if (!cpu_plat) + return -ENODEV; + + gd->cpu_clk = cpu_plat->timebase_freq; + return 0; +} + +int board_late_init(void) +{ + /* start usb so that usb keyboard can be used as input device */ + if (CONFIG_IS_ENABLED(USB_KEYBOARD)) + usb_init(); + + /* + * Make sure virtio bus is enumerated so that peripherals + * on the virtio bus can be discovered by their drivers + */ + virtio_init(); + + return 0; +} diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c index d4192e5ab52..3344653ba2d 100644 --- a/board/freescale/common/cmd_esbc_validate.c +++ b/board/freescale/common/cmd_esbc_validate.c @@ -63,14 +63,14 @@ static int do_esbc_validate(struct cmd_tbl *cmdtp, int flag, int argc, } /***************************************************/ -static char esbc_validate_help_text[] = +U_BOOT_LONGHELP(esbc_validate, "esbc_validate hdr_addr <hash_val> - Validates signature using\n" " RSA verification\n" " $hdr_addr Address of header of the image\n" " to be validated.\n" " $hash_val -Optional\n" " It provides Hash of public/srk key to be\n" - " used to verify signature.\n"; + " used to verify signature.\n"); U_BOOT_CMD( esbc_validate, 3, 0, do_esbc_validate, diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index f10d310a46d..e9cdede6214 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -118,13 +118,29 @@ static int dm_i2c_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set) return dm_i2c_write(dev, reg, &val, 1); } -static int power_init_board(void) +static int power_init_board(struct udevice *gsc) { const char *model = eeprom_get_model(); struct udevice *bus; struct udevice *dev; int ret; + /* Enable GSC voltage supervisor for new board models */ + if ((!strncmp(model, "GW7100", 6) && model[10] > 'D') || + (!strncmp(model, "GW7101", 6) && model[10] > 'D') || + (!strncmp(model, "GW7200", 6) && model[10] > 'E') || + (!strncmp(model, "GW7201", 6) && model[10] > 'E') || + (!strncmp(model, "GW7300", 6) && model[10] > 'E') || + (!strncmp(model, "GW7301", 6) && model[10] > 'E') || + (!strncmp(model, "GW740", 5) && model[7] > 'B')) { + u8 ver; + + if (!dm_i2c_read(gsc, 14, &ver, 1) && ver > 62) { + printf("GSC : enabling voltage supervisor\n"); + dm_i2c_clrsetbits(gsc, 25, 0, BIT(1)); + } + } + if ((!strncmp(model, "GW71", 4)) || (!strncmp(model, "GW72", 4)) || (!strncmp(model, "GW73", 4)) || @@ -286,6 +302,7 @@ void board_init_f(ulong dummy) mdelay(10); } pinctrl_select_state(bus, "default"); + mdelay(10); } } /* Wait indefiniately until the GSC probes */ @@ -297,7 +314,7 @@ void board_init_f(ulong dummy) dram_sz = venice_eeprom_init(0); /* PMIC */ - power_init_board(); + power_init_board(dev); /* DDR initialization */ spl_dram_init(dram_sz); diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index 5b105d7659e..d4c22121497 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -45,22 +45,6 @@ int board_fit_config_name_match(const char *path) return -1; } -static int __maybe_unused setup_fec(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - -#ifndef CONFIG_IMX8MP - /* Use 125M anatop REF_CLK1 for ENET1, not from external */ - clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); -#else - /* Enable RGMII TX clk output */ - setbits_le32(&gpr->gpr[1], BIT(22)); -#endif - - return 0; -} - #if (IS_ENABLED(CONFIG_NET)) int board_phy_config(struct phy_device *phydev) { @@ -75,6 +59,9 @@ int board_phy_config(struct phy_device *phydev) val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */ phy_write(phydev, MDIO_DEVAD_NONE, 24, val); break; + case 0xd565a401: /* MaxLinear GPY111 */ + puts("GPY111 "); + break; } if (phydev->drv->config) @@ -88,9 +75,6 @@ int board_init(void) { venice_eeprom_init(1); - if (IS_ENABLED(CONFIG_FEC_MXC)) - setup_fec(); - return 0; } diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c index 53c3435c92f..bd8ce633772 100644 --- a/board/google/veyron/veyron.c +++ b/board/google/veyron/veyron.c @@ -28,44 +28,38 @@ static int veyron_init(void) int ret; ret = regulator_get_by_platname("vdd_arm", &dev); - if (ret) { - debug("Cannot set regulator name\n"); - return ret; - } + if (ret) + return log_msg_ret("vdd", ret); /* Slowly raise to max CPU voltage to prevent overshoot */ ret = regulator_set_value(dev, 1200000); if (ret) - return ret; + return log_msg_ret("s12", ret); udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ ret = regulator_set_value(dev, 1400000); if (ret) - return ret; + return log_msg_ret("s14", ret); udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ ret = rockchip_get_clk(&clk.dev); if (ret) - return ret; + return log_msg_ret("clk", ret); clk.id = PLL_APLL; ret = clk_set_rate(&clk, 1800000000); if (IS_ERR_VALUE(ret)) - return ret; + return log_msg_ret("s18", ret); ret = regulator_get_by_platname("vcc33_sd", &dev); - if (ret) { - debug("Cannot get regulator name\n"); - return ret; - } + if (ret) + return log_msg_ret("vcc", ret); ret = regulator_set_value(dev, 3300000); if (ret) - return ret; + return log_msg_ret("s33", ret); ret = regulators_enable_boot_on(false); - if (ret) { - debug("%s: Cannot enable boot on regulators\n", __func__); - return ret; - } + if (ret) + return log_msg_ret("boo", ret); return 0; } @@ -80,7 +74,7 @@ int board_early_init_r(void) if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { ret = veyron_init(); if (ret) - return ret; + return log_msg_ret("vey", ret); } #endif /* diff --git a/board/hardkernel/odroid_go2/MAINTAINERS b/board/hardkernel/odroid_go2/MAINTAINERS index 4d4c6e8fef6..9e83bc9452c 100644 --- a/board/hardkernel/odroid_go2/MAINTAINERS +++ b/board/hardkernel/odroid_go2/MAINTAINERS @@ -1,5 +1,5 @@ GO2 -M: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> +M: Heiko Stuebner <heiko.stuebner@cherry.de> S: Maintained F: board/hardkernel/odroid_go2/ F: include/configs/odroid_go2.h diff --git a/board/indiedroid/nova/Kconfig b/board/indiedroid/nova/Kconfig new file mode 100644 index 00000000000..271d15a0ede --- /dev/null +++ b/board/indiedroid/nova/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NOVA_RK3588 + +config SYS_BOARD + default "nova-rk3588s" + +config SYS_VENDOR + default "indiedroid" + +config SYS_CONFIG_NAME + default "nova-rk3588s" + +endif diff --git a/board/indiedroid/nova/MAINTAINERS b/board/indiedroid/nova/MAINTAINERS new file mode 100644 index 00000000000..db1f11551b9 --- /dev/null +++ b/board/indiedroid/nova/MAINTAINERS @@ -0,0 +1,6 @@ +INDIEDROID-NOVA-RK3588 +M: Chris Morgan <macromorgan@hotmail.com> +S: Maintained +F: board/indiedroid/nova +F: configs/nova-rk3588s_defconfig +F: include/configs/nova-rk3588s.h diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 8a3f290f678..a35a7cd3b1f 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -29,18 +29,6 @@ #include <fdt_support.h> #include "igep00x0.h" -static const struct ns16550_plat igep_serial = { - .base = OMAP34XX_UART3, - .reg_shift = 2, - .clock = V_NS16550_CLK, - .fcr = UART_FCR_DEFVAL, -}; - -U_BOOT_DRVINFO(igep_uart) = { - "ns16550_serial", - &igep_serial -}; - /* * Routine: get_board_revision * Description: GPIO_28 and GPIO_129 are used to read board and revision from diff --git a/board/kontron/sl28/cmds.c b/board/kontron/sl28/cmds.c index 7851361c48c..07514778753 100644 --- a/board/kontron/sl28/cmds.c +++ b/board/kontron/sl28/cmds.c @@ -172,8 +172,8 @@ out: return CMD_RET_FAILURE; } -static char sl28_help_text[] = - "nvm [<hex>] - display/set the 16 non-volatile bits\n"; +U_BOOT_LONGHELP(sl28, + "nvm [<hex>] - display/set the 16 non-volatile bits\n"); U_BOOT_CMD_WITH_SUBCMDS(sl28, "SMARC-sAL28 specific", sl28_help_text, U_BOOT_SUBCMD_MKENT(nvm, 2, 1, do_sl28_nvm)); diff --git a/board/lenovo/ideapad-yoga-11/Kconfig b/board/lenovo/ideapad-yoga-11/Kconfig new file mode 100644 index 00000000000..67644409fc1 --- /dev/null +++ b/board/lenovo/ideapad-yoga-11/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IDEAPAD_YOGA_11 + +config SYS_BOARD + default "ideapad-yoga-11" + +config SYS_VENDOR + default "lenovo" + +config SYS_CONFIG_NAME + default "ideapad-yoga-11" + +endif diff --git a/board/lenovo/ideapad-yoga-11/MAINTAINERS b/board/lenovo/ideapad-yoga-11/MAINTAINERS new file mode 100644 index 00000000000..77e82534a95 --- /dev/null +++ b/board/lenovo/ideapad-yoga-11/MAINTAINERS @@ -0,0 +1,7 @@ +Lenovo Ideapad Yoga 11 +M: Jonas Schwöbel <jonasschwoebel@yahoo.de> +S: Maintained +F: board/lenovo/ideapad-yoga-11/ +F: configs/ideapad-yoga-11_defconfig +F: doc/board/lenovo/ideapad-yoga-11.rst +F: include/configs/ideapad-yoga-11.h diff --git a/board/lenovo/ideapad-yoga-11/Makefile b/board/lenovo/ideapad-yoga-11/Makefile new file mode 100644 index 00000000000..186f1cb4ee5 --- /dev/null +++ b/board/lenovo/ideapad-yoga-11/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 +# Open Surface RT + +obj-$(CONFIG_SPL_BUILD) += ideapad-yoga-11-spl.o diff --git a/board/lenovo/ideapad-yoga-11/ideapad-yoga-11-spl.c b/board/lenovo/ideapad-yoga-11/ideapad-yoga-11-spl.c new file mode 100644 index 00000000000..b8b3964a708 --- /dev/null +++ b/board/lenovo/ideapad-yoga-11/ideapad-yoga-11-spl.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Ideapad Yoga 11 SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2021 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +#define TPS65911_I2C_ADDR (0x2D << 1) +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +#define TPS62361B_I2C_ADDR (0x60 << 1) +#define TPS62361B_SET2_REG 0x02 +#define TPS62361B_SET2_DATA (0x4600 | TPS62361B_SET2_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET2_DATA); + + udelay(1000); + + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} diff --git a/board/microchip/mpfs_icicle/MAINTAINERS b/board/microchip/mpfs_icicle/MAINTAINERS index 22f3b97d8b1..d092b5a8111 100644 --- a/board/microchip/mpfs_icicle/MAINTAINERS +++ b/board/microchip/mpfs_icicle/MAINTAINERS @@ -1,5 +1,5 @@ Microchip MPFS icicle -M: Padmarao Begari <padmarao.begari@microchip.com> +M: Conor Dooley <conor.dooley@microchip.com> M: Cyril Jean <cyril.jean@microchip.com> S: Maintained F: board/microchip/mpfs_icicle/ diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c index 7beac33cfbd..4d7d843dfa3 100644 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c @@ -72,25 +72,13 @@ int board_early_init_f(void) int board_late_init(void) { u32 ret; - u32 node; + int node; u8 idx; u8 device_serial_number[16] = { 0 }; unsigned char mac_addr[6]; char icicle_mac_addr[20]; void *blob = (void *)gd->fdt_blob; - node = fdt_path_offset(blob, "/soc/ethernet@20112000"); - if (node < 0) { - printf("No ethernet0 path offset\n"); - return -ENODEV; - } - - ret = fdtdec_get_byte_array(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("No local-mac-address property for ethernet@20112000\n"); - return -EINVAL; - } - read_device_serial_number(device_serial_number, 16); /* Update MAC address with device serial number */ @@ -101,10 +89,13 @@ int board_late_init(void) mac_addr[4] = device_serial_number[1]; mac_addr[5] = device_serial_number[0]; - ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("Error setting local-mac-address property for ethernet@20112000\n"); - return -ENODEV; + node = fdt_path_offset(blob, "/soc/ethernet@20112000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20112000\n"); + return -ENODEV; + } } icicle_mac_addr[0] = '['; diff --git a/board/microsoft/surface-rt/Kconfig b/board/microsoft/surface-rt/Kconfig new file mode 100644 index 00000000000..9e66897f6b1 --- /dev/null +++ b/board/microsoft/surface-rt/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SURFACE_RT + +config SYS_BOARD + default "surface-rt" + +config SYS_VENDOR + default "microsoft" + +config SYS_CONFIG_NAME + default "surface-rt" + +endif diff --git a/board/microsoft/surface-rt/MAINTAINERS b/board/microsoft/surface-rt/MAINTAINERS new file mode 100644 index 00000000000..1bbd896de92 --- /dev/null +++ b/board/microsoft/surface-rt/MAINTAINERS @@ -0,0 +1,7 @@ +Microsoft Surface RT +M: Jonas Schwöbel <jonasschwoebel@yahoo.de> +S: Maintained +F: board/microsoft/surface-rt/ +F: configs/surface-rt_defconfig +F: doc/board/microsoft/surface-rt.rst +F: include/configs/surface-rt.h diff --git a/board/microsoft/surface-rt/Makefile b/board/microsoft/surface-rt/Makefile new file mode 100644 index 00000000000..da4094a7df3 --- /dev/null +++ b/board/microsoft/surface-rt/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2021 +# Open Surface RT + +obj-$(CONFIG_SPL_BUILD) += surface-rt-spl.o diff --git a/board/microsoft/surface-rt/surface-rt-spl.c b/board/microsoft/surface-rt/surface-rt-spl.c new file mode 100644 index 00000000000..f327a80efba --- /dev/null +++ b/board/microsoft/surface-rt/surface-rt-spl.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Surface RT SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2021 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +#define TPS65911_I2C_ADDR (0x2D << 1) +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +#define TPS62361B_I2C_ADDR (0x60 << 1) +#define TPS62361B_SET3_REG 0x03 +#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA); + + udelay(1000); + + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index 1077f0f4b61..f394ace786a 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -4,6 +4,13 @@ config PHYTEC_SOM_DETECTION help Support of I2C EEPROM based SoM detection. +config PHYTEC_SOM_DETECTION_BLOCKS + bool "Extend SoM detection with block support" + depends on PHYTEC_SOM_DETECTION + help + Extend the I2C EEPROM based SoM detection with API v3. This API + introduces blocks with different payloads. + config PHYTEC_IMX8M_SOM_DETECTION bool "Support SoM detection for i.MX8M PHYTEC platforms" depends on ARCH_IMX8M && PHYTEC_SOM_DETECTION @@ -16,6 +23,8 @@ config PHYTEC_AM62_SOM_DETECTION bool "Support SoM detection for AM62x PHYTEC platforms" depends on (TARGET_PHYCORE_AM62X_A53 || TARGET_PHYCORE_AM62X_R5) && \ PHYTEC_SOM_DETECTION + select PHYTEC_SOM_DETECTION_BLOCKS + depends on SPL_I2C && DM_I2C default y help Support of I2C EEPROM based SoM detection. Supported @@ -25,6 +34,8 @@ config PHYTEC_AM64_SOM_DETECTION bool "Support SoM detection for AM64x PHYTEC platforms" depends on (TARGET_PHYCORE_AM64X_A53 || TARGET_PHYCORE_AM64X_R5) && \ PHYTEC_SOM_DETECTION + select PHYTEC_SOM_DETECTION_BLOCKS + depends on SPL_I2C && DM_I2C default y help Support of I2C EEPROM based SoM detection. Supported diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index c34fc503059..04469d0a924 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -5,10 +5,8 @@ ifdef CONFIG_SPL_BUILD # necessary to create built-in.o obj- := __dummy__.o -else -obj-$(CONFIG_ARCH_K3) += k3/ endif -obj-y += phytec_som_detection.o -obj-$(CONFIG_ARCH_K3) += am6_som_detection.o +obj-y += phytec_som_detection.o phytec_som_detection_blocks.o +obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/ obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o diff --git a/board/phytec/common/am6_som_detection.c b/board/phytec/common/am6_som_detection.c index 2e9884dab44..7930ab42d1c 100644 --- a/board/phytec/common/am6_som_detection.c +++ b/board/phytec/common/am6_som_detection.c @@ -73,7 +73,7 @@ static u8 phytec_check_opt(struct phytec_eeprom_data *data, u8 option) * - The size * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_ddr_size(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_ddr_size(struct phytec_eeprom_data *data) { u8 ddr_id = phytec_check_opt(data, 3); @@ -89,7 +89,7 @@ u8 __maybe_unused phytec_get_am62_ddr_size(struct phytec_eeprom_data *data) * - Otherwise a board depended code for the size. * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data) { u8 spi = phytec_check_opt(data, 5); @@ -105,7 +105,7 @@ u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data) * - 0x1 if 10/100/1000 MBit Phy is populated. * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_eth(struct phytec_eeprom_data *data) { u8 eth = phytec_check_opt(data, 6); @@ -121,7 +121,7 @@ u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data) * - 1 if it is populated. * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_rtc(struct phytec_eeprom_data *data) { u8 rtc = phytec_check_opt(data, 7); @@ -131,28 +131,28 @@ u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data) #else -inline int __maybe_unused phytec_am62_detect(struct phytec_eeprom_data *data) +inline int __maybe_unused phytec_am6_detect(struct phytec_eeprom_data *data) { return -1; } inline u8 __maybe_unused -phytec_get_am62_ddr_size(struct phytec_eeprom_data *data) +phytec_get_am6_ddr_size(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } -inline u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } -inline u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_get_am6_eth(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } -inline u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_get_am6_rtc(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } diff --git a/board/phytec/common/am6_som_detection.h b/board/phytec/common/am6_som_detection.h index 032f9da3aab..c5c6e179da6 100644 --- a/board/phytec/common/am6_som_detection.h +++ b/board/phytec/common/am6_som_detection.h @@ -9,11 +9,19 @@ #include "phytec_som_detection.h" +#define EEPROM_ADDR 0x50 #define PHYTEC_AM62X_SOM 71 #define PHYTEC_AM64X_SOM 72 #define PHYTEC_EEPROM_VALUE_X 0x21 #define PHYTEC_EEPROM_NOR_FLASH_64MB_QSPI 0xC +enum { + EEPROM_RAM_SIZE_512MB = 0, + EEPROM_RAM_SIZE_1GB = 1, + EEPROM_RAM_SIZE_2GB = 2, + EEPROM_RAM_SIZE_4GB = 4 +}; + int __maybe_unused phytec_am6_detect(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_am6_ddr_size(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data); diff --git a/board/phytec/common/k3/Makefile b/board/phytec/common/k3/Makefile index bcca1a9f846..40e91a43e99 100644 --- a/board/phytec/common/k3/Makefile +++ b/board/phytec/common/k3/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y += board.o +obj-$(CONFIG_K3_DDRSS) += k3_ddrss_patch.o diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c index 9cb168c36cb..3d7e090ccaa 100644 --- a/board/phytec/common/k3/board.c +++ b/board/phytec/common/k3/board.c @@ -5,9 +5,12 @@ */ #include <env_internal.h> +#include <fdt_support.h> #include <spl.h> #include <asm/arch/hardware.h> +#include "../am6_som_detection.h" + #if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC) int mmc_get_env_dev(void) { @@ -68,6 +71,36 @@ int board_late_init(void) break; }; + if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) { + struct phytec_api3_element *block_element; + struct phytec_eeprom_data data; + int ret; + + ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + if (ret || !data.valid) + return 0; + + PHYTEC_API3_FOREACH_BLOCK(block_element, &data) { + switch (block_element->block_type) { + case PHYTEC_API3_BLOCK_MAC: + phytec_blocks_add_mac_to_env(block_element); + break; + default: + debug("%s: Unknown block type %i\n", __func__, + block_element->block_type); + } + } + } + + return 0; +} +#endif + +#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + fdt_copy_fixed_partitions(blob); + return 0; } #endif diff --git a/board/phytec/common/k3/k3_ddrss_patch.c b/board/phytec/common/k3/k3_ddrss_patch.c new file mode 100644 index 00000000000..5afe5a20c7f --- /dev/null +++ b/board/phytec/common/k3/k3_ddrss_patch.c @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + */ + +#include "k3_ddrss_patch.h" + +#include <fdt_support.h> +#include <linux/errno.h> + +#ifdef CONFIG_K3_AM64_DDRSS +#define LPDDR4_INTR_CTL_REG_COUNT (423U) +#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U) +#define LPDDR4_INTR_PHY_REG_COUNT (1406U) +#endif + +static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset, + const char *name, uint32_t idx, u32 val) +{ + val = cpu_to_be32(val); + return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name, + strlen(name), + idx * sizeof(val), &val, + sizeof(val)); +} + +int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss) +{ + int i, j; + int ret; + int mem_offset; + + mem_offset = fdt_path_offset(fdt, "/memorycontroller@f300000"); + if (mem_offset < 0) + return -ENODEV; + + for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++) + for (j = 0; j < ddrss->ctl_regs_num; j++) + if (i == ddrss->ctl_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,ctl-data", i, + ddrss->ctl_regs[j].val); + if (ret) + return ret; + } + + for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++) + for (j = 0; j < ddrss->pi_regs_num; j++) + if (i == ddrss->pi_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,pi-data", i, + ddrss->pi_regs[j].val); + if (ret) + return ret; + } + + for (i = 0; i < LPDDR4_INTR_PHY_REG_COUNT; i++) + for (j = 0; j < ddrss->phy_regs_num; j++) + if (i == ddrss->phy_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,phy-data", i, + ddrss->phy_regs[j].val); + if (ret) + return ret; + } + + return 0; +} diff --git a/board/phytec/common/k3/k3_ddrss_patch.h b/board/phytec/common/k3/k3_ddrss_patch.h new file mode 100644 index 00000000000..0a47c85116a --- /dev/null +++ b/board/phytec/common/k3/k3_ddrss_patch.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + */ + +#ifndef K3_DDRSS_PATCH +#define K3_DDRSS_PATCH + +#include <linux/types.h> + +struct ddr_reg { + u32 off; + u32 val; +}; + +struct ddrss { + struct ddr_reg *ctl_regs; + u32 ctl_regs_num; + struct ddr_reg *pi_regs; + u32 pi_regs_num; + struct ddr_reg *phy_regs; + u32 phy_regs_num; +}; + +int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss); + +#endif /* K3_DDRSS_PATCH */ diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index b14bb3dbb7f..166c3eae565 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -47,16 +47,9 @@ int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, return ret; } -int phytec_eeprom_data_init(struct phytec_eeprom_data *data, - int bus_num, int addr) +int phytec_eeprom_read(u8 *data, int bus_num, int addr, int size, int offset) { - int ret, i; - unsigned int crc; - u8 *ptr; - const unsigned int payload_size = sizeof(struct phytec_eeprom_payload); - - if (!data) - data = &eeprom_data; + int ret; #if CONFIG_IS_ENABLED(DM_I2C) struct udevice *dev; @@ -64,19 +57,182 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data, ret = i2c_get_chip_for_busnum(bus_num, addr, 2, &dev); if (ret) { pr_err("%s: i2c EEPROM not found: %i.\n", __func__, ret); - goto err; + return ret; } - ret = dm_i2c_read(dev, 0, (uint8_t *)data, payload_size); + ret = dm_i2c_read(dev, offset, (uint8_t *)data, size); if (ret) { pr_err("%s: Unable to read EEPROM data: %i\n", __func__, ret); - goto err; + return ret; } #else i2c_set_bus_num(bus_num); - ret = i2c_read(addr, 0, 2, (uint8_t *)data, - sizeof(struct phytec_eeprom_data)); + ret = i2c_read(addr, offset, 2, (uint8_t *)data, size); #endif + return ret; +} + +int phytec_eeprom_data_init_v2(struct phytec_eeprom_data *data) +{ + unsigned int crc; + + if (!data) + return -1; + + crc = crc8(0, (const unsigned char *)&data->payload, PHYTEC_API2_DATA_LEN); + debug("%s: crc: %x\n", __func__, crc); + + if (crc) { + pr_err("%s: CRC mismatch. EEPROM data is not usable.\n", + __func__); + return -EINVAL; + } + + return 0; +} + +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS) + +int phytec_eeprom_data_init_v3_block(struct phytec_eeprom_data *data, + struct phytec_api3_block_header *header, + u8 *payload) +{ + struct phytec_api3_element *element = NULL; + struct phytec_api3_element *list_iterator; + + if (!header) + return -1; + if (!payload) + return -1; + + debug("%s: block type: %i\n", __func__, header->block_type); + switch (header->block_type) { + case PHYTEC_API3_BLOCK_MAC: + element = phytec_blocks_init_mac(header, payload); + break; + default: + debug("%s: Unknown block type %i\n", __func__, + header->block_type); + } + if (!element) + return -1; + + if (!data->payload.block_head) { + data->payload.block_head = element; + return 0; + } + + list_iterator = data->payload.block_head; + while (list_iterator && list_iterator->next) + list_iterator = list_iterator->next; + list_iterator->next = element; + + return 0; +} + +int phytec_eeprom_data_init_v3(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + int ret, i; + struct phytec_api3_header header; + unsigned int crc; + u8 *payload; + int block_addr; + struct phytec_api3_block_header *block_header; + + if (!data) + return -1; + + ret = phytec_eeprom_read((uint8_t *)&header, bus_num, addr, + PHYTEC_API3_DATA_HEADER_LEN, + PHYTEC_API2_DATA_LEN); + if (ret) { + pr_err("%s: Failed to read API v3 data header.\n", __func__); + goto err; + } + + crc = crc8(0, (const unsigned char *)&header, + PHYTEC_API3_DATA_HEADER_LEN); + debug("%s: crc: %x\n", __func__, crc); + if (crc) { + pr_err("%s: CRC mismatch. API3 header is unusable.\n", + __func__); + goto err; + } + + debug("%s: data length: %i\n", __func__, header.data_length); + payload = malloc(header.data_length); + if (!payload) { + pr_err("%s: Unable to allocate memory\n", __func__); + goto err_payload; + } + + ret = phytec_eeprom_read(payload, bus_num, addr, header.data_length, + PHYTEC_API3_DATA_HEADER_LEN + + PHYTEC_API2_DATA_LEN); + if (ret) { + pr_err("%s: Failed to read API v3 data payload.\n", __func__); + goto err_payload; + } + + block_addr = 0; + debug("%s: block count: %i\n", __func__, header.block_count); + for (i = 0; i < header.block_count; i++) { + debug("%s: block_addr: %i\n", __func__, block_addr); + block_header = (struct phytec_api3_block_header *) + &payload[block_addr]; + crc = crc8(0, (const unsigned char *)block_header, + PHYTEC_API3_BLOCK_HEADER_LEN); + + debug("%s: crc: %x\n", __func__, crc); + if (crc) { + pr_err("%s: CRC mismatch. API3 block header is unusable\n", + __func__); + goto err_payload; + } + + ret = phytec_eeprom_data_init_v3_block(data, block_header, + &payload[block_addr + PHYTEC_API3_BLOCK_HEADER_LEN]); + /* Ignore failed block initialization and continue. */ + if (ret) + debug("%s: Unable to create block with index %i.\n", + __func__, i); + + block_addr = block_header->next_block; + } + + free(payload); + return 0; +err_payload: + free(payload); +err: + return -1; +} + +#else + +inline int phytec_eeprom_data_init_v3(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + return 0; +} + +#endif + +int phytec_eeprom_data_init(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + int ret, i; + u8 *ptr; + + if (!data) + data = &eeprom_data; + + ret = phytec_eeprom_read((u8 *)data, bus_num, addr, + PHYTEC_API2_DATA_LEN, 0); + if (ret) + goto err; + data->payload.block_head = NULL; if (data->payload.api_rev == 0xff) { pr_err("%s: EEPROM is not flashed. Prototype?\n", __func__); @@ -85,31 +241,28 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data, } ptr = (u8 *)data; - for (i = 0; i < payload_size; ++i) + for (i = 0; i < PHYTEC_API2_DATA_LEN; ++i) if (ptr[i] != 0x0) break; - if (i == payload_size) { + if (i == PHYTEC_API2_DATA_LEN) { pr_err("%s: EEPROM data is all zero. Erased?\n", __func__); ret = -EINVAL; goto err; } - /* We are done here for early revisions */ - if (data->payload.api_rev <= PHYTEC_API_REV1) { - data->valid = true; - return 0; + if (data->payload.api_rev >= PHYTEC_API_REV2) { + ret = phytec_eeprom_data_init_v2(data); + if (ret) + goto err; } - crc = crc8(0, (const unsigned char *)&data->payload, payload_size); - debug("%s: crc: %x\n", __func__, crc); - - if (crc) { - pr_err("%s: CRC mismatch. EEPROM data is not usable.\n", - __func__); - ret = -EINVAL; - goto err; - } + if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) + if (data->payload.api_rev >= PHYTEC_API_REV3) { + ret = phytec_eeprom_data_init_v3(data, bus_num, addr); + if (ret) + goto err; + } data->valid = true; return 0; @@ -248,6 +401,17 @@ struct extension *phytec_add_extension(const char *name, const char *overlay, } #endif /* IS_ENABLED(CONFIG_CMD_EXTENSION) */ +struct phytec_api3_element * + __maybe_unused phytec_get_block_head(struct phytec_eeprom_data *data) +{ + if (!data) + data = &eeprom_data; + if (!data->valid) + return NULL; + + return data->payload.block_head; +} + #else inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, @@ -288,6 +452,12 @@ u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data) return PHYTEC_EEPROM_INVAL; } +inline struct phytec_api3_element * __maybe_unused + phytec_get_block_head(struct phytec_eeprom_data *data) +{ + return NULL; +} + #if IS_ENABLED(CONFIG_CMD_EXTENSION) inline struct extension *phytec_add_extension(const char *name, const char *overlay, diff --git a/board/phytec/common/phytec_som_detection.h b/board/phytec/common/phytec_som_detection.h index 0ad5c14ef4e..5e35a13cb21 100644 --- a/board/phytec/common/phytec_som_detection.h +++ b/board/phytec/common/phytec_som_detection.h @@ -7,9 +7,13 @@ #ifndef _PHYTEC_SOM_DETECTION_H #define _PHYTEC_SOM_DETECTION_H +#include "phytec_som_detection_blocks.h" + #define PHYTEC_MAX_OPTIONS 17 #define PHYTEC_EEPROM_INVAL 0xff +#define PHYTEC_API2_DATA_LEN 32 + #define PHYTEC_GET_OPTION(option) \ (((option) > '9') ? (option) - 'A' + 10 : (option) - '0') @@ -17,6 +21,7 @@ enum { PHYTEC_API_REV0 = 0, PHYTEC_API_REV1, PHYTEC_API_REV2, + PHYTEC_API_REV3, }; enum phytec_som_type_str { @@ -61,6 +66,7 @@ struct phytec_eeprom_payload { struct phytec_api0_data data_api0; struct phytec_api2_data data_api2; } data; + struct phytec_api3_element *block_head; } __packed; struct phytec_eeprom_data { @@ -86,4 +92,7 @@ struct extension *phytec_add_extension(const char *name, const char *overlay, const char *other); #endif /* IS_ENABLED(CONFIG_CMD_EXTENSION) */ +struct phytec_api3_element * + __maybe_unused phytec_get_block_head(struct phytec_eeprom_data *data); + #endif /* _PHYTEC_SOM_DETECTION_H */ diff --git a/board/phytec/common/phytec_som_detection_blocks.c b/board/phytec/common/phytec_som_detection_blocks.c new file mode 100644 index 00000000000..5f3c27ef0c2 --- /dev/null +++ b/board/phytec/common/phytec_som_detection_blocks.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Daniel Schultz <d.schultz@phytec.de> + */ + +#include <malloc.h> +#include <u-boot/crc.h> +#include <net.h> +#include <vsprintf.h> + +#include "phytec_som_detection_blocks.h" + +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS) + +struct phytec_api3_element * + phytec_blocks_init_mac(struct phytec_api3_block_header *header, + uint8_t *payload) +{ + struct phytec_api3_element *element; + struct phytec_api3_block_mac *mac; + unsigned int crc; + unsigned int len = sizeof(struct phytec_api3_block_mac); + + if (!header) + return NULL; + if (!payload) + return NULL; + + element = (struct phytec_api3_element *) + calloc(8, PHYTEC_API3_ELEMENT_HEADER_SIZE + len); + if (!element) { + pr_err("%s: Unable to allocate memory\n", __func__); + return NULL; + } + element->block_type = header->block_type; + memcpy(&element->block.mac, payload, len); + mac = &element->block.mac; + + debug("%s: interface: %i\n", __func__, mac->interface); + debug("%s: MAC %pM\n", __func__, mac->address); + + crc = crc8(0, (const unsigned char *)mac, len); + debug("%s: crc: %x\n", __func__, crc); + if (crc) { + pr_err("%s: CRC mismatch. API3 block payload is unusable\n", + __func__); + return NULL; + } + + return element; +} + +int __maybe_unused + phytec_blocks_add_mac_to_env(struct phytec_api3_element *element) +{ + char enetenv[9] = "ethaddr"; + char buf[ARP_HLEN_ASCII + 1]; + struct phytec_api3_block_mac *block = &element->block.mac; + int ret; + + if (!is_valid_ethaddr(block->address)) { + pr_err("%s: Invalid MAC address in block.\n", __func__); + return -1; + } + + if (block->interface > 0) { + ret = sprintf(enetenv, "eth%iaddr", block->interface); + if (ret != 8) { + pr_err("%s: Unable to create env string\n", __func__); + return -1; + } + } + + ret = sprintf(buf, "%pM", block->address); + if (ret != ARP_HLEN_ASCII) { + pr_err("%s: Unable to convert MAC address\n", __func__); + return -1; + } + ret = env_set(enetenv, buf); + if (ret) { + pr_err("%s: Failed to set MAC address to env.\n", __func__); + return -1; + } + + debug("%s: Added %s to %s\n", __func__, buf, enetenv); + return 0; +} + +#else + +inline struct phytec_api3_element * + phytec_api3_init_mac_block(struct phytec_api3_block_header *header, + uint8_t *payload) +{ + return NULL; +} + +inline int __maybe_unused + phytec_blocks_add_mac_to_env(struct phytec_api3_element *element) +{ + return -1; +} + +#endif diff --git a/board/phytec/common/phytec_som_detection_blocks.h b/board/phytec/common/phytec_som_detection_blocks.h new file mode 100644 index 00000000000..2a5a83c9039 --- /dev/null +++ b/board/phytec/common/phytec_som_detection_blocks.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Daniel Schultz <d.schultz@phytec.de> + */ + +#ifndef _PHYTEC_SOM_DETECTION_BLOCKS_H +#define _PHYTEC_SOM_DETECTION_BLOCKS_H + +#define PHYTEC_API3_DATA_HEADER_LEN 8 +#define PHYTEC_API3_BLOCK_HEADER_LEN 4 +#define PHYTEC_API3_PAYLOAD_START \ + (PHYTEC_API2_DATA_LEN + PHYTEC_API3_DATA_HEADER_LEN) + +#define PHYTEC_API3_ELEMENT_HEADER_SIZE \ + (sizeof(struct phytec_api3_element *) + \ + sizeof(enum phytec_api3_block_types)) + +#define PHYTEC_API3_FOREACH_BLOCK(elem, data) \ + for (elem = phytec_get_block_head(data); elem; elem = elem->next) + +struct phytec_api3_header { + u16 data_length; /* Total length in Bytes of all blocks */ + u8 block_count; /* Number of blocks */ + u8 sub_version; /* Block specification version */ + u8 reserved[3]; /* Reserved */ + u8 crc8; /* checksum */ +} __packed; + +struct phytec_api3_block_header { + u8 block_type; /* Block payload identifier */ + u16 next_block; /* Address of the next block */ + u8 crc8; /* checksum */ +} __packed; + +enum phytec_api3_block_types { + PHYTEC_API3_BLOCK_MAC = 0, +}; + +struct phytec_api3_block_mac { + u8 interface; /* Ethernet interface number */ + u8 address[6]; /* MAC-Address */ + u8 crc8; /* checksum */ +} __packed; + +struct phytec_api3_element { + struct phytec_api3_element *next; + enum phytec_api3_block_types block_type; + union { + struct phytec_api3_block_mac mac; + } block; +} __packed; + +struct phytec_api3_element * + phytec_blocks_init_mac(struct phytec_api3_block_header *header, + uint8_t *payload); + +int __maybe_unused +phytec_blocks_add_mac_to_env(struct phytec_api3_element *element); + +#endif /* _PHYTEC_SOM_DETECTION_BLOCKS_H */ diff --git a/board/phytec/phycore_am62x/Kconfig b/board/phytec/phycore_am62x/Kconfig index 1de8850c6c4..7c179ef0078 100644 --- a/board/phytec/phycore_am62x/Kconfig +++ b/board/phytec/phycore_am62x/Kconfig @@ -35,3 +35,33 @@ config SPL_LDSCRIPT source "board/phytec/common/Kconfig" endif + +config PHYCORE_AM62X_RAM_SIZE_FIX + bool "Set phyCORE-AM62x RAM size fix instead of detecting" + default false + help + RAM size is automatic being detected with the help of + the EEPROM introspection data. Set RAM size to a fix value + instead. + +choice + prompt "phyCORE-AM62x RAM size" + depends on PHYCORE_AM62X_RAM_SIZE_FIX + default PHYCORE_AM62X_RAM_SIZE_2GB + +config PHYCORE_AM62X_RAM_SIZE_1GB + bool "1GB RAM" + help + Set RAM size fix to 1GB for phyCORE-AM62x. + +config PHYCORE_AM62X_RAM_SIZE_2GB + bool "2GB RAM" + help + Set RAM size fix to 2GB for phyCORE-AM62x. + +config PHYCORE_AM62X_RAM_SIZE_4GB + bool "4GB RAM" + help + Set RAM size fix to 4GB for phyCORE-AM62x. + +endchoice diff --git a/board/phytec/phycore_am62x/MAINTAINERS b/board/phytec/phycore_am62x/MAINTAINERS index 02ac88e58a4..42463ad054e 100644 --- a/board/phytec/phycore_am62x/MAINTAINERS +++ b/board/phytec/phycore_am62x/MAINTAINERS @@ -11,3 +11,4 @@ F: configs/phycore_am62x_a53_defconfig F: configs/phycore_am62x_r5_defconfig F: include/configs/phycore_am62x.h F: doc/board/phytec/phycore-am62x.rst +F: board/phytec/common/k3 diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index a082b886bda..9f6bc736cbb 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -4,10 +4,18 @@ * Author: Wadim Egorov <w.egorov@phytec.de> */ +#include <asm/arch/hardware.h> #include <asm/io.h> #include <spl.h> #include <fdt_support.h> +#include "phycore-ddr-data.h" +#include "../common/k3/k3_ddrss_patch.h" +#include "../common/am6_som_detection.h" + +#define AM64_DDRSS_SS_BASE 0x0F300000 +#define DDRSS_V2A_CTL_REG 0x0020 + DECLARE_GLOBAL_DATA_PTR; int board_init(void) @@ -15,16 +23,185 @@ int board_init(void) return 0; } +static u8 phytec_get_am62_ddr_size_default(void) +{ + int ret; + struct phytec_eeprom_data data; + + if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_1GB)) + return EEPROM_RAM_SIZE_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_2GB)) + return EEPROM_RAM_SIZE_2GB; + else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_4GB)) + return EEPROM_RAM_SIZE_4GB; + } + + ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + if (!ret && data.valid) + return phytec_get_am6_ddr_size(&data); + + /* Default DDR size is 2GB */ + return EEPROM_RAM_SIZE_2GB; +} + int dram_init(void) { - return fdtdec_setup_mem_size_base(); + u8 ram_size; + + if (!IS_ENABLED(CONFIG_CPU_V7R)) + return fdtdec_setup_mem_size_base(); + + ram_size = phytec_get_am62_ddr_size_default(); + + /* + * HACK: ddrss driver support 2GB RAM by default + * V2A_CTL_REG should be updated to support other RAM size + */ + if (IS_ENABLED(CONFIG_K3_AM64_DDRSS)) + if (ram_size == EEPROM_RAM_SIZE_4GB) + writel(0x00000210, AM64_DDRSS_SS_BASE + DDRSS_V2A_CTL_REG); + + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + gd->ram_size = 0x40000000; + break; + case EEPROM_RAM_SIZE_2GB: + gd->ram_size = 0x80000000; + break; + case EEPROM_RAM_SIZE_4GB: +#ifdef CONFIG_PHYS_64BIT + gd->ram_size = 0x100000000; +#else + gd->ram_size = 0x80000000; +#endif + break; + default: + gd->ram_size = 0x80000000; + } + + return 0; +} + +phys_size_t board_get_usable_ram_top(phys_size_t total_size) +{ +#ifdef CONFIG_PHYS_64BIT + /* Limit RAM used by U-Boot to the DDR low region */ + if (gd->ram_top > 0x100000000) + return 0x100000000; +#endif + return gd->ram_top; } int dram_init_banksize(void) { - return fdtdec_setup_memory_banksize(); + u8 ram_size; + + if (!IS_ENABLED(CONFIG_CPU_V7R)) + return fdtdec_setup_memory_banksize(); + + ram_size = phytec_get_am62_ddr_size_default(); + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x40000000; + gd->ram_size = 0x40000000; + break; + + case EEPROM_RAM_SIZE_2GB: + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + break; + + case EEPROM_RAM_SIZE_4GB: + /* Bank 0 declares the memory available in the DDR low region */ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + +#ifdef CONFIG_PHYS_64BIT + /* Bank 1 declares the memory available in the DDR upper region */ + gd->bd->bi_dram[1].start = 0x880000000; + gd->bd->bi_dram[1].size = 0x80000000; + gd->ram_size = 0x100000000; +#endif + break; + default: + /* Continue with default 2GB setup */ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + printf("DDR size %d is not supported\n", ram_size); + } + + return 0; +} + +#if defined(CONFIG_K3_DDRSS) +int update_ddrss_timings(void) +{ + int ret; + u8 ram_size; + struct ddrss *ddr_patch = NULL; + void *fdt = (void *)gd->fdt_blob; + + ram_size = phytec_get_am62_ddr_size_default(); + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + ddr_patch = &phycore_ddrss_data[PHYCORE_1GB]; + break; + case EEPROM_RAM_SIZE_2GB: + ddr_patch = NULL; + break; + case EEPROM_RAM_SIZE_4GB: + ddr_patch = &phycore_ddrss_data[PHYCORE_4GB]; + break; + default: + break; + } + + /* Nothing to patch */ + if (!ddr_patch) + return 0; + + debug("Applying DDRSS timings patch for ram_size %d\n", ram_size); + + ret = fdt_apply_ddrss_timings_patch(fdt, ddr_patch); + if (ret < 0) { + printf("Failed to apply ddrs timings patch %d\n", ret); + return ret; + } + + return 0; } +int do_board_detect(void) +{ + return update_ddrss_timings(); +} +#endif + +#if IS_ENABLED(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int bank; + int ret; + + dram_init(); + dram_init_banksize(); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start[bank] = gd->bd->bi_dram[bank].start; + size[bank] = gd->bd->bi_dram[bank].size; + } + + ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, CONFIG_NR_DRAM_BANKS); +} +#endif + #define CTRLMMR_USB0_PHY_CTRL 0x43004008 #define CTRLMMR_USB1_PHY_CTRL 0x43004018 #define CORE_VOLTAGE 0x80000000 diff --git a/board/phytec/phycore_am62x/phycore-ddr-data.h b/board/phytec/phycore_am62x/phycore-ddr-data.h new file mode 100644 index 00000000000..fe6eccd959e --- /dev/null +++ b/board/phytec/phycore_am62x/phycore-ddr-data.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + */ + +#ifndef PHYCORE_DDR_DATA +#define PHYCORE_DDR_DATA + +#include "../common/k3/k3_ddrss_patch.h" + +/* 1 GB variant delta */ +struct ddr_reg ddr_1gb_ctl_regs[] = { + { 55, 0x0400DB60 }, + { 58, 0x0400DB60 }, + { 61, 0x0400DB60 }, + { 73, 0x00001860 }, + { 75, 0x00001860 }, + { 77, 0x00001860 }, + { 119, 0x00061800 }, + { 120, 0x00061800 }, + { 121, 0x00061800 }, + { 122, 0x00061800 }, + { 123, 0x00061800 }, + { 125, 0x0000AAA0 }, + { 126, 0x00061800 }, + { 127, 0x00061800 }, + { 128, 0x00061800 }, + { 129, 0x00061800 }, + { 130, 0x00061800 }, + { 132, 0x0000AAA0 }, + { 133, 0x00061800 }, + { 134, 0x00061800 }, + { 135, 0x00061800 }, + { 136, 0x00061800 }, + { 137, 0x00061800 }, + { 139, 0x0000AAA0 }, + { 206, 0x00000000 }, + { 209, 0x00000000 }, + { 212, 0x00000000 }, + { 215, 0x00000000 }, + { 218, 0x00000000 }, + { 221, 0x00000000 }, + { 230, 0x00000000 }, + { 231, 0x00000000 }, + { 232, 0x00000000 }, + { 233, 0x00000000 }, + { 234, 0x00000000 }, + { 235, 0x00000000 }, + { 316, 0x01010000 }, + { 318, 0x3FFF0000 }, + { 327, 0x00000C01 }, + { 328, 0x00000000 }, + { 385, 0x000030C0 }, + { 390, 0x0000DB60 }, + { 391, 0x0001E780 }, + { 394, 0x000030C0 }, + { 399, 0x0000DB60 }, + { 400, 0x0001E780 }, + { 403, 0x000030C0 }, + { 408, 0x0000DB60 }, + { 409, 0x0001E780 } +}; + +struct ddr_reg ddr_1gb_pi_regs[] = { + { 77, 0x04000100 }, + { 176, 0x00001860 }, + { 178, 0x00001860 }, + { 180, 0x04001860 }, + { 233, 0x0000C570 }, + { 238, 0x0000C570 }, + { 243, 0x0000C570 }, + { 247, 0x000030C0 }, + { 248, 0x0001E780 }, + { 249, 0x000030C0 }, + { 250, 0x0001E780 }, + { 251, 0x000030C0 }, + { 252, 0x0001E780 }, + { 299, 0x00000000 }, + { 301, 0x00000000 }, + { 307, 0x00000000 }, + { 309, 0x00000000 }, + { 315, 0x00000000 }, + { 317, 0x00000000 }, + { 323, 0x00000000 }, + { 325, 0x00000000 }, + { 331, 0x00000000 }, + { 333, 0x00000000 }, + { 339, 0x00000000 }, + { 341, 0x00000000 } +}; + +struct ddr_reg ddr_1gb_phy_regs[] = { + { 1371, 0x0001F7C2 }, +}; + +/* 4 GB variant delta */ +struct ddr_reg ddr_4gb_ctl_regs[] = { + { 55, 0x0400DB60 }, + { 58, 0x0400DB60 }, + { 61, 0x0400DB60 }, + { 73, 0x00001860 }, + { 75, 0x00001860 }, + { 77, 0x00001860 }, + { 119, 0x00061800 }, + { 120, 0x00061800 }, + { 121, 0x00061800 }, + { 122, 0x00061800 }, + { 123, 0x00061800 }, + { 125, 0x0000AAA0 }, + { 126, 0x00061800 }, + { 127, 0x00061800 }, + { 128, 0x00061800 }, + { 129, 0x00061800 }, + { 130, 0x00061800 }, + { 132, 0x0000AAA0 }, + { 133, 0x00061800 }, + { 134, 0x00061800 }, + { 135, 0x00061800 }, + { 136, 0x00061800 }, + { 137, 0x00061800 }, + { 139, 0x0000AAA0 }, + { 206, 0x00000000 }, + { 209, 0x00000000 }, + { 212, 0x00000000 }, + { 215, 0x00000000 }, + { 218, 0x00000000 }, + { 221, 0x00000000 }, + { 230, 0x00000000 }, + { 231, 0x00000000 }, + { 232, 0x00000000 }, + { 233, 0x00000000 }, + { 234, 0x00000000 }, + { 235, 0x00000000 }, + { 316, 0x00000000 }, + { 318, 0x7FFF0000 }, + { 327, 0x01000C01 }, + { 328, 0x00000001 }, + { 385, 0x000030C0 }, + { 390, 0x0000DB60 }, + { 391, 0x0001E780 }, + { 394, 0x000030C0 }, + { 399, 0x0000DB60 }, + { 400, 0x0001E780 }, + { 403, 0x000030C0 }, + { 408, 0x0000DB60 }, + { 409, 0x0001E780 } +}; + +struct ddr_reg ddr_4gb_pi_regs[] = { + { 77, 0x04000000 }, + { 176, 0x00001860 }, + { 178, 0x00001860 }, + { 180, 0x04001860 }, + { 233, 0x0000C570 }, + { 238, 0x0000C570 }, + { 243, 0x0000C570 }, + { 247, 0x000030C0 }, + { 248, 0x0001E780 }, + { 249, 0x000030C0 }, + { 250, 0x0001E780 }, + { 251, 0x000030C0 }, + { 252, 0x0001E780 }, + { 299, 0x00000000 }, + { 301, 0x00000000 }, + { 307, 0x00000000 }, + { 309, 0x00000000 }, + { 315, 0x00000000 }, + { 317, 0x00000000 }, + { 323, 0x00000000 }, + { 325, 0x00000000 }, + { 331, 0x00000000 }, + { 333, 0x00000000 }, + { 339, 0x00000000 }, + { 341, 0x00000000 } +}; + +struct ddr_reg ddr_4gb_phy_regs[] = { + { 1371, 0x0001F7C2 }, +}; + +enum { + PHYCORE_1GB, + PHYCORE_4GB, +}; + +struct ddrss phycore_ddrss_data[] = { + [PHYCORE_1GB] = { + .ctl_regs = &ddr_1gb_ctl_regs[0], + .ctl_regs_num = ARRAY_SIZE(ddr_1gb_ctl_regs), + .pi_regs = &ddr_1gb_pi_regs[0], + .pi_regs_num = ARRAY_SIZE(ddr_1gb_pi_regs), + .phy_regs = &ddr_1gb_phy_regs[0], + .phy_regs_num = ARRAY_SIZE(ddr_1gb_phy_regs), + }, + [PHYCORE_4GB] = { + .ctl_regs = &ddr_4gb_ctl_regs[0], + .ctl_regs_num = ARRAY_SIZE(ddr_4gb_ctl_regs), + .pi_regs = &ddr_4gb_pi_regs[0], + .pi_regs_num = ARRAY_SIZE(ddr_4gb_pi_regs), + .phy_regs = &ddr_4gb_phy_regs[0], + .phy_regs_num = ARRAY_SIZE(ddr_4gb_phy_regs), + }, +}; + +#endif /* PHYCORE_DDR_DATA */ diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env index ada3a9233be..42db26a5990 100644 --- a/board/phytec/phycore_am62x/phycore_am62x.env +++ b/board/phytec/phycore_am62x/phycore_am62x.env @@ -1,3 +1,5 @@ +#include <env/ti/k3_dfu.env> + fdtaddr=0x88000000 loadaddr=0x82000000 scriptaddr=0x80000000 diff --git a/board/phytec/phycore_imx8mm/MAINTAINERS b/board/phytec/phycore_imx8mm/MAINTAINERS index e46e3691bac..58c5e2d0af9 100644 --- a/board/phytec/phycore_imx8mm/MAINTAINERS +++ b/board/phytec/phycore_imx8mm/MAINTAINERS @@ -2,10 +2,7 @@ phyCORE-i.MX8M Mini M: Teresa Remmet <t.remmet@phytec.de> W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/ S: Maintained -F: arch/arm/dts/imx8mm-phyboard-polis-rdk.dts -F: arch/arm/dts/imx8mm-phycore-som.dtsi F: arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi -F: arch/arm/dts/imx8mm-phygate-tauri-l.dts F: arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi F: board/phytec/phycore_imx8mm/ F: configs/imx8mm-phygate-tauri-l_defconfig diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig index f846d10bad9..bdf9e97beaa 100644 --- a/board/phytec/phycore_imx8mp/Kconfig +++ b/board/phytec/phycore_imx8mp/Kconfig @@ -12,5 +12,72 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg" +config PHYCORE_IMX8MP_RAM_SIZE_FIX + bool "Set phyCORE-i.MX8MP RAM size fix instead of detecting" + default false + help + RAM size is automatic being detected with the help of + the EEPROM introspection data. Set RAM size to a fix value + instead. + +choice + prompt "phyCORE-i.MX8MP RAM size" + depends on PHYCORE_IMX8MP_RAM_SIZE_FIX + default PHYCORE_IMX8MP_RAM_SIZE_2GB + +config PHYCORE_IMX8MP_RAM_SIZE_1GB + bool "1GB RAM" + help + Set RAM size fix to 1GB for phyCORE-i.MX8MP. + RAM frequency is configured independent. + +config PHYCORE_IMX8MP_RAM_SIZE_2GB + bool "2GB RAM" + help + Set RAM size fix to 2GB for phyCORE-i.MX8MP. + RAM frequency is configured independent. + +config PHYCORE_IMX8MP_RAM_SIZE_4GB + bool "4GB RAM" + help + Set RAM size fix to 4GB for phyCORE-i.MX8MP. + RAM frequency is configured independent. + +config PHYCORE_IMX8MP_RAM_SIZE_8GB + bool "8GB RAM" + select PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS + help + Set RAM size fix to 8GB for phyCORE-i.MX8MP. + Only 2GHz RAMs are supported. + +endchoice + +config PHYCORE_IMX8MP_RAM_FREQ_FIX + bool "Set phyCORE-i.MX8MP RAM frequency fix instead of detecting" + default false + help + RAM frequency is automatic being detected with the help of + the EEPROM introspection data. Set RAM frequency to a fix value + instead. + +choice + prompt "phyCORE-i.MX8MP RAM frequency" + depends on PHYCORE_IMX8MP_RAM_FREQ_FIX + default PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS + +config PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS + bool "Use 2GHz RAM timings" + help + Use fix 2GHz RAM timings for phyCORE-i.MX8MP instead of + 1.5GHz timings. + +config PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS + depends on !PHYCORE_IMX8MP_RAM_SIZE_8GB + bool "Use 1.5GHz RAM timings" + help + Use fix 1.5GHz RAM timings for phyCORE-i.MX8MP instead of + 2GHz timings. +endchoice + source "board/phytec/common/Kconfig" endif diff --git a/board/phytec/phycore_imx8mp/MAINTAINERS b/board/phytec/phycore_imx8mp/MAINTAINERS index d3beb978d3a..645476ae30a 100644 --- a/board/phytec/phycore_imx8mp/MAINTAINERS +++ b/board/phytec/phycore_imx8mp/MAINTAINERS @@ -2,7 +2,6 @@ phyCORE-i.MX8M Plus M: Teresa Remmet <t.remmet@phytec.de> W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-plus/ S: Maintained -F: arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts F: arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi F: board/phytec/phycore_imx8mp/ F: configs/phycore-imx8mp_defconfig diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.c b/board/phytec/phycore_imx8mp/lpddr4_timing.c index f2707b85960..9984b6c2601 100644 --- a/board/phytec/phycore_imx8mp/lpddr4_timing.c +++ b/board/phytec/phycore_imx8mp/lpddr4_timing.c @@ -1839,3 +1839,156 @@ struct dram_timing_info dram_timing = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 3000, 400, 100, }, }; + +void set_dram_timings_2ghz_2gb(void) +{ + dram_timing.ddrc_cfg[3].val = 0x1323; + dram_timing.ddrc_cfg[4].val = 0x1e84800; + dram_timing.ddrc_cfg[5].val = 0x7a0118; + dram_timing.ddrc_cfg[8].val = 0xc00307a3; + dram_timing.ddrc_cfg[9].val = 0xc50000; + dram_timing.ddrc_cfg[10].val = 0xf4003f; + dram_timing.ddrc_cfg[11].val = 0xf30000; + dram_timing.ddrc_cfg[14].val = 0x2028222a; + dram_timing.ddrc_cfg[15].val = 0x8083f; + dram_timing.ddrc_cfg[16].val = 0xe0e000; + dram_timing.ddrc_cfg[17].val = 0x12040a12; + dram_timing.ddrc_cfg[18].val = 0x2050f0f; + dram_timing.ddrc_cfg[19].val = 0x1010009; + dram_timing.ddrc_cfg[20].val = 0x502; + dram_timing.ddrc_cfg[21].val = 0x20800; + dram_timing.ddrc_cfg[22].val = 0xe100002; + dram_timing.ddrc_cfg[23].val = 0x120; + dram_timing.ddrc_cfg[24].val = 0xc80064; + dram_timing.ddrc_cfg[25].val = 0x3e8001e; + dram_timing.ddrc_cfg[26].val = 0x3207a12; + dram_timing.ddrc_cfg[28].val = 0x4a3820e; + dram_timing.ddrc_cfg[30].val = 0x230e; + dram_timing.ddrc_cfg[37].val = 0x799; + dram_timing.ddrc_cfg[38].val = 0x9141d1c; + dram_timing.ddrc_cfg[74].val = 0x302; + dram_timing.ddrc_cfg[83].val = 0x599; + dram_timing.ddrc_cfg[99].val = 0x302; + dram_timing.ddrc_cfg[108].val = 0x599; + dram_timing.ddrphy_cfg[66].val = 0x18; + dram_timing.ddrphy_cfg[75].val = 0x1e3; + dram_timing.ddrphy_cfg[77].val = 0x1e3; + dram_timing.ddrphy_cfg[79].val = 0x1e3; + dram_timing.ddrphy_cfg[145].val = 0x3e8; + dram_timing.fsp_msg[0].drate = 4000; + dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0; + dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f; + dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f; + dram_timing.fsp_msg[3].drate = 4000; + dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0; + dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f; + dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f; + dram_timing.ddrphy_pie[480].val = 0x465; + dram_timing.ddrphy_pie[481].val = 0xfa; + dram_timing.ddrphy_pie[482].val = 0x9c4; + dram_timing.fsp_table[0] = 4000; +} + +void set_dram_timings_1_5ghz_1gb(void) +{ + dram_timing.ddrc_cfg[3].val = 0x1233; + dram_timing.ddrc_cfg[5].val = 0x5b0087; + dram_timing.ddrc_cfg[6].val = 0x61027f10; + dram_timing.ddrc_cfg[7].val = 0x7b0; + dram_timing.ddrc_cfg[11].val = 0xf30000; + dram_timing.ddrc_cfg[23].val = 0x8d; + dram_timing.ddrc_cfg[45].val = 0xf070707; + dram_timing.ddrc_cfg[59].val = 0x1031; + dram_timing.ddrc_cfg[62].val = 0xc0012; + dram_timing.ddrc_cfg[77].val = 0x13; + dram_timing.ddrc_cfg[84].val = 0x1031; + dram_timing.ddrc_cfg[87].val = 0x30005; + dram_timing.ddrc_cfg[102].val = 0x5; + dram_timing.ddrphy_cfg[75].val = 0x1e3; + dram_timing.ddrphy_cfg[77].val = 0x1e3; + dram_timing.ddrphy_cfg[79].val = 0x1e3; + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf32d; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf32d; + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf32d; + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf32d; +} + +void set_dram_timings_2ghz_1gb(void) +{ + set_dram_timings_2ghz_2gb(); + dram_timing.ddrc_cfg[5].val = 0x7a00b4; + dram_timing.ddrc_cfg[23].val = 0xbc; + dram_timing.ddrc_cfg[45].val = 0xf070707; + dram_timing.ddrc_cfg[62].val = 0xc0012; + dram_timing.ddrc_cfg[77].val = 0x13; + dram_timing.ddrc_cfg[87].val = 0x30005; + dram_timing.ddrc_cfg[102].val = 0x5; +} + +void set_dram_timings_1_5ghz_4gb(void) +{ + dram_timing.ddrc_cfg[2].val = 0xa3080020; + dram_timing.ddrc_cfg[39].val = 0x17; + dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310; + dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3; + dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3; +} + +void set_dram_timings_2ghz_4gb(void) +{ + set_dram_timings_2ghz_2gb(); + dram_timing.ddrc_cfg[2].val = 0xa3080020; + dram_timing.ddrc_cfg[39].val = 0x17; + dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310; + dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3; + dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3; +} + +void set_dram_timings_2ghz_8gb(void) +{ + set_dram_timings_2ghz_2gb(); + dram_timing.ddrc_cfg[2].val = 0xa3080020; + dram_timing.ddrc_cfg[5].val = 0x7a017c; + dram_timing.ddrc_cfg[23].val = 0x184; + dram_timing.ddrc_cfg[39].val = 0x18; + dram_timing.ddrc_cfg[46].val = 0xf07; + dram_timing.ddrc_cfg[62].val = 0xc0026; + dram_timing.ddrc_cfg[77].val = 0x27; + dram_timing.ddrc_cfg[87].val = 0x3000a; + dram_timing.ddrc_cfg[102].val = 0xa; + + dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310; + dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3; + dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3; +} diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.h b/board/phytec/phycore_imx8mp/lpddr4_timing.h new file mode 100644 index 00000000000..1c10e085a92 --- /dev/null +++ b/board/phytec/phycore_imx8mp/lpddr4_timing.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + */ + +#ifndef __LPDDR4_TIMING_H__ +#define __LPDDR4_TIMING_H__ + +void set_dram_timings_2ghz_2gb(void); +void set_dram_timings_2ghz_1gb(void); +void set_dram_timings_2ghz_4gb(void); +void set_dram_timings_1_5ghz_1gb(void); +void set_dram_timings_1_5ghz_4gb(void); +void set_dram_timings_2ghz_8gb(void); + +#endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c index 35683591433..ef951361844 100644 --- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c +++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c @@ -9,6 +9,7 @@ #include <asm/io.h> #include <asm/mach-imx/boot_mode.h> #include <env.h> +#include <init.h> #include <miiphy.h> DECLARE_GLOBAL_DATA_PTR; @@ -55,3 +56,13 @@ int board_late_init(void) return 0; } + +int board_phys_sdram_size(phys_size_t *size) +{ + if (!size) + return -EINVAL; + + *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE); + + return 0; +} diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 352f803e454..0610d8bbd0b 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -20,95 +20,103 @@ #include <power/pca9450.h> #include <spl.h> +#include "lpddr4_timing.h" #include "../common/imx8m_som_detection.h" DECLARE_GLOBAL_DATA_PTR; -#define EEPROM_ADDR 0x51 -#define EEPROM_ADDR_FALLBACK 0x59 +#define EEPROM_ADDR 0x51 +#define EEPROM_ADDR_FALLBACK 0x59 int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; } +enum phytec_imx8mp_ddr_eeprom_code { + PHYTEC_IMX8MP_DDR_1GB = 2, + PHYTEC_IMX8MP_DDR_2GB = 3, + PHYTEC_IMX8MP_DDR_4GB = 5, + PHYTEC_IMX8MP_DDR_8GB = 7, + PHYTEC_IMX8MP_DDR_4GB_2GHZ = 8, +}; + void spl_dram_init(void) { int ret; + bool use_2ghz_timings = false; + enum phytec_imx8mp_ddr_eeprom_code size = PHYTEC_EEPROM_INVAL; ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR, EEPROM_ADDR_FALLBACK); - if (ret) + if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX)) goto out; ret = phytec_imx8m_detect(NULL); if (!ret) phytec_print_som_info(NULL); - u8 rev = phytec_get_rev(NULL); - u8 somtype = phytec_get_som_type(NULL); - - if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) { - dram_timing.ddrc_cfg[3].val = 0x1323; - dram_timing.ddrc_cfg[4].val = 0x1e84800; - dram_timing.ddrc_cfg[5].val = 0x7a0118; - dram_timing.ddrc_cfg[8].val = 0xc00307a3; - dram_timing.ddrc_cfg[9].val = 0xc50000; - dram_timing.ddrc_cfg[10].val = 0xf4003f; - dram_timing.ddrc_cfg[11].val = 0xf30000; - dram_timing.ddrc_cfg[14].val = 0x2028222a; - dram_timing.ddrc_cfg[15].val = 0x8083f; - dram_timing.ddrc_cfg[16].val = 0xe0e000; - dram_timing.ddrc_cfg[17].val = 0x12040a12; - dram_timing.ddrc_cfg[18].val = 0x2050f0f; - dram_timing.ddrc_cfg[19].val = 0x1010009; - dram_timing.ddrc_cfg[20].val = 0x502; - dram_timing.ddrc_cfg[21].val = 0x20800; - dram_timing.ddrc_cfg[22].val = 0xe100002; - dram_timing.ddrc_cfg[23].val = 0x120; - dram_timing.ddrc_cfg[24].val = 0xc80064; - dram_timing.ddrc_cfg[25].val = 0x3e8001e; - dram_timing.ddrc_cfg[26].val = 0x3207a12; - dram_timing.ddrc_cfg[28].val = 0x4a3820e; - dram_timing.ddrc_cfg[30].val = 0x230e; - dram_timing.ddrc_cfg[37].val = 0x799; - dram_timing.ddrc_cfg[38].val = 0x9141d1c; - dram_timing.ddrc_cfg[74].val = 0x302; - dram_timing.ddrc_cfg[83].val = 0x599; - dram_timing.ddrc_cfg[99].val = 0x302; - dram_timing.ddrc_cfg[108].val = 0x599; - dram_timing.ddrphy_cfg[66].val = 0x18; - dram_timing.ddrphy_cfg[75].val = 0x1e3; - dram_timing.ddrphy_cfg[77].val = 0x1e3; - dram_timing.ddrphy_cfg[79].val = 0x1e3; - dram_timing.ddrphy_cfg[145].val = 0x3e8; - dram_timing.fsp_msg[0].drate = 4000; - dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0; - dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4; - dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3; - dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4; - dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3; - dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400; - dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f; - dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400; - dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f; - dram_timing.fsp_msg[3].drate = 4000; - dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0; - dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4; - dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3; - dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4; - dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3; - dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400; - dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f; - dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400; - dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f; - dram_timing.ddrphy_pie[480].val = 0x465; - dram_timing.ddrphy_pie[481].val = 0xfa; - dram_timing.ddrphy_pie[482].val = 0x9c4; - dram_timing.fsp_table[0] = 4000; + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_1GB)) + size = PHYTEC_IMX8MP_DDR_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_2GB)) + size = PHYTEC_IMX8MP_DDR_2GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_4GB)) + size = PHYTEC_IMX8MP_DDR_4GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_8GB)) + size = PHYTEC_IMX8MP_DDR_8GB; + } else { + size = phytec_get_imx8m_ddr_size(NULL); + } + + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_FREQ_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS)) { + if (size == PHYTEC_IMX8MP_DDR_4GB) + size = PHYTEC_IMX8MP_DDR_4GB_2GHZ; + else + use_2ghz_timings = true; + } else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS)) { + if (size == PHYTEC_IMX8MP_DDR_4GB_2GHZ) + size = PHYTEC_IMX8MP_DDR_4GB; + else + use_2ghz_timings = false; + } + } else { + u8 rev = phytec_get_rev(NULL); + u8 somtype = phytec_get_som_type(NULL); + + if (rev != PHYTEC_EEPROM_INVAL && + (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) + use_2ghz_timings = true; } + switch (size) { + case PHYTEC_IMX8MP_DDR_1GB: + if (use_2ghz_timings) + set_dram_timings_2ghz_1gb(); + else + set_dram_timings_1_5ghz_1gb(); + break; + case PHYTEC_IMX8MP_DDR_2GB: + if (use_2ghz_timings) + set_dram_timings_2ghz_2gb(); + break; + case PHYTEC_IMX8MP_DDR_4GB: + set_dram_timings_1_5ghz_4gb(); + break; + case PHYTEC_IMX8MP_DDR_4GB_2GHZ: + set_dram_timings_2ghz_4gb(); + break; + case PHYTEC_IMX8MP_DDR_8GB: + set_dram_timings_2ghz_8gb(); + break; + default: + goto out; + } + ddr_init(&dram_timing); + return; out: + printf("Could not detect correct RAM size. Fallback to default.\n"); ddr_init(&dram_timing); } diff --git a/board/powkiddy/x55/Kconfig b/board/powkiddy/x55/Kconfig new file mode 100644 index 00000000000..a7b3ed4d0d9 --- /dev/null +++ b/board/powkiddy/x55/Kconfig @@ -0,0 +1,15 @@ +if TARGET_POWKIDDY_X55_RK3566 + +config SYS_BOARD + default "x55" + +config SYS_VENDOR + default "powkiddy" + +config SYS_CONFIG_NAME + default "powkiddy-x55-rk3566" + +config BOARD_SPECIFIC_OPTIONS + def_bool y + +endif diff --git a/board/powkiddy/x55/MAINTAINERS b/board/powkiddy/x55/MAINTAINERS new file mode 100644 index 00000000000..01ae8da19d9 --- /dev/null +++ b/board/powkiddy/x55/MAINTAINERS @@ -0,0 +1,7 @@ +X55 +M: Chris Morgan <macromorgan@hotmail.com> +S: Maintained +F: board/powkiddy/x55 +F: include/configs/powkiddy-x55-rk3566.h +F: configs/powkiddy-x55-rk3566_defconfig +F: arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi diff --git a/board/powkiddy/x55/Makefile b/board/powkiddy/x55/Makefile new file mode 100644 index 00000000000..55c8c16aa17 --- /dev/null +++ b/board/powkiddy/x55/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2023 Chris Morgan <macromorgan@hotmail.com> +# + +obj-y += x55.o diff --git a/board/powkiddy/x55/x55.c b/board/powkiddy/x55/x55.c new file mode 100644 index 00000000000..b2703e6382d --- /dev/null +++ b/board/powkiddy/x55/x55.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023 Chris Morgan <macromorgan@hotmail.com> + */ + +#include <asm/io.h> + +#define GPIO4_BASE 0xfe770000 +#define GPIO_SWPORT_DR_L 0x0000 +#define GPIO_SWPORT_DDR_L 0x0008 +#define GPIO_B4 BIT(12) +#define GPIO_B5 BIT(13) +#define GPIO_B6 BIT(14) + +#define GPIO_WRITEMASK(bits) ((bits) << 16) + +/* + * Start LED very early so user knows device is on. Set color + * to red. + */ +void spl_board_init(void) +{ + /* Set GPIO4_B4, GPIO4_B5, and GPIO4_B6 to output. */ + writel(GPIO_WRITEMASK(GPIO_B6 | GPIO_B5 | GPIO_B4) | \ + (GPIO_B6 | GPIO_B5 | GPIO_B4), + (GPIO4_BASE + GPIO_SWPORT_DDR_L)); + /* Set GPIO4_B5 and GPIO4_B6 to 0 and GPIO4_B4 to 1. */ + writel(GPIO_WRITEMASK(GPIO_B6 | GPIO_B5 | GPIO_B4) | GPIO_B4, + (GPIO4_BASE + GPIO_SWPORT_DR_L)); +} + +int rk_board_late_init(void) +{ + /* Turn off red LED and turn on orange LED. */ + writel(GPIO_WRITEMASK(GPIO_B6 | GPIO_B5 | GPIO_B4) | GPIO_B6, + (GPIO4_BASE + GPIO_SWPORT_DR_L)); + + return 0; +} diff --git a/board/qualcomm/default.env b/board/qualcomm/default.env new file mode 100644 index 00000000000..dbf6f4e7260 --- /dev/null +++ b/board/qualcomm/default.env @@ -0,0 +1,11 @@ +stdin=serial,button-kbd +stdout=serial,vidconsole +stderr=serial,vidconsole +preboot=scsi scan; usb start +fastboot=fastboot -l $fastboot_addr_r usb 0 +do_boot=bootefi bootmgr +bootmenu_0=Boot first available device=run do_boot +bootmenu_1=Enable fastboot mode=run fastboot +bootmenu_2=Reset device=reset +menucmd=bootmenu +bootcmd=run do_boot diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index d996eb0cf69..ab5ea85cf9f 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -381,7 +381,7 @@ static void set_board_info(void) snprintf(s, sizeof(s), "0x%X", revision); env_set("board_revision", s); - snprintf(s, sizeof(s), "%d", rev_scheme); + snprintf(s, sizeof(s), "%u", rev_scheme); env_set("board_rev_scheme", s); /* Can't rename this to board_rev_type since it's an ABI for scripts */ snprintf(s, sizeof(s), "0x%X", rev_type); @@ -493,10 +493,6 @@ static void get_board_revision(void) int board_init(void) { -#ifdef CONFIG_HW_WATCHDOG - hw_watchdog_init(); -#endif - get_board_revision(); gd->bd->bi_boot_params = 0x100; diff --git a/board/samsung/common/exynos-uboot-spl.lds b/board/samsung/common/exynos-uboot-spl.lds index 73cd97a1b1d..9d3b57e98db 100644 --- a/board/samsung/common/exynos-uboot-spl.lds +++ b/board/samsung/common/exynos-uboot-spl.lds @@ -41,11 +41,7 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - - .end : - { - *(.__end) - } >.sram + _end = .; .bss : { diff --git a/board/samsung/e850-96/MAINTAINERS b/board/samsung/e850-96/MAINTAINERS index e8b9365eea8..b0987943fa4 100644 --- a/board/samsung/e850-96/MAINTAINERS +++ b/board/samsung/e850-96/MAINTAINERS @@ -2,7 +2,6 @@ WINLINK E850-96 BOARD M: Sam Protsenko <semen.protsenko@linaro.org> S: Maintained F: arch/arm/dts/exynos850-e850-96-u-boot.dtsi -F: arch/arm/dts/exynos850-e850-96.dts F: board/samsung/e850-96/ F: configs/e850-96_defconfig F: doc/board/samsung/e850-96.rst diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index b555189556a..b794b73b6bd 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -86,6 +86,43 @@ static const struct starfive_vf2_pro starfive_verb[] = { "tx-internal-delay-ps", "0"}, }; +static const struct starfive_vf2_pro star64_pine64[] = { + {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL}, + {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL}, + + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,tx-clk-adj-enabled", NULL}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,tx-clk-10-inverted", NULL}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,tx-clk-100-inverted", NULL}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,tx-clk-1000-inverted", NULL}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,rx-clk-drv-microamp", "2910"}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,rx-data-drv-microamp", "2910"}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "rx-internal-delay-ps", "1900"}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "tx-internal-delay-ps", "1500"}, + + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "motorcomm,tx-clk-adj-enabled", NULL}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "motorcomm,tx-clk-10-inverted", NULL}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "motorcomm,tx-clk-100-inverted", NULL}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "motorcomm,rx-clk-drv-microamp", "2910"}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "motorcomm,rx-data-drv-microamp", "2910"}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "rx-internal-delay-ps", "0"}, + {"/soc/ethernet@16040000/mdio/ethernet-phy@1", + "tx-internal-delay-ps", "300"}, +}; + void spl_fdt_fixup_mars(void *fdt) { static const char compat[] = "milkv,mars\0starfive,jh7110"; @@ -250,6 +287,56 @@ void spl_fdt_fixup_version_b(void *fdt) } } +void spl_fdt_fixup_star64(void *fdt) +{ + static const char compat[] = "pine64,star64\0starfive,jh7110"; + u32 phandle; + u8 i; + int offset; + int ret; + + fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); + fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", + "Pine64 Star64"); + + /* gmac0 */ + offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000"); + phandle = fdt_get_phandle(fdt, offset); + offset = fdt_path_offset(fdt, "/soc/ethernet@16030000"); + + fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX); + fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", + JH7110_AONCLK_GMAC0_RMII_RTX); + + /* gmac1 */ + offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000"); + phandle = fdt_get_phandle(fdt, offset); + offset = fdt_path_offset(fdt, "/soc/ethernet@16040000"); + + fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX); + fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", + JH7110_SYSCLK_GMAC1_RMII_RTX); + + for (i = 0; i < ARRAY_SIZE(star64_pine64); i++) { + offset = fdt_path_offset(fdt, star64_pine64[i].path); + + if (star64_pine64[i].value) + ret = fdt_setprop_u32(fdt, offset, star64_pine64[i].name, + dectoul(star64_pine64[i].value, NULL)); + else + ret = fdt_setprop_empty(fdt, offset, star64_pine64[i].name); + + if (ret) { + pr_err("%s set prop %s fail.\n", __func__, star64_pine64[i].name); + break; + } + } +} + void spl_perform_fixups(struct spl_image_info *spl_image) { u8 version; @@ -278,6 +365,8 @@ void spl_perform_fixups(struct spl_image_info *spl_image) spl_fdt_fixup_version_b(spl_image->fdt_addr); break; }; + } else if (!strncmp(product_id, "STAR64", 6)) { + spl_fdt_fixup_star64(spl_image->fdt_addr); } else { pr_err("Unknown product %s\n", product_id); }; diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c index 6be53489626..f6114602f88 100644 --- a/board/starfive/visionfive2/starfive_visionfive2.c +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -27,6 +27,8 @@ DECLARE_GLOBAL_DATA_PTR; "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb" #define FDTFILE_VISIONFIVE2_1_3B \ "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb" +#define FDTFILE_PINE64_STAR64 \ + "starfive/jh7110-pine64-star64.dtb" /* enable U74-mc hart1~hart4 prefetcher */ static void enable_prefetcher(void) @@ -87,6 +89,8 @@ static void set_fdtfile(void) fdtfile = FDTFILE_VISIONFIVE2_1_3B; break; } + } else if (!strncmp(product_id, "STAR64", 6)) { + fdtfile = FDTFILE_PINE64_STAR64; } else { log_err("Unknown product\n"); return; diff --git a/board/theobroma-systems/jaguar_rk3588/MAINTAINERS b/board/theobroma-systems/jaguar_rk3588/MAINTAINERS index 28fae4b479f..ab7051b427f 100644 --- a/board/theobroma-systems/jaguar_rk3588/MAINTAINERS +++ b/board/theobroma-systems/jaguar_rk3588/MAINTAINERS @@ -1,6 +1,6 @@ JAGUAR-RK3588 (SBC-RK3588-AMR Single Board Computer) -M: Klaus Goger <klaus.goger@theobroma-systems.com> -M: Quentin Schulz <quentin.schulz@theobroma-systems.com> +M: Klaus Goger <klaus.goger@cherry.de> +M: Quentin Schulz <quentin.schulz@cherry.de> M: Heiko Stuebner <heiko.stuebner@cherry.de> S: Maintained F: board/theobroma-systems/jaguar_rk3588 @@ -9,5 +9,5 @@ F: doc/board/theobroma-systems/ F: include/configs/jaguar_rk3588.h F: arch/arm/dts/rk3588-jaguar* F: configs/jaguar-rk3588_defconfig -W: https://theobroma-systems.com/product/jaguar-sbc-rk3588/ -T: git git://git.theobroma-systems.com/jaguar-u-boot.git +W: https://embedded.cherry.de/product/jaguar-sbc-rk3588/ +T: git git://git.embedded.cherry.de/jaguar-u-boot.git diff --git a/board/theobroma-systems/lion_rk3368/MAINTAINERS b/board/theobroma-systems/lion_rk3368/MAINTAINERS index a5b4cb31b4a..ed35fee6468 100644 --- a/board/theobroma-systems/lion_rk3368/MAINTAINERS +++ b/board/theobroma-systems/lion_rk3368/MAINTAINERS @@ -1,6 +1,6 @@ LION-RK3368 (RK3368-uQ7 system-on-module) -M: Quentin Schulz <quentin.schulz@theobroma-systems.com> -M: Klaus Goger <klaus.goger@theobroma-systems.com> +M: Quentin Schulz <quentin.schulz@cherry.de> +M: Klaus Goger <klaus.goger@cherry.de> S: Maintained F: board/theobroma-systems/lion_rk3368 F: include/configs/lion_rk3368.h diff --git a/board/theobroma-systems/puma_rk3399/MAINTAINERS b/board/theobroma-systems/puma_rk3399/MAINTAINERS index 7e84a5be262..2536e348887 100644 --- a/board/theobroma-systems/puma_rk3399/MAINTAINERS +++ b/board/theobroma-systems/puma_rk3399/MAINTAINERS @@ -1,6 +1,6 @@ PUMA-RK3399 -M: Quentin Schulz <quentin.schulz@theobroma-systems.com> -M: Klaus Goger <klaus.goger@theobroma-systems.com> +M: Quentin Schulz <quentin.schulz@cherry.de> +M: Klaus Goger <klaus.goger@cherry.de> S: Maintained F: board/theobroma-systems/puma_rk3399 F: board/theobroma-systems/common @@ -8,5 +8,5 @@ F: doc/board/theobroma-systems F: include/configs/puma_rk3399.h F: arch/arm/dts/rk3399-puma* F: configs/puma-rk3399_defconfig -W: https://www.theobroma-systems.com/rk3399-q7/tech-specs -T: git git://git.theobroma-systems.com/puma-u-boot.git +W: https://embedded.cherry.de/product/puma-som-rk3399-q7/ +T: git git://git.embedded.cherry.de/puma-u-boot.git diff --git a/board/theobroma-systems/ringneck_px30/MAINTAINERS b/board/theobroma-systems/ringneck_px30/MAINTAINERS index 97baf334d02..2aff91f4207 100644 --- a/board/theobroma-systems/ringneck_px30/MAINTAINERS +++ b/board/theobroma-systems/ringneck_px30/MAINTAINERS @@ -1,6 +1,6 @@ RINGNECK-PX30 -M: Quentin Schulz <quentin.schulz@theobroma-systems.com> -M: Klaus Goger <klaus.goger@theobroma-systems.com> +M: Quentin Schulz <quentin.schulz@cherry.de> +M: Klaus Goger <klaus.goger@cherry.de> S: Maintained F: board/theobroma-systems/ringneck_px30 F: board/theobroma-systems/common @@ -8,4 +8,5 @@ F: doc/board/theobroma-systems/ F: include/configs/ringneck_px30.h F: arch/arm/dts/px30-ringneck* F: configs/ringneck-px30_defconfig -W: https://theobroma-systems.com/product/ringneck-som-px30-uq7/ +W: https://embedded.cherry.de/product/ringneck-som-px30-uq7/ +T: git git://git.embedded.cherry.de/ringneck-u-boot.git diff --git a/board/theobroma-systems/tiger_rk3588/Kconfig b/board/theobroma-systems/tiger_rk3588/Kconfig new file mode 100644 index 00000000000..2c6ac6a9a83 --- /dev/null +++ b/board/theobroma-systems/tiger_rk3588/Kconfig @@ -0,0 +1,16 @@ +if TARGET_TIGER_RK3588 + +config SYS_BOARD + default "tiger_rk3588" + +config SYS_VENDOR + default "theobroma-systems" + +config SYS_CONFIG_NAME + default "tiger_rk3588" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ENV_IS_NOWHERE + +endif diff --git a/board/theobroma-systems/tiger_rk3588/MAINTAINERS b/board/theobroma-systems/tiger_rk3588/MAINTAINERS new file mode 100644 index 00000000000..e5aab4b29f3 --- /dev/null +++ b/board/theobroma-systems/tiger_rk3588/MAINTAINERS @@ -0,0 +1,13 @@ +TIGER-RK3588 (SOM-RK3588-Q7) +M: Klaus Goger <klaus.goger@cherry.de> +M: Quentin Schulz <quentin.schulz@cherry.de> +M: Heiko Stuebner <heiko.stuebner@cherry.de> +S: Maintained +F: board/theobroma-systems/tiger_rk3588 +F: board/theobroma-systems/common +F: doc/board/theobroma-systems/ +F: include/configs/tiger_rk3588.h +F: arch/arm/dts/rk3588-tiger* +F: configs/tiger-rk3588_defconfig +W: https://embedded.cherry.de/product/tiger-som-rk3588-q7/ +T: git git://git.embedded.cherry.de/tiger-u-boot.git diff --git a/board/theobroma-systems/tiger_rk3588/Makefile b/board/theobroma-systems/tiger_rk3588/Makefile new file mode 100644 index 00000000000..5c4c484657a --- /dev/null +++ b/board/theobroma-systems/tiger_rk3588/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += tiger_rk3588.o +ifneq ($(CONFIG_SPL_BUILD),y) +obj-y += ../common/common.o +endif diff --git a/board/theobroma-systems/tiger_rk3588/tiger_rk3588.c b/board/theobroma-systems/tiger_rk3588/tiger_rk3588.c new file mode 100644 index 00000000000..a6d44f10db3 --- /dev/null +++ b/board/theobroma-systems/tiger_rk3588/tiger_rk3588.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 Theobroma Systems Design und Consulting GmbH + */ + +#include <phy.h> +#include <eth_phy.h> + +#include <asm/types.h> +#include <asm/arch-rockchip/cru_rk3588.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/ioc_rk3588.h> +#include <asm-generic/u-boot.h> +#include <dm/device.h> +#include <dm/uclass-id.h> +#include <linux/bitfield.h> + +#include "../common/common.h" + +#define GPIO2C3_SEL_MASK GENMASK(15, 12) +#define GPIO2C3_ETH0_REFCLKO_25M FIELD_PREP(GPIO2C3_SEL_MASK, 1) + +#define REFCLKO25M_ETH0_OUT_SEL_MASK BIT(15) +#define REFCLKO25M_ETH0_OUT_SEL_CPLL FIELD_PREP(REFCLKO25M_ETH0_OUT_SEL_MASK, 1) +#define REFCLKO25M_ETH0_OUT_DIV_MASK GENMASK(14, 8) +#define REFCLKO25M_ETH0_OUT_DIV(x) FIELD_PREP(REFCLKO25M_ETH0_OUT_DIV_MASK, (x) - 1) + +#define REFCLKO25M_ETH0_OUT_EN BIT(4) + +void setup_eth0refclko(void) +{ + /* Configure and enable ETH0_REFCLKO_25MHz */ + static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE; + static struct rk3588_cru * const cru = (void *)CRU_BASE; + + /* 1. Pinmux */ + rk_clrsetreg(&bus_ioc->gpio2c_iomux_sel_l, GPIO2C3_SEL_MASK, GPIO2C3_ETH0_REFCLKO_25M); + /* 2. Parent clock selection + divider => CPLL (1.5GHz) / 60 => 25MHz */ + rk_clrsetreg(&cru->clksel_con[15], + REFCLKO25M_ETH0_OUT_SEL_MASK | REFCLKO25M_ETH0_OUT_DIV_MASK, + REFCLKO25M_ETH0_OUT_SEL_CPLL | REFCLKO25M_ETH0_OUT_DIV(60)); + /* 3. Enable clock */ + rk_clrreg(&cru->clkgate_con[5], REFCLKO25M_ETH0_OUT_EN); +} + +int rockchip_early_misc_init_r(void) +{ + setup_boottargets(); + + setup_eth0refclko(); + + return 0; +} diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS index 219c8715bf1..ed8800a2663 100644 --- a/board/ti/am335x/MAINTAINERS +++ b/board/ti/am335x/MAINTAINERS @@ -3,6 +3,5 @@ M: Tom Rini <trini@konsulko.com> S: Maintained F: board/ti/am335x/ F: include/configs/am335x_evm.h -F: configs/am335x_boneblack_vboot_defconfig F: configs/am335x_evm_defconfig F: configs/am335x_evm_spiboot_defconfig diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c index 97a95ce8cc2..1a2c46c462b 100644 --- a/board/ti/am62px/evm.c +++ b/board/ti/am62px/evm.c @@ -6,6 +6,7 @@ * */ +#include <efi_loader.h> #include <asm/arch/hardware.h> #include <asm/io.h> #include <dm/uclass.h> @@ -13,6 +14,39 @@ #include <fdt_support.h> #include <spl.h> +struct efi_fw_image fw_images[] = { + { + .image_type_id = AM62PX_SK_TIBOOT3_IMAGE_GUID, + .fw_name = u"AM62PX_SK_TIBOOT3", + .image_index = 1, + }, + { + .image_type_id = AM62PX_SK_SPL_IMAGE_GUID, + .fw_name = u"AM62PX_SK_SPL", + .image_index = 2, + }, + { + .image_type_id = AM62PX_SK_UBOOT_IMAGE_GUID, + .fw_name = u"AM62PX_SK_UBOOT", + .image_index = 3, + } +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "sf 0:0=tiboot3.bin raw 0 80000;" + "tispl.bin raw 80000 200000;u-boot.img raw 280000 400000", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; + +#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO) +void set_dfu_alt_info(char *interface, char *devstr) +{ + if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)) + env_set("dfu_alt_info", update_info.dfu_string); +} +#endif + int board_init(void) { return 0; diff --git a/board/ti/am62x/MAINTAINERS b/board/ti/am62x/MAINTAINERS index 105e741995e..562a5c67669 100644 --- a/board/ti/am62x/MAINTAINERS +++ b/board/ti/am62x/MAINTAINERS @@ -1,8 +1,10 @@ AM62x BOARD -M: Dave Gerlach <d-gerlach@ti.com> +M: Bryan Brattlof <bb@ti.com> M: Tom Rini <trini@konsulko.com> S: Maintained F: board/ti/am62x/ F: include/configs/am62x_evm.h F: configs/am62x_evm_r5_defconfig F: configs/am62x_evm_a53_defconfig +F: configs/am62x_lpsk_r5_defconfig +F: configs/am62x_lpsk_a53_defconfig diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index b3e8680dfab..9bdd0223cdb 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -7,6 +7,7 @@ * */ +#include <efi_loader.h> #include <env.h> #include <spl.h> #include <init.h> @@ -46,6 +47,39 @@ int splash_screen_prepare(void) } #endif +struct efi_fw_image fw_images[] = { + { + .image_type_id = AM62X_SK_TIBOOT3_IMAGE_GUID, + .fw_name = u"AM62X_SK_TIBOOT3", + .image_index = 1, + }, + { + .image_type_id = AM62X_SK_SPL_IMAGE_GUID, + .fw_name = u"AM62X_SK_SPL", + .image_index = 2, + }, + { + .image_type_id = AM62X_SK_UBOOT_IMAGE_GUID, + .fw_name = u"AM62X_SK_UBOOT", + .image_index = 3, + } +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "sf 0:0=tiboot3.bin raw 0 80000;" + "tispl.bin raw 80000 200000;u-boot.img raw 280000 400000", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; + +#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO) +void set_dfu_alt_info(char *interface, char *devstr) +{ + if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)) + env_set("dfu_alt_info", update_info.dfu_string); +} +#endif + int board_init(void) { return 0; diff --git a/board/ti/am64x/am64x.env b/board/ti/am64x/am64x.env index 9a8812d4ee5..8ad805a613c 100644 --- a/board/ti/am64x/am64x.env +++ b/board/ti/am64x/am64x.env @@ -39,3 +39,8 @@ usbboot=setenv boot usb; run get_kern_usb; run get_fdt_usb; run run_kern; + +#if CONFIG_TI_ICSSG_PRUETH +storage_interface=mmc +fw_dev_part=1:2 +#endif diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index b8de69da06c..609e5cf6d51 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -7,6 +7,7 @@ * */ +#include <efi_loader.h> #include <asm/io.h> #include <dm/uclass.h> #include <k3-ddrss.h> @@ -27,6 +28,39 @@ DECLARE_GLOBAL_DATA_PTR; +struct efi_fw_image fw_images[] = { + { + .image_type_id = AM64X_SK_TIBOOT3_IMAGE_GUID, + .fw_name = u"AM64X_SK_TIBOOT3", + .image_index = 1, + }, + { + .image_type_id = AM64X_SK_SPL_IMAGE_GUID, + .fw_name = u"AM64X_SK_SPL", + .image_index = 2, + }, + { + .image_type_id = AM64X_SK_UBOOT_IMAGE_GUID, + .fw_name = u"AM64X_SK_UBOOT", + .image_index = 3, + } +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "sf 0:0=tiboot3.bin raw 0 100000;" + "tispl.bin raw 100000 200000;u-boot.img raw 300000 400000", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; + +#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO) +void set_dfu_alt_info(char *interface, char *devstr) +{ + if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)) + env_set("dfu_alt_info", update_info.dfu_string); +} +#endif + int board_init(void) { return 0; diff --git a/board/ti/common/fdt_ops.c b/board/ti/common/fdt_ops.c index eb917be9e0d..8a3300993ed 100644 --- a/board/ti/common/fdt_ops.c +++ b/board/ti/common/fdt_ops.c @@ -6,7 +6,7 @@ */ #include <env.h> -#include <vsprintf.h> +#include <stdio.h> #include "fdt_ops.h" void ti_set_fdt_env(const char *board_name, struct ti_fdt_map *fdt_map) diff --git a/board/ti/j721e/MAINTAINERS b/board/ti/j721e/MAINTAINERS index f5ca7d06a34..06aba53d9b0 100644 --- a/board/ti/j721e/MAINTAINERS +++ b/board/ti/j721e/MAINTAINERS @@ -5,5 +5,7 @@ F: board/ti/j721e F: include/configs/j721e_evm.h F: configs/j721e_evm_r5_defconfig F: configs/j721e_evm_a72_defconfig +F: configs/j721e_sk_r5_defconfig +F: configs/j721e_sk_a72_defconfig F: configs/j7200_evm_r5_defconfig F: configs/j7200_evm_a72_defconfig diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index 539eaf47186..f3452ff0a8f 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -7,6 +7,7 @@ * */ +#include <efi_loader.h> #include <generic-phy.h> #include <image.h> #include <net.h> @@ -32,6 +33,45 @@ DECLARE_GLOBAL_DATA_PTR; +struct efi_fw_image fw_images[] = { + { + .image_type_id = J721E_SK_TIBOOT3_IMAGE_GUID, + .fw_name = u"J721E_SK_TIBOOT3", + .image_index = 1, + }, + { + .image_type_id = J721E_SK_SPL_IMAGE_GUID, + .fw_name = u"J721E_SK_SPL", + .image_index = 2, + }, + { + .image_type_id = J721E_SK_UBOOT_IMAGE_GUID, + .fw_name = u"J721E_SK_UBOOT", + .image_index = 3, + }, + { + .image_type_id = J721E_SK_SYSFW_IMAGE_GUID, + .fw_name = u"J721E_SK_SYSFW", + .image_index = 4, + } +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "sf 0:0=tiboot3.bin raw 0 80000;" + "tispl.bin raw 80000 200000;u-boot.img raw 280000 400000;" + "sysfw.itb raw 6C0000 100000", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; + +#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO) +void set_dfu_alt_info(char *interface, char *devstr) +{ + if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)) + env_set("dfu_alt_info", update_info.dfu_string); +} +#endif + int board_init(void) { return 0; diff --git a/board/ti/j722s/Kconfig b/board/ti/j722s/Kconfig new file mode 100644 index 00000000000..68c214e473b --- /dev/null +++ b/board/ti/j722s/Kconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# + +if TARGET_J722S_R5_EVM || TARGET_J722S_A53_EVM + +config SYS_BOARD + default "j722s" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "j722s_evm" + +source "board/ti/common/Kconfig" + +endif + +if TARGET_J722S_R5_EVM + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +endif diff --git a/board/ti/j722s/MAINTAINERS b/board/ti/j722s/MAINTAINERS new file mode 100644 index 00000000000..7908c30def2 --- /dev/null +++ b/board/ti/j722s/MAINTAINERS @@ -0,0 +1,9 @@ +J722S BOARD +M: Vaishnav Achath <vaishnav.a@ti.com> +M: Jayesh Choudhary <j-choudhary@ti.com> +M: Tom Rini <trini@konsulko.com> +S: Maintained +F: board/ti/j722s/ +F: include/configs/j722s_evm.h +F: configs/j722s_evm_r5_defconfig +F: configs/j722s_evm_a53_defconfig diff --git a/board/ti/j722s/Makefile b/board/ti/j722s/Makefile new file mode 100644 index 00000000000..20d2ec934b1 --- /dev/null +++ b/board/ti/j722s/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evm.o diff --git a/board/ti/j722s/board-cfg.yaml b/board/ti/j722s/board-cfg.yaml new file mode 100644 index 00000000000..f9a4c438ca9 --- /dev/null +++ b/board/ti/j722s/board-cfg.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for J722S +# + +--- + +board-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable: 0x5A + main_isolation_hostid: 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor: 0x1 + scaling_profile: 0x1 + disable_main_nav_secure_proxy: 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size: 0x0 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables: 0x00 + trace_src_enables: 0x00 diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c new file mode 100644 index 00000000000..515aaa81878 --- /dev/null +++ b/board/ti/j722s/evm.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board specific initialization for J722S platforms + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#include <asm/arch/hardware.h> +#include <asm/io.h> +#include <dm/uclass.h> +#include <env.h> +#include <fdt_support.h> +#include <spl.h> + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} diff --git a/board/ti/j722s/j722s.env b/board/ti/j722s/j722s.env new file mode 100644 index 00000000000..f8b6aff2c2f --- /dev/null +++ b/board/ti/j722s/j722s.env @@ -0,0 +1,15 @@ +#include <env/ti/ti_common.env> +#include <env/ti/mmc.env> + +name_kern=Image +console=ttyS2,115200n8 +args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000 + ${mtdparts} +run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr} + +boot_targets=mmc1 mmc0 pxe dhcp +boot=mmc +mmcdev=1 +bootpart=1:2 +bootdir=/boot +rd_spec=- diff --git a/board/ti/j722s/pm-cfg.yaml b/board/ti/j722s/pm-cfg.yaml new file mode 100644 index 00000000000..46b3ad20109 --- /dev/null +++ b/board/ti/j722s/pm-cfg.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for J722S +# + +--- + +pm-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 diff --git a/board/ti/j722s/rm-cfg.yaml b/board/ti/j722s/rm-cfg.yaml new file mode 100644 index 00000000000..21ca30104c7 --- /dev/null +++ b/board/ti/j722s/rm-cfg.yaml @@ -0,0 +1,1119 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for J722S +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size: 356 + host_cfg_entries: + - + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - + host_id: 20 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - + host_id: 22 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - + host_id: 38 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + 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0 diff --git a/board/ti/j722s/sec-cfg.yaml b/board/ti/j722s/sec-cfg.yaml new file mode 100644 index 00000000000..a41374b30c9 --- /dev/null +++ b/board/ti/j722s/sec-cfg.yaml @@ -0,0 +1,379 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# +# Security management configuration for J722S +# + +--- + +sec-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + supervisor_host_id: 0 + - + host_id: 0 + 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host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + - + host_id: 0 + host_perms: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci: 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size: 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0x5A + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock: 0x5A + allow_wildcard_unlock: 0x5A + allowed_debug_level_rsvd: 0 + rsvd: 0 + min_cert_rev: 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender: 0 + handover_to_host_id: 0 + rsvd: [0, 0, 0, 0] diff --git a/board/ti/j722s/tifs-rm-cfg.yaml b/board/ti/j722s/tifs-rm-cfg.yaml new file mode 100644 index 00000000000..5e8d7e04441 --- /dev/null +++ b/board/ti/j722s/tifs-rm-cfg.yaml @@ -0,0 +1,981 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for J722S +# + +--- + +tifs-rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size: 356 + host_cfg_entries: + - #1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #2 + host_id: 20 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #3 + host_id: 22 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #4 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #5 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #6 + host_id: 38 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #32 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + resasg: + subhdr: + magic: 0x7B25 + size: 8 + resasg_entries_size: 976 + reserved: 0 + resasg_entries: + - + start_resource: 0 + num_resource: 16 + type: 1677 + host_id: 12 + reserved: 0 + - + start_resource: 16 + num_resource: 6 + type: 1677 + host_id: 20 + reserved: 0 + - + start_resource: 16 + num_resource: 6 + type: 1677 + host_id: 36 + reserved: 0 + - + start_resource: 22 + num_resource: 2 + type: 1677 + host_id: 30 + reserved: 0 + - + start_resource: 24 + num_resource: 4 + type: 1677 + host_id: 22 + reserved: 0 + - + start_resource: 28 + num_resource: 4 + type: 1677 + host_id: 38 + reserved: 0 + - + start_resource: 57 + num_resource: 16 + type: 1678 + host_id: 12 + reserved: 0 + - + start_resource: 73 + num_resource: 5 + type: 1678 + host_id: 20 + reserved: 0 + - + start_resource: 73 + num_resource: 5 + type: 1678 + host_id: 36 + reserved: 0 + - + start_resource: 78 + num_resource: 2 + type: 1678 + host_id: 30 + reserved: 0 + - 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host_id: 38 + reserved: 0 + - + start_resource: 1536 + num_resource: 8 + type: 12823 + host_id: 128 + reserved: 0 + - + start_resource: 2048 + num_resource: 8 + type: 12824 + host_id: 128 + reserved: 0 + - + start_resource: 2560 + num_resource: 8 + type: 12825 + host_id: 128 + reserved: 0 + - + start_resource: 3072 + num_resource: 32 + type: 12826 + host_id: 128 + reserved: 0 + - + start_resource: 3584 + num_resource: 32 + type: 12827 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 32 + type: 12828 + host_id: 128 + reserved: 0 diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c index aed0ea5b949..548dbd5925d 100644 --- a/board/ti/j784s4/evm.c +++ b/board/ti/j784s4/evm.c @@ -7,12 +7,46 @@ * */ +#include <efi_loader.h> #include <init.h> #include <spl.h> #include "../common/fdt_ops.h" DECLARE_GLOBAL_DATA_PTR; +struct efi_fw_image fw_images[] = { + { + .image_type_id = AM69_SK_TIBOOT3_IMAGE_GUID, + .fw_name = u"AM69_SK_TIBOOT3", + .image_index = 1, + }, + { + .image_type_id = AM69_SK_SPL_IMAGE_GUID, + .fw_name = u"AM69_SK_SPL", + .image_index = 2, + }, + { + .image_type_id = AM69_SK_UBOOT_IMAGE_GUID, + .fw_name = u"AM69_SK_UBOOT", + .image_index = 3, + } +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "sf 0:0=tiboot3.bin raw 0 80000;" + "tispl.bin raw 80000 200000;u-boot.img raw 280000 400000", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; + +#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO) +void set_dfu_alt_info(char *interface, char *devstr) +{ + if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)) + env_set("dfu_alt_info", update_info.dfu_string); +} +#endif + int board_init(void) { return 0; diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env index 7e54ca042ef..f5b72c7505e 100644 --- a/board/ti/j784s4/j784s4.env +++ b/board/ti/j784s4/j784s4.env @@ -3,6 +3,10 @@ #include <env/ti/ufs.env> #include <env/ti/k3_dfu.env> +#if CONFIG_CMD_REMOTEPROC +#include <env/ti/k3_rproc.env> +#endif + name_kern=Image console=ttyS2,115200n8 args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02880000 @@ -15,3 +19,5 @@ mmcdev=1 bootpart=1:2 bootdir=/boot rd_spec=- + +rproc_fw_binaries= 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw diff --git a/board/toradex/apalis-imx8/MAINTAINERS b/board/toradex/apalis-imx8/MAINTAINERS index 198399c879a..761034a516a 100644 --- a/board/toradex/apalis-imx8/MAINTAINERS +++ b/board/toradex/apalis-imx8/MAINTAINERS @@ -1,5 +1,5 @@ Apalis iMX8 -M: Marcel Ziswiler <marcel.ziswiler@toradex.com> +M: Francesco Dolcini <francesco.dolcini@toradex.com> W: http://developer.toradex.com/software/linux/linux-software S: Maintained F: arch/arm/dts/fsl-imx8qm-apalis.dts diff --git a/board/toradex/apalis-tk1/MAINTAINERS b/board/toradex/apalis-tk1/MAINTAINERS index e2c6f63dcc7..393c8dcf801 100644 --- a/board/toradex/apalis-tk1/MAINTAINERS +++ b/board/toradex/apalis-tk1/MAINTAINERS @@ -1,5 +1,5 @@ Apalis TK1 -M: Marcel Ziswiler <marcel.ziswiler@toradex.com> +M: Francesco Dolcini <francesco.dolcini@toradex.com> S: Maintained F: board/toradex/apalis-tk1/ F: board/toradex/common/ diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS index 0b2907bbe70..d84527c0678 100644 --- a/board/toradex/apalis_imx6/MAINTAINERS +++ b/board/toradex/apalis_imx6/MAINTAINERS @@ -1,5 +1,5 @@ Apalis iMX6 -M: Marcel Ziswiler <marcel.ziswiler@toradex.com> +M: Francesco Dolcini <francesco.dolcini@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/apalis_t30/MAINTAINERS b/board/toradex/apalis_t30/MAINTAINERS index 097db7deb08..368decf6674 100644 --- a/board/toradex/apalis_t30/MAINTAINERS +++ b/board/toradex/apalis_t30/MAINTAINERS @@ -1,5 +1,5 @@ Apalis T30 -M: Marcel Ziswiler <marcel.ziswiler@toradex.com> +M: Francesco Dolcini <francesco.dolcini@toradex.com> S: Maintained F: board/toradex/apalis_t30/ F: board/toradex/common/ diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS index ee6fe6c13ea..6c93e35cc65 100644 --- a/board/toradex/colibri-imx6ull/MAINTAINERS +++ b/board/toradex/colibri-imx6ull/MAINTAINERS @@ -1,5 +1,5 @@ Colibri iMX6ULL -M: Marcel Ziswiler <marcel.ziswiler@toradex.com> +M: Francesco Dolcini <francesco.dolcini@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri-imx8x/MAINTAINERS b/board/toradex/colibri-imx8x/MAINTAINERS index 8c9bf1f63f4..938c2ca0ca0 100644 --- a/board/toradex/colibri-imx8x/MAINTAINERS +++ b/board/toradex/colibri-imx8x/MAINTAINERS @@ -1,5 +1,5 @@ Colibri iMX8X -M: Marcel Ziswiler <marcel.ziswiler@toradex.com> +M: Francesco Dolcini <francesco.dolcini@toradex.com> W: http://developer.toradex.com/software/linux/linux-software S: Maintained F: arch/arm/dts/fsl-imx8x-colibri.dts diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS index 25d3a06a852..c1067502c08 100644 --- a/board/toradex/colibri_imx6/MAINTAINERS +++ b/board/toradex/colibri_imx6/MAINTAINERS @@ -1,5 +1,5 @@ Colibri iMX6 -M: Marcel Ziswiler <marcel.ziswiler@toradex.com> +M: Francesco Dolcini <francesco.dolcini@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS index e4583d5a86a..80770cc71a9 100644 --- a/board/toradex/colibri_imx7/MAINTAINERS +++ b/board/toradex/colibri_imx7/MAINTAINERS @@ -1,5 +1,5 @@ Colibri iMX7 -M: Marcel Ziswiler <marcel.ziswiler@toradex.com> +M: Francesco Dolcini <francesco.dolcini@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri_t20/MAINTAINERS b/board/toradex/colibri_t20/MAINTAINERS index d0c5b113331..58842434024 100644 --- a/board/toradex/colibri_t20/MAINTAINERS +++ b/board/toradex/colibri_t20/MAINTAINERS @@ -1,5 +1,5 @@ COLIBRI_T20 -M: Marcel Ziswiler <marcel.ziswiler@toradex.com> +M: Francesco Dolcini <francesco.dolcini@toradex.com> S: Maintained F: board/toradex/colibri_t20/ F: board/toradex/common/ diff --git a/board/toradex/colibri_t30/MAINTAINERS b/board/toradex/colibri_t30/MAINTAINERS index 006a0e55f11..73859fd25c2 100644 --- a/board/toradex/colibri_t30/MAINTAINERS +++ b/board/toradex/colibri_t30/MAINTAINERS @@ -1,5 +1,5 @@ Colibri T30 -M: Marcel Ziswiler <marcel.ziswiler@toradex.com> +M: Francesco Dolcini <francesco.dolcini@toradex.com> S: Maintained F: board/toradex/colibri_t30/ F: board/toradex/common/ diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS index 2e1a74c2db7..a41bd165a7c 100644 --- a/board/toradex/colibri_vf/MAINTAINERS +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -1,5 +1,5 @@ Colibri VFxx -M: Marcel Ziswiler <marcel.ziswiler@toradex.com> +M: Francesco Dolcini <francesco.dolcini@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 2225cefec16..a6e3c6afae8 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -158,6 +158,9 @@ const struct toradex_som toradex_modules[] = { [85] = { "Apalis iMX6Q 2GB IT", TARGET_IS_ENABLED(APALIS_IMX6) }, [86] = { "Verdin iMX8M Mini DualLite 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, [87] = { "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + [88] = { "Aquila AM69 Octa 32GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + [89] = { "Verdin iMX95 Hexa 16GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX95) }, + [90] = { "Verdin iMX8M Mini Quad 4GB WB ET", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, }; struct pid4list { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 183ee0f2dc9..0d6dd1c3a72 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -113,6 +113,9 @@ enum { APALIS_IMX6Q_IT_NOWINCE, /* 85 */ VERDIN_IMX8MMDL_2G_IT, VERDIN_IMX8MMQ_2G_IT_NO_CAN, + AQUILA_AM69O_32G_WIFI_BT_IT, + VERDIN_IMX95H_16G_WIFI_BT_IT, + VERDIN_IMX8MMQ_4G_WIFI_BT_ET, /* 90 */ }; enum { diff --git a/board/toradex/verdin-am62/MAINTAINERS b/board/toradex/verdin-am62/MAINTAINERS index 3e30d1d5112..3f69ea88c00 100644 --- a/board/toradex/verdin-am62/MAINTAINERS +++ b/board/toradex/verdin-am62/MAINTAINERS @@ -8,6 +8,6 @@ F: configs/verdin-am62_a53_defconfig F: configs/verdin-am62_r5_defconfig F: doc/board/toradex/verdin-am62.rst F: include/configs/verdin-am62.h -M: Marcel Ziswiler <marcel.ziswiler@toradex.com> +M: Francesco Dolcini <francesco.dolcini@toradex.com> S: Maintained W: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am-62 diff --git a/board/toradex/verdin-imx8mm/MAINTAINERS b/board/toradex/verdin-imx8mm/MAINTAINERS index d567f0e1097..0d58a73b930 100644 --- a/board/toradex/verdin-imx8mm/MAINTAINERS +++ b/board/toradex/verdin-imx8mm/MAINTAINERS @@ -1,5 +1,5 @@ Verdin iMX8M Mini -M: Marcel Ziswiler <marcel.ziswiler@toradex.com> +M: Francesco Dolcini <francesco.dolcini@toradex.com> W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini S: Maintained F: arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi diff --git a/board/toradex/verdin-imx8mm/lpddr4_timing.c b/board/toradex/verdin-imx8mm/lpddr4_timing.c index 4dfec679b11..eece226b513 100644 --- a/board/toradex/verdin-imx8mm/lpddr4_timing.c +++ b/board/toradex/verdin-imx8mm/lpddr4_timing.c @@ -18,7 +18,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400000, 0xa1080020}, {0x3d400020, 0x202}, {0x3d400024, 0x3a980}, - {0x3d400064, 0x2d00d2}, + {0x3d400064, 0x2d011d}, {0x3d4000d0, 0xc00305ba}, {0x3d4000d4, 0x940000}, {0x3d4000dc, 0xd4002d}, @@ -34,7 +34,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d40011c, 0x402}, {0x3d400130, 0x20600}, {0x3d400134, 0xc100002}, - {0x3d400138, 0xd8}, + {0x3d400138, 0x123}, {0x3d400144, 0x96004b}, {0x3d400180, 0x2ee0017}, {0x3d400184, 0x2605b8e}, @@ -56,7 +56,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400204, 0x80808}, {0x3d400214, 0x7070707}, {0x3d400218, 0x7070707}, - {0x3d40021c, 0xf0f}, + {0x3d40021c, 0xf07}, {0x3d400250, 0x29001701}, {0x3d400254, 0x2c}, {0x3d40025c, 0x4000030}, @@ -71,7 +71,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d402020, 0x0}, {0x3d402024, 0x7d00}, {0x3d402050, 0x20d040}, - {0x3d402064, 0x6001c}, + {0x3d402064, 0x60026}, {0x3d4020dc, 0x840000}, {0x3d4020e0, 0x310000}, {0x3d4020e8, 0x66004d}, @@ -86,7 +86,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d40211c, 0x302}, {0x3d402130, 0x20300}, {0x3d402134, 0xa100002}, - {0x3d402138, 0x1d}, + {0x3d402138, 0x27}, {0x3d402144, 0x14000a}, {0x3d402180, 0x640004}, {0x3d402190, 0x3818200}, @@ -96,7 +96,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d403020, 0x0}, {0x3d403024, 0x1f40}, {0x3d403050, 0x20d040}, - {0x3d403064, 0x30007}, + {0x3d403064, 0x3000A}, {0x3d4030dc, 0x840000}, {0x3d4030e0, 0x310000}, {0x3d4030e8, 0x66004d}, @@ -111,7 +111,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d40311c, 0x302}, {0x3d403130, 0x20300}, {0x3d403134, 0xa100002}, - {0x3d403138, 0x8}, + {0x3d403138, 0xA}, {0x3d403144, 0x50003}, {0x3d403180, 0x190004}, {0x3d403190, 0x3818200}, diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 020ee677480..9359e0ac6bf 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -84,7 +84,8 @@ static void select_dt_from_module_version(void) */ is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) || (tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT) || - (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN); + (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN) || + (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_4G_WIFI_BT_ET); } switch (get_pcb_revision()) { @@ -117,7 +118,7 @@ int board_phys_sdram_size(phys_size_t *size) if (!size) return -EINVAL; - *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE); return 0; } @@ -125,6 +126,35 @@ int board_phys_sdram_size(phys_size_t *size) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { + const char *canoscpath = "/oscillator"; + int freq = 40000000; /* 40 MHz is used on most variants */ + int canoscoff, ret; + + canoscoff = fdt_path_offset(blob, canoscpath); + if (canoscoff < 0) /* No CAN oscillator found. */ + goto exit; + + /* + * The following "prodid" (PID4 in Toradex naming) use + * a 20MHz CAN oscillator: + * - 0055, V1.1A, V1.1B, V1.1C and V1.1D + * - 0059, V1.1A and V1.1B + */ + if ((tdx_hw_tag.ver_major == 1 && tdx_hw_tag.ver_minor == 1) && + ((tdx_hw_tag.prodid == VERDIN_IMX8MMQ_IT && + tdx_hw_tag.ver_assembly <= 1) || /* 0059 rev. A or B */ + (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT && + tdx_hw_tag.ver_assembly <= 3))) { /* 0055 rev. A/B/C/D */ + freq = 20000000; + } + + ret = fdt_setprop_u32(blob, canoscoff, "clock-frequency", freq); + if (ret < 0) { + printf("Failed to set CAN oscillator clock-frequency, ret=%d\n", + ret); + } + +exit: return ft_common_board_setup(blob, bd); } #endif diff --git a/board/toradex/verdin-imx8mp/MAINTAINERS b/board/toradex/verdin-imx8mp/MAINTAINERS index 9fe76d8e42f..a6834488539 100644 --- a/board/toradex/verdin-imx8mp/MAINTAINERS +++ b/board/toradex/verdin-imx8mp/MAINTAINERS @@ -5,6 +5,6 @@ F: board/toradex/common/ F: configs/verdin-imx8mp_defconfig F: doc/board/toradex/verdin-imx8mp.rst F: include/configs/verdin-imx8mp.h -M: Marcel Ziswiler <marcel.ziswiler@toradex.com> +M: Francesco Dolcini <francesco.dolcini@toradex.com> S: Maintained W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus diff --git a/board/wexler/qc750/Kconfig b/board/wexler/qc750/Kconfig new file mode 100644 index 00000000000..45a1e5e057b --- /dev/null +++ b/board/wexler/qc750/Kconfig @@ -0,0 +1,12 @@ +if TARGET_QC750 + +config SYS_BOARD + default "qc750" + +config SYS_VENDOR + default "wexler" + +config SYS_CONFIG_NAME + default "qc750" + +endif diff --git a/board/wexler/qc750/MAINTAINERS b/board/wexler/qc750/MAINTAINERS new file mode 100644 index 00000000000..017f6f2b707 --- /dev/null +++ b/board/wexler/qc750/MAINTAINERS @@ -0,0 +1,7 @@ +QC750 BOARD +M: Svyatoslav Ryhel <clamor95@gmail.com> +S: Maintained +F: board/wexler/qc750/ +F: configs/qc750_defconfig +F: doc/board/wexler/qc750.rst +F: include/configs/qc750.h diff --git a/board/wexler/qc750/Makefile b/board/wexler/qc750/Makefile new file mode 100644 index 00000000000..4daefc4159a --- /dev/null +++ b/board/wexler/qc750/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation <www.nvidia.com> +# +# (C) Copyright 2023 +# Svyatoslav Ryhel <clamor95@gmail.com> + +obj-$(CONFIG_SPL_BUILD) += qc750-spl.o + +obj-y += qc750.o diff --git a/board/wexler/qc750/qc750-spl.c b/board/wexler/qc750/qc750-spl.c new file mode 100644 index 00000000000..707be7779eb --- /dev/null +++ b/board/wexler/qc750/qc750-spl.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * T30 QC750 SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2023 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +#define MAX77663_I2C_ADDR (0x3c << 1) + +#define MAX77663_REG_SD0 0x16 +#define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0) +#define MAX77663_REG_SD1 0x17 +#define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1) +#define MAX77663_REG_LDO4 0x2b +#define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4) + +#define MAX77663_REG_GPIO4 0x3a +#define MAX77663_REG_GPIO4_DATA (0x0100 | MAX77663_REG_GPIO4) + +void pmic_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA); + + udelay(1000); + + /* Bring up VDD_CPU to 1.0125V. */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD0_DATA); + udelay(1000); + + /* Bring up VDD_RTC to 1.200V. */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_LDO4_DATA); + udelay(10 * 1000); + + /* Set 32k-out gpio state */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA); +} diff --git a/board/wexler/qc750/qc750.c b/board/wexler/qc750/qc750.c new file mode 100644 index 00000000000..5234211aea3 --- /dev/null +++ b/board/wexler/qc750/qc750.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2023 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <fdt_support.h> + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Remove TrustZone nodes */ + fdt_del_node_and_alias(blob, "/firmware"); + fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000"); + + return 0; +} +#endif diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 5c4ad8f1df9..c7df4ab5781 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -42,7 +42,7 @@ endif config XILINX_OF_BOARD_DTB_ADDR hex "Default DTB pickup address" - default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET + default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 default 0x8000 if MICROBLAZE default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP default 0x23000000 if TARGET_XILINX_MBV @@ -52,10 +52,10 @@ config XILINX_OF_BOARD_DTB_ADDR config BOOT_SCRIPT_OFFSET hex "Boot script offset" - depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || MICROBLAZE || TARGET_XILINX_MBV + depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 || MICROBLAZE || TARGET_XILINX_MBV default 0xFC0000 if ARCH_ZYNQ || MICROBLAZE default 0x3E80000 if ARCH_ZYNQMP - default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET + default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 default 0 if TARGET_XILINX_MBV help Specifies distro boot script offset in NAND/QSPI/NOR flash. diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 30a81376ac4..0b43407b9e9 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -701,11 +701,6 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) #define MAX_RAND_SIZE 8 int ft_board_setup(void *blob, struct bd_info *bd) { - size_t n = MAX_RAND_SIZE; - struct udevice *dev; - u8 buf[MAX_RAND_SIZE]; - int nodeoffset, ret; - static const struct node_info nodes[] = { { "arm,pl353-nand-r2p1", MTD_DEV_TYPE_NAND, }, }; @@ -713,41 +708,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS) && IS_ENABLED(CONFIG_NAND_ZYNQ)) fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); - if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) { - debug("No RNG device\n"); - return 0; - } - - if (dm_rng_read(dev, buf, n)) { - debug("Reading RNG failed\n"); - return 0; - } - - if (!blob) { - debug("No FDT memory address configured. Please configure\n" - "the FDT address via \"fdt addr <address>\" command.\n" - "Aborting!\n"); - return 0; - } - - ret = fdt_check_header(blob); - if (ret < 0) { - debug("fdt_chosen: %s\n", fdt_strerror(ret)); - return ret; - } - - nodeoffset = fdt_find_or_add_subnode(blob, 0, "chosen"); - if (nodeoffset < 0) { - debug("Reading chosen node failed\n"); - return nodeoffset; - } - - ret = fdt_setprop(blob, nodeoffset, "kaslr-seed", buf, sizeof(buf)); - if (ret < 0) { - debug("Unable to set kaslr-seed on chosen node: %s\n", fdt_strerror(ret)); - return ret; - } - return 0; } #endif diff --git a/board/xilinx/versal-net/cmds.c b/board/xilinx/versal-net/cmds.c index 4d52084846b..e8b669f0fd4 100644 --- a/board/xilinx/versal-net/cmds.c +++ b/board/xilinx/versal-net/cmds.c @@ -71,10 +71,9 @@ static int do_versalnet_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc, return cmd_process_error(cmdtp, ret); } -static char versalnet_help_text[] = +U_BOOT_LONGHELP(versalnet, "loadpdi addr len - Load pdi image\n" - "load pdi image at ddr address 'addr' with pdi image size 'len'\n" -; + "load pdi image at ddr address 'addr' with pdi image size 'len'\n"); U_BOOT_CMD_WITH_SUBCMDS(versalnet, "Versal NET sub-system", versalnet_help_text, U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1, diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 77ba783501e..39474674cca 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -150,14 +150,29 @@ static int boot_targets_setup(void) break; case QSPI_MODE_24BIT: puts("QSPI_MODE_24\n"); + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1030000", &dev)) { + debug("QSPI driver for QSPI device is not present\n"); + break; + } mode = "xspi0"; break; case QSPI_MODE_32BIT: puts("QSPI_MODE_32\n"); + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1030000", &dev)) { + debug("QSPI driver for QSPI device is not present\n"); + break; + } mode = "xspi0"; break; case OSPI_MODE: puts("OSPI_MODE\n"); + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1010000", &dev)) { + debug("OSPI driver for OSPI device is not present\n"); + break; + } mode = "xspi0"; break; case EMMC_MODE: diff --git a/board/xilinx/zynqmp/Kconfig b/board/xilinx/zynqmp/Kconfig deleted file mode 100644 index ffa2f0215d4..00000000000 --- a/board/xilinx/zynqmp/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2018, Xilinx, Inc. -# -# SPDX-License-Identifier: GPL-2.0 - -if ARCH_ZYNQMP - -config CMD_ZYNQMP - bool "Enable ZynqMP specific commands" - depends on ZYNQMP_FIRMWARE - default y - help - Enable ZynqMP specific commands like "zynqmp secure" - which is used for zynqmp secure image verification. - The secure image is a xilinx specific BOOT.BIN with - either authentication or encryption or both encryption - and authentication feature enabled while generating - BOOT.BIN using Xilinx bootgen tool. - -endif diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 204e4fadf0e..9ab50eca400 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -40,10 +40,6 @@ $(obj)/pm_cfg_obj.o: $(shell cd $(srctree); readlink -f $(CONFIG_ZYNQMP_SPL_PM_C endif endif -ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_CMD_ZYNQMP) += cmds.o -endif - # Suppress "warning: function declaration isn't a prototype" CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c deleted file mode 100644 index bf39c5472ea..00000000000 --- a/board/xilinx/zynqmp/cmds.c +++ /dev/null @@ -1,431 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * (C) Copyright 2018 Xilinx, Inc. - * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> - */ - -#include <command.h> -#include <cpu_func.h> -#include <env.h> -#include <malloc.h> -#include <memalign.h> -#include <vsprintf.h> -#include <zynqmp_firmware.h> -#include <linux/errno.h> -#include <asm/arch/hardware.h> -#include <asm/arch/sys_proto.h> -#include <asm/io.h> -#include <mach/zynqmp_aes.h> - -static int do_zynqmp_verify_secure(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - u64 src_addr, addr; - u32 len, src_lo, src_hi; - u8 *key_ptr = NULL; - int ret; - u32 key_lo = 0; - u32 key_hi = 0; - u32 ret_payload[PAYLOAD_ARG_CNT]; - - if (argc < 4) - return CMD_RET_USAGE; - - src_addr = simple_strtoull(argv[2], NULL, 16); - len = hextoul(argv[3], NULL); - - if (argc == 5) - key_ptr = (uint8_t *)(uintptr_t)simple_strtoull(argv[4], - NULL, 16); - - if ((ulong)src_addr != ALIGN((ulong)src_addr, - CONFIG_SYS_CACHELINE_SIZE)) { - printf("Failed: source address not aligned:%lx\n", - (ulong)src_addr); - return -EINVAL; - } - - src_lo = lower_32_bits((ulong)src_addr); - src_hi = upper_32_bits((ulong)src_addr); - flush_dcache_range((ulong)src_addr, (ulong)(src_addr + len)); - - if (key_ptr) { - key_lo = lower_32_bits((ulong)key_ptr); - key_hi = upper_32_bits((ulong)key_ptr); - flush_dcache_range((ulong)key_ptr, - (ulong)(key_ptr + KEY_PTR_LEN)); - } - - ret = xilinx_pm_request(PM_SECURE_IMAGE, src_lo, src_hi, - key_lo, key_hi, ret_payload); - if (ret) { - printf("Failed: secure op status:0x%x\n", ret); - } else { - addr = (u64)ret_payload[1] << 32 | ret_payload[2]; - printf("Verified image at 0x%llx\n", addr); - env_set_hex("zynqmp_verified_img_addr", addr); - } - - return ret; -} - -static int do_zynqmp_mmio_read(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - u32 read_val, addr; - int ret; - - if (argc != cmdtp->maxargs) - return CMD_RET_USAGE; - - addr = hextoul(argv[2], NULL); - - ret = zynqmp_mmio_read(addr, &read_val); - if (!ret) - printf("mmio read value at 0x%x = 0x%x\n", - addr, read_val); - else - printf("Failed: mmio read\n"); - - return ret; -} - -static int do_zynqmp_mmio_write(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - u32 addr, mask, val; - int ret; - - if (argc != cmdtp->maxargs) - return CMD_RET_USAGE; - - addr = hextoul(argv[2], NULL); - mask = hextoul(argv[3], NULL); - val = hextoul(argv[4], NULL); - - ret = zynqmp_mmio_write(addr, mask, val); - if (ret != 0) - printf("Failed: mmio write\n"); - - return ret; -} - -static int do_zynqmp_aes(struct cmd_tbl *cmdtp, int flag, int argc, - char * const argv[]) -{ - ALLOC_CACHE_ALIGN_BUFFER(struct zynqmp_aes, aes, 1); - - if (zynqmp_firmware_version() <= PMUFW_V1_0) { - puts("ERR: PMUFW v1.0 or less is detected\n"); - puts("ERR: Encrypt/Decrypt feature is not supported\n"); - puts("ERR: Please upgrade PMUFW\n"); - return CMD_RET_FAILURE; - } - - if (argc < cmdtp->maxargs - 1) - return CMD_RET_USAGE; - - aes->srcaddr = hextoul(argv[2], NULL); - aes->ivaddr = hextoul(argv[3], NULL); - aes->len = hextoul(argv[4], NULL); - aes->op = hextoul(argv[5], NULL); - aes->keysrc = hextoul(argv[6], NULL); - aes->dstaddr = hextoul(argv[7], NULL); - - if (aes->keysrc == 0) { - if (argc < cmdtp->maxargs) - return CMD_RET_USAGE; - - aes->keyaddr = hextoul(argv[8], NULL); - } - - return zynqmp_aes_operation(aes); -} - -#ifdef CONFIG_DEFINE_TCM_OCM_MMAP -static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - u8 mode; - - if (argc != cmdtp->maxargs) - return CMD_RET_USAGE; - - if (strcmp(argv[2], "lockstep") && strcmp(argv[2], "split")) { - printf("mode param should be lockstep or split\n"); - return CMD_RET_FAILURE; - } - - mode = hextoul(argv[2], NULL); - if (mode != TCM_LOCK && mode != TCM_SPLIT) { - printf("Mode should be either 0(lock)/1(split)\n"); - return CMD_RET_FAILURE; - } - - dcache_disable(); - tcm_init(mode); - dcache_enable(); - - return CMD_RET_SUCCESS; -} -#endif - -static int do_zynqmp_pmufw(struct cmd_tbl *cmdtp, int flag, int argc, - char * const argv[]) -{ - u32 addr, size; - - if (argc != cmdtp->maxargs) - return CMD_RET_USAGE; - - if (!strncmp(argv[2], "node", 4)) { - u32 id; - int ret; - - if (!strncmp(argv[3], "close", 5)) - return zynqmp_pmufw_config_close(); - - id = dectoul(argv[3], NULL); - if (!id) { - printf("Incorrect ID passed\n"); - return CMD_RET_USAGE; - } - - printf("Enable permission for node ID %d\n", id); - - ret = zynqmp_pmufw_node(id); - if (ret == -ENODEV) - ret = 0; - - return ret; - } - - addr = hextoul(argv[2], NULL); - size = hextoul(argv[3], NULL); - - zynqmp_pmufw_load_config_object((const void *)(uintptr_t)addr, - (size_t)size); - - return 0; -} - -static int do_zynqmp_rsa(struct cmd_tbl *cmdtp, int flag, int argc, - char * const argv[]) -{ - u64 srcaddr, mod, exp; - u32 srclen, rsaop, size, ret_payload[PAYLOAD_ARG_CNT]; - int ret; - - if (argc != cmdtp->maxargs) - return CMD_RET_USAGE; - - if (zynqmp_firmware_version() <= PMUFW_V1_0) { - puts("ERR: PMUFW v1.0 or less is detected\n"); - puts("ERR: Encrypt/Decrypt feature is not supported\n"); - puts("ERR: Please upgrade PMUFW\n"); - return CMD_RET_FAILURE; - } - - srcaddr = hextoul(argv[2], NULL); - srclen = hextoul(argv[3], NULL); - if (srclen != RSA_KEY_SIZE) { - puts("ERR: srclen should be equal to 0x200(512 bytes)\n"); - return CMD_RET_USAGE; - } - - mod = hextoul(argv[4], NULL); - exp = hextoul(argv[5], NULL); - rsaop = hextoul(argv[6], NULL); - if (!(rsaop == 0 || rsaop == 1)) { - puts("ERR: rsaop should be either 0 or 1\n"); - return CMD_RET_USAGE; - } - - memcpy((void *)srcaddr + srclen, (void *)mod, MODULUS_LEN); - - /* - * For encryption we load public exponent (key size 4096-bits), - * for decryption we load private exponent (32-bits) - */ - if (rsaop) { - memcpy((void *)srcaddr + srclen + MODULUS_LEN, - (void *)exp, PUB_EXPO_LEN); - size = srclen + MODULUS_LEN + PUB_EXPO_LEN; - } else { - memcpy((void *)srcaddr + srclen + MODULUS_LEN, - (void *)exp, PRIV_EXPO_LEN); - size = srclen + MODULUS_LEN + PRIV_EXPO_LEN; - } - - flush_dcache_range((ulong)srcaddr, - (ulong)(srcaddr) + roundup(size, ARCH_DMA_MINALIGN)); - - ret = xilinx_pm_request(PM_SECURE_RSA, upper_32_bits((ulong)srcaddr), - lower_32_bits((ulong)srcaddr), srclen, rsaop, - ret_payload); - if (ret || ret_payload[1]) { - printf("Failed: RSA status:0x%x, errcode:0x%x\n", - ret, ret_payload[1]); - return CMD_RET_FAILURE; - } - - return CMD_RET_SUCCESS; -} - -static int do_zynqmp_sha3(struct cmd_tbl *cmdtp, int flag, - int argc, char * const argv[]) -{ - u64 srcaddr, hashaddr; - u32 srclen, ret_payload[PAYLOAD_ARG_CNT]; - int ret; - - if (argc > cmdtp->maxargs || argc < (cmdtp->maxargs - 1)) - return CMD_RET_USAGE; - - if (zynqmp_firmware_version() <= PMUFW_V1_0) { - puts("ERR: PMUFW v1.0 or less is detected\n"); - puts("ERR: Encrypt/Decrypt feature is not supported\n"); - puts("ERR: Please upgrade PMUFW\n"); - return CMD_RET_FAILURE; - } - - srcaddr = hextoul(argv[2], NULL); - srclen = hextoul(argv[3], NULL); - - if (argc == 5) { - hashaddr = hextoul(argv[4], NULL); - flush_dcache_range(hashaddr, - hashaddr + roundup(ZYNQMP_SHA3_SIZE, - ARCH_DMA_MINALIGN)); - } else { - hashaddr = srcaddr; - } - - /* Check srcaddr or srclen != 0 */ - if (!srcaddr || !srclen) { - puts("ERR: srcaddr & srclen should not be 0\n"); - return CMD_RET_USAGE; - } - - flush_dcache_range(srcaddr, - srcaddr + roundup(srclen, ARCH_DMA_MINALIGN)); - - ret = xilinx_pm_request(PM_SECURE_SHA, 0, 0, 0, - ZYNQMP_SHA3_INIT, ret_payload); - if (ret || ret_payload[1]) { - printf("Failed: SHA INIT status:0x%x, errcode:0x%x\n", - ret, ret_payload[1]); - return CMD_RET_FAILURE; - } - - ret = xilinx_pm_request(PM_SECURE_SHA, upper_32_bits((ulong)srcaddr), - lower_32_bits((ulong)srcaddr), - srclen, ZYNQMP_SHA3_UPDATE, ret_payload); - if (ret || ret_payload[1]) { - printf("Failed: SHA UPDATE status:0x%x, errcode:0x%x\n", - ret, ret_payload[1]); - return CMD_RET_FAILURE; - } - - ret = xilinx_pm_request(PM_SECURE_SHA, upper_32_bits((ulong)hashaddr), - lower_32_bits((ulong)hashaddr), - ZYNQMP_SHA3_SIZE, ZYNQMP_SHA3_FINAL, - ret_payload); - if (ret || ret_payload[1]) { - printf("Failed: SHA FINAL status:0x%x, errcode:0x%x\n", - ret, ret_payload[1]); - return CMD_RET_FAILURE; - } - - return CMD_RET_SUCCESS; -} - -static struct cmd_tbl cmd_zynqmp_sub[] = { - U_BOOT_CMD_MKENT(secure, 5, 0, do_zynqmp_verify_secure, "", ""), - U_BOOT_CMD_MKENT(pmufw, 4, 0, do_zynqmp_pmufw, "", ""), - U_BOOT_CMD_MKENT(mmio_read, 3, 0, do_zynqmp_mmio_read, "", ""), - U_BOOT_CMD_MKENT(mmio_write, 5, 0, do_zynqmp_mmio_write, "", ""), - U_BOOT_CMD_MKENT(aes, 9, 0, do_zynqmp_aes, "", ""), - U_BOOT_CMD_MKENT(rsa, 7, 0, do_zynqmp_rsa, "", ""), - U_BOOT_CMD_MKENT(sha3, 5, 0, do_zynqmp_sha3, "", ""), -#ifdef CONFIG_DEFINE_TCM_OCM_MMAP - U_BOOT_CMD_MKENT(tcminit, 3, 0, do_zynqmp_tcm_init, "", ""), -#endif -}; - -/** - * do_zynqmp - Handle the "zynqmp" command-line command - * @cmdtp: Command data struct pointer - * @flag: Command flag - * @argc: Command-line argument count - * @argv: Array of command-line arguments - * - * Processes the zynqmp specific commands - * - * Return: return 0 on success and CMD_RET_USAGE incase of misuse and error - */ -static int do_zynqmp(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - struct cmd_tbl *c; - int ret = CMD_RET_USAGE; - - if (argc < 2) - return CMD_RET_USAGE; - - c = find_cmd_tbl(argv[1], &cmd_zynqmp_sub[0], - ARRAY_SIZE(cmd_zynqmp_sub)); - if (c) - ret = c->cmd(c, flag, argc, argv); - - return cmd_process_error(c, ret); -} - -/***************************************************/ -U_BOOT_LONGHELP(zynqmp, - "secure src len [key_addr] - verifies secure images of $len bytes\n" - " long at address $src. Optional key_addr\n" - " can be specified if user key needs to\n" - " be used for decryption\n" - "zynqmp mmio_read address - read from address\n" - "zynqmp mmio_write address mask value - write value after masking to\n" - " address\n" - "zynqmp aes srcaddr ivaddr len aesop keysrc dstaddr [keyaddr] -\n" - " Encrypts or decrypts blob of data at src address and puts it\n" - " back to dstaddr using key and iv at keyaddr and ivaddr\n" - " respectively. keysrc value specifies from which source key\n" - " has to be used, it can be User/Device/PUF key. A value of 0\n" - " for KUP(user key),1 for DeviceKey and 2 for PUF key. The\n" - " aesop value specifies the operation which can be 0 for\n" - " decrypt and 1 for encrypt operation\n" -#ifdef CONFIG_DEFINE_TCM_OCM_MMAP - "zynqmp tcminit mode - Initialize the TCM with zeros. TCM needs to be\n" - " initialized before accessing to avoid ECC\n" - " errors. mode specifies in which mode TCM has\n" - " to be initialized. Supported modes will be\n" - " lock(0)/split(1)\n" -#endif - "zynqmp pmufw address size - load PMU FW configuration object\n" - "zynqmp pmufw node <id> - load PMU FW configuration object, <id> in dec\n" - "zynqmp pmufw node close - disable config object loading\n" - " node: keyword, id: NODE_ID in decimal format\n" - "zynqmp rsa srcaddr srclen mod exp rsaop -\n" - " Performs RSA encryption and RSA decryption on blob of data\n" - " at srcaddr and puts it back in srcaddr using modulus and\n" - " public or private exponent\n" - " srclen : must be key size(4096 bits)\n" - " exp : private key exponent for RSA decryption(4096 bits)\n" - " public key exponent for RSA encryption(32 bits)\n" - " rsaop : 0 for RSA Decryption, 1 for RSA Encryption\n" - "zynqmp sha3 srcaddr srclen [key_addr] -\n" - " Generates sha3 hash value for data blob at srcaddr and puts\n" - " 48 bytes hash value into srcaddr\n" - " Optional key_addr can be specified for saving sha3 hash value\n" - " Note: srcaddr/srclen should not be 0\n" - ); - -U_BOOT_CMD( - zynqmp, 9, 1, do_zynqmp, - "ZynqMP sub-system", - zynqmp_help_text -); diff --git a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c index 166e61431ba..274203ffaa3 100644 --- a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c @@ -528,8 +528,8 @@ static unsigned long psu_mio_init_data(void) psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x00000000U); psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U); psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02020U); psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); @@ -569,21 +569,16 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFD1A0100, 0x0001807CU, 0x00000000U); psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); - psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); - psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U); - psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); - psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000080U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000010U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000004U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); @@ -591,13 +586,15 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x01000000U); + psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x01000000U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0100U); mask_delay(1); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0000U); mask_delay(5); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0100U); return 1; } diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index c4050af2a5a..b4c15b041cc 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -285,6 +285,18 @@ int dram_init(void) #if !CONFIG_IS_ENABLED(SYSRESET) void reset_cpu(void) { + if (!IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) { + log_warning("reset failed: ZYNQMP_FIRMWARE disabled"); + return; + } + + /* In case of !CONFIG_ZYNQMP_FIRMWARE the call to 'xilinx_pm_request()' + * will be removed by the compiler due to the early return. + * If CONFIG_ZYNQMP_FIRMWARE is defined in SPL 'xilinx_pm_request()' + * will send command over IPI and requires pmufw to be present. + */ + xilinx_pm_request(PM_RESET_ASSERT, ZYNQMP_PM_RESET_SOFT, + PM_RESET_ACTION_ASSERT, 0, 0, NULL); } #endif @@ -519,6 +531,10 @@ int board_late_init(void) usb_ether_init(); #endif + multiboot = multi_boot(); + if (multiboot >= 0) + env_set_hex("multiboot", multiboot); + if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { debug("Saved variables - Skipping\n"); return 0; @@ -531,10 +547,6 @@ int board_late_init(void) if (ret) return ret; - multiboot = multi_boot(); - if (multiboot >= 0) - env_set_hex("multiboot", multiboot); - if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) { ret = boot_targets_setup(); if (ret) diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env index 846eceb0118..69e333c5388 100644 --- a/board/xilinx/zynqmp/zynqmp_kria.env +++ b/board/xilinx/zynqmp/zynqmp_kria.env @@ -65,6 +65,7 @@ kd240_setup=i2c dev 1 && run usb_hub_init;zynqmp pmufw node 33; zynqmp pmufw nod tpm_setup=tpm autostart; board_setup=\ +zynqmp mmio_write 0xFFCA0010 0xfff 0; \ if test ${card1_name} = SCK-KV-G; then run kv260_setup; fi;\ if test ${card1_name} = SCK-KR-G; then run kr260_setup; fi;\ if test ${card1_name} = SCK-KD-G; then run kd240_setup; fi;\ |