diff options
Diffstat (limited to 'cpu')
106 files changed, 748 insertions, 748 deletions
diff --git a/cpu/arm1136/mx31/serial.c b/cpu/arm1136/mx31/serial.c index a829ba7dacd..1cad8f9d8c5 100644 --- a/cpu/arm1136/mx31/serial.c +++ b/cpu/arm1136/mx31/serial.c @@ -77,9 +77,9 @@ #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ #define UCR1_DOZE (1<<1) /* Doze */ #define UCR1_UARTEN (1<<0) /* UART enabled */ -#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ -#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ -#define UCR2_CTSC (1<<13) /* CTS pin control */ +#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ +#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ +#define UCR2_CTSC (1<<13) /* CTS pin control */ #define UCR2_CTS (1<<12) /* Clear to send */ #define UCR2_ESCEN (1<<11) /* Escape enable */ #define UCR2_PREN (1<<8) /* Parity enable */ @@ -89,8 +89,8 @@ #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ #define UCR2_TXEN (1<<2) /* Transmitter enabled */ #define UCR2_RXEN (1<<1) /* Receiver enabled */ -#define UCR2_SRST (1<<0) /* SW reset */ -#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ +#define UCR2_SRST (1<<0) /* SW reset */ +#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ #define UCR3_PARERREN (1<<12) /* Parity enable */ #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ #define UCR3_DSR (1<<10) /* Data set ready */ @@ -100,51 +100,51 @@ #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ -#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ -#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ -#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ -#define UCR3_BPEN (1<<0) /* Preset registers enable */ +#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ +#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ +#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ +#define UCR3_BPEN (1<<0) /* Preset registers enable */ #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ -#define UCR4_INVR (1<<9) /* Inverted infrared reception */ -#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ -#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ -#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ -#define UCR4_IRSC (1<<5) /* IR special case */ -#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ -#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ -#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ -#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ +#define UCR4_INVR (1<<9) /* Inverted infrared reception */ +#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ +#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ +#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ +#define UCR4_IRSC (1<<5) /* IR special case */ +#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ +#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ +#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ +#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ -#define USR1_RTSS (1<<14) /* RTS pin status */ -#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ -#define USR1_RTSD (1<<12) /* RTS delta */ -#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ +#define USR1_RTSS (1<<14) /* RTS pin status */ +#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ +#define USR1_RTSD (1<<12) /* RTS delta */ +#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ -#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ +#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ -#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ -#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ -#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ -#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ -#define USR2_IDLE (1<<12) /* Idle condition */ -#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ -#define USR2_WAKE (1<<7) /* Wake */ -#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ -#define USR2_TXDC (1<<3) /* Transmitter complete */ -#define USR2_BRCD (1<<2) /* Break condition */ +#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ +#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ +#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ +#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ +#define USR2_IDLE (1<<12) /* Idle condition */ +#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ +#define USR2_WAKE (1<<7) /* Wake */ +#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ +#define USR2_TXDC (1<<3) /* Transmitter complete */ +#define USR2_BRCD (1<<2) /* Break condition */ #define USR2_ORE (1<<1) /* Overrun error */ #define USR2_RDR (1<<0) /* Recv data ready */ #define UTS_FRCPERR (1<<13) /* Force parity error */ #define UTS_LOOP (1<<12) /* Loop tx and rx */ #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ -#define UTS_TXFULL (1<<4) /* TxFIFO full */ -#define UTS_RXFULL (1<<3) /* RxFIFO full */ +#define UTS_TXFULL (1<<4) /* TxFIFO full */ +#define UTS_RXFULL (1<<3) /* RxFIFO full */ #define UTS_SOFTRST (1<<0) /* Software reset */ DECLARE_GLOBAL_DATA_PTR; diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S index 56009d0fb33..51b664d9355 100644 --- a/cpu/arm1136/start.S +++ b/cpu/arm1136/start.S @@ -131,7 +131,7 @@ reset: #ifdef CONFIG_OMAP2420H4 /* Copy vectors to mask ROM indirect addr */ adr r0, _start /* r0 <- current position of code */ - add r0, r0, #4 /* skip reset vector */ + add r0, r0, #4 /* skip reset vector */ mov r2, #64 /* r2 <- size to copy */ add r2, r0, r2 /* r2 <- source end address */ mov r1, #SRAM_OFFSET0 /* build vect addr */ diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c index 475607d95a2..9854016d43e 100644 --- a/cpu/arm720t/interrupts.c +++ b/cpu/arm720t/interrupts.c @@ -182,7 +182,7 @@ int interrupt_init (void) PUT32(T0IR, 0); /* disable all timer0 interrupts */ PUT32(T0TCR, 0); /* disable timer0 */ PUT32(T0PR, CFG_SYS_CLK_FREQ / CFG_HZ); - PUT32(T0MCR, 0); + PUT32(T0MCR, 0); PUT32(T0TC, 0); PUT32(T0TCR, 1); /* enable timer0 */ diff --git a/cpu/arm720t/serial_netarm.c b/cpu/arm720t/serial_netarm.c index bc6bf30b69e..a593cbc32f0 100644 --- a/cpu/arm720t/serial_netarm.c +++ b/cpu/arm720t/serial_netarm.c @@ -44,7 +44,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif /* wait until transmitter is ready for another character */ -#define TXWAITRDY(registers) \ +#define TXWAITRDY(registers) \ { \ ulong tmo = get_timer(0) + 1 * CFG_HZ; \ while (((registers)->status_a & NETARM_SER_STATA_TX_RDY) == 0 ) { \ diff --git a/cpu/arm920t/at91rm9200/ether.c b/cpu/arm920t/at91rm9200/ether.c index c8f56aa52de..f20e0703432 100644 --- a/cpu/arm920t/at91rm9200/ether.c +++ b/cpu/arm920t/at91rm9200/ether.c @@ -105,7 +105,7 @@ void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac) * Arguments: * dev - pointer to struct net_device * RegisterAddress - unsigned char - * pInput - pointer to value read from register + * pInput - pointer to value read from register * Return value: * TRUE - if data read successfully */ @@ -134,7 +134,7 @@ UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac, * Arguments: * dev - pointer to struct net_device * RegisterAddress - unsigned char - * pOutput - pointer to value to be written in the register + * pOutput - pointer to value to be written in the register * Return value: * TRUE - if data read successfully */ diff --git a/cpu/arm920t/imx/serial.c b/cpu/arm920t/imx/serial.c index 9dbaa569a09..6c56acbfde5 100644 --- a/cpu/arm920t/imx/serial.c +++ b/cpu/arm920t/imx/serial.c @@ -115,7 +115,7 @@ int serial_init (void) /* Enable FIFOs */ base->ucr2 |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN; - /* Clear status flags */ + /* Clear status flags */ base->usr2 |= USR2_ADET | USR2_DTRF | USR2_IDLE | @@ -126,7 +126,7 @@ int serial_init (void) USR2_ORE | USR2_RDR; - /* Clear status flags */ + /* Clear status flags */ base->usr1 |= USR1_PARITYERR | USR1_RTSD | USR1_ESCF | diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c index 96e43d0fa68..b57c2d8950b 100644 --- a/cpu/arm920t/s3c24x0/usb_ohci.c +++ b/cpu/arm920t/s3c24x0/usb_ohci.c @@ -971,13 +971,13 @@ static unsigned char root_hub_str_index1[] = /*-------------------------------------------------------------------------*/ -#define OK(x) len = (x); break +#define OK(x) len = (x); break #ifdef DEBUG -#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} -#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} +#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} +#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} #else -#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) -#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) +#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) +#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) #endif #define RD_RH_STAT roothub_status(&gohci) #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) @@ -1163,7 +1163,7 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); data_buf [1] = 0x29; data_buf [2] = temp & RH_A_NDP; data_buf [3] = 0; - if (temp & RH_A_PSM) /* per-port power switching? */ + if (temp & RH_A_PSM) /* per-port power switching? */ data_buf [3] |= 0x1; if (temp & RH_A_NOCP) /* no overcurrent reporting? */ data_buf [3] |= 0x10; @@ -1188,9 +1188,9 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); OK (len); } - case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); + case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); - case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); + case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); default: dbg ("unsupported root hub command"); diff --git a/cpu/arm920t/s3c24x0/usb_ohci.h b/cpu/arm920t/s3c24x0/usb_ohci.h index 5e9a0fdfc4e..3af5fca804a 100644 --- a/cpu/arm920t/s3c24x0/usb_ohci.h +++ b/cpu/arm920t/s3c24x0/usb_ohci.h @@ -11,30 +11,30 @@ static int cc_to_error[16] = { /* mapping of the OHCI CC status to error codes */ - /* No Error */ 0, - /* CRC Error */ USB_ST_CRC_ERR, - /* Bit Stuff */ USB_ST_BIT_ERR, - /* Data Togg */ USB_ST_CRC_ERR, - /* Stall */ USB_ST_STALLED, - /* DevNotResp */ -1, - /* PIDCheck */ USB_ST_BIT_ERR, - /* UnExpPID */ USB_ST_BIT_ERR, - /* DataOver */ USB_ST_BUF_ERR, - /* DataUnder */ USB_ST_BUF_ERR, - /* reservd */ -1, - /* reservd */ -1, - /* BufferOver */ USB_ST_BUF_ERR, - /* BuffUnder */ USB_ST_BUF_ERR, - /* Not Access */ -1, - /* Not Access */ -1 + /* No Error */ 0, + /* CRC Error */ USB_ST_CRC_ERR, + /* Bit Stuff */ USB_ST_BIT_ERR, + /* Data Togg */ USB_ST_CRC_ERR, + /* Stall */ USB_ST_STALLED, + /* DevNotResp */ -1, + /* PIDCheck */ USB_ST_BIT_ERR, + /* UnExpPID */ USB_ST_BIT_ERR, + /* DataOver */ USB_ST_BUF_ERR, + /* DataUnder */ USB_ST_BUF_ERR, + /* reservd */ -1, + /* reservd */ -1, + /* BufferOver */ USB_ST_BUF_ERR, + /* BuffUnder */ USB_ST_BUF_ERR, + /* Not Access */ -1, + /* Not Access */ -1 }; /* ED States */ -#define ED_NEW 0x00 -#define ED_UNLINK 0x01 +#define ED_NEW 0x00 +#define ED_UNLINK 0x01 #define ED_OPER 0x02 #define ED_DEL 0x04 -#define ED_URB_DEL 0x08 +#define ED_URB_DEL 0x08 /* usb_ohci_ed */ struct ed { @@ -60,53 +60,53 @@ typedef struct ed ed_t; /* TD info field */ -#define TD_CC 0xf0000000 -#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) -#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) -#define TD_EC 0x0C000000 -#define TD_T 0x03000000 -#define TD_T_DATA0 0x02000000 -#define TD_T_DATA1 0x03000000 -#define TD_T_TOGGLE 0x00000000 -#define TD_R 0x00040000 -#define TD_DI 0x00E00000 -#define TD_DI_SET(X) (((X) & 0x07)<< 21) -#define TD_DP 0x00180000 -#define TD_DP_SETUP 0x00000000 -#define TD_DP_IN 0x00100000 -#define TD_DP_OUT 0x00080000 - -#define TD_ISO 0x00010000 -#define TD_DEL 0x00020000 +#define TD_CC 0xf0000000 +#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) +#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) +#define TD_EC 0x0C000000 +#define TD_T 0x03000000 +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_T_TOGGLE 0x00000000 +#define TD_R 0x00040000 +#define TD_DI 0x00E00000 +#define TD_DI_SET(X) (((X) & 0x07)<< 21) +#define TD_DP 0x00180000 +#define TD_DP_SETUP 0x00000000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 + +#define TD_ISO 0x00010000 +#define TD_DEL 0x00020000 /* CC Codes */ -#define TD_CC_NOERROR 0x00 -#define TD_CC_CRC 0x01 -#define TD_CC_BITSTUFFING 0x02 -#define TD_CC_DATATOGGLEM 0x03 -#define TD_CC_STALL 0x04 -#define TD_DEVNOTRESP 0x05 -#define TD_PIDCHECKFAIL 0x06 -#define TD_UNEXPECTEDPID 0x07 -#define TD_DATAOVERRUN 0x08 -#define TD_DATAUNDERRUN 0x09 -#define TD_BUFFEROVERRUN 0x0C -#define TD_BUFFERUNDERRUN 0x0D -#define TD_NOTACCESSED 0x0F +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D +#define TD_NOTACCESSED 0x0F #define MAXPSW 1 struct td { __u32 hwINFO; - __u32 hwCBP; /* Current Buffer Pointer */ - __u32 hwNextTD; /* Next TD Pointer */ - __u32 hwBE; /* Memory Buffer End Pointer */ - - __u8 unused; - __u8 index; - struct ed *ed; - struct td *next_dl_td; + __u32 hwCBP; /* Current Buffer Pointer */ + __u32 hwNextTD; /* Next TD Pointer */ + __u32 hwBE; /* Memory Buffer End Pointer */ + + __u8 unused; + __u8 index; + struct ed *ed; + struct td *next_dl_td; struct usb_device *usb_dev; int transfer_len; __u32 data; @@ -129,7 +129,7 @@ struct ohci_hcca { __u16 frame_no; /* current frame number */ __u16 pad1; /* set to 0 on each frame_no change */ __u32 done_head; /* info returned for an interrupt */ - u8 reserved_for_hc[116]; + u8 reserved_for_hc[116]; } __attribute((aligned(256))); @@ -140,7 +140,7 @@ struct ohci_hcca { /* * This is the structure of the OHCI controller's memory mapped I/O - * region. This is Memory Mapped I/O. You must use the readl() and + * region. This is Memory Mapped I/O. You must use the readl() and * writel() macros defined in asm/io.h to access these!! */ struct ohci_regs { @@ -200,10 +200,10 @@ struct ohci_regs { * HcCommandStatus (cmdstatus) register masks */ #define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ -#define OHCI_SOC (3 << 16) /* scheduling overrun count */ +#define OHCI_CLF (1 << 1) /* control list filled */ +#define OHCI_BLF (1 << 2) /* bulk list filled */ +#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_SOC (3 << 16) /* scheduling overrun count */ /* * masks used with interrupt registers: @@ -234,93 +234,93 @@ struct virt_root_hub { /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ /* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 /* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 #define RH_SET_ADDRESS 0x0500 #define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 +#define RH_SET_DESCRIPTOR 0x0700 #define RH_GET_CONFIGURATION 0x0880 #define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 /* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 +#define RH_SET_EP 0x2000 /* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 - -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 /* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 /* OHCI ROOT HUB REGISTER MASKS */ /* roothub.portstatus [i] bits */ -#define RH_PS_CCS 0x00000001 /* current connect status */ -#define RH_PS_PES 0x00000002 /* port enable status*/ -#define RH_PS_PSS 0x00000004 /* port suspend status */ -#define RH_PS_POCI 0x00000008 /* port over current indicator */ -#define RH_PS_PRS 0x00000010 /* port reset status */ -#define RH_PS_PPS 0x00000100 /* port power status */ -#define RH_PS_LSDA 0x00000200 /* low speed device attached */ -#define RH_PS_CSC 0x00010000 /* connect status change */ -#define RH_PS_PESC 0x00020000 /* port enable status change */ -#define RH_PS_PSSC 0x00040000 /* port suspend status change */ -#define RH_PS_OCIC 0x00080000 /* over current indicator change */ -#define RH_PS_PRSC 0x00100000 /* port reset status change */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status*/ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ /* roothub.status bits */ -#define RH_HS_LPS 0x00000001 /* local power status */ -#define RH_HS_OCI 0x00000002 /* over current indicator */ -#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ -#define RH_HS_LPSC 0x00010000 /* local power status change */ -#define RH_HS_OCIC 0x00020000 /* over current indicator change */ -#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ /* roothub.b masks */ -#define RH_B_DR 0x0000ffff /* device removable flags */ -#define RH_B_PPCM 0xffff0000 /* port power control mask */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ /* roothub.a masks */ -#define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ -#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ /* urb */ #define N_URB_TD 48 @@ -345,39 +345,39 @@ typedef struct typedef struct ohci { - struct ohci_hcca *hcca; /* hcca */ - /*dma_addr_t hcca_dma;*/ + struct ohci_hcca *hcca; /* hcca */ + /*dma_addr_t hcca_dma; */ int irq; - int disabled; /* e.g. got a UE, we're hung */ + int disabled; /* e.g. got a UE, we're hung */ int sleeping; - unsigned long flags; /* for HC bugs */ + unsigned long flags; /* for HC bugs */ struct ohci_regs *regs; /* OHCI controller's memory */ - ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ - ed_t *ed_bulktail; /* last endpoint of bulk list */ - ed_t *ed_controltail; /* last endpoint of control list */ + ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ + ed_t *ed_bulktail; /* last endpoint of bulk list */ + ed_t *ed_controltail; /* last endpoint of control list */ int intrstatus; - __u32 hc_control; /* copy of the hc control reg */ + __u32 hc_control; /* copy of the hc control reg */ struct usb_device *dev[32]; struct virt_root_hub rh; - const char *slot_name; + const char *slot_name; } ohci_t; #define NUM_EDS 8 /* num of preallocated endpoint descriptors */ struct ohci_device { - ed_t ed[NUM_EDS]; + ed_t ed[NUM_EDS]; int ed_cnt; }; /* hcd */ /* endpoint */ -static int ep_link(ohci_t * ohci, ed_t * ed); -static int ep_unlink(ohci_t * ohci, ed_t * ed); -static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); +static int ep_link (ohci_t * ohci, ed_t * ed); +static int ep_unlink (ohci_t * ohci, ed_t * ed); +static ed_t *ep_add_ed (struct usb_device *usb_dev, unsigned long pipe); /*-------------------------------------------------------------------------*/ @@ -385,22 +385,20 @@ static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); #define NUM_TD 64 /* +1 so we can align the storage */ -td_t gtd[NUM_TD+1]; +td_t gtd[NUM_TD + 1]; + /* pointers to aligned storage */ td_t *ptd; /* TDs ... */ -static inline struct td * -td_alloc (struct usb_device *usb_dev) +static inline struct td *td_alloc (struct usb_device *usb_dev) { int i; - struct td *td; + struct td *td; td = NULL; - for (i = 0; i < NUM_TD; i++) - { - if (ptd[i].usb_dev == NULL) - { + for (i = 0; i < NUM_TD; i++) { + if (ptd[i].usb_dev == NULL) { td = &ptd[i]; td->usb_dev = usb_dev; break; @@ -410,8 +408,7 @@ td_alloc (struct usb_device *usb_dev) return td; } -static inline void -ed_free (struct ed *ed) +static inline void ed_free (struct ed *ed) { ed->usb_dev = NULL; } diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index acc00ad9706..62231f85665 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -212,7 +212,7 @@ stack_setup: clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 @@ -377,31 +377,31 @@ cpu_init_crit: undefined_instruction: get_bad_stack bad_save_user_regs - bl do_undefined_instruction + bl do_undefined_instruction .align 5 software_interrupt: get_bad_stack bad_save_user_regs - bl do_software_interrupt + bl do_software_interrupt .align 5 prefetch_abort: get_bad_stack bad_save_user_regs - bl do_prefetch_abort + bl do_prefetch_abort .align 5 data_abort: get_bad_stack bad_save_user_regs - bl do_data_abort + bl do_data_abort .align 5 not_used: get_bad_stack bad_save_user_regs - bl do_not_used + bl do_not_used #ifdef CONFIG_USE_IRQ @@ -409,7 +409,7 @@ not_used: irq: get_irq_stack irq_save_user_regs - bl do_irq + bl do_irq irq_restore_user_regs .align 5 @@ -417,7 +417,7 @@ fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs - bl do_fiq + bl do_fiq irq_restore_user_regs #else @@ -426,12 +426,12 @@ fiq: irq: get_bad_stack bad_save_user_regs - bl do_irq + bl do_irq .align 5 fiq: get_bad_stack bad_save_user_regs - bl do_fiq + bl do_fiq #endif diff --git a/cpu/arm925t/start.S b/cpu/arm925t/start.S index acd77426d30..5ddda54bdde 100644 --- a/cpu/arm925t/start.S +++ b/cpu/arm925t/start.S @@ -9,7 +9,7 @@ * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> * Copyright (c) 2002 Gary Jennejohn <gj@denx.de> * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> - * Copyright (c) 2003 Kshitij <kshitij@ti.com> + * Copyright (c) 2003 Kshitij <kshitij@ti.com> * * See file CREDITS for list of people who contributed to this * project. @@ -200,7 +200,7 @@ stack_setup: clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 @@ -357,31 +357,31 @@ cpu_init_crit: undefined_instruction: get_bad_stack bad_save_user_regs - bl do_undefined_instruction + bl do_undefined_instruction .align 5 software_interrupt: get_bad_stack bad_save_user_regs - bl do_software_interrupt + bl do_software_interrupt .align 5 prefetch_abort: get_bad_stack bad_save_user_regs - bl do_prefetch_abort + bl do_prefetch_abort .align 5 data_abort: get_bad_stack bad_save_user_regs - bl do_data_abort + bl do_data_abort .align 5 not_used: get_bad_stack bad_save_user_regs - bl do_not_used + bl do_not_used #ifdef CONFIG_USE_IRQ @@ -389,7 +389,7 @@ not_used: irq: get_irq_stack irq_save_user_regs - bl do_irq + bl do_irq irq_restore_user_regs .align 5 @@ -397,7 +397,7 @@ fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs - bl do_fiq + bl do_fiq irq_restore_user_regs #else @@ -406,13 +406,13 @@ fiq: irq: get_bad_stack bad_save_user_regs - bl do_irq + bl do_irq .align 5 fiq: get_bad_stack bad_save_user_regs - bl do_fiq + bl do_fiq #endif diff --git a/cpu/arm926ejs/davinci/dp83848.c b/cpu/arm926ejs/davinci/dp83848.c index 5719845b340..2aa9ef128b8 100644 --- a/cpu/arm926ejs/davinci/dp83848.c +++ b/cpu/arm926ejs/davinci/dp83848.c @@ -125,7 +125,7 @@ int dp83848_auto_negotiate(int phy_addr) * 10BaseTFD and HD, IEEE 802.3 */ tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX | - DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3; + DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3; dm644x_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp); diff --git a/cpu/arm926ejs/davinci/ether.c b/cpu/arm926ejs/davinci/ether.c index 766bc7d66c5..d286ec0c33c 100644 --- a/cpu/arm926ejs/davinci/ether.c +++ b/cpu/arm926ejs/davinci/ether.c @@ -489,7 +489,7 @@ static void dm644x_eth_ch_teardown(int ch) dly--; udelay(1); if (dly == 0) - break; + break; } adap_emac->TX0CP = cnt; adap_emac->TX0HDP = 0; @@ -504,7 +504,7 @@ static void dm644x_eth_ch_teardown(int ch) dly--; udelay(1); if (dly == 0) - break; + break; } adap_emac->RX0CP = cnt; adap_emac->RX0HDP = 0; @@ -535,83 +535,85 @@ static int tx_send_loop = 0; * This function sends a single packet on the network and returns * positive number (number of bytes transmitted) or negative for error */ -static int dm644x_eth_send_packet(volatile void *packet, int length) +static int dm644x_eth_send_packet (volatile void *packet, int length) { int ret_status = -1; + tx_send_loop = 0; /* Return error if no link */ - if (!phy.get_link_speed(active_phy_addr)) - { - printf("WARN: emac_send_packet: No link\n"); + if (!phy.get_link_speed (active_phy_addr)) { + printf ("WARN: emac_send_packet: No link\n"); return (ret_status); } /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ - if (length < EMAC_MIN_ETHERNET_PKT_SIZE) - { + if (length < EMAC_MIN_ETHERNET_PKT_SIZE) { length = EMAC_MIN_ETHERNET_PKT_SIZE; } /* Populate the TX descriptor */ - emac_tx_desc->next = 0; - emac_tx_desc->buffer = (u_int8_t *)packet; + emac_tx_desc->next = 0; + emac_tx_desc->buffer = (u_int8_t *) packet; emac_tx_desc->buff_off_len = (length & 0xffff); emac_tx_desc->pkt_flag_len = ((length & 0xffff) | - EMAC_CPPI_SOP_BIT | - EMAC_CPPI_OWNERSHIP_BIT | - EMAC_CPPI_EOP_BIT); + EMAC_CPPI_SOP_BIT | + EMAC_CPPI_OWNERSHIP_BIT | + EMAC_CPPI_EOP_BIT); /* Send the packet */ - adap_emac->TX0HDP = (unsigned int)emac_tx_desc; + adap_emac->TX0HDP = (unsigned int) emac_tx_desc; /* Wait for packet to complete or link down */ while (1) { - if (!phy.get_link_speed(active_phy_addr)) { - dm644x_eth_ch_teardown(EMAC_CH_TX); - return (ret_status); - } - if (adap_emac->TXINTSTATRAW & 0x01) { - ret_status = length; - break; + if (!phy.get_link_speed (active_phy_addr)) { + dm644x_eth_ch_teardown (EMAC_CH_TX); + return (ret_status); + } + if (adap_emac->TXINTSTATRAW & 0x01) { + ret_status = length; + break; } - tx_send_loop++; + tx_send_loop++; } - return(ret_status); + return (ret_status); } /* * This function handles receipt of a packet from the network */ -static int dm644x_eth_rcv_packet(void) +static int dm644x_eth_rcv_packet (void) { - volatile emac_desc *rx_curr_desc; - volatile emac_desc *curr_desc; - volatile emac_desc *tail_desc; - int status, ret = -1; + volatile emac_desc *rx_curr_desc; + volatile emac_desc *curr_desc; + volatile emac_desc *tail_desc; + int status, ret = -1; rx_curr_desc = emac_rx_active_head; status = rx_curr_desc->pkt_flag_len; if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { - if (status & EMAC_CPPI_RX_ERROR_FRAME) { - /* Error in packet - discard it and requeue desc */ - printf("WARN: emac_rcv_pkt: Error in packet\n"); + if (status & EMAC_CPPI_RX_ERROR_FRAME) { + /* Error in packet - discard it and requeue desc */ + printf ("WARN: emac_rcv_pkt: Error in packet\n"); } else { - NetReceive(rx_curr_desc->buffer, (rx_curr_desc->buff_off_len & 0xffff)); + NetReceive (rx_curr_desc->buffer, + (rx_curr_desc->buff_off_len & 0xffff)); ret = rx_curr_desc->buff_off_len & 0xffff; - } + } - /* Ack received packet descriptor */ - adap_emac->RX0CP = (unsigned int)rx_curr_desc; - curr_desc = rx_curr_desc; - emac_rx_active_head = (volatile emac_desc *)rx_curr_desc->next; + /* Ack received packet descriptor */ + adap_emac->RX0CP = (unsigned int) rx_curr_desc; + curr_desc = rx_curr_desc; + emac_rx_active_head = + (volatile emac_desc *) rx_curr_desc->next; - if (status & EMAC_CPPI_EOQ_BIT) { - if (emac_rx_active_head) { - adap_emac->RX0HDP = (unsigned int)emac_rx_active_head; + if (status & EMAC_CPPI_EOQ_BIT) { + if (emac_rx_active_head) { + adap_emac->RX0HDP = + (unsigned int) emac_rx_active_head; } else { emac_rx_queue_active = 0; - printf("INFO:emac_rcv_packet: RX Queue not active\n"); + printf ("INFO:emac_rcv_packet: RX Queue not active\n"); } } @@ -621,28 +623,29 @@ static int dm644x_eth_rcv_packet(void) rx_curr_desc->next = 0; if (emac_rx_active_head == 0) { - printf("INFO: emac_rcv_pkt: active queue head = 0\n"); + printf ("INFO: emac_rcv_pkt: active queue head = 0\n"); emac_rx_active_head = curr_desc; emac_rx_active_tail = curr_desc; if (emac_rx_queue_active != 0) { - adap_emac->RX0HDP = (unsigned int)emac_rx_active_head; - printf("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); + adap_emac->RX0HDP = + (unsigned int) emac_rx_active_head; + printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); emac_rx_queue_active = 1; } } else { tail_desc = emac_rx_active_tail; emac_rx_active_tail = curr_desc; - tail_desc->next = (unsigned int)curr_desc; + tail_desc->next = (unsigned int) curr_desc; status = tail_desc->pkt_flag_len; if (status & EMAC_CPPI_EOQ_BIT) { - adap_emac->RX0HDP = (unsigned int)curr_desc; + adap_emac->RX0HDP = (unsigned int) curr_desc; status &= ~EMAC_CPPI_EOQ_BIT; tail_desc->pkt_flag_len = status; } } - return(ret); + return (ret); } - return(0); + return (0); } #endif /* CONFIG_CMD_NET */ diff --git a/cpu/arm926ejs/davinci/lowlevel_init.S b/cpu/arm926ejs/davinci/lowlevel_init.S index a87c112eca4..0a4b2cf674d 100644 --- a/cpu/arm926ejs/davinci/lowlevel_init.S +++ b/cpu/arm926ejs/davinci/lowlevel_init.S @@ -110,7 +110,7 @@ checkGemStatClkStop: str r10, [r6] /*------------------------------------------------------* - * DDR2 PLL Initialization * + * DDR2 PLL Initialization * *------------------------------------------------------*/ /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */ @@ -547,7 +547,7 @@ VTP1Lock: /* * Call board-specific lowlevel init. - * That MUST be present and THAT returns + * That MUST be present and THAT returns * back to arch calling code with "mov pc, lr." */ b dv_board_init diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c index 127be9fcd43..ffc770fd1b9 100644 --- a/cpu/arm926ejs/davinci/nand.c +++ b/cpu/arm926ejs/davinci/nand.c @@ -325,17 +325,17 @@ static void nand_flash_init(void) * * *------------------------------------------------------------------*/ acfg1 = 0 - | (0 << 31 ) /* selectStrobe */ - | (0 << 30 ) /* extWait */ - | (1 << 26 ) /* writeSetup 10 ns */ - | (3 << 20 ) /* writeStrobe 40 ns */ - | (1 << 17 ) /* writeHold 10 ns */ - | (1 << 13 ) /* readSetup 10 ns */ - | (5 << 7 ) /* readStrobe 60 ns */ - | (1 << 4 ) /* readHold 10 ns */ - | (3 << 2 ) /* turnAround ?? ns */ - | (0 << 0 ) /* asyncSize 8-bit bus */ - ; + | (0 << 31 ) /* selectStrobe */ + | (0 << 30 ) /* extWait */ + | (1 << 26 ) /* writeSetup 10 ns */ + | (3 << 20 ) /* writeStrobe 40 ns */ + | (1 << 17 ) /* writeHold 10 ns */ + | (1 << 13 ) /* readSetup 10 ns */ + | (5 << 7 ) /* readStrobe 60 ns */ + | (1 << 4 ) /* readHold 10 ns */ + | (3 << 2 ) /* turnAround ?? ns */ + | (0 << 0 ) /* asyncSize 8-bit bus */ + ; emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; diff --git a/cpu/arm926ejs/interrupts.c b/cpu/arm926ejs/interrupts.c index 1819f6b0787..7a41f0b12d8 100644 --- a/cpu/arm926ejs/interrupts.c +++ b/cpu/arm926ejs/interrupts.c @@ -49,7 +49,7 @@ int interrupt_init (void) { extern void timer_init(void); - timer_init(); + timer_init(); return 0; } diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S index 297efe07c26..a61fa1847de 100644 --- a/cpu/arm926ejs/start.S +++ b/cpu/arm926ejs/start.S @@ -175,7 +175,7 @@ stack_setup: clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 @@ -370,7 +370,7 @@ not_used: irq: get_irq_stack irq_save_user_regs - bl do_irq + bl do_irq irq_restore_user_regs .align 5 @@ -378,7 +378,7 @@ fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs - bl do_fiq + bl do_fiq irq_restore_user_regs #else diff --git a/cpu/arm946es/start.S b/cpu/arm946es/start.S index e8c908bf281..9e97f530f8a 100644 --- a/cpu/arm946es/start.S +++ b/cpu/arm946es/start.S @@ -167,7 +167,7 @@ stack_setup: clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 @@ -358,7 +358,7 @@ not_used: irq: get_irq_stack irq_save_user_regs - bl do_irq + bl do_irq irq_restore_user_regs .align 5 @@ -366,7 +366,7 @@ fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs - bl do_fiq + bl do_fiq irq_restore_user_regs #else diff --git a/cpu/arm_intcm/start.S b/cpu/arm_intcm/start.S index 75fe9174ab9..d5778a046c6 100644 --- a/cpu/arm_intcm/start.S +++ b/cpu/arm_intcm/start.S @@ -165,7 +165,7 @@ stack_setup: clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 @@ -339,7 +339,7 @@ not_used: irq: get_irq_stack irq_save_user_regs - bl do_irq + bl do_irq irq_restore_user_regs .align 5 @@ -348,7 +348,7 @@ fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs - bl do_fiq + bl do_fiq irq_restore_user_regs #else diff --git a/cpu/blackfin/flush.S b/cpu/blackfin/flush.S index 8072b8643ff..417f798f858 100644 --- a/cpu/blackfin/flush.S +++ b/cpu/blackfin/flush.S @@ -223,7 +223,7 @@ ENDPROC(_dcplb_flush) .align 4; page_prefix_table: -.byte4 0xFFFFFC00; /* 1K */ +.byte4 0xFFFFFC00; /* 1K */ .byte4 0xFFFFF000; /* 4K */ .byte4 0xFFF00000; /* 1M */ .byte4 0xFFC00000; /* 4M */ diff --git a/cpu/blackfin/i2c.c b/cpu/blackfin/i2c.c index 47be2587d54..60f03d47a15 100644 --- a/cpu/blackfin/i2c.c +++ b/cpu/blackfin/i2c.c @@ -302,7 +302,7 @@ void i2c_init(int speed, int slaveaddr) * i2c_probe: - Test if a chip answers for a given i2c address * * @chip: address of the chip which is searched for - * @return: 0 if a chip was found, -1 otherwhise + * @return: 0 if a chip was found, -1 otherwhise */ int i2c_probe(uchar chip) diff --git a/cpu/blackfin/serial.c b/cpu/blackfin/serial.c index 0dfee514234..406d9d023d6 100644 --- a/cpu/blackfin/serial.c +++ b/cpu/blackfin/serial.c @@ -4,7 +4,7 @@ * Copyright (c) 2005-2008 Analog Devices Inc. * * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>, - * BuyWays B.V. (www.buyways.nl) + * BuyWays B.V. (www.buyways.nl) * * Based heavily on: * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs. diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c index d0a73418827..640b25584a5 100644 --- a/cpu/i386/sc520.c +++ b/cpu/i386/sc520.c @@ -406,7 +406,7 @@ void reset_timer(void) ulong get_timer(ulong base) { /* fixme: 30 or 33 */ - return read_mmcr_word(SC520_GPTMR0CNT) / 33; + return read_mmcr_word(SC520_GPTMR0CNT) / 33; } void set_timer(ulong t) diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S index 8fc713d93bb..34322ea2514 100644 --- a/cpu/i386/sc520_asm.S +++ b/cpu/i386/sc520_asm.S @@ -512,7 +512,7 @@ dram_done: shrl $2, %eax movl %eax, %ebx -bank2: movl (%edi), %eax +bank2: movl (%edi), %eax movl %eax, %ecx andl $0x00800000, %ecx jz bank1 @@ -520,7 +520,7 @@ bank2: movl (%edi), %eax shll $6, %eax movl %eax, %ebx -bank1: movl (%edi), %eax +bank1: movl (%edi), %eax movl %eax, %ecx andl $0x00008000, %ecx jz bank0 @@ -528,7 +528,7 @@ bank1: movl (%edi), %eax shll $14, %eax movl %eax, %ebx -bank0: movl (%edi), %eax +bank0: movl (%edi), %eax movl %eax, %ecx andl $0x00000080, %ecx jz done @@ -563,7 +563,7 @@ set_ecc: xorl %eax, %eax shrl $2, %ecx cld - rep stosl + rep stosl /* enable read, write buffers */ movb $0x11, %al movl $DBCTL, %edi diff --git a/cpu/i386/start.S b/cpu/i386/start.S index 51a27aa21d2..264ac0940b6 100644 --- a/cpu/i386/start.S +++ b/cpu/i386/start.S @@ -34,8 +34,8 @@ .globl _i386boot_start _i386boot_start: _start: - movl $0x18,%eax /* Load our segement registes, the - * gdt have already been loaded by start16.S */ + movl $0x18,%eax /* Load our segement registes, the + * gdt have already been loaded by start16.S */ movw %ax,%fs movw %ax,%ds movw %ax,%gs @@ -76,7 +76,7 @@ mem_init_ret: movl $.progress0a, %ebp jmp show_boot_progress .progress0a: - jmp die + jmp die mem_ok: /* indicate progress */ @@ -138,7 +138,7 @@ data_fail: movl $.progress2a, %ebp jmp show_boot_progress .progress2a: - jmp die + jmp die data_ok: @@ -162,7 +162,7 @@ bss: movl $0, (%edi) add $4, %edi loop bss - jmp bss_ok + jmp bss_ok bss_fail: /* indicate (lack of) progress */ @@ -170,7 +170,7 @@ bss_fail: movl $.progress3a, %ebp jmp show_boot_progress .progress3a: - jmp die + jmp die bss_ok: diff --git a/cpu/i386/start16.S b/cpu/i386/start16.S index 239f2ff39b2..1ebb6bc8b63 100644 --- a/cpu/i386/start16.S +++ b/cpu/i386/start16.S @@ -39,74 +39,74 @@ start16: board_init16_ret: /* Turn of cache (this might require a 486-class CPU) */ - movl %cr0, %eax - orl $0x60000000,%eax - movl %eax, %cr0 + movl %cr0, %eax + orl $0x60000000,%eax + movl %eax, %cr0 wbinvd /* load the descriptor tables */ o32 cs lidt idt_ptr -o32 cs lgdt gdt_ptr +o32 cs lgdt gdt_ptr /* Now, we enter protected mode */ - movl %cr0, %eax - orl $1,%eax - movl %eax, %cr0 + movl %cr0, %eax + orl $1,%eax + movl %eax, %cr0 /* Flush the prefetch queue */ - jmp ff + jmp ff ff: /* Finally jump to the 32bit initialization code */ movw $code32start, %ax - movw %ax,%bp + movw %ax,%bp o32 cs ljmp *(%bp) /* 48-bit far pointer */ code32start: - .long _start /* offset */ - .word 0x10 /* segment */ + .long _start /* offset */ + .word 0x10 /* segment */ idt_ptr: - .word 0 /* limit */ - .long 0 /* base */ + .word 0 /* limit */ + .long 0 /* base */ gdt_ptr: - .word 0x30 /* limit (48 bytes = 6 GDT entries) */ - .long BOOT_SEG + gdt /* base */ + .word 0x30 /* limit (48 bytes = 6 GDT entries) */ + .long BOOT_SEG + gdt /* base */ /* The GDT table ... * - * Selector Type - * 0x00 NULL - * 0x08 Unused + * Selector Type + * 0x00 NULL + * 0x08 Unused * 0x10 32bit code * 0x18 32bit data/stack * 0x20 16bit code - * 0x28 16bit data/stack + * 0x28 16bit data/stack */ gdt: - .word 0, 0, 0, 0 /* NULL */ - .word 0, 0, 0, 0 /* unused */ - - .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ - .word 0 /* base address = 0 */ - .word 0x9B00 /* code read/exec */ - .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ - - .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ - .word 0x0 /* base address = 0 */ - .word 0x9300 /* data read/write */ - .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ - - .word 0xFFFF /* 64kb */ - .word 0 /* base address = 0 */ - .word 0x9b00 /* data read/write */ - .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ - - .word 0xFFFF /* 64kb */ - .word 0 /* base address = 0 */ - .word 0x9300 /* data read/write */ - .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ + .word 0, 0, 0, 0 /* NULL */ + .word 0, 0, 0, 0 /* unused */ + + .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ + .word 0 /* base address = 0 */ + .word 0x9B00 /* code read/exec */ + .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ + + .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ + .word 0x0 /* base address = 0 */ + .word 0x9300 /* data read/write */ + .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ + + .word 0xFFFF /* 64kb */ + .word 0 /* base address = 0 */ + .word 0x9b00 /* data read/write */ + .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ + + .word 0xFFFF /* 64kb */ + .word 0 /* base address = 0 */ + .word 0x9300 /* data read/write */ + .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ diff --git a/cpu/ixp/npe/IxEthAcc.c b/cpu/ixp/npe/IxEthAcc.c index d981649da68..061b24bb505 100644 --- a/cpu/ixp/npe/IxEthAcc.c +++ b/cpu/ixp/npe/IxEthAcc.c @@ -215,7 +215,7 @@ PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId) if ( ! IX_ETH_ACC_IS_SERVICE_INITIALIZED() ) { - return(IX_ETH_ACC_FAIL); + return(IX_ETH_ACC_FAIL); } /* @@ -235,8 +235,8 @@ PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId) if ( IX_ETH_IS_PORT_INITIALIZED(portId) ) { - /* Already initialized */ - return(IX_ETH_ACC_FAIL); + /* Already initialized */ + return(IX_ETH_ACC_FAIL); } if(ixEthAccMacInit(portId)!=IX_ETH_ACC_SUCCESS) diff --git a/cpu/ixp/npe/IxEthAccCommon.c b/cpu/ixp/npe/IxEthAccCommon.c index bda2c447929..211203dffd5 100644 --- a/cpu/ixp/npe/IxEthAccCommon.c +++ b/cpu/ixp/npe/IxEthAccCommon.c @@ -96,7 +96,7 @@ extern IxEthAccInfo ixEthAccDataInfo; IX_ETH_ACC_PRIVATE IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate = { - IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */ + IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */ "Eth Rx Q", ixEthRxFrameQMCallback, /**< Functional callback */ (IxQMgrCallbackId) 0, /**< Callback tag */ @@ -104,7 +104,7 @@ IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate = IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ TRUE, /**< Enable Q notification at startup */ IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ + IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */ }; @@ -116,7 +116,7 @@ IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate = IX_ETH_ACC_PRIVATE IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate = { - IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */ + IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */ "Eth Rx Q", ixEthRxFrameQMCallback, /**< Functional callback */ (IxQMgrCallbackId) 0, /**< Callback tag */ @@ -124,7 +124,7 @@ IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate = IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ TRUE, /**< Enable Q notification at startup */ IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ + IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */ }; @@ -146,7 +146,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ FALSE, /**< Disable Q notification at startup */ IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /***< Q Low water mark */ + IX_QMGR_Q_WM_LEVEL0, /***< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ }, @@ -159,7 +159,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ FALSE, /**< Disable Q notification at startup */ IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ + IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ }, #ifdef __ixp46X @@ -172,7 +172,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ FALSE, /**< Disable Q notification at startup */ IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ + IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ }, #endif @@ -185,7 +185,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ FALSE, /**< Disable Q notification at startup */ IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ + IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ }, @@ -198,7 +198,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ FALSE, /**< Disable Q notification at startup */ IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ + IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ }, #ifdef __ixp46X @@ -211,7 +211,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= IX_QMGR_Q_ENTRY_SIZE1, /** Queue Entry Sizes - all Q entries are single ord entries */ FALSE, /** Disable Q notification at startup */ IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE, /** Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /* No queues use almost empty */ + IX_QMGR_Q_WM_LEVEL0, /* No queues use almost empty */ IX_QMGR_Q_WM_LEVEL64, /** Q High water mark - needed used */ }, #endif @@ -224,7 +224,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ TRUE, /**< Enable Q notification at startup */ IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ + IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL2, /**< Q High water mark - needed by NPE */ }, diff --git a/cpu/ixp/npe/IxEthAccDataPlane.c b/cpu/ixp/npe/IxEthAccDataPlane.c index e46fc9b25a9..b62f0d016e2 100644 --- a/cpu/ixp/npe/IxEthAccDataPlane.c +++ b/cpu/ixp/npe/IxEthAccDataPlane.c @@ -544,7 +544,7 @@ ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf) IX_OSAL_MBUF_MLEN(ptr) = (len >> IX_ETHNPE_ACC_LENGTH_OFFSET); /* get the next pointer */ - PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr); + PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr); if (nextPtr != NULL) { nextPtr = (IX_OSAL_MBUF *)((UINT8 *)nextPtr - offsetof(IX_OSAL_MBUF,ix_ne)); diff --git a/cpu/ixp/npe/IxEthAccMac.c b/cpu/ixp/npe/IxEthAccMac.c index d57e71678ef..369ee91d946 100644 --- a/cpu/ixp/npe/IxEthAccMac.c +++ b/cpu/ixp/npe/IxEthAccMac.c @@ -2423,14 +2423,14 @@ ixEthAccMacStateUpdate(IxEthAccPortId portId) REG_READ(ixEthAccMacBase[portId], IX_ETH_ACC_MAC_RX_CNTRL1, regval); - REG_WRITE(ixEthAccMacBase[portId], + REG_WRITE(ixEthAccMacBase[portId], IX_ETH_ACC_MAC_RX_CNTRL1, regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN); REG_READ(ixEthAccMacBase[portId], IX_ETH_ACC_MAC_TX_CNTRL1, regval); - REG_WRITE(ixEthAccMacBase[portId], + REG_WRITE(ixEthAccMacBase[portId], IX_ETH_ACC_MAC_TX_CNTRL1, regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN); } @@ -2493,7 +2493,7 @@ ixEthAccMacStateUpdate(IxEthAccPortId portId) REG_READ(ixEthAccMacBase[portId], IX_ETH_ACC_MAC_TX_CNTRL1, regval); - REG_WRITE(ixEthAccMacBase[portId], + REG_WRITE(ixEthAccMacBase[portId], IX_ETH_ACC_MAC_TX_CNTRL1, regval | IX_ETH_ACC_TX_CNTRL1_TX_EN); } diff --git a/cpu/ixp/npe/IxEthAccMii.c b/cpu/ixp/npe/IxEthAccMii.c index 86368a4734d..d282aa6725b 100644 --- a/cpu/ixp/npe/IxEthAccMii.c +++ b/cpu/ixp/npe/IxEthAccMii.c @@ -324,7 +324,7 @@ ixEthAccMiiWriteRtn (UINT8 phyAddr, /*The "GO" bit is reset to 0 when the write completes*/ if((regval & IX_ETH_ACC_MII_GO) == 0x0) - { + { break; } /* Sleep for a while */ diff --git a/cpu/ixp/npe/IxNpeDlImageMgr.c b/cpu/ixp/npe/IxNpeDlImageMgr.c index 75b42f2f8fa..ccc0da7ebde 100644 --- a/cpu/ixp/npe/IxNpeDlImageMgr.c +++ b/cpu/ixp/npe/IxNpeDlImageMgr.c @@ -164,7 +164,7 @@ ixNpeDlImageMgrImageIdCompare (IxNpeDlImageId *imageIdA, PRIVATE BOOL ixNpeDlImageMgrNpeFunctionIdCompare (IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB); + IxNpeDlImageId *imageIdB); #if 0 PRIVATE IX_STATUS diff --git a/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c b/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c index 9dcf3c1e4d2..18cac502088 100644 --- a/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c +++ b/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c @@ -613,9 +613,9 @@ ixNpeDlNpeMgrLogicalRegWrite ( if (verify) { - status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr, - regSize, ctxtNum, &retRegVal); - + status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr, + regSize, ctxtNum, &retRegVal); + if (IX_SUCCESS == status) { if (regVal != retRegVal) diff --git a/cpu/ixp/npe/IxOsalIoMem.c b/cpu/ixp/npe/IxOsalIoMem.c index 9e540c18e06..34df92bf79f 100644 --- a/cpu/ixp/npe/IxOsalIoMem.c +++ b/cpu/ixp/npe/IxOsalIoMem.c @@ -281,7 +281,7 @@ ixOsalIoMemUnmap (UINT32 requestedAddress, UINT32 endianType) * Return value: corresponding physical address, or NULL * if there is no physical address addressable * by the given virtual address - * OS: VxWorks, Linux, WinCE, QNX, eCos + * OS: VxWorks, Linux, WinCE, QNX, eCos * Reentrant: Yes * IRQ safe: Yes */ @@ -310,7 +310,7 @@ ixOsalIoMemVirtToPhys (UINT32 virtualAddress, UINT32 requestedCoherency) * Return value: corresponding physical address, or NULL * if there is no physical address addressable * by the given virtual address - * OS: VxWorks, Linux, WinCE, QNX, eCos + * OS: VxWorks, Linux, WinCE, QNX, eCos * Reentrant: Yes * IRQ safe: Yes */ diff --git a/cpu/ixp/npe/IxQMgrAqmIf.c b/cpu/ixp/npe/IxQMgrAqmIf.c index b27b3a28774..738651322c8 100644 --- a/cpu/ixp/npe/IxQMgrAqmIf.c +++ b/cpu/ixp/npe/IxQMgrAqmIf.c @@ -209,7 +209,7 @@ ixQMgrAqmIfInit (void) */ /* AQM Queue access reg addresses, per queue */ - ixQMgrAqmIfQueAccRegAddr[i] = + ixQMgrAqmIfQueAccRegAddr[i] = (UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i)); ixQMgrQInlinedReadWriteInfo[i].qAccRegAddr = (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i)); diff --git a/cpu/ixp/npe/IxQMgrQAccess.c b/cpu/ixp/npe/IxQMgrQAccess.c index 2c3e302696c..8885736246d 100644 --- a/cpu/ixp/npe/IxQMgrQAccess.c +++ b/cpu/ixp/npe/IxQMgrQAccess.c @@ -360,7 +360,7 @@ ixQMgrQNumEntriesGet (IxQMgrQId qId, } else { - /* The queue is either empty, either moving, + /* The queue is either empty, either moving, * Client can retry if they wish */ *numEntriesPtr = 0; diff --git a/cpu/ixp/npe/include/IxDmaAcc.h b/cpu/ixp/npe/include/IxDmaAcc.h index 53d26255912..45c7527de9d 100644 --- a/cpu/ixp/npe/include/IxDmaAcc.h +++ b/cpu/ixp/npe/include/IxDmaAcc.h @@ -172,7 +172,7 @@ typedef UINT32 IxDmaAccRequestId; #define IX_DMA_REQUEST_FULL 16 /** - * @ingroup IxDmaAcc + * @ingroup IxDmaAcc * @brief DMA completion notification * This function is called to notify a client that the DMA has been completed * @param status @ref IxDmaReturnStatus [out] - reporting to client @@ -181,11 +181,11 @@ typedef UINT32 IxDmaAccRequestId; typedef void (*IxDmaAccDmaCompleteCallback) (IxDmaReturnStatus status); /** - * @ingroup IxDmaAcc + * @ingroup IxDmaAcc * * @fn ixDmaAccInit(IxNpeDlNpeId npeId) * - * @brief Initialise the DMA Access component + * @brief Initialise the DMA Access component * This function will initialise the DMA Access component internals * @param npeId @ref IxNpeDlNpeId [in] - NPE to use for Dma Transfer * @return @li IX_SUCCESS succesfully initialised the component @@ -196,7 +196,7 @@ PUBLIC IX_STATUS ixDmaAccInit(IxNpeDlNpeId npeId); /** - * @ingroup IxDmaAcc + * @ingroup IxDmaAcc * * @fn ixDmaAccDmaTransfer( IxDmaAccDmaCompleteCallback callback, @@ -225,8 +225,8 @@ ixDmaAccInit(IxNpeDlNpeId npeId); * @param AddressingMode @ref IxDmaAddressingMode [in] - The DMA addressing mode * @param TransferWidth @ref IxDmaTransferWidth [in] - The DMA transfer width * - * @return @li IX_DMA_SUCCESS Notification that the DMA request is succesful - * @return @li IX_DMA_FAIL IxDmaAcc not yet initialised or some internal error has occured + * @return @li IX_DMA_SUCCESS Notification that the DMA request is succesful + * @return @li IX_DMA_FAIL IxDmaAcc not yet initialised or some internal error has occured * @return @li IX_DMA_INVALID_TRANSFER_WIDTH Transfer width is nit valid * @return @li IX_DMA_INVALID_TRANSFER_LENGTH Transfer length outside of valid range * @return @li IX_DMA_INVALID_TRANSFER_MODE Transfer Mode not valid diff --git a/cpu/ixp/npe/include/IxEthAcc.h b/cpu/ixp/npe/include/IxEthAcc.h index b424648e9d8..ff706c451de 100644 --- a/cpu/ixp/npe/include/IxEthAcc.h +++ b/cpu/ixp/npe/include/IxEthAcc.h @@ -626,8 +626,8 @@ PUBLIC void ixEthAccUnload(void); * required features. * * Dependant on Services: (Must be initialized before using this service may be initialized) - * ixNPEmh - NPE Message handling service. - * ixQmgr - Queue Manager component. + * ixNPEmh - NPE Message handling service. + * ixQmgr - Queue Manager component. * * @param portId @ref IxEthAccPortId [in] * @@ -745,7 +745,7 @@ typedef void (*IxEthAccPortTxDoneCallback) ( UINT32 callbackTag, IX_OSAL_MBUF *b * * @fn ixEthAccPortTxDoneCallbackRegister( IxEthAccPortId portId, IxEthAccPortTxDoneCallback txCallbackFn, - UINT32 callbackTag) + UINT32 callbackTag) * * @brief Register a callback function to allow * the transmitted buffers to return to the user. diff --git a/cpu/ixp/npe/include/IxEthAccMii_p.h b/cpu/ixp/npe/include/IxEthAccMii_p.h index aa42f9c2a1c..568d4a0fa4f 100644 --- a/cpu/ixp/npe/include/IxEthAccMii_p.h +++ b/cpu/ixp/npe/include/IxEthAccMii_p.h @@ -81,13 +81,13 @@ #define IX_ETH_ACC_MII_STAT_REG 0x1 /* Status Register */ #define IX_ETH_ACC_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */ #define IX_ETH_ACC_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */ -#define IX_ETH_ACC_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */ +#define IX_ETH_ACC_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */ /* Advertisement Register */ -#define IX_ETH_ACC_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */ +#define IX_ETH_ACC_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */ /* partner ability Register */ #define IX_ETH_ACC_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */ /* Expansion Register */ -#define IX_ETH_ACC_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */ +#define IX_ETH_ACC_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */ /* next-page transmit Register */ IxEthAccStatus ixEthAccMdioShow (void); diff --git a/cpu/ixp/npe/include/IxEthAcc_p.h b/cpu/ixp/npe/include/IxEthAcc_p.h index 37c55605d34..0ee4123557e 100644 --- a/cpu/ixp/npe/include/IxEthAcc_p.h +++ b/cpu/ixp/npe/include/IxEthAcc_p.h @@ -262,7 +262,7 @@ typedef struct { IxEthAccPortTxDoneCallback txBufferDoneCallbackFn; UINT32 txCallbackTag; - IxEthAccDataPlaneQList txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */ + IxEthAccDataPlaneQList txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */ IxEthAccSchedulerDiscipline schDiscipline; /**< Transmit Xscale QoS */ IxQMgrQId txQueue; /**< txQueue for this port */ IxEthAccTxDataStats stats; /**< Transmit s/w stats */ diff --git a/cpu/ixp/npe/include/IxEthMii.h b/cpu/ixp/npe/include/IxEthMii.h index a1bfe067241..397253a9474 100644 --- a/cpu/ixp/npe/include/IxEthMii.h +++ b/cpu/ixp/npe/include/IxEthMii.h @@ -106,9 +106,9 @@ PUBLIC IX_STATUS ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount); * @ingroup IxEthMii * * @fn ixEthMiiPhyConfig(UINT32 phyAddr, - BOOL speed100, - BOOL fullDuplex, - BOOL autonegotiate) + BOOL speed100, + BOOL fullDuplex, + BOOL autonegotiate) * * * @brief Configure a PHY @@ -209,10 +209,10 @@ PUBLIC IX_STATUS ixEthMiiPhyReset(UINT32 phyAddr); * @ingroup IxEthMii * * @fn ixEthMiiLinkStatus(UINT32 phyAddr, - BOOL *linkUp, - BOOL *speed100, - BOOL *fullDuplex, - BOOL *autoneg) + BOOL *linkUp, + BOOL *speed100, + BOOL *fullDuplex, + BOOL *autoneg) * * @brief Retrieve the current status of a PHY * Retrieve the link, speed, duplex and autonegotiation status of a PHY diff --git a/cpu/ixp/npe/include/IxI2cDrv.h b/cpu/ixp/npe/include/IxI2cDrv.h index 2472f31a710..92c6b24b46e 100644 --- a/cpu/ixp/npe/include/IxI2cDrv.h +++ b/cpu/ixp/npe/include/IxI2cDrv.h @@ -64,8 +64,8 @@ /** * @ingroup IxI2cDrv * @brief The interval of micro/mili seconds the IXP will wait before it polls for - * status from the ixI2cIntrXferStatus; Every 20us is 1 byte @ - * 400Kbps and 4 bytes @ 100Kbps. This is dependent on delay type selected + * status from the ixI2cIntrXferStatus; Every 20us is 1 byte @ + * 400Kbps and 4 bytes @ 100Kbps. This is dependent on delay type selected * through the API ixI2cDrvDelayTypeSelect. */ #define IX_I2C_US_POLL_FOR_XFER_STATUS 20 diff --git a/cpu/ixp/npe/include/IxOsalAssert.h b/cpu/ixp/npe/include/IxOsalAssert.h index 45cebcdaa6b..04a4f515aa9 100644 --- a/cpu/ixp/npe/include/IxOsalAssert.h +++ b/cpu/ixp/npe/include/IxOsalAssert.h @@ -1,6 +1,6 @@ /* * @file IxOsalAssert.h - * @author Intel Corporation + * @author Intel Corporation * @date 25-08-2004 * * @brief description goes here diff --git a/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h b/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h index 5ac3f0cac00..4cf80d31eb7 100644 --- a/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h +++ b/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h @@ -76,7 +76,7 @@ typedef IX_OSAL_MBUF_POOL IX_MBUF_POOL; #define IX_MBUF_MTYPE(m_blk_ptr) \ IX_OSAL_MBUF_MTYPE(m_blk_ptr) -#define IX_MBUF_FLAGS(m_blk_ptr) \ +#define IX_MBUF_FLAGS(m_blk_ptr) \ IX_OSAL_MBUF_FLAGS(m_blk_ptr) diff --git a/cpu/ixp/npe/include/IxOsalBackwardMemMap.h b/cpu/ixp/npe/include/IxOsalBackwardMemMap.h index 18f8f24df44..3881a3b6dac 100644 --- a/cpu/ixp/npe/include/IxOsalBackwardMemMap.h +++ b/cpu/ixp/npe/include/IxOsalBackwardMemMap.h @@ -136,6 +136,6 @@ #define IX_OSSERV_MEM_MAP(physAddr, size) IX_OSAL_MEM_MAP(physAddr, size) -#define IX_OSSERV_MEM_UNMAP(virtAddr) IX_OSAL_MEM_UNMAP(virtAddr) +#define IX_OSSERV_MEM_UNMAP(virtAddr) IX_OSAL_MEM_UNMAP(virtAddr) #endif /* IX_OSAL_BACKWARD_MEM_MAP_H */ diff --git a/cpu/ixp/npe/include/IxOsalIoMem.h b/cpu/ixp/npe/include/IxOsalIoMem.h index ac0ce657037..ea6d64d0006 100644 --- a/cpu/ixp/npe/include/IxOsalIoMem.h +++ b/cpu/ixp/npe/include/IxOsalIoMem.h @@ -1,6 +1,6 @@ /* * @file IxOsalIoMem.h - * @author Intel Corporation + * @author Intel Corporation * @date 25-08-2004 * * @brief description goes here diff --git a/cpu/ixp/npe/include/IxOsalMemAccess.h b/cpu/ixp/npe/include/IxOsalMemAccess.h index 2ad0ccfbb27..9e7fb87be5b 100644 --- a/cpu/ixp/npe/include/IxOsalMemAccess.h +++ b/cpu/ixp/npe/include/IxOsalMemAccess.h @@ -410,7 +410,7 @@ ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData) #define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_BE(wAddr) #define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_BE(sAddr) #define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_BE(bAddr) -#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_BE(wAddr, wData) +#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_BE(wAddr, wData) #define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_BE(sAddr, sData) #define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_BE(bAddr, bData) @@ -419,7 +419,7 @@ ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData) #define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_LE_AC(wAddr) #define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_LE_AC(sAddr) #define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_LE_AC(bAddr) -#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData) +#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData) #define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData) #define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData) @@ -428,7 +428,7 @@ ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData) #define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_LE_DC(wAddr) #define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_LE_DC(sAddr) #define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_LE_DC(bAddr) -#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData) +#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData) #define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData) #define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData) diff --git a/cpu/ixp/npe/include/IxOsalTypes.h b/cpu/ixp/npe/include/IxOsalTypes.h index c617ec57813..a190a707e32 100644 --- a/cpu/ixp/npe/include/IxOsalTypes.h +++ b/cpu/ixp/npe/include/IxOsalTypes.h @@ -175,7 +175,7 @@ typedef volatile INT32 VINT32; #ifndef __inline__ -#define __inline__ IX_OSAL_INLINE +#define __inline__ IX_OSAL_INLINE #endif diff --git a/cpu/ixp/npe/include/IxQMgr.h b/cpu/ixp/npe/include/IxQMgr.h index c083a2b322d..165ed96e545 100644 --- a/cpu/ixp/npe/include/IxQMgr.h +++ b/cpu/ixp/npe/include/IxQMgr.h @@ -1134,7 +1134,7 @@ ixQMgrQRead (IxQMgrQId qId, * day scenario there are many entries in the queue * and the counter does not reach zero. */ - if (infoPtr->qReadCount-- == 0) + if (infoPtr->qReadCount-- == 0) { /* There is maybe no entry in the queue * qReadCount is now negative, but will be corrected before @@ -1475,7 +1475,7 @@ ixQMgrQWrite (IxQMgrQId qId, ++entry; IX_QMGR_INLINE_WRITE_LONG(++qAccRegAddr, *entry); } - entrySize = infoPtr->qEntrySizeInWords; + entrySize = infoPtr->qEntrySizeInWords; } /* overflow is available for lower queues only */ diff --git a/cpu/ixp/npe/include/IxQMgrAqmIf_p.h b/cpu/ixp/npe/include/IxQMgrAqmIf_p.h index 7f5733c5d24..4f0f64d273c 100644 --- a/cpu/ixp/npe/include/IxQMgrAqmIf_p.h +++ b/cpu/ixp/npe/include/IxQMgrAqmIf_p.h @@ -498,7 +498,7 @@ ixQMgrAqmIfQPop (IxQMgrQId qId, volatile UINT32 *accRegAddr; accRegAddr = (UINT32*)(aqmBaseAddress + - IX_QMGR_Q_ACCESS_ADDR_GET(qId)); + IX_QMGR_Q_ACCESS_ADDR_GET(qId)); switch (numWords) { @@ -533,7 +533,7 @@ ixQMgrAqmIfQPush (IxQMgrQId qId, volatile UINT32 *accRegAddr; accRegAddr = (UINT32*)(aqmBaseAddress + - IX_QMGR_Q_ACCESS_ADDR_GET(qId)); + IX_QMGR_Q_ACCESS_ADDR_GET(qId)); switch (numWords) { @@ -683,9 +683,9 @@ ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId, * multiple queues split accross registers */ registerAddress = (UINT32*)(aqmBaseAddress + - registerBaseAddrOffset + - ((qId / queuesPerRegWord) * - IX_QMGR_NUM_BYTES_PER_WORD)); + registerBaseAddrOffset + + ((qId / queuesPerRegWord) * + IX_QMGR_NUM_BYTES_PER_WORD)); /* * Get the status word diff --git a/cpu/ixp/npe/include/IxQueueAssignments.h b/cpu/ixp/npe/include/IxQueueAssignments.h index 0c1543fa792..f7194e72ec4 100644 --- a/cpu/ixp/npe/include/IxQueueAssignments.h +++ b/cpu/ixp/npe/include/IxQueueAssignments.h @@ -409,7 +409,7 @@ * @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration * */ -#define IX_ETH_ACC_RX_FRAME_ETH_Q (IX_QMGR_QUEUE_4) +#define IX_ETH_ACC_RX_FRAME_ETH_Q (IX_QMGR_QUEUE_4) /** * diff --git a/cpu/ixp/pci.c b/cpu/ixp/pci.c index 84c4339ee6b..8c6b0b21b48 100644 --- a/cpu/ixp/pci.c +++ b/cpu/ixp/pci.c @@ -259,7 +259,7 @@ void pci_ixp_init (struct pci_controller *hose) /* ========================================================== - Init IXP PCI + Init IXP PCI ========================================================== */ REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); diff --git a/cpu/ixp/start.S b/cpu/ixp/start.S index 757cfaa2d5f..d4c8e33bc5e 100644 --- a/cpu/ixp/start.S +++ b/cpu/ixp/start.S @@ -140,7 +140,7 @@ reset: CPWAIT r0 /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 + mcr p15, 0, r0, c8, c7, 0 CPWAIT r0 /* drain write and fill buffers */ @@ -160,22 +160,22 @@ reset: /* make sure flash is visible at 0 */ #if 0 - ldr r2, =IXP425_EXP_CFG0 + ldr r2, =IXP425_EXP_CFG0 ldr r1, [r2] orr r1, r1, #0x80000000 str r1, [r2] #endif - mov r1, #CFG_SDR_CONFIG + mov r1, #CFG_SDR_CONFIG ldr r2, =IXP425_SDR_CONFIG str r1, [r2] /* disable refresh cycles */ - mov r1, #0 + mov r1, #0 ldr r3, =IXP425_SDR_REFRESH str r1, [r3] /* send nop command */ - mov r1, #3 + mov r1, #3 ldr r4, =IXP425_SDR_IR str r1, [r4] DELAY_FOR 0x4000, r0 @@ -226,7 +226,7 @@ reset: CPWAIT r0 /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 + mcr p15, 0, r0, c8, c7, 0 CPWAIT r0 /* drain write and fill buffers */ @@ -234,7 +234,7 @@ reset: CPWAIT r0 /* move flash to 0x50000000 */ - ldr r2, =IXP425_EXP_CFG0 + ldr r2, =IXP425_EXP_CFG0 ldr r1, [r2] bic r1, r1, #0x80000000 str r1, [r2] @@ -247,7 +247,7 @@ reset: nop /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 + mcr p15, 0, r0, c8, c7, 0 CPWAIT r0 /* enable I cache */ @@ -293,7 +293,7 @@ stack_setup: clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 @@ -482,13 +482,13 @@ fiq: .globl reset_cpu reset_cpu: - ldr r1, =0x482e + ldr r1, =0x482e ldr r2, =IXP425_OSWK str r1, [r2] - ldr r1, =0x0fff + ldr r1, =0x0fff ldr r2, =IXP425_OSWT str r1, [r2] - ldr r1, =0x5 + ldr r1, =0x5 ldr r2, =IXP425_OSWE str r1, [r2] b reset_endless diff --git a/cpu/leon2/start.S b/cpu/leon2/start.S index 60d3fadef49..f23f4993716 100644 --- a/cpu/leon2/start.S +++ b/cpu/leon2/start.S @@ -31,10 +31,10 @@ /* Entry for traps which jump to a programmer-specified trap handler. */ #define TRAPR(H) \ - wr %g0, 0xfe0, %psr; \ - mov %g0, %tbr; \ - ba (H); \ - mov %g0, %wim; + wr %g0, 0xfe0, %psr; \ + mov %g0, %tbr; \ + ba (H); \ + mov %g0, %wim; #define TRAP(H) \ mov %psr, %l0; \ @@ -42,10 +42,10 @@ nop; nop; #define TRAPI(ilevel) \ - mov ilevel, %l7; \ - mov %psr, %l0; \ - b _irq_entry; \ - mov %wim, %l3 + mov ilevel, %l7; \ + mov %psr, %l0; \ + b _irq_entry; \ + mov %wim, %l3 /* Unexcpected trap will halt the processor by forcing it to error state */ #undef BAD_TRAP @@ -76,7 +76,7 @@ MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4) #define SA(X) (((X)+(STACK_ALIGN-1)) & ~(STACK_ALIGN-1)) .section ".start", "ax" - .globl _start, start, _trap_table + .globl _start, start, _trap_table .globl _irq_entry, nmi_trap .globl _reset_reloc @@ -515,7 +515,7 @@ _window_underflow: nop; nop; nop restore ! Two restores to get into the restore ! window to restore - ld [%sp + 0], %l0; ! Restore window from the stack + ld [%sp + 0], %l0; ! Restore window from the stack ld [%sp + 4], %l1; ld [%sp + 8], %l2; ld [%sp + 12], %l3; @@ -547,7 +547,7 @@ _hwerr: ta 0 nop nop - b _hwerr ! loop infinite + b _hwerr ! loop infinite nop /* Registers to not touch at all. */ diff --git a/cpu/leon3/start.S b/cpu/leon3/start.S index 2f1d099e374..d421898d883 100644 --- a/cpu/leon3/start.S +++ b/cpu/leon3/start.S @@ -31,10 +31,10 @@ /* Entry for traps which jump to a programmer-specified trap handler. */ #define TRAPR(H) \ - wr %g0, 0xfe0, %psr; \ - mov %g0, %tbr; \ - ba (H); \ - mov %g0, %wim; + wr %g0, 0xfe0, %psr; \ + mov %g0, %tbr; \ + ba (H); \ + mov %g0, %wim; #define TRAP(H) \ mov %psr, %l0; \ @@ -42,10 +42,10 @@ nop; nop; #define TRAPI(ilevel) \ - mov ilevel, %l7; \ - mov %psr, %l0; \ - b _irq_entry; \ - mov %wim, %l3 + mov ilevel, %l7; \ + mov %psr, %l0; \ + b _irq_entry; \ + mov %wim, %l3 /* Unexcpected trap will halt the processor by forcing it to error state */ #undef BAD_TRAP @@ -76,7 +76,7 @@ MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4) #define SA(X) (((X)+(STACK_ALIGN-1)) & ~(STACK_ALIGN-1)) .section ".start", "ax" - .globl _start, start, _trap_table + .globl _start, start, _trap_table .globl _irq_entry, nmi_trap .globl _reset_reloc @@ -118,7 +118,7 @@ _trap_table: TRAPI(13); ! 1d IRQ level 13 TRAPI(14); ! 1e IRQ level 14 TRAP(_nmi_trap); ! 1f IRQ level 15 / - ! NMI (non maskable interrupt) + ! NMI (non maskable interrupt) BAD_TRAP; ! 20 r_register_access_error BAD_TRAP; ! 21 instruction access error BAD_TRAP; ! 22 @@ -470,7 +470,7 @@ _window_underflow: nop; nop; nop restore ! Two restores to get into the restore ! window to restore - ld [%sp + 0], %l0; ! Restore window from the stack + ld [%sp + 0], %l0; ! Restore window from the stack ld [%sp + 4], %l1; ld [%sp + 8], %l2; ld [%sp + 12], %l3; @@ -502,7 +502,7 @@ _hwerr: ta 0 nop nop - b _hwerr ! loop infinite + b _hwerr ! loop infinite nop /* Registers to not touch at all. */ diff --git a/cpu/lh7a40x/start.S b/cpu/lh7a40x/start.S index fb748cffc63..e4655d69b16 100644 --- a/cpu/lh7a40x/start.S +++ b/cpu/lh7a40x/start.S @@ -184,7 +184,7 @@ clear_bss: @add r0, r0, #4 /* start at first byte of bss */ /* why inc. 4 bytes past then? */ ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 @@ -347,31 +347,31 @@ cpu_init_crit: undefined_instruction: get_bad_stack bad_save_user_regs - bl do_undefined_instruction + bl do_undefined_instruction .align 5 software_interrupt: get_bad_stack bad_save_user_regs - bl do_software_interrupt + bl do_software_interrupt .align 5 prefetch_abort: get_bad_stack bad_save_user_regs - bl do_prefetch_abort + bl do_prefetch_abort .align 5 data_abort: get_bad_stack bad_save_user_regs - bl do_data_abort + bl do_data_abort .align 5 not_used: get_bad_stack bad_save_user_regs - bl do_not_used + bl do_not_used #ifdef CONFIG_USE_IRQ @@ -379,7 +379,7 @@ not_used: irq: get_irq_stack irq_save_user_regs - bl do_irq + bl do_irq irq_restore_user_regs .align 5 @@ -387,7 +387,7 @@ fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs - bl do_fiq + bl do_fiq irq_restore_user_regs #else @@ -396,13 +396,13 @@ fiq: irq: get_bad_stack bad_save_user_regs - bl do_irq + bl do_irq .align 5 fiq: get_bad_stack bad_save_user_regs - bl do_fiq + bl do_fiq #endif diff --git a/cpu/mcf523x/start.S b/cpu/mcf523x/start.S index ad04c0984a8..2b638dfef22 100644 --- a/cpu/mcf523x/start.S +++ b/cpu/mcf523x/start.S @@ -49,7 +49,7 @@ _vectors: INITSP: .long 0x00000000 /* Initial SP */ -INITPC: .long _START /* Initial PC */ +INITPC: .long _START /* Initial PC */ vector02: .long _FAULT /* Access Error */ vector03: .long _FAULT /* Address Error */ vector04: .long _FAULT /* Illegal Instruction */ diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 2bc0df39cad..a05490432fe 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -248,14 +248,14 @@ relocate_code: * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ - move.l %a0, %a1 + move.l %a0, %a1 add.l #(in_ram - CFG_MONITOR_BASE), %a1 jmp (%a1) in_ram: clear_bss: - /* + /* * Now clear BSS segment */ move.l %a0, %a1 @@ -416,7 +416,7 @@ icache_enable: * Note: The 5249 Documentation doesn't give a bit position for CINV! * From the 5272 and the 5307 documentation, I have deduced that it is * probably CACR[24]. Should someone say something to Motorola? - * ~Jeremy + * ~Jeremy */ move.l #0x01000000, %d0 /* Invalidate whole cache */ move.c %d0,%CACR diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S index a524f707830..c806f7a96e5 100644 --- a/cpu/mcf532x/start.S +++ b/cpu/mcf532x/start.S @@ -49,7 +49,7 @@ _vectors: INITSP: .long 0x00000000 /* Initial SP */ -INITPC: .long _START /* Initial PC */ +INITPC: .long _START /* Initial PC */ vector02: .long _FAULT /* Access Error */ vector03: .long _FAULT /* Address Error */ vector04: .long _FAULT /* Illegal Instruction */ diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S index 0c5194acdb0..3241b278e1c 100644 --- a/cpu/mcf5445x/start.S +++ b/cpu/mcf5445x/start.S @@ -54,7 +54,7 @@ _vectors: INITSP: .long 0x00000000 /* Initial SP */ -INITPC: .long _START /* Initial PC */ +INITPC: .long _START /* Initial PC */ vector02: .long _FAULT /* Access Error */ vector03: .long _FAULT /* Address Error */ vector04: .long _FAULT /* Illegal Instruction */ diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S index c12d7a0fcbb..8b8708d030b 100644 --- a/cpu/mcf547x_8x/start.S +++ b/cpu/mcf547x_8x/start.S @@ -54,7 +54,7 @@ _vectors: INITSP: .long 0x00000000 /* Initial SP */ -INITPC: .long _START /* Initial PC */ +INITPC: .long _START /* Initial PC */ vector02: .long _FAULT /* Access Error */ vector03: .long _FAULT /* Address Error */ vector04: .long _FAULT /* Illegal Instruction */ diff --git a/cpu/mips/asc_serial.c b/cpu/mips/asc_serial.c index d95ec3fd2fc..3498b61e8be 100644 --- a/cpu/mips/asc_serial.c +++ b/cpu/mips/asc_serial.c @@ -34,10 +34,10 @@ /* Interrupt status register bits */ #define FBS_ISR_AT 0x00000040 /* ASC transmit interrupt */ -#define FBS_ISR_AR 0x00000020 /* ASC receive interrupt */ +#define FBS_ISR_AR 0x00000020 /* ASC receive interrupt */ #define FBS_ISR_AE 0x00000010 /* ASC error interrupt */ #define FBS_ISR_AB 0x00000008 /* ASC transmit buffer interrupt */ -#define FBS_ISR_AS 0x00000004 /* ASC start of autobaud detection interrupt */ +#define FBS_ISR_AS 0x00000004 /* ASC start of autobaud detection interrupt */ #define FBS_ISR_AF 0x00000002 /* ASC end of autobaud detection interrupt */ #else diff --git a/cpu/mips/au1x00_usb_ohci.h b/cpu/mips/au1x00_usb_ohci.h index 4ef06ffdeb8..a606d459c26 100644 --- a/cpu/mips/au1x00_usb_ohci.h +++ b/cpu/mips/au1x00_usb_ohci.h @@ -11,31 +11,31 @@ static int cc_to_error[16] = { /* mapping of the OHCI CC status to error codes */ - /* No Error */ 0, - /* CRC Error */ USB_ST_CRC_ERR, - /* Bit Stuff */ USB_ST_BIT_ERR, - /* Data Togg */ USB_ST_CRC_ERR, - /* Stall */ USB_ST_STALLED, - /* DevNotResp */ -1, - /* PIDCheck */ USB_ST_BIT_ERR, - /* UnExpPID */ USB_ST_BIT_ERR, - /* DataOver */ USB_ST_BUF_ERR, - /* DataUnder */ USB_ST_BUF_ERR, - /* reservd */ -1, - /* reservd */ -1, - /* BufferOver */ USB_ST_BUF_ERR, - /* BuffUnder */ USB_ST_BUF_ERR, - /* Not Access */ -1, - /* Not Access */ -1 + /* No Error */ 0, + /* CRC Error */ USB_ST_CRC_ERR, + /* Bit Stuff */ USB_ST_BIT_ERR, + /* Data Togg */ USB_ST_CRC_ERR, + /* Stall */ USB_ST_STALLED, + /* DevNotResp */ -1, + /* PIDCheck */ USB_ST_BIT_ERR, + /* UnExpPID */ USB_ST_BIT_ERR, + /* DataOver */ USB_ST_BUF_ERR, + /* DataUnder */ USB_ST_BUF_ERR, + /* reservd */ -1, + /* reservd */ -1, + /* BufferOver */ USB_ST_BUF_ERR, + /* BuffUnder */ USB_ST_BUF_ERR, + /* Not Access */ -1, + /* Not Access */ -1 }; /* ED States */ -#define ED_NEW 0x00 -#define ED_UNLINK 0x01 +#define ED_NEW 0x00 +#define ED_UNLINK 0x01 #define ED_OPER 0x02 #define ED_DEL 0x04 -#define ED_URB_DEL 0x08 +#define ED_URB_DEL 0x08 /* usb_ohci_ed */ struct ed { @@ -61,54 +61,54 @@ typedef struct ed ed_t; /* TD info field */ -#define TD_CC 0xf0000000 -#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) -#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) -#define TD_EC 0x0C000000 -#define TD_T 0x03000000 -#define TD_T_DATA0 0x02000000 -#define TD_T_DATA1 0x03000000 -#define TD_T_TOGGLE 0x00000000 -#define TD_R 0x00040000 -#define TD_DI 0x00E00000 -#define TD_DI_SET(X) (((X) & 0x07)<< 21) -#define TD_DP 0x00180000 -#define TD_DP_SETUP 0x00000000 -#define TD_DP_IN 0x00100000 -#define TD_DP_OUT 0x00080000 - -#define TD_ISO 0x00010000 -#define TD_DEL 0x00020000 +#define TD_CC 0xf0000000 +#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) +#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) +#define TD_EC 0x0C000000 +#define TD_T 0x03000000 +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_T_TOGGLE 0x00000000 +#define TD_R 0x00040000 +#define TD_DI 0x00E00000 +#define TD_DI_SET(X) (((X) & 0x07)<< 21) +#define TD_DP 0x00180000 +#define TD_DP_SETUP 0x00000000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 + +#define TD_ISO 0x00010000 +#define TD_DEL 0x00020000 /* CC Codes */ -#define TD_CC_NOERROR 0x00 -#define TD_CC_CRC 0x01 -#define TD_CC_BITSTUFFING 0x02 -#define TD_CC_DATATOGGLEM 0x03 -#define TD_CC_STALL 0x04 -#define TD_DEVNOTRESP 0x05 -#define TD_PIDCHECKFAIL 0x06 -#define TD_UNEXPECTEDPID 0x07 -#define TD_DATAOVERRUN 0x08 -#define TD_DATAUNDERRUN 0x09 -#define TD_BUFFEROVERRUN 0x0C -#define TD_BUFFERUNDERRUN 0x0D -#define TD_NOTACCESSED 0x0F +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D +#define TD_NOTACCESSED 0x0F #define MAXPSW 1 struct td { __u32 hwINFO; - __u32 hwCBP; /* Current Buffer Pointer */ - __u32 hwNextTD; /* Next TD Pointer */ - __u32 hwBE; /* Memory Buffer End Pointer */ - - __u16 hwPSW[MAXPSW]; - __u8 unused; - __u8 index; - struct ed *ed; - struct td *next_dl_td; + __u32 hwCBP; /* Current Buffer Pointer */ + __u32 hwNextTD; /* Next TD Pointer */ + __u32 hwBE; /* Memory Buffer End Pointer */ + + __u16 hwPSW[MAXPSW]; + __u8 unused; + __u8 index; + struct ed *ed; + struct td *next_dl_td; struct usb_device *usb_dev; int transfer_len; __u32 data; @@ -142,7 +142,7 @@ struct ohci_hcca { /* * This is the structure of the OHCI controller's memory mapped I/O - * region. This is Memory Mapped I/O. You must use the readl() and + * region. This is Memory Mapped I/O. You must use the readl() and * writel() macros defined in asm/io.h to access these!! */ struct ohci_regs { @@ -202,10 +202,10 @@ struct ohci_regs { * HcCommandStatus (cmdstatus) register masks */ #define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ -#define OHCI_SOC (3 << 16) /* scheduling overrun count */ +#define OHCI_CLF (1 << 1) /* control list filled */ +#define OHCI_BLF (1 << 2) /* bulk list filled */ +#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_SOC (3 << 16) /* scheduling overrun count */ /* * masks used with interrupt registers: @@ -236,101 +236,101 @@ struct virt_root_hub { /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ /* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 /* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 #define RH_SET_ADDRESS 0x0500 #define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 +#define RH_SET_DESCRIPTOR 0x0700 #define RH_GET_CONFIGURATION 0x0880 #define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 /* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 +#define RH_SET_EP 0x2000 /* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 - -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 /* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 /* OHCI ROOT HUB REGISTER MASKS */ /* roothub.portstatus [i] bits */ -#define RH_PS_CCS 0x00000001 /* current connect status */ -#define RH_PS_PES 0x00000002 /* port enable status*/ -#define RH_PS_PSS 0x00000004 /* port suspend status */ -#define RH_PS_POCI 0x00000008 /* port over current indicator */ -#define RH_PS_PRS 0x00000010 /* port reset status */ -#define RH_PS_PPS 0x00000100 /* port power status */ -#define RH_PS_LSDA 0x00000200 /* low speed device attached */ -#define RH_PS_CSC 0x00010000 /* connect status change */ -#define RH_PS_PESC 0x00020000 /* port enable status change */ -#define RH_PS_PSSC 0x00040000 /* port suspend status change */ -#define RH_PS_OCIC 0x00080000 /* over current indicator change */ -#define RH_PS_PRSC 0x00100000 /* port reset status change */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status*/ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ /* roothub.status bits */ -#define RH_HS_LPS 0x00000001 /* local power status */ -#define RH_HS_OCI 0x00000002 /* over current indicator */ -#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ -#define RH_HS_LPSC 0x00010000 /* local power status change */ -#define RH_HS_OCIC 0x00020000 /* over current indicator change */ -#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ /* roothub.b masks */ -#define RH_B_DR 0x0000ffff /* device removable flags */ -#define RH_B_PPCM 0xffff0000 /* port power control mask */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ /* roothub.a masks */ -#define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ -#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ /* urb */ #define N_URB_TD 48 typedef struct { ed_t *ed; - __u16 length; /* number of tds associated with this request */ - __u16 td_cnt; /* number of tds already serviced */ + __u16 length; /* number of tds associated with this request */ + __u16 td_cnt; /* number of tds already serviced */ int state; unsigned long pipe; int actual_length; @@ -355,11 +355,11 @@ typedef struct ohci { int sleeping; unsigned long flags; /* for HC bugs */ - struct ohci_regs *regs; /* OHCI controller's memory */ + struct ohci_regs *regs; /* OHCI controller's memory */ - ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ - ed_t *ed_bulktail; /* last endpoint of bulk list */ - ed_t *ed_controltail; /* last endpoint of control list */ + ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ + ed_t *ed_bulktail; /* last endpoint of bulk list */ + ed_t *ed_controltail; /* last endpoint of control list */ int intrstatus; __u32 hc_control; /* copy of the hc control reg */ struct usb_device *dev[32]; @@ -371,7 +371,7 @@ typedef struct ohci { #define NUM_EDS 8 /* num of preallocated endpoint descriptors */ struct ohci_device { - ed_t ed[NUM_EDS]; + ed_t ed[NUM_EDS]; int ed_cnt; }; diff --git a/cpu/mips/incaip_wdt.S b/cpu/mips/incaip_wdt.S index 2ebcc911398..329386bd335 100644 --- a/cpu/mips/incaip_wdt.S +++ b/cpu/mips/incaip_wdt.S @@ -51,7 +51,7 @@ disable_incaip_wdt: and t3, 0xFFFFFF01 or t3, t2 - or t3, 0xF0 + or t3, 0xF0 sw t3, WD_CON0(t0) /* write password */ diff --git a/cpu/mips/start.S b/cpu/mips/start.S index 947128dd813..d881879d77a 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -345,7 +345,7 @@ relocate_code: jr t0 nop - .word _gp + .word _gp .word _GLOBAL_OFFSET_TABLE_ .word uboot_end_data .word uboot_end diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S index 5a9d8687f5b..fb8acb5df6b 100644 --- a/cpu/mpc512x/start.S +++ b/cpu/mpc512x/start.S @@ -219,7 +219,7 @@ boot_cold: * The SRAM window has a fixed size (256K), so only the start address * is necessary */ - lis r4, START_REG(CFG_SRAM_BASE) & 0xff00 + lis r4, START_REG(CFG_SRAM_BASE) & 0xff00 stw r4, SRAMBAR(r3) /* diff --git a/cpu/mpc5xx/config.mk b/cpu/mpc5xx/config.mk index 6d66c32bee1..157ddc54915 100644 --- a/cpu/mpc5xx/config.mk +++ b/cpu/mpc5xx/config.mk @@ -28,7 +28,7 @@ # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float diff --git a/cpu/mpc5xx/cpu_init.c b/cpu/mpc5xx/cpu_init.c index f4cd24bf7cc..5bbb7986b48 100644 --- a/cpu/mpc5xx/cpu_init.c +++ b/cpu/mpc5xx/cpu_init.c @@ -23,7 +23,7 @@ * File: cpu_init.c * * Discription: Contains initialisation functions to setup - * the cpu properly + * the cpu properly * */ @@ -118,6 +118,6 @@ void cpu_init_f (volatile immap_t * immr) */ int cpu_init_r (void) { - /* Nothing to do at the moment */ + /* Nothing to do at the moment */ return (0); } diff --git a/cpu/mpc5xx/serial.c b/cpu/mpc5xx/serial.c index ac5556f05cd..39f57a12102 100644 --- a/cpu/mpc5xx/serial.c +++ b/cpu/mpc5xx/serial.c @@ -24,8 +24,8 @@ * File: serial.c * * Discription: Serial interface driver for SCI1 and SCI2. - * Since this code will be called from ROM use - * only non-static local variables. + * Since this code will be called from ROM use + * only non-static local variables. * */ diff --git a/cpu/mpc5xx/speed.c b/cpu/mpc5xx/speed.c index 6a1fa155e29..7b7c5b96192 100644 --- a/cpu/mpc5xx/speed.c +++ b/cpu/mpc5xx/speed.c @@ -49,8 +49,8 @@ int get_clocks (void) if(immr->im_clkrst.car_plprcr & PLPRCR_CSRC_MSK) { gd->cpu_clk = vcoout / (2^(((immr->im_clkrst.car_sccr & SCCR_DFNL_MSK) >> SCCR_DFNL_SHIFT) + 1)); } else { - gd->cpu_clk = vcoout / (2^(immr->im_clkrst.car_sccr & SCCR_DFNH_MSK)); - } + gd->cpu_clk = vcoout / (2^(immr->im_clkrst.car_sccr & SCCR_DFNH_MSK)); + } #else /* CONFIG_5xx_GCLK_FREQ */ gd->bus_clk = CONFIG_5xx_GCLK_FREQ; diff --git a/cpu/mpc5xx/spi.c b/cpu/mpc5xx/spi.c index 81c9ddbd4e6..3c187bee590 100644 --- a/cpu/mpc5xx/spi.c +++ b/cpu/mpc5xx/spi.c @@ -208,9 +208,9 @@ void spi_init_f (void) * Setup RAM */ for(i=0;i<32;i++) { - qsmcm->qsmcm_recram[i]=0x0000; - qsmcm->qsmcm_tranram[i]=0x0000; - qsmcm->qsmcm_comdram[i]=0x00; + qsmcm->qsmcm_recram[i]=0x0000; + qsmcm->qsmcm_tranram[i]=0x0000; + qsmcm->qsmcm_comdram[i]=0x00; } return; } @@ -238,9 +238,9 @@ ssize_t short_spi_write (uchar *addr, int alen, uchar *buffer, int len) immr = (immap_t *) CFG_IMMR; qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; for(i=0;i<32;i++) { - qsmcm->qsmcm_recram[i]=0x0000; - qsmcm->qsmcm_tranram[i]=0x0000; - qsmcm->qsmcm_comdram[i]=0x00; + qsmcm->qsmcm_recram[i]=0x0000; + qsmcm->qsmcm_tranram[i]=0x0000; + qsmcm->qsmcm_comdram[i]=0x00; } qsmcm->qsmcm_tranram[0] = SPI_EEPROM_WREN; /* write enable */ spi_xfer(1); @@ -312,9 +312,9 @@ ssize_t short_spi_read (uchar *addr, int alen, uchar *buffer, int len) qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; for(i=0;i<32;i++) { - qsmcm->qsmcm_recram[i]=0x0000; - qsmcm->qsmcm_tranram[i]=0x0000; - qsmcm->qsmcm_comdram[i]=0x00; + qsmcm->qsmcm_recram[i]=0x0000; + qsmcm->qsmcm_tranram[i]=0x0000; + qsmcm->qsmcm_comdram[i]=0x00; } i=0; qsmcm->qsmcm_tranram[i++] = (SPI_EEPROM_READ); /* READ memory array */ diff --git a/cpu/mpc5xx/traps.c b/cpu/mpc5xx/traps.c index d22b89a1f52..78c820ae7e3 100644 --- a/cpu/mpc5xx/traps.c +++ b/cpu/mpc5xx/traps.c @@ -223,8 +223,8 @@ void UnknownException(struct pt_regs *regs) void DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); + show_regs(regs); #if defined(CONFIG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); + do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc5xx/u-boot.lds b/cpu/mpc5xx/u-boot.lds index 386a6e01f47..7434e3fb621 100644 --- a/cpu/mpc5xx/u-boot.lds +++ b/cpu/mpc5xx/u-boot.lds @@ -33,11 +33,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c index 2aded1a5f13..82640ab7718 100644 --- a/cpu/mpc5xxx/fec.c +++ b/cpu/mpc5xxx/fec.c @@ -884,7 +884,7 @@ int mpc5xxx_fec_initialize(bd_t * bis) fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec)); dev = (struct eth_device *)malloc(sizeof(*dev)); - memset(dev, 0, sizeof *dev); + memset(dev, 0, sizeof *dev); fec->eth = (ethernet_regs *)MPC5XXX_FEC; fec->tbdBase = (FEC_TBD *)FEC_BD_BASE; diff --git a/cpu/mpc5xxx/u-boot-customlayout.lds b/cpu/mpc5xxx/u-boot-customlayout.lds index bbb6cf8e04b..38478601ab4 100644 --- a/cpu/mpc5xxx/u-boot-customlayout.lds +++ b/cpu/mpc5xxx/u-boot-customlayout.lds @@ -33,11 +33,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/cpu/mpc5xxx/u-boot.lds b/cpu/mpc5xxx/u-boot.lds index db6c6f29a02..13fffb808fa 100644 --- a/cpu/mpc5xxx/u-boot.lds +++ b/cpu/mpc5xxx/u-boot.lds @@ -33,11 +33,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/cpu/mpc8220/u-boot.lds b/cpu/mpc8220/u-boot.lds index ff4f3dce202..e34a9d48421 100644 --- a/cpu/mpc8220/u-boot.lds +++ b/cpu/mpc8220/u-boot.lds @@ -33,11 +33,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/cpu/mpc824x/drivers/epic/epic2.S b/cpu/mpc824x/drivers/epic/epic2.S index 8cc2fc60bb6..52d19aae8e2 100644 --- a/cpu/mpc824x/drivers/epic/epic2.S +++ b/cpu/mpc824x/drivers/epic/epic2.S @@ -169,7 +169,7 @@ epic_exception: xor r3,r3,r3 xor r4,r4,r4 or r3, r3, r6 /* eumbbar in r3 */ - andi. r4,r7,0x00ff /* Mask off bits, vector in r4 */ + andi. r4,r7,0x00ff /* Mask off bits, vector in r4 */ stw r4,0x04(r1) /* save the vector value */ diff --git a/cpu/mpc824x/drivers/errors.h b/cpu/mpc824x/drivers/errors.h index 887f284fc4e..20794a2e893 100644 --- a/cpu/mpc824x/drivers/errors.h +++ b/cpu/mpc824x/drivers/errors.h @@ -61,7 +61,7 @@ to standardize the error handling in the current project */ message back to the user. */ /*----------------------------------------------------------------------*/ -/* these are specifically for the parser routines */ +/* these are specifically for the parser routines */ #define UNKNOWN_COMMAND 0xfb00 /* "unrecognized command " */ #define UNKNOWN_REGISTER 0xfb01 /* "unknown register "*/ @@ -73,8 +73,8 @@ to standardize the error handling in the current project */ #define UNIMPLEMENTED_STAGE 0xfb05 /* invalid rd or rmm parameter format */ #define REG_NOT_WRITEABLE 0xfb06 /* "unknown operator in arguements"*/ #define INVALID_FILENAME 0xfb07 /* "invalid download filename" */ -#define INVALID_BAUD_RATE 0xfb08 /* invalid baud rate from sb command */ -#define UNSUPPORTED_REGISTER 0xfb09 /* Special register is not supported */ +#define INVALID_BAUD_RATE 0xfb08 /* invalid baud rate from sb command */ +#define UNSUPPORTED_REGISTER 0xfb09 /* Special register is not supported */ #define FOR_BOARD_ONLY 0xfb0a /* "Not available for Unix." */ @@ -140,20 +140,20 @@ to standardize the error handling in the current project */ #define INVALID_FLAG 0xfd0c /* invalid flag */ /*----------------------------------------------------------------------*/ -/* these are for the getarg toolbox */ +/* these are for the getarg toolbox */ -#define INVALID_NUMBER_ARGS 0xFE00 /* invalid number of commd arguements */ +#define INVALID_NUMBER_ARGS 0xFE00 /* invalid number of commd arguements */ #define UNKNOWN_PARAMETER 0xFE01 /* "unknown type of parameter "*/ /*----------------------------------------------------------------------*/ -/* these are for the tokenizer toolbox */ +/* these are for the tokenizer toolbox */ -#define ILLEGAL_CHARACTER 0xFF00 /* unrecognized char. in input stream*/ -#define TTL_NOT_SORTED 0xFF01 /* token translation list not sorted */ -#define TTL_NOT_DEFINED 0xFF02 /* token translation list not assigned*/ -#define INVALID_STRING 0xFF03 /* unable to extract string from input */ -#define BUFFER_EMPTY 0xFF04 /* "input buffer is empty" */ +#define ILLEGAL_CHARACTER 0xFF00 /* unrecognized char. in input stream*/ +#define TTL_NOT_SORTED 0xFF01 /* token translation list not sorted */ +#define TTL_NOT_DEFINED 0xFF02 /* token translation list not assigned*/ +#define INVALID_STRING 0xFF03 /* unable to extract string from input */ +#define BUFFER_EMPTY 0xFF04 /* "input buffer is empty" */ #define INVALID_MODE 0xFF05 /* input buf is in an unrecognized mode*/ #define TOK_INTERNAL_ERROR 0xFF06 /* "internal tokenizer error" */ #define TOO_MANY_IBS 0xFF07 /* "too many open input buffers" */ @@ -172,7 +172,7 @@ to standardize the error handling in the current project */ /* THESE are for the downloader */ -#define NOT_IN_S_RECORD_FORMAT 0xf900 /* "not in S-Record Format" */ +#define NOT_IN_S_RECORD_FORMAT 0xf900 /* "not in S-Record Format" */ #define UNREC_RECORD_TYPE 0xf901 /* "unrecognized record type" */ #define CONVERSION_ERROR 0xf902 /* "ascii to int conversion error" */ #define INVALID_MEMORY 0xf903 /* "bad s-record memory address " */ @@ -190,7 +190,7 @@ to standardize the error handling in the current project */ /* these are for the DUART handling things */ /* "unrecognized serial port configuration" */ -#define UNKNOWN_PORT_STATE 0xf700 +#define UNKNOWN_PORT_STATE 0xf700 /* these are for the register toolbox */ @@ -208,5 +208,5 @@ to standardize the error handling in the current project */ /*----------------------------------------------------------------------*/ -/* these are specifically for the flash routines */ -#define FLASH_ERROR 0xf100 /* general flash error */ +/* these are specifically for the flash routines */ +#define FLASH_ERROR 0xf100 /* general flash error */ diff --git a/cpu/mpc824x/u-boot.lds b/cpu/mpc824x/u-boot.lds index 1f2e7d72760..aa3050dbd75 100644 --- a/cpu/mpc824x/u-boot.lds +++ b/cpu/mpc824x/u-boot.lds @@ -33,11 +33,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c index 34bd3897f6d..c3af7b6d839 100644 --- a/cpu/mpc8260/i2c.c +++ b/cpu/mpc8260/i2c.c @@ -191,10 +191,10 @@ static int i2c_setrate(int hz, int speed) if ((diff >= 0) && (diff < bestspeed_diff)) { - bestspeed_diff = diff ; - bestspeed_modval = modval; - bestspeed_brgval = brgval; - bestspeed_filter = filter; + bestspeed_diff = diff ; + bestspeed_modval = modval; + bestspeed_brgval = brgval; + bestspeed_filter = filter; } } } @@ -242,7 +242,7 @@ void i2c_init(int speed, int slaveadd) /* * initialise data in dual port ram: * - * dpaddr -> parameter ram (64 bytes) + * dpaddr -> parameter ram (64 bytes) * rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes) * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes) * tx buffer (MAX_TX_SPACE bytes) diff --git a/cpu/mpc8260/speed.h b/cpu/mpc8260/speed.h index b66393bec58..3f32a143cc1 100644 --- a/cpu/mpc8260/speed.h +++ b/cpu/mpc8260/speed.h @@ -28,10 +28,10 @@ * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 * * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock + * GCLK CPU clock * SPEED_TMR2_PS prescaler */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ +#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ /*----------------------------------------------------------------------- * Timer value for PIT diff --git a/cpu/mpc8260/u-boot.lds b/cpu/mpc8260/u-boot.lds index 6f500c42f2f..39f2ce9de47 100644 --- a/cpu/mpc8260/u-boot.lds +++ b/cpu/mpc8260/u-boot.lds @@ -33,11 +33,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index fba5b02eceb..fb184d816b6 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -218,7 +218,7 @@ void cpu_init_f (volatile immap_t * im) im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM; im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM; #else -#error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined +#error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined #endif #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 70cd410298a..76f2474491a 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -510,7 +510,7 @@ long int spd_sdram() ddr->timing_cfg_1 = (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */ ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */ - (trcd_clk << 20 ) | /* ACTTORW */ + (trcd_clk << 20 ) | /* ACTTORW */ (caslat_ctrl << 16 ) | /* CASLAT */ (trfc_low << 12 ) | /* REFEC */ ((twr_clk & 0x07) << 8) | /* WRRREC */ diff --git a/cpu/mpc83xx/u-boot.lds b/cpu/mpc83xx/u-boot.lds index 8da6f147259..99ad6759d8a 100644 --- a/cpu/mpc83xx/u-boot.lds +++ b/cpu/mpc83xx/u-boot.lds @@ -31,11 +31,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/cpu/mpc85xx/qe_io.c b/cpu/mpc85xx/qe_io.c index 98075bbe54f..21ea38b7a69 100644 --- a/cpu/mpc85xx/qe_io.c +++ b/cpu/mpc85xx/qe_io.c @@ -34,7 +34,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) u32 pin_2bit_assign; u32 pin_1bit_mask; u32 tmp_val; - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); volatile par_io_t *par_io = (volatile par_io_t *) &(gur->qe_par_io); diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 15b804d9fcb..2b5d90e2784 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -89,7 +89,7 @@ _start_e500: /* L1 */ li r0,2 mtspr L1CSR0,r0 /* invalidate d-cache */ - mtspr L1CSR1,r0 /* invalidate i-cache */ + mtspr L1CSR1,r0 /* invalidate i-cache */ mfspr r1,DBSR mtspr DBSR,r1 /* Clear all valid bits */ diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 8485841a453..5cc0c266f06 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -528,7 +528,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, caslat -= 1; else if (busfreq > max_data_rate) { printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n", - busfreq, max_data_rate); + busfreq, max_data_rate); return 0; } } diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index c71c92659d3..c39dc4681d7 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -486,25 +486,25 @@ setup_bats: .globl early_bats early_bats: /* IBAT 5 */ - lis r4, CFG_IBAT5L@h + lis r4, CFG_IBAT5L@h ori r4, r4, CFG_IBAT5L@l - lis r3, CFG_IBAT5U@h + lis r3, CFG_IBAT5U@h ori r3, r3, CFG_IBAT5U@l mtspr IBAT5L, r4 mtspr IBAT5U, r3 isync /* DBAT 5 */ - lis r4, CFG_DBAT5L@h + lis r4, CFG_DBAT5L@h ori r4, r4, CFG_DBAT5L@l - lis r3, CFG_DBAT5U@h + lis r3, CFG_DBAT5U@h ori r3, r3, CFG_DBAT5U@l mtspr DBAT5L, r4 mtspr DBAT5U, r3 isync /* IBAT 6 */ - lis r4, CFG_IBAT6L@h + lis r4, CFG_IBAT6L@h ori r4, r4, CFG_IBAT6L@l lis r3, CFG_IBAT6U@h ori r3, r3, CFG_IBAT6U@l @@ -513,9 +513,9 @@ early_bats: isync /* DBAT 6 */ - lis r4, CFG_DBAT6L@h + lis r4, CFG_DBAT6L@h ori r4, r4, CFG_DBAT6L@l - lis r3, CFG_DBAT6U@h + lis r3, CFG_DBAT6U@h ori r3, r3, CFG_DBAT6U@l mtspr DBAT6L, r4 mtspr DBAT6U, r3 diff --git a/cpu/mpc8xx/i2c.c b/cpu/mpc8xx/i2c.c index 6c59374e3fb..f05b666b883 100644 --- a/cpu/mpc8xx/i2c.c +++ b/cpu/mpc8xx/i2c.c @@ -590,7 +590,7 @@ i2c_test_callback(int flags, int xnum) int i2c_probe(uchar chip) { i2c_state_t state; - int rc; + int rc; uchar buf[1]; i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c index 744dcdde91f..09a3db107b7 100644 --- a/cpu/mpc8xx/scc.c +++ b/cpu/mpc8xx/scc.c @@ -1,7 +1,7 @@ /* * File: scc.c * Description: - * Basic ET HW initialization and packet RX/TX routines + * Basic ET HW initialization and packet RX/TX routines * * NOTE <<<IMPORTANT: PLEASE READ>>>: * Do not cache Rx/Tx buffers! diff --git a/cpu/mpc8xx/video.c b/cpu/mpc8xx/video.c index 918de679435..8bf8e469ccf 100644 --- a/cpu/mpc8xx/video.c +++ b/cpu/mpc8xx/video.c @@ -115,9 +115,9 @@ DECLARE_GLOBAL_DATA_PTR; #define VIDEO_BURST_LEN (VIDEO_COLS/8) #ifdef VIDEO_MODE_YUYV -#define VIDEO_BG_COL 0x80D880D8 /* Background color in YUYV format */ +#define VIDEO_BG_COL 0x80D880D8 /* Background color in YUYV format */ #else -#define VIDEO_BG_COL 0xF8F8F8F8 /* Background color in RGB format */ +#define VIDEO_BG_COL 0xF8F8F8F8 /* Background color in RGB format */ #endif /************************************************************************/ diff --git a/cpu/nios/asmi.c b/cpu/nios/asmi.c index ce2863e5c62..c2cd8fead0e 100644 --- a/cpu/nios/asmi.c +++ b/cpu/nios/asmi.c @@ -183,7 +183,7 @@ static void asmi_status_wr (unsigned char status) * Device information ***********************************************************************/ typedef struct asmi_devinfo_t { - const char *name; /* Device name */ + const char *name; /* Device name */ unsigned char id; /* Device silicon id */ unsigned char size; /* Total size log2(bytes)*/ unsigned char num_sects; /* Number of sectors */ diff --git a/cpu/nios/start.S b/cpu/nios/start.S index cb1af3c8b60..9e73941a5e8 100644 --- a/cpu/nios/start.S +++ b/cpu/nios/start.S @@ -208,7 +208,7 @@ __start: * A control register that counts system clock cycles would be * a handy feature -- hint for Altera ;-) */ - .globl dly_clks + .globl dly_clks /* Each loop is 4 instructions as delay slot is always * executed. Each instruction is approximately 4 clocks * (according to some lame info from Altera). So ... diff --git a/cpu/nios2/start.S b/cpu/nios2/start.S index 4c6e47066a3..6c6f294b011 100644 --- a/cpu/nios2/start.S +++ b/cpu/nios2/start.S @@ -178,20 +178,20 @@ _reloc: * Instruction performance varies based on the core. For cores * with icache and static/dynamic branch prediction (II/f, II/s): * - * Normal ALU (e.g. add, cmp, etc): 1 cycle - * Branch (correctly predicted, taken): 2 cycles + * Normal ALU (e.g. add, cmp, etc): 1 cycle + * Branch (correctly predicted, taken): 2 cycles * Negative offset is predicted (II/s). * * For cores without icache and no branch prediction (II/e): * - * Normal ALU (e.g. add, cmp, etc): 6 cycles - * Branch (no prediction): 6 cycles + * Normal ALU (e.g. add, cmp, etc): 6 cycles + * Branch (no prediction): 6 cycles * * For simplicity, if an instruction cache is implemented we * assume II/f or II/s. Otherwise, we use the II/e. * */ - .globl dly_clks + .globl dly_clks dly_clks: diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index 941d4dc7881..c28c7ac86dd 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -46,7 +46,7 @@ * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not * really required after a reset since PMMxMAs are already - * disabled but is a good practice nonetheless. JWB + * disabled but is a good practice nonetheless. JWB * 12-Jun-01 stefan.roese@esd-electronics.com * - PCI host/adapter handling reworked * 09-Jul-01 stefan.roese@esd-electronics.com diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index f9a1988d417..503facca306 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -444,8 +444,8 @@ static void ppc4xx_setup_utl(u32 port) /* * TODO: double check PCI express SDR based on the latest user manual - * Some registers specified here no longer exist.. has to be - * updated based on the final EAS spec. + * Some registers specified here no longer exist.. has to be + * updated based on the final EAS spec. */ static int check_error(void) { diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c index 47c264e222c..d8be2cef1f7 100644 --- a/cpu/ppc4xx/i2c.c +++ b/cpu/ppc4xx/i2c.c @@ -61,7 +61,7 @@ static void _i2c_bus_reset(void) /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ out_8((u8 *)IIC_EXTSTS, 0x8F); - /* Place chip in the reset state */ + /* Place chip in the reset state */ out_8((u8 *)IIC_XTCNTLSS, IIC_XTCNTLSS_SRST); /* Check if bus is free */ diff --git a/cpu/ppc4xx/kgdb.S b/cpu/ppc4xx/kgdb.S index 42b9546d3d2..4227a4c15b6 100644 --- a/cpu/ppc4xx/kgdb.S +++ b/cpu/ppc4xx/kgdb.S @@ -45,7 +45,7 @@ kgdb_flush_cache_all: iccci r0,r0 /* iccci invalidates the entire I cache */ /* dcache */ addi r6,0,0x0000 /* clear GPR 6 */ - addi r7,r0, 128 /* do loop for # of dcache lines */ + addi r7,r0, 128 /* do loop for # of dcache lines */ /* NOTE: dccci invalidates both */ mtctr r7 /* ways in the D cache */ ..dcloop: diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 8b4e64a19cb..ef47ffc9521 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -1126,7 +1126,7 @@ void get_sys_info (sys_info_t * sysInfo) m = sysInfo->pllFwdDiv * plb2xDiv * 2 * sysInfo->pllOpbDiv * sysInfo->pllExtBusDiv; break; - case PLL_FBK_PLL_LOCAL: + case PLL_FBK_PLL_LOCAL: break; default: printf("%s unknown m\n", __FUNCTION__); diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index a513b4507ab..0008170128a 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -852,7 +852,7 @@ _start: mtdccr r1 /* data cache */ addis r1,r0,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */ + ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */ li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ stwu r0, -4(r1) /* stack backtraces terminate cleanly */ @@ -947,11 +947,11 @@ _start: /*----------------------------------------------------------------------- */ /* DMA Status, clear to come up clean */ /*----------------------------------------------------------------------- */ - addis r3,r0, 0xFFFF /* Clear all existing DMA status */ + addis r3,r0, 0xFFFF /* Clear all existing DMA status */ ori r3,r3, 0xFFFF mtdcr dmasr, r3 - bl ppc405ep_init /* do ppc405ep specific init */ + bl ppc405ep_init /* do ppc405ep specific init */ #endif /* CONFIG_405EP */ #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE) @@ -1809,13 +1809,13 @@ ppc405ep_init: !----------------------------------------------------------------------- */ mfdcr r5, CPC0_PLLMR1 - rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */ + rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */ cmpi cr0,0,r4,0x1 - beq pll_done /* if SSCS =b'1' then PLL has */ - /* already been set */ - /* and CPU has been reset */ - /* so skip to next section */ + beq pll_done /* if SSCS =b'1' then PLL has */ + /* already been set */ + /* and CPU has been reset */ + /* so skip to next section */ #ifdef CONFIG_BUBINGA /* @@ -1837,13 +1837,13 @@ ppc405ep_init: lwz r4, 0(r3) addis r5,0,NVRVFY1@h addi r5,r5,NVRVFY1@l - cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/ + cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/ bne ..no_pllset addi r3,r3,4 lwz r4, 0(r3) addis r5,0,NVRVFY2@h addi r5,r5,NVRVFY2@l - cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */ + cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */ bne ..no_pllset addi r3,r3,8 /* Skip over conf_size */ lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */ @@ -1867,7 +1867,7 @@ ppc405ep_init: #if defined(CONFIG_ZEUS) mfdcr r4, CPC0_BOOT andi. r5, r4, CPC0_BOOT_SEP@l - bne strap_1 /* serial eeprom present */ + bne strap_1 /* serial eeprom present */ lis r3,0x0000 addi r3,r3,0x3030 lis r4,0x8042 @@ -1879,10 +1879,10 @@ strap_1: b 1f #endif - addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ - ori r3,r3,PLLMR0_DEFAULT@l /* */ - addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ - ori r4,r4,PLLMR1_DEFAULT@l /* */ + addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ + ori r3,r3,PLLMR0_DEFAULT@l /* */ + addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ + ori r4,r4,PLLMR1_DEFAULT@l /* */ #ifdef CONFIG_TAIHU b 1f @@ -1898,7 +1898,7 @@ strap_1: #endif /* CONFIG_TAIHU */ 1: - b pll_write /* Write the CPC0_PLLMR with new value */ + b pll_write /* Write the CPC0_PLLMR with new value */ pll_done: /* @@ -1915,7 +1915,7 @@ pll_done: pci_wait: bdnz pci_wait - blr /* return to main code */ + blr /* return to main code */ /* !----------------------------------------------------------------------------- @@ -1936,20 +1936,20 @@ pci_wait: pll_write: mfdcr r5, CPC0_UCR andis. r5,r5,0xFFFF - ori r5,r5,0x0101 /* Stop the UART clocks */ - mtdcr CPC0_UCR,r5 /* Before changing PLL */ + ori r5,r5,0x0101 /* Stop the UART clocks */ + mtdcr CPC0_UCR,r5 /* Before changing PLL */ mfdcr r5, CPC0_PLLMR1 - rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */ + rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */ mtdcr CPC0_PLLMR1,r5 - oris r5,r5,0x4000 /* Set PLL Reset */ + oris r5,r5,0x4000 /* Set PLL Reset */ mtdcr CPC0_PLLMR1,r5 - mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */ - rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */ - oris r5,r5,0x4000 /* Set PLL Reset */ - mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */ - rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */ + mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */ + rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */ + oris r5,r5,0x4000 /* Set PLL Reset */ + mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */ + rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */ mtdcr CPC0_PLLMR1,r5 /* @@ -1970,9 +1970,9 @@ pll_wait: * Not sure if this is needed... */ addis r3,0,0x1000 - mtspr dbcr0,r3 /* This will cause a CPU core reset, and */ - /* execution will continue from the poweron */ - /* vector of 0xfffffffc */ + mtspr dbcr0,r3 /* This will cause a CPU core reset, and */ + /* execution will continue from the poweron */ + /* vector of 0xfffffffc */ #endif /* CONFIG_405EP */ #if defined(CONFIG_440) diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c index 7dbb288ebf0..5dbd8422745 100644 --- a/cpu/ppc4xx/usb_ohci.c +++ b/cpu/ppc4xx/usb_ohci.c @@ -1600,7 +1600,7 @@ int usb_lowlevel_init(void) gohci.sleeping = 0; gohci.irq = -1; #if defined(CONFIG_440EP) - gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000); + gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000); #elif defined(CONFIG_440EPX) || defined(CFG_USB_HOST) gohci.regs = (struct ohci_regs *)(CFG_USB_HOST); #endif diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c index 92dd19f95f2..df537c4351f 100644 --- a/cpu/pxa/i2c.c +++ b/cpu/pxa/i2c.c @@ -45,7 +45,7 @@ #include <asm/arch/pxa-regs.h> #include <i2c.h> -/*#define DEBUG_I2C 1 /###* activate local debugging output */ +/*#define DEBUG_I2C 1 /###* activate local debugging output */ #define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */ #if (CFG_I2C_SPEED == 400000) @@ -191,8 +191,8 @@ int i2c_transfer(struct i2c_msg *msg) /* start receive */ ICR &= ~ICR_START; ICR &= ~ICR_STOP; - if (msg->condition == I2C_COND_START) ICR |= ICR_START; - if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; + if (msg->condition == I2C_COND_START) ICR |= ICR_START; + if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; ICR &= ~ICR_ALDIE; @@ -267,7 +267,7 @@ void i2c_init(int speed, int slaveaddr) * i2c_probe: - Test if a chip answers for a given i2c address * * @chip: address of the chip which is searched for - * @return: 0 if a chip was found, -1 otherwhise + * @return: 0 if a chip was found, -1 otherwhise */ int i2c_probe(uchar chip) diff --git a/cpu/s3c44b0/start.S b/cpu/s3c44b0/start.S index 7affe87b3a1..1d88c1c030a 100644 --- a/cpu/s3c44b0/start.S +++ b/cpu/s3c44b0/start.S @@ -188,7 +188,7 @@ _start_armboot: .word start_armboot #define WTCON (0x01c00000+0x130000) cpu_init_crit: /* disable watch dog */ - ldr r0, =WTCON + ldr r0, =WTCON ldr r1, =0x0 str r1, [r0] @@ -211,7 +211,7 @@ cpu_init_crit: ldr r1, =PLLCON #if CONFIG_S3C44B0_CLOCK_SPEED==66 - ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */ + ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */ #elif CONFIG_S3C44B0_CLOCK_SPEED==75 ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */ #else diff --git a/cpu/sa1100/start.S b/cpu/sa1100/start.S index 431ee656e8d..910650d15bb 100644 --- a/cpu/sa1100/start.S +++ b/cpu/sa1100/start.S @@ -157,7 +157,7 @@ stack_setup: clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 @@ -349,31 +349,31 @@ cpu_init_crit: undefined_instruction: get_bad_stack bad_save_user_regs - bl do_undefined_instruction + bl do_undefined_instruction .align 5 software_interrupt: get_bad_stack bad_save_user_regs - bl do_software_interrupt + bl do_software_interrupt .align 5 prefetch_abort: get_bad_stack bad_save_user_regs - bl do_prefetch_abort + bl do_prefetch_abort .align 5 data_abort: get_bad_stack bad_save_user_regs - bl do_data_abort + bl do_data_abort .align 5 not_used: get_bad_stack bad_save_user_regs - bl do_not_used + bl do_not_used #ifdef CONFIG_USE_IRQ @@ -381,7 +381,7 @@ not_used: irq: get_irq_stack irq_save_user_regs - bl do_irq + bl do_irq irq_restore_user_regs .align 5 @@ -389,7 +389,7 @@ fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs - bl do_fiq + bl do_fiq irq_restore_user_regs #else @@ -398,13 +398,13 @@ fiq: irq: get_bad_stack bad_save_user_regs - bl do_irq + bl do_irq .align 5 fiq: get_bad_stack bad_save_user_regs - bl do_fiq + bl do_fiq #endif diff --git a/cpu/sh4/cache.c b/cpu/sh4/cache.c index 4e744d71453..377005cd4d3 100644 --- a/cpu/sh4/cache.c +++ b/cpu/sh4/cache.c @@ -72,9 +72,9 @@ static inline void cache_wback_all(void) jump_to_P2(); for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++){ for (j = 0; j < CACHE_OC_NUM_WAYS; j++) { - addr = CACHE_OC_ADDRESS_ARRAY | (j << CACHE_OC_WAY_SHIFT) + addr = CACHE_OC_ADDRESS_ARRAY | (j << CACHE_OC_WAY_SHIFT) | (i << CACHE_OC_ENTRY_SHIFT); - data = inl(addr); + data = inl(addr); if (data & CACHE_UPDATED) { data &= ~CACHE_UPDATED; outl(data, addr); |