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-rw-r--r--drivers/spi/Kconfig10
-rw-r--r--drivers/spi/mpc8xxx_spi.c279
-rw-r--r--drivers/spi/mxc_spi.c77
3 files changed, 246 insertions, 120 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b80d3634324..04ddb32a8f3 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -137,6 +137,11 @@ config MPC8XX_SPI
help
Enable support for SPI on MPC8XX
+config MPC8XXX_SPI
+ bool "MPC8XXX SPI Driver"
+ help
+ Enable support for SPI on the MPC8XXX PowerPC SoCs.
+
config MT7621_SPI
bool "MediaTek MT7621 SPI driver"
depends on SOC_MT7628
@@ -378,11 +383,6 @@ config LPC32XX_SSP
help
Enable support for SPI on LPC32xx
-config MPC8XXX_SPI
- bool "MPC8XXX SPI Driver"
- help
- Enable support for SPI on the MPC8XXX PowerPC SoCs.
-
config MXC_SPI
bool "MXC SPI Driver"
help
diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c
index 8d6d86d2b0a..1c7bf10f91e 100644
--- a/drivers/spi/mpc8xxx_spi.c
+++ b/drivers/spi/mpc8xxx_spi.c
@@ -5,161 +5,258 @@
*/
#include <common.h>
-
+#include <dm.h>
+#include <errno.h>
#include <malloc.h>
#include <spi.h>
#include <asm/mpc8xxx_spi.h>
+#include <asm-generic/gpio.h>
+
+enum {
+ SPI_EV_NE = BIT(31 - 22), /* Receiver Not Empty */
+ SPI_EV_NF = BIT(31 - 23), /* Transmitter Not Full */
+};
+
+enum {
+ SPI_MODE_LOOP = BIT(31 - 1), /* Loopback mode */
+ SPI_MODE_CI = BIT(31 - 2), /* Clock invert */
+ SPI_MODE_CP = BIT(31 - 3), /* Clock phase */
+ SPI_MODE_DIV16 = BIT(31 - 4), /* Divide clock source by 16 */
+ SPI_MODE_REV = BIT(31 - 5), /* Reverse mode - MSB first */
+ SPI_MODE_MS = BIT(31 - 6), /* Always master */
+ SPI_MODE_EN = BIT(31 - 7), /* Enable interface */
+
+ SPI_MODE_LEN_MASK = 0xf00000,
+ SPI_MODE_PM_MASK = 0xf0000,
+
+ SPI_COM_LST = BIT(31 - 9),
+};
+
+struct mpc8xxx_priv {
+ spi8xxx_t *spi;
+ struct gpio_desc gpios[16];
+ int max_cs;
+};
+
+static inline u32 to_prescale_mod(u32 val)
+{
+ return (min(val, (u32)15) << 16);
+}
-#define SPI_EV_NE (0x80000000 >> 22) /* Receiver Not Empty */
-#define SPI_EV_NF (0x80000000 >> 23) /* Transmitter Not Full */
-
-#define SPI_MODE_LOOP (0x80000000 >> 1) /* Loopback mode */
-#define SPI_MODE_REV (0x80000000 >> 5) /* Reverse mode - MSB first */
-#define SPI_MODE_MS (0x80000000 >> 6) /* Always master */
-#define SPI_MODE_EN (0x80000000 >> 7) /* Enable interface */
+static void set_char_len(spi8xxx_t *spi, u32 val)
+{
+ clrsetbits_be32(&spi->mode, SPI_MODE_LEN_MASK, (val << 20));
+}
#define SPI_TIMEOUT 1000
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static int __spi_set_speed(spi8xxx_t *spi, uint speed)
{
- struct spi_slave *slave;
+ /* TODO(mario.six@gdsys.cc): This only ever sets one fixed speed */
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
+ /* Use SYSCLK / 8 (16.67MHz typ.) */
+ clrsetbits_be32(&spi->mode, SPI_MODE_PM_MASK, to_prescale_mod(1));
- slave = spi_alloc_slave_base(bus, cs);
- if (!slave)
- return NULL;
-
- /*
- * TODO: Some of the code in spi_init() should probably move
- * here, or into spi_claim_bus() below.
- */
-
- return slave;
+ return 0;
}
-void spi_free_slave(struct spi_slave *slave)
+static int mpc8xxx_spi_ofdata_to_platdata(struct udevice *dev)
{
- free(slave);
+ struct mpc8xxx_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->spi = (spi8xxx_t *)dev_read_addr(dev);
+
+ /* TODO(mario.six@gdsys.cc): Read clock and save the value */
+
+ ret = gpio_request_list_by_name(dev, "gpios", priv->gpios,
+ ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
+ if (ret < 0)
+ return -EINVAL;
+
+ priv->max_cs = ret;
+
+ return 0;
}
-void spi_init(void)
+static int mpc8xxx_spi_probe(struct udevice *dev)
{
- volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
+ struct mpc8xxx_priv *priv = dev_get_priv(dev);
/*
* SPI pins on the MPC83xx are not muxed, so all we do is initialize
* some registers
*/
- spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
- spi->mode = (spi->mode & 0xfff0ffff) | BIT(16); /* Use SYSCLK / 8
- (16.67MHz typ.) */
- spi->event = 0xffffffff; /* Clear all SPI events */
- spi->mask = 0x00000000; /* Mask all SPI interrupts */
- spi->com = 0; /* LST bit doesn't do anything, so disregard */
+ out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN);
+
+ __spi_set_speed(priv->spi, 16666667);
+
+ /* Clear all SPI events */
+ setbits_be32(&priv->spi->event, 0xffffffff);
+ /* Mask all SPI interrupts */
+ clrbits_be32(&priv->spi->mask, 0xffffffff);
+ /* LST bit doesn't do anything, so disregard */
+ out_be32(&priv->spi->com, 0);
+
+ return 0;
}
-int spi_claim_bus(struct spi_slave *slave)
+static void mpc8xxx_spi_cs_activate(struct udevice *dev)
{
- return 0;
+ struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
+ struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+
+ dm_gpio_set_dir_flags(&priv->gpios[platdata->cs], GPIOD_IS_OUT);
+ dm_gpio_set_value(&priv->gpios[platdata->cs], 0);
}
-void spi_release_bus(struct spi_slave *slave)
+static void mpc8xxx_spi_cs_deactivate(struct udevice *dev)
{
+ struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
+ struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+ dm_gpio_set_dir_flags(&priv->gpios[platdata->cs], GPIOD_IS_OUT);
+ dm_gpio_set_value(&priv->gpios[platdata->cs], 1);
}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
+static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen,
+ const void *dout, void *din, ulong flags)
{
- volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
- unsigned int tmpdout, tmpdin, event;
- int numBlks = DIV_ROUND_UP(bitlen, 32);
- int tm, isRead = 0;
- unsigned char charSize = 32;
+ struct udevice *bus = dev->parent;
+ struct mpc8xxx_priv *priv = dev_get_priv(bus);
+ spi8xxx_t *spi = priv->spi;
+ struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+ u32 tmpdin = 0;
+ int num_blks = DIV_ROUND_UP(bitlen, 32);
- debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
- slave->bus, slave->cs, *(uint *) dout, *(uint *) din, bitlen);
+ debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__,
+ bus->name, platdata->cs, *(uint *)dout, *(uint *)din, bitlen);
if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+ mpc8xxx_spi_cs_activate(dev);
+
+ /* Clear all SPI events */
+ setbits_be32(&spi->event, 0xffffffff);
+
+ /* Handle data in 32-bit chunks */
+ while (num_blks--) {
+ u32 tmpdout = 0;
+ uchar xfer_bitlen = (bitlen >= 32 ? 32 : bitlen);
+ ulong start;
- spi->event = 0xffffffff; /* Clear all SPI events */
+ clrbits_be32(&spi->mode, SPI_MODE_EN);
- /* handle data in 32-bit chunks */
- while (numBlks--) {
- tmpdout = 0;
- charSize = (bitlen >= 32 ? 32 : bitlen);
+ /* Set up length for this transfer */
+
+ if (bitlen <= 4) /* 4 bits or less */
+ set_char_len(spi, 3);
+ else if (bitlen <= 16) /* at most 16 bits */
+ set_char_len(spi, bitlen - 1);
+ else /* more than 16 bits -> full 32 bit transfer */
+ set_char_len(spi, 0);
+
+ setbits_be32(&spi->mode, SPI_MODE_EN);
/* Shift data so it's msb-justified */
- tmpdout = *(u32 *) dout >> (32 - charSize);
-
- /* The LEN field of the SPMODE register is set as follows:
- *
- * Bit length setting
- * len <= 4 3
- * 4 < len <= 16 len - 1
- * len > 16 0
- */
+ tmpdout = *(u32 *)dout >> (32 - xfer_bitlen);
- spi->mode &= ~SPI_MODE_EN;
-
- if (bitlen <= 16) {
- if (bitlen <= 4)
- spi->mode = (spi->mode & 0xff0fffff) |
- (3 << 20);
- else
- spi->mode = (spi->mode & 0xff0fffff) |
- ((bitlen - 1) << 20);
- } else {
- spi->mode = (spi->mode & 0xff0fffff);
+ if (bitlen > 32) {
/* Set up the next iteration if sending > 32 bits */
bitlen -= 32;
dout += 4;
}
- spi->mode |= SPI_MODE_EN;
+ /* Write the data out */
+ out_be32(&spi->tx, tmpdout);
- spi->tx = tmpdout; /* Write the data out */
- debug("*** spi_xfer: ... %08x written\n", tmpdout);
+ debug("*** %s: ... %08x written\n", __func__, tmpdout);
/*
* Wait for SPI transmit to get out
* or time out (1 second = 1000 ms)
* The NE event must be read and cleared first
*/
- for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) {
- event = spi->event;
- if (event & SPI_EV_NE) {
- tmpdin = spi->rx;
- spi->event |= SPI_EV_NE;
- isRead = 1;
-
- *(u32 *) din = (tmpdin << (32 - charSize));
- if (charSize == 32) {
- /* Advance output buffer by 32 bits */
- din += 4;
- }
+ start = get_timer(0);
+ do {
+ u32 event = in_be32(&spi->event);
+ bool have_ne = event & SPI_EV_NE;
+ bool have_nf = event & SPI_EV_NF;
+
+ if (!have_ne)
+ continue;
+
+ tmpdin = in_be32(&spi->rx);
+ setbits_be32(&spi->event, SPI_EV_NE);
+
+ *(u32 *)din = (tmpdin << (32 - xfer_bitlen));
+ if (xfer_bitlen == 32) {
+ /* Advance output buffer by 32 bits */
+ din += 4;
}
+
/*
* Only bail when we've had both NE and NF events.
* This will cause timeouts on RO devices, so maybe
* in the future put an arbitrary delay after writing
* the device. Arbitrary delays suck, though...
*/
- if (isRead && (event & SPI_EV_NF))
+ if (have_nf)
break;
+
+ mdelay(1);
+ } while (get_timer(start) < SPI_TIMEOUT);
+
+ if (get_timer(start) >= SPI_TIMEOUT) {
+ debug("*** %s: Time out during SPI transfer\n",
+ __func__);
+ return -ETIMEDOUT;
}
- if (tm >= SPI_TIMEOUT)
- puts("*** spi_xfer: Time out during SPI transfer");
- debug("*** spi_xfer: transfer ended. Value=%08x\n", tmpdin);
+ debug("*** %s: transfer ended. Value=%08x\n", __func__, tmpdin);
}
if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ mpc8xxx_spi_cs_deactivate(dev);
return 0;
}
+
+static int mpc8xxx_spi_set_speed(struct udevice *dev, uint speed)
+{
+ struct mpc8xxx_priv *priv = dev_get_priv(dev);
+
+ return __spi_set_speed(priv->spi, speed);
+}
+
+static int mpc8xxx_spi_set_mode(struct udevice *dev, uint mode)
+{
+ /* TODO(mario.six@gdsys.cc): Using SPI_CPHA (for clock phase) and
+ * SPI_CPOL (for clock polarity) should work
+ */
+ return 0;
+}
+
+static const struct dm_spi_ops mpc8xxx_spi_ops = {
+ .xfer = mpc8xxx_spi_xfer,
+ .set_speed = mpc8xxx_spi_set_speed,
+ .set_mode = mpc8xxx_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+static const struct udevice_id mpc8xxx_spi_ids[] = {
+ { .compatible = "fsl,spi" },
+ { }
+};
+
+U_BOOT_DRIVER(mpc8xxx_spi) = {
+ .name = "mpc8xxx_spi",
+ .id = UCLASS_SPI,
+ .of_match = mpc8xxx_spi_ids,
+ .ops = &mpc8xxx_spi_ops,
+ .ofdata_to_platdata = mpc8xxx_spi_ofdata_to_platdata,
+ .probe = mpc8xxx_spi_probe,
+ .priv_auto_alloc_size = sizeof(struct mpc8xxx_priv),
+};
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 68467627199..d94aaf9fdbd 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -38,6 +38,8 @@ __weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
#define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
#endif
+#define MAX_CS_COUNT 4
+
struct mxc_spi_slave {
struct spi_slave slave;
unsigned long base;
@@ -50,6 +52,8 @@ struct mxc_spi_slave {
unsigned int max_hz;
unsigned int mode;
struct gpio_desc ss;
+ struct gpio_desc cs_gpios[MAX_CS_COUNT];
+ struct udevice *dev;
};
static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
@@ -59,22 +63,38 @@ static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
{
- if (CONFIG_IS_ENABLED(DM_SPI)) {
- dm_gpio_set_value(&mxcs->ss, 1);
- } else {
- if (mxcs->gpio > 0)
- gpio_set_value(mxcs->gpio, mxcs->ss_pol);
- }
+#if defined(CONFIG_DM_SPI)
+ struct udevice *dev = mxcs->dev;
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+
+ u32 cs = slave_plat->cs;
+
+ if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
+ return;
+
+ dm_gpio_set_value(&mxcs->cs_gpios[cs], 1);
+#else
+ if (mxcs->gpio > 0)
+ gpio_set_value(mxcs->gpio, mxcs->ss_pol);
+#endif
}
static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
{
- if (CONFIG_IS_ENABLED(DM_SPI)) {
- dm_gpio_set_value(&mxcs->ss, 0);
- } else {
- if (mxcs->gpio > 0)
- gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
- }
+#if defined(CONFIG_DM_SPI)
+ struct udevice *dev = mxcs->dev;
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+
+ u32 cs = slave_plat->cs;
+
+ if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
+ return;
+
+ dm_gpio_set_value(&mxcs->cs_gpios[cs], 0);
+#else
+ if (mxcs->gpio > 0)
+ gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
+#endif
}
u32 get_cspi_div(u32 div)
@@ -488,28 +508,35 @@ void spi_release_bus(struct spi_slave *slave)
static int mxc_spi_probe(struct udevice *bus)
{
- struct mxc_spi_slave *plat = bus->platdata;
struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
int node = dev_of_offset(bus);
const void *blob = gd->fdt_blob;
int ret;
+ int i;
- if (gpio_request_by_name(bus, "cs-gpios", 0, &plat->ss,
- GPIOD_IS_OUT)) {
- dev_err(bus, "No cs-gpios property\n");
- return -EINVAL;
+ ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios,
+ ARRAY_SIZE(mxcs->cs_gpios), 0);
+ if (ret < 0) {
+ pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
+ return ret;
}
- plat->base = devfdt_get_addr(bus);
- if (plat->base == FDT_ADDR_T_NONE)
- return -ENODEV;
+ for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) {
+ if (!dm_gpio_is_valid(&mxcs->cs_gpios[i]))
+ continue;
- ret = dm_gpio_set_value(&plat->ss, 0);
- if (ret) {
- dev_err(bus, "Setting cs error\n");
- return ret;
+ ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i],
+ GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
+ if (ret) {
+ dev_err(bus, "Setting cs %d error\n", i);
+ return ret;
+ }
}
+ mxcs->base = devfdt_get_addr(bus);
+ if (mxcs->base == FDT_ADDR_T_NONE)
+ return -ENODEV;
+
mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
20000000);
@@ -530,6 +557,8 @@ static int mxc_spi_claim_bus(struct udevice *dev)
struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ mxcs->dev = dev;
+
return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-13 06:20:49 +0000