diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/config_fallbacks.h | 1 | ||||
| -rw-r--r-- | include/configs/imx6-engicam.h | 14 | ||||
| -rw-r--r-- | include/configs/uniphier.h | 3 | ||||
| -rw-r--r-- | include/dm/ofnode.h | 2 | ||||
| -rw-r--r-- | include/dm/read.h | 20 | ||||
| -rw-r--r-- | include/imximage.h | 200 | ||||
| -rw-r--r-- | include/sdp.h | 16 |
7 files changed, 252 insertions, 4 deletions
diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index 961a83d7581..d1bde5f07c2 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -50,6 +50,7 @@ defined(CONFIG_CMD_PART) || \ defined(CONFIG_CMD_GPT) || \ defined(CONFIG_MMC) || \ + defined(CONFIG_NVME) || \ defined(CONFIG_SYSTEMACE) || \ defined(CONFIG_SANDBOX) #define HAVE_BLOCK_DEVICE diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index e0bdb656b26..a1b70361560 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -183,6 +183,20 @@ # define CONFIG_MII #endif +/* Falcon Mode */ +#ifdef CONFIG_SPL_OS_BOOT +# define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" +# define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +# define CONFIG_CMD_SPL +# define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 +# define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K) + +/* MMC support: args@1MB kernel@2MB */ +# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ +# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +# define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ +#endif + /* Framebuffer */ #ifdef CONFIG_VIDEO_IPUV3 # define CONFIG_IPUV3_CLK 260000000 diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 9a64063c3ee..884e59c35e4 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -83,7 +83,6 @@ #endif #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_MAX_CHIPS 2 #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_NAND_DENALI_ECC_SIZE 1024 @@ -91,8 +90,6 @@ #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 -#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) - #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 210ddb2e5d7..de2769ed537 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -625,5 +625,7 @@ int ofnode_read_simple_size_cells(ofnode node); bool ofnode_pre_reloc(ofnode node); int ofnode_read_resource(ofnode node, uint index, struct resource *res); +int ofnode_read_resource_byname(ofnode node, const char *name, + struct resource *res); #endif diff --git a/include/dm/read.h b/include/dm/read.h index c3a4a5611a7..49d69c990f6 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -359,13 +359,24 @@ int dev_read_enabled(struct udevice *dev); /** * dev_read_resource() - obtain an indexed resource from a device. * - * @dev: devuce to examine + * @dev: device to examine * @index index of the resource to retrieve (0 = first) * @res returns the resource * @return 0 if ok, negative on error */ int dev_read_resource(struct udevice *dev, uint index, struct resource *res); +/** + * dev_read_resource_byname() - obtain a named resource from a device. + * + * @dev: device to examine + * @name: name of the resource to retrieve + * @res: returns the resource + * @return 0 if ok, negative on error + */ +int dev_read_resource_byname(struct udevice *dev, const char *name, + struct resource *res); + #else /* CONFIG_DM_DEV_READ_INLINE is enabled */ static inline int dev_read_u32_default(struct udevice *dev, @@ -513,6 +524,13 @@ static inline int dev_read_resource(struct udevice *dev, uint index, return ofnode_read_resource(dev_ofnode(dev), index, res); } +static inline int dev_read_resource_byname(struct udevice *dev, + const char *name, + struct resource *res) +{ + return ofnode_read_resource_byname(dev_ofnode(dev), name, res); +} + #endif /* CONFIG_DM_DEV_READ_INLINE */ /** diff --git a/include/imximage.h b/include/imximage.h new file mode 100644 index 00000000000..de1ea8ff147 --- /dev/null +++ b/include/imximage.h @@ -0,0 +1,200 @@ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IMXIMAGE_H_ +#define _IMXIMAGE_H_ + +#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */ +#define MAX_PLUGIN_CODE_SIZE (64 * 1024) +#define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */ +#define APP_CODE_BARKER 0xB1 +#define DCD_BARKER 0xB17219E9 + +/* + * NOTE: This file must be kept in sync with arch/arm/include/asm/\ + * mach-imx/imximage.cfg because tools/imximage.c can not + * cross-include headers from arch/arm/ and vice-versa. + */ +#define CMD_DATA_STR "DATA" + +/* Initial Vector Table Offset */ +#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF +#define FLASH_OFFSET_STANDARD 0x400 +#define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD +#define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD +#define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD +#define FLASH_OFFSET_ONENAND 0x100 +#define FLASH_OFFSET_NOR 0x1000 +#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD +#define FLASH_OFFSET_QSPI 0x1000 + +/* Initial Load Region Size */ +#define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF +#define FLASH_LOADSIZE_STANDARD 0x1000 +#define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD +#define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD +#define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD +#define FLASH_LOADSIZE_ONENAND 0x400 +#define FLASH_LOADSIZE_NOR 0x0 /* entire image */ +#define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD +#define FLASH_LOADSIZE_QSPI 0x0 /* entire image */ + +/* Command tags and parameters */ +#define IVT_HEADER_TAG 0xD1 +#define IVT_VERSION 0x40 +#define DCD_HEADER_TAG 0xD2 +#define DCD_VERSION 0x40 +#define DCD_WRITE_DATA_COMMAND_TAG 0xCC +#define DCD_WRITE_DATA_PARAM 0x4 +#define DCD_WRITE_CLR_BIT_PARAM 0xC +#define DCD_WRITE_SET_BIT_PARAM 0x1C +#define DCD_CHECK_DATA_COMMAND_TAG 0xCF +#define DCD_CHECK_BITS_SET_PARAM 0x14 +#define DCD_CHECK_BITS_CLR_PARAM 0x04 + +enum imximage_cmd { + CMD_INVALID, + CMD_IMAGE_VERSION, + CMD_BOOT_FROM, + CMD_BOOT_OFFSET, + CMD_WRITE_DATA, + CMD_WRITE_CLR_BIT, + CMD_WRITE_SET_BIT, + CMD_CHECK_BITS_SET, + CMD_CHECK_BITS_CLR, + CMD_CSF, + CMD_PLUGIN, +}; + +enum imximage_fld_types { + CFG_INVALID = -1, + CFG_COMMAND, + CFG_REG_SIZE, + CFG_REG_ADDRESS, + CFG_REG_VALUE +}; + +enum imximage_version { + IMXIMAGE_VER_INVALID = -1, + IMXIMAGE_V1 = 1, + IMXIMAGE_V2 +}; + +typedef struct { + uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */ + uint32_t addr; /* Address to write to */ + uint32_t value; /* Data to write */ +} dcd_type_addr_data_t; + +typedef struct { + uint32_t barker; /* Barker for sanity check */ + uint32_t length; /* Device configuration length (without preamble) */ +} dcd_preamble_t; + +typedef struct { + dcd_preamble_t preamble; + dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1]; +} dcd_v1_t; + +typedef struct { + uint32_t app_code_jump_vector; + uint32_t app_code_barker; + uint32_t app_code_csf; + uint32_t dcd_ptr_ptr; + uint32_t super_root_key; + uint32_t dcd_ptr; + uint32_t app_dest_ptr; +} flash_header_v1_t; + +typedef struct { + uint32_t length; /* Length of data to be read from flash */ +} flash_cfg_parms_t; + +typedef struct { + flash_header_v1_t fhdr; + dcd_v1_t dcd_table; + flash_cfg_parms_t ext_header; +} imx_header_v1_t; + +typedef struct { + uint32_t addr; + uint32_t value; +} dcd_addr_data_t; + +typedef struct { + uint8_t tag; + uint16_t length; + uint8_t version; +} __attribute__((packed)) ivt_header_t; + +typedef struct { + uint8_t tag; + uint16_t length; + uint8_t param; +} __attribute__((packed)) write_dcd_command_t; + +struct dcd_v2_cmd { + write_dcd_command_t write_dcd_command; + dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2]; +}; + +typedef struct { + ivt_header_t header; + struct dcd_v2_cmd dcd_cmd; + uint32_t padding[1]; /* end up on an 8-byte boundary */ +} dcd_v2_t; + +typedef struct { + uint32_t start; + uint32_t size; + uint32_t plugin; +} boot_data_t; + +typedef struct { + ivt_header_t header; + uint32_t entry; + uint32_t reserved1; + uint32_t dcd_ptr; + uint32_t boot_data_ptr; + uint32_t self; + uint32_t csf; + uint32_t reserved2; +} flash_header_v2_t; + +typedef struct { + flash_header_v2_t fhdr; + boot_data_t boot_data; + union { + dcd_v2_t dcd_table; + char plugin_code[MAX_PLUGIN_CODE_SIZE]; + } data; +} imx_header_v2_t; + +/* The header must be aligned to 4k on MX53 for NAND boot */ +struct imx_header { + union { + imx_header_v1_t hdr_v1; + imx_header_v2_t hdr_v2; + } header; +}; + +typedef void (*set_dcd_val_t)(struct imx_header *imxhdr, + char *name, int lineno, + int fld, uint32_t value, + uint32_t off); + +typedef void (*set_dcd_param_t)(struct imx_header *imxhdr, uint32_t dcd_len, + int32_t cmd); + +typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr, + uint32_t dcd_len, + char *name, int lineno); + +typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len, + uint32_t entry_point, uint32_t flash_offset); + +#endif /* _IMXIMAGE_H_ */ diff --git a/include/sdp.h b/include/sdp.h new file mode 100644 index 00000000000..f476bab8f10 --- /dev/null +++ b/include/sdp.h @@ -0,0 +1,16 @@ +/* + * sdp.h - Serial Download Protocol + * + * Copyright (C) 2017 Toradex + * Author: Stefan Agner <stefan.agner@toradex.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SDP_H_ +#define __SDP_H_ + +int sdp_init(int controller_index); +void sdp_handle(int controller_index); + +#endif /* __SDP_H_ */ |