diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/adp-ae3xx.h | 18 | ||||
| -rw-r--r-- | include/configs/adp-ag101p.h | 3 | ||||
| -rw-r--r-- | include/configs/ls1043a_common.h | 2 | ||||
| -rw-r--r-- | include/configs/ls2080ardb.h | 8 | ||||
| -rw-r--r-- | include/configs/socfpga_common.h | 2 | ||||
| -rw-r--r-- | include/configs/stih410-b2260.h | 15 | ||||
| -rw-r--r-- | include/configs/stm32h743-disco.h | 51 | ||||
| -rw-r--r-- | include/configs/stm32h743-eval.h | 51 | ||||
| -rw-r--r-- | include/dt-bindings/clock/stm32h7-clks.h | 167 | ||||
| -rw-r--r-- | include/dt-bindings/memory/stm32-sdram.h | 7 | ||||
| -rw-r--r-- | include/dt-bindings/mfd/stm32h7-rcc.h | 138 | ||||
| -rw-r--r-- | include/dt-bindings/pinctrl/stm32h7-pinfunc.h | 1612 | ||||
| -rw-r--r-- | include/dwc3-sti-glue.h | 41 | ||||
| -rw-r--r-- | include/usb/ehci-ci.h | 2 |
14 files changed, 2101 insertions, 16 deletions
diff --git a/include/configs/adp-ae3xx.h b/include/configs/adp-ae3xx.h index f47e45b433e..69460293330 100644 --- a/include/configs/adp-ae3xx.h +++ b/include/configs/adp-ae3xx.h @@ -23,8 +23,7 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_PANIC_HANG -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_ARCH_MAP_SYSMEM #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_BOOTP_SERVERIP @@ -221,14 +220,25 @@ /* max number of sectors on one chip */ #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) -#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE #define CONFIG_SYS_MAX_FLASH_SECT 512 /* environments */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 50000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x140000 #define CONFIG_ENV_SIZE 8192 #define CONFIG_ENV_OVERWRITE + +/* SPI FLASH */ +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#define CONFIG_SF_DEFAULT_MODE 0 + /* * For booting Linux, the board info and command line data * have to be in the first 16 MB of memory, since this is diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index bf713b806d1..fad4d308e03 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -22,8 +22,7 @@ #define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_ARCH_MAP_SYSMEM #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_BOOTP_SERVERIP diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 002830c27e4..1f9efffa562 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -22,7 +22,7 @@ #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) #define SPL_NO_MMC #endif -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT)) +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI)) #define SPL_NO_IFC #endif diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 145b2856850..9e9979e1c7f 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -18,7 +18,6 @@ #define CONFIG_QIXIS_I2C_ACCESS #endif #define CONFIG_SYS_I2C_EARLY_INIT -#define CONFIG_DISPLAY_BOARDINFO_LATE #endif #define I2C_MUX_CH_VOL_MONITOR 0xa @@ -289,19 +288,15 @@ unsigned long get_board_sys_clk(void); /* SPI */ #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) #define CONFIG_SPI_FLASH -#ifdef CONFIG_FSL_QSPI +#ifdef CONFIG_FSL_DSPI #define CONFIG_SPI_FLASH_STMICRO #endif #ifdef CONFIG_FSL_QSPI -#ifdef CONFIG_TARGET_LS2081ARDB -#define CONFIG_SPI_FLASH_STMICRO -#else #define CONFIG_SPI_FLASH_SPANSION #endif #define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */ #define FSL_QSPI_FLASH_NUM 2 #endif -#endif /* * RTC configuration @@ -392,6 +387,7 @@ unsigned long get_board_sys_clk(void); "load_addr=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "console=ttyAMA0,38400n8\0" \ + "mcmemsize=0x70000000\0" \ MC_INIT_CMD \ BOOTENV \ "boot_scripts=ls2088ardb_boot.scr\0" \ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 9897e11b591..7b5417a75bc 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -142,12 +142,10 @@ */ #ifdef CONFIG_NAND_DENALI #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_NAND_DENALI_ECC_SIZE 512 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS -#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) #endif /* diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index e07dd0e1030..372c0836012 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -45,4 +45,19 @@ #define CONFIG_SKIP_LOWLEVEL_INIT +/* USB Configs */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_SMSC95XX + +/* NET Configs */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + #endif /* __CONFIG_H */ diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h new file mode 100644 index 00000000000..b0061cd0de1 --- /dev/null +++ b/include/configs/stm32h743-disco.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) STMicroelectronics SA 2017 + * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <config.h> + +#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x30020000 +#define CONFIG_SYS_TEXT_BASE 0x08000000 + +/* + * Configuration of the external SDRAM memory + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_RAM_BASE 0xD0000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE +#define CONFIG_SYS_LOAD_ADDR 0xD0400000 +#define CONFIG_LOADADDR 0xD0400000 + +#define CONFIG_ENV_SIZE (8 << 10) + +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ_CLOCK 250000000 + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" + +/* + * Command line configuration. + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_CMD_CACHE +#define CONFIG_BOARD_LATE_INIT + +#endif /* __CONFIG_H */ diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h new file mode 100644 index 00000000000..b0061cd0de1 --- /dev/null +++ b/include/configs/stm32h743-eval.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) STMicroelectronics SA 2017 + * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <config.h> + +#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x30020000 +#define CONFIG_SYS_TEXT_BASE 0x08000000 + +/* + * Configuration of the external SDRAM memory + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_RAM_BASE 0xD0000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE +#define CONFIG_SYS_LOAD_ADDR 0xD0400000 +#define CONFIG_LOADADDR 0xD0400000 + +#define CONFIG_ENV_SIZE (8 << 10) + +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ_CLOCK 250000000 + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" + +/* + * Command line configuration. + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_CMD_CACHE +#define CONFIG_BOARD_LATE_INIT + +#endif /* __CONFIG_H */ diff --git a/include/dt-bindings/clock/stm32h7-clks.h b/include/dt-bindings/clock/stm32h7-clks.h new file mode 100644 index 00000000000..4d87e7ebc39 --- /dev/null +++ b/include/dt-bindings/clock/stm32h7-clks.h @@ -0,0 +1,167 @@ +/* SYS, CORE AND BUS CLOCKS */ +#define SYS_D1CPRE 0 +#define HCLK 1 +#define PCLK1 2 +#define PCLK2 3 +#define PCLK3 4 +#define PCLK4 5 +#define HSI_DIV 6 +#define HSE_1M 7 +#define I2S_CKIN 8 +#define CK_DSI_PHY 9 +#define HSE_CK 10 +#define LSE_CK 11 +#define CSI_KER_DIV122 12 +#define RTC_CK 13 +#define CPU_SYSTICK 14 + +/* OSCILLATOR BANK */ +#define OSC_BANK 18 +#define HSI_CK 18 +#define HSI_KER_CK 19 +#define CSI_CK 20 +#define CSI_KER_CK 21 +#define RC48_CK 22 +#define LSI_CK 23 + +/* MCLOCK BANK */ +#define MCLK_BANK 28 +#define PER_CK 28 +#define PLLSRC 29 +#define SYS_CK 30 +#define TRACEIN_CK 31 + +/* ODF BANK */ +#define ODF_BANK 32 +#define PLL1_P 32 +#define PLL1_Q 33 +#define PLL1_R 34 +#define PLL2_P 35 +#define PLL2_Q 36 +#define PLL2_R 37 +#define PLL3_P 38 +#define PLL3_Q 39 +#define PLL3_R 40 + +/* MCO BANK */ +#define MCO_BANK 41 +#define MCO1 41 +#define MCO2 42 + +/* PERIF BANK */ +#define PERIF_BANK 50 +#define D1SRAM1_CK 50 +#define ITCM_CK 51 +#define DTCM2_CK 52 +#define DTCM1_CK 53 +#define FLITF_CK 54 +#define JPGDEC_CK 55 +#define DMA2D_CK 56 +#define MDMA_CK 57 +#define USB2ULPI_CK 58 +#define USB1ULPI_CK 59 +#define ETH1RX_CK 60 +#define ETH1TX_CK 61 +#define ETH1MAC_CK 62 +#define ART_CK 63 +#define DMA2_CK 64 +#define DMA1_CK 65 +#define D2SRAM3_CK 66 +#define D2SRAM2_CK 67 +#define D2SRAM1_CK 68 +#define HASH_CK 69 +#define CRYPT_CK 70 +#define CAMITF_CK 71 +#define BKPRAM_CK 72 +#define HSEM_CK 73 +#define BDMA_CK 74 +#define CRC_CK 75 +#define GPIOK_CK 76 +#define GPIOJ_CK 77 +#define GPIOI_CK 78 +#define GPIOH_CK 79 +#define GPIOG_CK 80 +#define GPIOF_CK 81 +#define GPIOE_CK 82 +#define GPIOD_CK 83 +#define GPIOC_CK 84 +#define GPIOB_CK 85 +#define GPIOA_CK 86 +#define WWDG1_CK 87 +#define DAC12_CK 88 +#define WWDG2_CK 89 +#define TIM14_CK 90 +#define TIM13_CK 91 +#define TIM12_CK 92 +#define TIM7_CK 93 +#define TIM6_CK 94 +#define TIM5_CK 95 +#define TIM4_CK 96 +#define TIM3_CK 97 +#define TIM2_CK 98 +#define MDIOS_CK 99 +#define OPAMP_CK 100 +#define CRS_CK 101 +#define TIM17_CK 102 +#define TIM16_CK 103 +#define TIM15_CK 104 +#define TIM8_CK 105 +#define TIM1_CK 106 +#define TMPSENS_CK 107 +#define RTCAPB_CK 108 +#define VREF_CK 109 +#define COMP12_CK 110 +#define SYSCFG_CK 111 +/* must be equal to last peripheral clock index */ +#define LAST_PERIF_BANK SYSCFG_CK + +/* KERNEL BANK */ +#define KERN_BANK 120 +#define SDMMC1_CK 120 +#define QUADSPI_CK 121 +#define FMC_CK 122 +#define USB2OTG_CK 123 +#define USB1OTG_CK 124 +#define ADC12_CK 125 +#define SDMMC2_CK 126 +#define RNG_CK 127 +#define ADC3_CK 128 +#define DSI_CK 129 +#define LTDC_CK 130 +#define USART8_CK 131 +#define USART7_CK 132 +#define HDMICEC_CK 133 +#define I2C3_CK 134 +#define I2C2_CK 135 +#define I2C1_CK 136 +#define UART5_CK 137 +#define UART4_CK 138 +#define USART3_CK 139 +#define USART2_CK 140 +#define SPDIFRX_CK 141 +#define SPI3_CK 142 +#define SPI2_CK 143 +#define LPTIM1_CK 144 +#define FDCAN_CK 145 +#define SWP_CK 146 +#define HRTIM_CK 147 +#define DFSDM1_CK 148 +#define SAI3_CK 149 +#define SAI2_CK 150 +#define SAI1_CK 151 +#define SPI5_CK 152 +#define SPI4_CK 153 +#define SPI1_CK 154 +#define USART6_CK 155 +#define USART1_CK 156 +#define SAI4B_CK 157 +#define SAI4A_CK 158 +#define LPTIM5_CK 159 +#define LPTIM4_CK 160 +#define LPTIM3_CK 161 +#define LPTIM2_CK 162 +#define I2C4_CK 163 +#define SPI6_CK 164 +#define LPUART1_CK 165 + +#define STM32H7_MAX_CLKS 166 diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h index 89b719af534..c2b911febfb 100644 --- a/include/dt-bindings/memory/stm32-sdram.h +++ b/include/dt-bindings/memory/stm32-sdram.h @@ -18,7 +18,9 @@ #define CAS_1 0x1 #define CAS_2 0x2 #define CAS_3 0x3 +#define SDCLK_DIS 0x0 #define SDCLK_2 0x2 +#define SDCLK_3 0x3 #define RD_BURST_EN 0x1 #define RD_BURST_DIS 0x0 #define RD_PIPE_DL_0 0x0 @@ -26,12 +28,17 @@ #define RD_PIPE_DL_2 0x2 /* Timing = value +1 cycles */ +#define TMRD_1 (1 - 1) #define TMRD_2 (2 - 1) +#define TXSR_1 (1 - 1) #define TXSR_6 (6 - 1) +#define TRAS_1 (1 - 1) #define TRAS_4 (4 - 1) #define TRC_6 (6 - 1) +#define TWR_1 (1 - 1) #define TWR_2 (2 - 1) #define TRP_2 (2 - 1) +#define TRCD_1 (1 - 1) #define TRCD_2 (2 - 1) #endif diff --git a/include/dt-bindings/mfd/stm32h7-rcc.h b/include/dt-bindings/mfd/stm32h7-rcc.h new file mode 100644 index 00000000000..b96b3c3ac1a --- /dev/null +++ b/include/dt-bindings/mfd/stm32h7-rcc.h @@ -0,0 +1,138 @@ +/* + * This header provides constants for the STM32H7 RCC IP + */ + +#ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H +#define _DT_BINDINGS_MFD_STM32H7_RCC_H + +/* AHB3 */ +#define STM32H7_RCC_AHB3_MDMA 0 +#define STM32H7_RCC_AHB3_DMA2D 4 +#define STM32H7_RCC_AHB3_JPGDEC 5 +#define STM32H7_RCC_AHB3_FMC 12 +#define STM32H7_RCC_AHB3_QUADSPI 14 +#define STM32H7_RCC_AHB3_SDMMC1 16 +#define STM32H7_RCC_AHB3_CPU1 31 + +#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) + +/* AHB1 */ +#define STM32H7_RCC_AHB1_DMA1 0 +#define STM32H7_RCC_AHB1_DMA2 1 +#define STM32H7_RCC_AHB1_ADC12 5 +#define STM32H7_RCC_AHB1_ART 14 +#define STM32H7_RCC_AHB1_ETH1MAC 15 +#define STM32H7_RCC_AHB1_USB1OTG 25 +#define STM32H7_RCC_AHB1_USB2OTG 27 +#define STM32H7_RCC_AHB1_CPU2 31 + +#define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8)) + +/* AHB2 */ +#define STM32H7_RCC_AHB2_CAMITF 0 +#define STM32H7_RCC_AHB2_CRYPT 4 +#define STM32H7_RCC_AHB2_HASH 5 +#define STM32H7_RCC_AHB2_RNG 6 +#define STM32H7_RCC_AHB2_SDMMC2 9 + +#define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8)) + +/* AHB4 */ +#define STM32H7_RCC_AHB4_GPIOA 0 +#define STM32H7_RCC_AHB4_GPIOB 1 +#define STM32H7_RCC_AHB4_GPIOC 2 +#define STM32H7_RCC_AHB4_GPIOD 3 +#define STM32H7_RCC_AHB4_GPIOE 4 +#define STM32H7_RCC_AHB4_GPIOF 5 +#define STM32H7_RCC_AHB4_GPIOG 6 +#define STM32H7_RCC_AHB4_GPIOH 7 +#define STM32H7_RCC_AHB4_GPIOI 8 +#define STM32H7_RCC_AHB4_GPIOJ 9 +#define STM32H7_RCC_AHB4_GPIOK 10 +#define STM32H7_RCC_AHB4_CRC 19 +#define STM32H7_RCC_AHB4_BDMA 21 +#define STM32H7_RCC_AHB4_ADC3 24 +#define STM32H7_RCC_AHB4_HSEM 25 + +#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) + + +/* APB3 */ +#define STM32H7_RCC_APB3_LTDC 3 +#define STM32H7_RCC_APB3_DSI 4 + +#define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8)) + +/* APB1L */ +#define STM32H7_RCC_APB1L_TIM2 0 +#define STM32H7_RCC_APB1L_TIM3 1 +#define STM32H7_RCC_APB1L_TIM4 2 +#define STM32H7_RCC_APB1L_TIM5 3 +#define STM32H7_RCC_APB1L_TIM6 4 +#define STM32H7_RCC_APB1L_TIM7 5 +#define STM32H7_RCC_APB1L_TIM12 6 +#define STM32H7_RCC_APB1L_TIM13 7 +#define STM32H7_RCC_APB1L_TIM14 8 +#define STM32H7_RCC_APB1L_LPTIM1 9 +#define STM32H7_RCC_APB1L_SPI2 14 +#define STM32H7_RCC_APB1L_SPI3 15 +#define STM32H7_RCC_APB1L_SPDIF_RX 16 +#define STM32H7_RCC_APB1L_USART2 17 +#define STM32H7_RCC_APB1L_USART3 18 +#define STM32H7_RCC_APB1L_UART4 19 +#define STM32H7_RCC_APB1L_UART5 20 +#define STM32H7_RCC_APB1L_I2C1 21 +#define STM32H7_RCC_APB1L_I2C2 22 +#define STM32H7_RCC_APB1L_I2C3 23 +#define STM32H7_RCC_APB1L_HDMICEC 27 +#define STM32H7_RCC_APB1L_DAC12 29 +#define STM32H7_RCC_APB1L_USART7 30 +#define STM32H7_RCC_APB1L_USART8 31 + +#define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8)) + +/* APB1H */ +#define STM32H7_RCC_APB1H_CRS 1 +#define STM32H7_RCC_APB1H_SWP 2 +#define STM32H7_RCC_APB1H_OPAMP 4 +#define STM32H7_RCC_APB1H_MDIOS 5 +#define STM32H7_RCC_APB1H_FDCAN 8 + +#define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8)) + +/* APB2 */ +#define STM32H7_RCC_APB2_TIM1 0 +#define STM32H7_RCC_APB2_TIM8 1 +#define STM32H7_RCC_APB2_USART1 4 +#define STM32H7_RCC_APB2_USART6 5 +#define STM32H7_RCC_APB2_SPI1 12 +#define STM32H7_RCC_APB2_SPI4 13 +#define STM32H7_RCC_APB2_TIM15 16 +#define STM32H7_RCC_APB2_TIM16 17 +#define STM32H7_RCC_APB2_TIM17 18 +#define STM32H7_RCC_APB2_SPI5 20 +#define STM32H7_RCC_APB2_SAI1 22 +#define STM32H7_RCC_APB2_SAI2 23 +#define STM32H7_RCC_APB2_SAI3 24 +#define STM32H7_RCC_APB2_DFSDM1 28 +#define STM32H7_RCC_APB2_HRTIM 29 + +#define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8)) + +/* APB4 */ +#define STM32H7_RCC_APB4_SYSCFG 1 +#define STM32H7_RCC_APB4_LPUART1 3 +#define STM32H7_RCC_APB4_SPI6 5 +#define STM32H7_RCC_APB4_I2C4 7 +#define STM32H7_RCC_APB4_LPTIM2 9 +#define STM32H7_RCC_APB4_LPTIM3 10 +#define STM32H7_RCC_APB4_LPTIM4 11 +#define STM32H7_RCC_APB4_LPTIM5 12 +#define STM32H7_RCC_APB4_COMP12 14 +#define STM32H7_RCC_APB4_VREF 15 +#define STM32H7_RCC_APB4_SAI4 21 +#define STM32H7_RCC_APB4_TMPSENS 26 + +#define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8)) + +#endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */ diff --git a/include/dt-bindings/pinctrl/stm32h7-pinfunc.h b/include/dt-bindings/pinctrl/stm32h7-pinfunc.h new file mode 100644 index 00000000000..cb673b5e8e1 --- /dev/null +++ b/include/dt-bindings/pinctrl/stm32h7-pinfunc.h @@ -0,0 +1,1612 @@ +#ifndef _DT_BINDINGS_STM32H7_PINFUNC_H +#define _DT_BINDINGS_STM32H7_PINFUNC_H + +#define STM32H7_PA0_FUNC_GPIO 0x0 +#define STM32H7_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2 +#define STM32H7_PA0_FUNC_TIM5_CH1 0x3 +#define STM32H7_PA0_FUNC_TIM8_ETR 0x4 +#define STM32H7_PA0_FUNC_TIM15_BKIN 0x5 +#define STM32H7_PA0_FUNC_USART2_CTS_NSS 0x8 +#define STM32H7_PA0_FUNC_UART4_TX 0x9 +#define STM32H7_PA0_FUNC_SDMMC2_CMD 0xa +#define STM32H7_PA0_FUNC_SAI2_SD_B 0xb +#define STM32H7_PA0_FUNC_ETH_MII_CRS 0xc +#define STM32H7_PA0_FUNC_EVENTOUT 0x10 +#define STM32H7_PA0_FUNC_ANALOG 0x11 + +#define STM32H7_PA1_FUNC_GPIO 0x100 +#define STM32H7_PA1_FUNC_TIM2_CH2 0x102 +#define STM32H7_PA1_FUNC_TIM5_CH2 0x103 +#define STM32H7_PA1_FUNC_LPTIM3_OUT 0x104 +#define STM32H7_PA1_FUNC_TIM15_CH1N 0x105 +#define STM32H7_PA1_FUNC_USART2_RTS 0x108 +#define STM32H7_PA1_FUNC_UART4_RX 0x109 +#define STM32H7_PA1_FUNC_QUADSPI_BK1_IO3 0x10a +#define STM32H7_PA1_FUNC_SAI2_MCK_B 0x10b +#define STM32H7_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c +#define STM32H7_PA1_FUNC_LCD_R2 0x10f +#define STM32H7_PA1_FUNC_EVENTOUT 0x110 +#define STM32H7_PA1_FUNC_ANALOG 0x111 + +#define STM32H7_PA2_FUNC_GPIO 0x200 +#define STM32H7_PA2_FUNC_TIM2_CH3 0x202 +#define STM32H7_PA2_FUNC_TIM5_CH3 0x203 +#define STM32H7_PA2_FUNC_LPTIM4_OUT 0x204 +#define STM32H7_PA2_FUNC_TIM15_CH1 0x205 +#define STM32H7_PA2_FUNC_USART2_TX 0x208 +#define STM32H7_PA2_FUNC_SAI2_SCK_B 0x209 +#define STM32H7_PA2_FUNC_ETH_MDIO 0x20c +#define STM32H7_PA2_FUNC_MDIOS_MDIO 0x20d +#define STM32H7_PA2_FUNC_LCD_R1 0x20f +#define STM32H7_PA2_FUNC_EVENTOUT 0x210 +#define STM32H7_PA2_FUNC_ANALOG 0x211 + +#define STM32H7_PA3_FUNC_GPIO 0x300 +#define STM32H7_PA3_FUNC_TIM2_CH4 0x302 +#define STM32H7_PA3_FUNC_TIM5_CH4 0x303 +#define STM32H7_PA3_FUNC_LPTIM5_OUT 0x304 +#define STM32H7_PA3_FUNC_TIM15_CH2 0x305 +#define STM32H7_PA3_FUNC_USART2_RX 0x308 +#define STM32H7_PA3_FUNC_LCD_B2 0x30a +#define STM32H7_PA3_FUNC_OTG_HS_ULPI_D0 0x30b +#define STM32H7_PA3_FUNC_ETH_MII_COL 0x30c +#define STM32H7_PA3_FUNC_LCD_B5 0x30f +#define STM32H7_PA3_FUNC_EVENTOUT 0x310 +#define STM32H7_PA3_FUNC_ANALOG 0x311 + +#define STM32H7_PA4_FUNC_GPIO 0x400 +#define STM32H7_PA4_FUNC_TIM5_ETR 0x403 +#define STM32H7_PA4_FUNC_SPI1_NSS_I2S1_WS 0x406 +#define STM32H7_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407 +#define STM32H7_PA4_FUNC_USART2_CK 0x408 +#define STM32H7_PA4_FUNC_SPI6_NSS 0x409 +#define STM32H7_PA4_FUNC_OTG_HS_SOF 0x40d +#define STM32H7_PA4_FUNC_DCMI_HSYNC 0x40e +#define STM32H7_PA4_FUNC_LCD_VSYNC 0x40f +#define STM32H7_PA4_FUNC_EVENTOUT 0x410 +#define STM32H7_PA4_FUNC_ANALOG 0x411 + +#define STM32H7_PA5_FUNC_GPIO 0x500 +#define STM32H7_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502 +#define STM32H7_PA5_FUNC_TIM8_CH1N 0x504 +#define STM32H7_PA5_FUNC_SPI1_SCK_I2S1_CK 0x506 +#define STM32H7_PA5_FUNC_SPI6_SCK 0x509 +#define STM32H7_PA5_FUNC_OTG_HS_ULPI_CK 0x50b +#define STM32H7_PA5_FUNC_LCD_R4 0x50f +#define STM32H7_PA5_FUNC_EVENTOUT 0x510 +#define STM32H7_PA5_FUNC_ANALOG 0x511 + +#define STM32H7_PA6_FUNC_GPIO 0x600 +#define STM32H7_PA6_FUNC_TIM1_BKIN 0x602 +#define STM32H7_PA6_FUNC_TIM3_CH1 0x603 +#define STM32H7_PA6_FUNC_TIM8_BKIN 0x604 +#define STM32H7_PA6_FUNC_SPI1_MISO_I2S1_SDI 0x606 +#define STM32H7_PA6_FUNC_SPI6_MISO 0x609 +#define STM32H7_PA6_FUNC_TIM13_CH1 0x60a +#define STM32H7_PA6_FUNC_TIM8_BKIN_COMP12 0x60b +#define STM32H7_PA6_FUNC_MDIOS_MDC 0x60c +#define STM32H7_PA6_FUNC_TIM1_BKIN_COMP12 0x60d +#define STM32H7_PA6_FUNC_DCMI_PIXCLK 0x60e +#define STM32H7_PA6_FUNC_LCD_G2 0x60f +#define STM32H7_PA6_FUNC_EVENTOUT 0x610 +#define STM32H7_PA6_FUNC_ANALOG 0x611 + +#define STM32H7_PA7_FUNC_GPIO 0x700 +#define STM32H7_PA7_FUNC_TIM1_CH1N 0x702 +#define STM32H7_PA7_FUNC_TIM3_CH2 0x703 +#define STM32H7_PA7_FUNC_TIM8_CH1N 0x704 +#define STM32H7_PA7_FUNC_SPI1_MOSI_I2S1_SDO 0x706 +#define STM32H7_PA7_FUNC_SPI6_MOSI 0x709 +#define STM32H7_PA7_FUNC_TIM14_CH1 0x70a +#define STM32H7_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c +#define STM32H7_PA7_FUNC_FMC_SDNWE 0x70d +#define STM32H7_PA7_FUNC_EVENTOUT 0x710 +#define STM32H7_PA7_FUNC_ANALOG 0x711 + +#define STM32H7_PA8_FUNC_GPIO 0x800 +#define STM32H7_PA8_FUNC_MCO1 0x801 +#define STM32H7_PA8_FUNC_TIM1_CH1 0x802 +#define STM32H7_PA8_FUNC_HRTIM_CHB2 0x803 +#define STM32H7_PA8_FUNC_TIM8_BKIN2 0x804 +#define STM32H7_PA8_FUNC_I2C3_SCL 0x805 +#define STM32H7_PA8_FUNC_USART1_CK 0x808 +#define STM32H7_PA8_FUNC_OTG_FS_SOF 0x80b +#define STM32H7_PA8_FUNC_UART7_RX 0x80c +#define STM32H7_PA8_FUNC_TIM8_BKIN2_COMP12 0x80d +#define STM32H7_PA8_FUNC_LCD_B3 0x80e +#define STM32H7_PA8_FUNC_LCD_R6 0x80f +#define STM32H7_PA8_FUNC_EVENTOUT 0x810 +#define STM32H7_PA8_FUNC_ANALOG 0x811 + +#define STM32H7_PA9_FUNC_GPIO 0x900 +#define STM32H7_PA9_FUNC_TIM1_CH2 0x902 +#define STM32H7_PA9_FUNC_HRTIM_CHC1 0x903 +#define STM32H7_PA9_FUNC_LPUART1_TX 0x904 +#define STM32H7_PA9_FUNC_I2C3_SMBA 0x905 +#define STM32H7_PA9_FUNC_SPI2_SCK_I2S2_CK 0x906 +#define STM32H7_PA9_FUNC_USART1_TX 0x908 +#define STM32H7_PA9_FUNC_CAN1_RXFD 0x90a +#define STM32H7_PA9_FUNC_ETH_TX_ER 0x90c +#define STM32H7_PA9_FUNC_DCMI_D0 0x90e +#define STM32H7_PA9_FUNC_LCD_R5 0x90f +#define STM32H7_PA9_FUNC_EVENTOUT 0x910 +#define STM32H7_PA9_FUNC_ANALOG 0x911 + +#define STM32H7_PA10_FUNC_GPIO 0xa00 +#define STM32H7_PA10_FUNC_TIM1_CH3 0xa02 +#define STM32H7_PA10_FUNC_HRTIM_CHC2 0xa03 +#define STM32H7_PA10_FUNC_LPUART1_RX 0xa04 +#define STM32H7_PA10_FUNC_USART1_RX 0xa08 +#define STM32H7_PA10_FUNC_CAN1_TXFD 0xa0a +#define STM32H7_PA10_FUNC_OTG_FS_ID 0xa0b +#define STM32H7_PA10_FUNC_MDIOS_MDIO 0xa0c +#define STM32H7_PA10_FUNC_LCD_B4 0xa0d +#define STM32H7_PA10_FUNC_DCMI_D1 0xa0e +#define STM32H7_PA10_FUNC_LCD_B1 0xa0f +#define STM32H7_PA10_FUNC_EVENTOUT 0xa10 +#define STM32H7_PA10_FUNC_ANALOG 0xa11 + +#define STM32H7_PA11_FUNC_GPIO 0xb00 +#define STM32H7_PA11_FUNC_TIM1_CH4 0xb02 +#define STM32H7_PA11_FUNC_HRTIM_CHD1 0xb03 +#define STM32H7_PA11_FUNC_LPUART1_CTS 0xb04 +#define STM32H7_PA11_FUNC_SPI2_NSS_I2S2_WS 0xb06 +#define STM32H7_PA11_FUNC_UART4_RX 0xb07 +#define STM32H7_PA11_FUNC_USART1_CTS_NSS 0xb08 +#define STM32H7_PA11_FUNC_CAN1_RX 0xb0a +#define STM32H7_PA11_FUNC_OTG_FS_DM 0xb0b +#define STM32H7_PA11_FUNC_LCD_R4 0xb0f +#define STM32H7_PA11_FUNC_EVENTOUT 0xb10 +#define STM32H7_PA11_FUNC_ANALOG 0xb11 + +#define STM32H7_PA12_FUNC_GPIO 0xc00 +#define STM32H7_PA12_FUNC_TIM1_ETR 0xc02 +#define STM32H7_PA12_FUNC_HRTIM_CHD2 0xc03 +#define STM32H7_PA12_FUNC_LPUART1_RTS 0xc04 +#define STM32H7_PA12_FUNC_SPI2_SCK_I2S2_CK 0xc06 +#define STM32H7_PA12_FUNC_UART4_TX 0xc07 +#define STM32H7_PA12_FUNC_USART1_RTS 0xc08 +#define STM32H7_PA12_FUNC_SAI2_FS_B 0xc09 +#define STM32H7_PA12_FUNC_CAN1_TX 0xc0a +#define STM32H7_PA12_FUNC_OTG_FS_DP 0xc0b +#define STM32H7_PA12_FUNC_LCD_R5 0xc0f +#define STM32H7_PA12_FUNC_EVENTOUT 0xc10 +#define STM32H7_PA12_FUNC_ANALOG 0xc11 + +#define STM32H7_PA13_FUNC_GPIO 0xd00 +#define STM32H7_PA13_FUNC_JTMS_SWDIO 0xd01 +#define STM32H7_PA13_FUNC_EVENTOUT 0xd10 +#define STM32H7_PA13_FUNC_ANALOG 0xd11 + +#define STM32H7_PA14_FUNC_GPIO 0xe00 +#define STM32H7_PA14_FUNC_JTCK_SWCLK 0xe01 +#define STM32H7_PA14_FUNC_EVENTOUT 0xe10 +#define STM32H7_PA14_FUNC_ANALOG 0xe11 + +#define STM32H7_PA15_FUNC_GPIO 0xf00 +#define STM32H7_PA15_FUNC_JTDI 0xf01 +#define STM32H7_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02 +#define STM32H7_PA15_FUNC_HRTIM_FLT1 0xf03 +#define STM32H7_PA15_FUNC_HDMI_CEC 0xf05 +#define STM32H7_PA15_FUNC_SPI1_NSS_I2S1_WS 0xf06 +#define STM32H7_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07 +#define STM32H7_PA15_FUNC_SPI6_NSS 0xf08 +#define STM32H7_PA15_FUNC_UART4_RTS 0xf09 +#define STM32H7_PA15_FUNC_UART7_TX 0xf0c +#define STM32H7_PA15_FUNC_DSI_TE 0xf0e +#define STM32H7_PA15_FUNC_EVENTOUT 0xf10 +#define STM32H7_PA15_FUNC_ANALOG 0xf11 + +#define STM32H7_PB0_FUNC_GPIO 0x1000 +#define STM32H7_PB0_FUNC_TIM1_CH2N 0x1002 +#define STM32H7_PB0_FUNC_TIM3_CH3 0x1003 +#define STM32H7_PB0_FUNC_TIM8_CH2N 0x1004 +#define STM32H7_PB0_FUNC_DFSDM_CKOUT 0x1007 +#define STM32H7_PB0_FUNC_UART4_CTS 0x1009 +#define STM32H7_PB0_FUNC_LCD_R3 0x100a +#define STM32H7_PB0_FUNC_OTG_HS_ULPI_D1 0x100b +#define STM32H7_PB0_FUNC_ETH_MII_RXD2 0x100c +#define STM32H7_PB0_FUNC_LCD_G1 0x100f +#define STM32H7_PB0_FUNC_EVENTOUT 0x1010 +#define STM32H7_PB0_FUNC_ANALOG 0x1011 + +#define STM32H7_PB1_FUNC_GPIO 0x1100 +#define STM32H7_PB1_FUNC_TIM1_CH3N 0x1102 +#define STM32H7_PB1_FUNC_TIM3_CH4 0x1103 +#define STM32H7_PB1_FUNC_TIM8_CH3N 0x1104 +#define STM32H7_PB1_FUNC_DFSDM_DATIN1 0x1107 +#define STM32H7_PB1_FUNC_LCD_R6 0x110a +#define STM32H7_PB1_FUNC_OTG_HS_ULPI_D2 0x110b +#define STM32H7_PB1_FUNC_ETH_MII_RXD3 0x110c +#define STM32H7_PB1_FUNC_LCD_G0 0x110f +#define STM32H7_PB1_FUNC_EVENTOUT 0x1110 +#define STM32H7_PB1_FUNC_ANALOG 0x1111 + +#define STM32H7_PB2_FUNC_GPIO 0x1200 +#define STM32H7_PB2_FUNC_SAI1_D1 0x1203 +#define STM32H7_PB2_FUNC_DFSDM_CKIN1 0x1205 +#define STM32H7_PB2_FUNC_SAI1_SD_A 0x1207 +#define STM32H7_PB2_FUNC_SPI3_MOSI_I2S3_SDO 0x1208 +#define STM32H7_PB2_FUNC_SAI4_SD_A 0x1209 +#define STM32H7_PB2_FUNC_QUADSPI_CLK 0x120a +#define STM32H7_PB2_FUNC_SAI4_D1 0x120b +#define STM32H7_PB2_FUNC_ETH_TX_ER 0x120c +#define STM32H7_PB2_FUNC_EVENTOUT 0x1210 +#define STM32H7_PB2_FUNC_ANALOG 0x1211 + +#define STM32H7_PB3_FUNC_GPIO 0x1300 +#define STM32H7_PB3_FUNC_JTDO_TRACESWO 0x1301 +#define STM32H7_PB3_FUNC_TIM2_CH2 0x1302 +#define STM32H7_PB3_FUNC_HRTIM_FLT4 0x1303 +#define STM32H7_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306 +#define STM32H7_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307 +#define STM32H7_PB3_FUNC_SPI6_SCK 0x1309 +#define STM32H7_PB3_FUNC_SDMMC2_D2 0x130a +#define STM32H7_PB3_FUNC_UART7_RX 0x130c +#define STM32H7_PB3_FUNC_EVENTOUT 0x1310 +#define STM32H7_PB3_FUNC_ANALOG 0x1311 + +#define STM32H7_PB4_FUNC_GPIO 0x1400 +#define STM32H7_PB4_FUNC_NJTRST 0x1401 +#define STM32H7_PB4_FUNC_TIM16_BKIN 0x1402 +#define STM32H7_PB4_FUNC_TIM3_CH1 0x1403 +#define STM32H7_PB4_FUNC_HRTIM_EEV6 0x1404 +#define STM32H7_PB4_FUNC_SPI1_MISO_I2S1_SDI 0x1406 +#define STM32H7_PB4_FUNC_SPI3_MISO_I2S3_SDI 0x1407 +#define STM32H7_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408 +#define STM32H7_PB4_FUNC_SPI6_MISO 0x1409 +#define STM32H7_PB4_FUNC_SDMMC2_D3 0x140a +#define STM32H7_PB4_FUNC_UART7_TX 0x140c +#define STM32H7_PB4_FUNC_EVENTOUT 0x1410 +#define STM32H7_PB4_FUNC_ANALOG 0x1411 + +#define STM32H7_PB5_FUNC_GPIO 0x1500 +#define STM32H7_PB5_FUNC_TIM17_BKIN 0x1502 +#define STM32H7_PB5_FUNC_TIM3_CH2 0x1503 +#define STM32H7_PB5_FUNC_HRTIM_EEV7 0x1504 +#define STM32H7_PB5_FUNC_I2C1_SMBA 0x1505 +#define STM32H7_PB5_FUNC_SPI1_MOSI_I2S1_SDO 0x1506 +#define STM32H7_PB5_FUNC_I2C4_SMBA 0x1507 +#define STM32H7_PB5_FUNC_SPI3_MOSI_I2S3_SDO 0x1508 +#define STM32H7_PB5_FUNC_SPI6_MOSI 0x1509 +#define STM32H7_PB5_FUNC_CAN2_RX 0x150a +#define STM32H7_PB5_FUNC_OTG_HS_ULPI_D7 0x150b +#define STM32H7_PB5_FUNC_ETH_PPS_OUT 0x150c +#define STM32H7_PB5_FUNC_FMC_SDCKE1 0x150d +#define STM32H7_PB5_FUNC_DCMI_D10 0x150e +#define STM32H7_PB5_FUNC_UART5_RX 0x150f +#define STM32H7_PB5_FUNC_EVENTOUT 0x1510 +#define STM32H7_PB5_FUNC_ANALOG 0x1511 + +#define STM32H7_PB6_FUNC_GPIO 0x1600 +#define STM32H7_PB6_FUNC_TIM16_CH1N 0x1602 +#define STM32H7_PB6_FUNC_TIM4_CH1 0x1603 +#define STM32H7_PB6_FUNC_HRTIM_EEV8 0x1604 +#define STM32H7_PB6_FUNC_I2C1_SCL 0x1605 +#define STM32H7_PB6_FUNC_HDMI_CEC 0x1606 +#define STM32H7_PB6_FUNC_I2C4_SCL 0x1607 +#define STM32H7_PB6_FUNC_USART1_TX 0x1608 +#define STM32H7_PB6_FUNC_LPUART1_TX 0x1609 +#define STM32H7_PB6_FUNC_CAN2_TX 0x160a +#define STM32H7_PB6_FUNC_QUADSPI_BK1_NCS 0x160b +#define STM32H7_PB6_FUNC_DFSDM_DATIN5 0x160c +#define STM32H7_PB6_FUNC_FMC_SDNE1 0x160d +#define STM32H7_PB6_FUNC_DCMI_D5 0x160e +#define STM32H7_PB6_FUNC_UART5_TX 0x160f +#define STM32H7_PB6_FUNC_EVENTOUT 0x1610 +#define STM32H7_PB6_FUNC_ANALOG 0x1611 + +#define STM32H7_PB7_FUNC_GPIO 0x1700 +#define STM32H7_PB7_FUNC_TIM17_CH1N 0x1702 +#define STM32H7_PB7_FUNC_TIM4_CH2 0x1703 +#define STM32H7_PB7_FUNC_HRTIM_EEV9 0x1704 +#define STM32H7_PB7_FUNC_I2C1_SDA 0x1705 +#define STM32H7_PB7_FUNC_I2C4_SDA 0x1707 +#define STM32H7_PB7_FUNC_USART1_RX 0x1708 +#define STM32H7_PB7_FUNC_LPUART1_RX 0x1709 +#define STM32H7_PB7_FUNC_CAN2_TXFD 0x170a +#define STM32H7_PB7_FUNC_DFSDM_CKIN5 0x170c +#define STM32H7_PB7_FUNC_FMC_NL 0x170d +#define STM32H7_PB7_FUNC_DCMI_VSYNC 0x170e +#define STM32H7_PB7_FUNC_EVENTOUT 0x1710 +#define STM32H7_PB7_FUNC_ANALOG 0x1711 + +#define STM32H7_PB8_FUNC_GPIO 0x1800 +#define STM32H7_PB8_FUNC_TIM16_CH1 0x1802 +#define STM32H7_PB8_FUNC_TIM4_CH3 0x1803 +#define STM32H7_PB8_FUNC_DFSDM_CKIN7 0x1804 +#define STM32H7_PB8_FUNC_I2C1_SCL 0x1805 +#define STM32H7_PB8_FUNC_I2C4_SCL 0x1807 +#define STM32H7_PB8_FUNC_SDMMC1_CKIN 0x1808 +#define STM32H7_PB8_FUNC_UART4_RX 0x1809 +#define STM32H7_PB8_FUNC_CAN1_RX 0x180a +#define STM32H7_PB8_FUNC_SDMMC2_D4 0x180b +#define STM32H7_PB8_FUNC_ETH_MII_TXD3 0x180c +#define STM32H7_PB8_FUNC_SDMMC1_D4 0x180d +#define STM32H7_PB8_FUNC_DCMI_D6 0x180e +#define STM32H7_PB8_FUNC_LCD_B6 0x180f +#define STM32H7_PB8_FUNC_EVENTOUT 0x1810 +#define STM32H7_PB8_FUNC_ANALOG 0x1811 + +#define STM32H7_PB9_FUNC_GPIO 0x1900 +#define STM32H7_PB9_FUNC_TIM17_CH1 0x1902 +#define STM32H7_PB9_FUNC_TIM4_CH4 0x1903 +#define STM32H7_PB9_FUNC_DFSDM_DATIN7 0x1904 +#define STM32H7_PB9_FUNC_I2C1_SDA 0x1905 +#define STM32H7_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906 +#define STM32H7_PB9_FUNC_I2C4_SDA 0x1907 +#define STM32H7_PB9_FUNC_SDMMC1_CDIR 0x1908 +#define STM32H7_PB9_FUNC_UART4_TX 0x1909 +#define STM32H7_PB9_FUNC_CAN1_TX 0x190a +#define STM32H7_PB9_FUNC_SDMMC2_D5 0x190b +#define STM32H7_PB9_FUNC_I2C4_SMBA 0x190c +#define STM32H7_PB9_FUNC_SDMMC1_D5 0x190d +#define STM32H7_PB9_FUNC_DCMI_D7 0x190e +#define STM32H7_PB9_FUNC_LCD_B7 0x190f +#define STM32H7_PB9_FUNC_EVENTOUT 0x1910 +#define STM32H7_PB9_FUNC_ANALOG 0x1911 + +#define STM32H7_PB10_FUNC_GPIO 0x1a00 +#define STM32H7_PB10_FUNC_TIM2_CH3 0x1a02 +#define STM32H7_PB10_FUNC_HRTIM_SCOUT 0x1a03 +#define STM32H7_PB10_FUNC_LPTIM2_IN1 0x1a04 +#define STM32H7_PB10_FUNC_I2C2_SCL 0x1a05 +#define STM32H7_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06 +#define STM32H7_PB10_FUNC_DFSDM_DATIN7 0x1a07 +#define STM32H7_PB10_FUNC_USART3_TX 0x1a08 +#define STM32H7_PB10_FUNC_QUADSPI_BK1_NCS 0x1a0a +#define STM32H7_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b +#define STM32H7_PB10_FUNC_ETH_MII_RX_ER 0x1a0c +#define STM32H7_PB10_FUNC_LCD_G4 0x1a0f +#define STM32H7_PB10_FUNC_EVENTOUT 0x1a10 +#define STM32H7_PB10_FUNC_ANALOG 0x1a11 + +#define STM32H7_PB11_FUNC_GPIO 0x1b00 +#define STM32H7_PB11_FUNC_TIM2_CH4 0x1b02 +#define STM32H7_PB11_FUNC_HRTIM_SCIN 0x1b03 +#define STM32H7_PB11_FUNC_LPTIM2_ETR 0x1b04 +#define STM32H7_PB11_FUNC_I2C2_SDA 0x1b05 +#define STM32H7_PB11_FUNC_DFSDM_CKIN7 0x1b07 +#define STM32H7_PB11_FUNC_USART3_RX 0x1b08 +#define STM32H7_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b +#define STM32H7_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c +#define STM32H7_PB11_FUNC_DSI_TE 0x1b0e +#define STM32H7_PB11_FUNC_LCD_G5 0x1b0f +#define STM32H7_PB11_FUNC_EVENTOUT 0x1b10 +#define STM32H7_PB11_FUNC_ANALOG 0x1b11 + +#define STM32H7_PB12_FUNC_GPIO 0x1c00 +#define STM32H7_PB12_FUNC_TIM1_BKIN 0x1c02 +#define STM32H7_PB12_FUNC_I2C2_SMBA 0x1c05 +#define STM32H7_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06 +#define STM32H7_PB12_FUNC_DFSDM_DATIN1 0x1c07 +#define STM32H7_PB12_FUNC_USART3_CK 0x1c08 +#define STM32H7_PB12_FUNC_CAN2_RX 0x1c0a +#define STM32H7_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b +#define STM32H7_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c +#define STM32H7_PB12_FUNC_OTG_HS_ID 0x1c0d +#define STM32H7_PB12_FUNC_TIM1_BKIN_COMP12 0x1c0e +#define STM32H7_PB12_FUNC_UART5_RX 0x1c0f +#define STM32H7_PB12_FUNC_EVENTOUT 0x1c10 +#define STM32H7_PB12_FUNC_ANALOG 0x1c11 + +#define STM32H7_PB13_FUNC_GPIO 0x1d00 +#define STM32H7_PB13_FUNC_TIM1_CH1N 0x1d02 +#define STM32H7_PB13_FUNC_LPTIM2_OUT 0x1d04 +#define STM32H7_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06 +#define STM32H7_PB13_FUNC_DFSDM_CKIN1 0x1d07 +#define STM32H7_PB13_FUNC_USART3_CTS_NSS 0x1d08 +#define STM32H7_PB13_FUNC_CAN2_TX 0x1d0a +#define STM32H7_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b +#define STM32H7_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c +#define STM32H7_PB13_FUNC_UART5_TX 0x1d0f +#define STM32H7_PB13_FUNC_EVENTOUT 0x1d10 +#define STM32H7_PB13_FUNC_ANALOG 0x1d11 + +#define STM32H7_PB14_FUNC_GPIO 0x1e00 +#define STM32H7_PB14_FUNC_TIM1_CH2N 0x1e02 +#define STM32H7_PB14_FUNC_TIM8_CH2N 0x1e04 +#define STM32H7_PB14_FUNC_USART1_TX 0x1e05 +#define STM32H7_PB14_FUNC_SPI2_MISO_I2S2_SDI 0x1e06 +#define STM32H7_PB14_FUNC_DFSDM_DATIN2 0x1e07 +#define STM32H7_PB14_FUNC_USART3_RTS 0x1e08 +#define STM32H7_PB14_FUNC_UART4_RTS 0x1e09 +#define STM32H7_PB14_FUNC_SDMMC2_D0 0x1e0a +#define STM32H7_PB14_FUNC_OTG_HS_DM 0x1e0d +#define STM32H7_PB14_FUNC_EVENTOUT 0x1e10 +#define STM32H7_PB14_FUNC_ANALOG 0x1e11 + +#define STM32H7_PB15_FUNC_GPIO 0x1f00 +#define STM32H7_PB15_FUNC_RTC_REFIN 0x1f01 +#define STM32H7_PB15_FUNC_TIM1_CH3N 0x1f02 +#define STM32H7_PB15_FUNC_TIM8_CH3N 0x1f04 +#define STM32H7_PB15_FUNC_USART1_RX 0x1f05 +#define STM32H7_PB15_FUNC_SPI2_MOSI_I2S2_SDO 0x1f06 +#define STM32H7_PB15_FUNC_DFSDM_CKIN2 0x1f07 +#define STM32H7_PB15_FUNC_UART4_CTS 0x1f09 +#define STM32H7_PB15_FUNC_SDMMC2_D1 0x1f0a +#define STM32H7_PB15_FUNC_OTG_HS_DP 0x1f0d +#define STM32H7_PB15_FUNC_EVENTOUT 0x1f10 +#define STM32H7_PB15_FUNC_ANALOG 0x1f11 + +#define STM32H7_PC0_FUNC_GPIO 0x2000 +#define STM32H7_PC0_FUNC_DFSDM_CKIN0 0x2004 +#define STM32H7_PC0_FUNC_DFSDM_DATIN4 0x2007 +#define STM32H7_PC0_FUNC_SAI2_FS_B 0x2009 +#define STM32H7_PC0_FUNC_OTG_HS_ULPI_STP 0x200b +#define STM32H7_PC0_FUNC_FMC_SDNWE 0x200d +#define STM32H7_PC0_FUNC_LCD_R5 0x200f +#define STM32H7_PC0_FUNC_EVENTOUT 0x2010 +#define STM32H7_PC0_FUNC_ANALOG 0x2011 + +#define STM32H7_PC1_FUNC_GPIO 0x2100 +#define STM32H7_PC1_FUNC_TRACED0 0x2101 +#define STM32H7_PC1_FUNC_SAI1_D1 0x2103 +#define STM32H7_PC1_FUNC_DFSDM_DATIN0 0x2104 +#define STM32H7_PC1_FUNC_DFSDM_CKIN4 0x2105 +#define STM32H7_PC1_FUNC_SPI2_MOSI_I2S2_SDO 0x2106 +#define STM32H7_PC1_FUNC_SAI1_SD_A 0x2107 +#define STM32H7_PC1_FUNC_SAI4_SD_A 0x2109 +#define STM32H7_PC1_FUNC_SDMMC2_CK 0x210a +#define STM32H7_PC1_FUNC_SAI4_D1 0x210b +#define STM32H7_PC1_FUNC_ETH_MDC 0x210c +#define STM32H7_PC1_FUNC_MDIOS_MDC 0x210d +#define STM32H7_PC1_FUNC_EVENTOUT 0x2110 +#define STM32H7_PC1_FUNC_ANALOG 0x2111 + +#define STM32H7_PC2_FUNC_GPIO 0x2200 +#define STM32H7_PC2_FUNC_DFSDM_CKIN1 0x2204 +#define STM32H7_PC2_FUNC_SPI2_MISO_I2S2_SDI 0x2206 +#define STM32H7_PC2_FUNC_DFSDM_CKOUT 0x2207 +#define STM32H7_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b +#define STM32H7_PC2_FUNC_ETH_MII_TXD2 0x220c +#define STM32H7_PC2_FUNC_FMC_SDNE0 0x220d +#define STM32H7_PC2_FUNC_EVENTOUT 0x2210 +#define STM32H7_PC2_FUNC_ANALOG 0x2211 + +#define STM32H7_PC3_FUNC_GPIO 0x2300 +#define STM32H7_PC3_FUNC_DFSDM_DATIN1 0x2304 +#define STM32H7_PC3_FUNC_SPI2_MOSI_I2S2_SDO 0x2306 +#define STM32H7_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b +#define STM32H7_PC3_FUNC_ETH_MII_TX_CLK 0x230c +#define STM32H7_PC3_FUNC_FMC_SDCKE0 0x230d +#define STM32H7_PC3_FUNC_EVENTOUT 0x2310 +#define STM32H7_PC3_FUNC_ANALOG 0x2311 + +#define STM32H7_PC4_FUNC_GPIO 0x2400 +#define STM32H7_PC4_FUNC_DFSDM_CKIN2 0x2404 +#define STM32H7_PC4_FUNC_I2S1_MCK 0x2406 +#define STM32H7_PC4_FUNC_SPDIFRX_IN2 0x240a +#define STM32H7_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c +#define STM32H7_PC4_FUNC_FMC_SDNE0 0x240d +#define STM32H7_PC4_FUNC_EVENTOUT 0x2410 +#define STM32H7_PC4_FUNC_ANALOG 0x2411 + +#define STM32H7_PC5_FUNC_GPIO 0x2500 +#define STM32H7_PC5_FUNC_SAI1_D3 0x2503 +#define STM32H7_PC5_FUNC_DFSDM_DATIN2 0x2504 +#define STM32H7_PC5_FUNC_SPDIFRX_IN3 0x250a +#define STM32H7_PC5_FUNC_SAI4_D3 0x250b +#define STM32H7_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c +#define STM32H7_PC5_FUNC_FMC_SDCKE0 0x250d +#define STM32H7_PC5_FUNC_COMP_1_OUT 0x250e +#define STM32H7_PC5_FUNC_EVENTOUT 0x2510 +#define STM32H7_PC5_FUNC_ANALOG 0x2511 + +#define STM32H7_PC6_FUNC_GPIO 0x2600 +#define STM32H7_PC6_FUNC_HRTIM_CHA1 0x2602 +#define STM32H7_PC6_FUNC_TIM3_CH1 0x2603 +#define STM32H7_PC6_FUNC_TIM8_CH1 0x2604 +#define STM32H7_PC6_FUNC_DFSDM_CKIN3 0x2605 +#define STM32H7_PC6_FUNC_I2S2_MCK 0x2606 +#define STM32H7_PC6_FUNC_USART6_TX 0x2608 +#define STM32H7_PC6_FUNC_SDMMC1_D0DIR 0x2609 +#define STM32H7_PC6_FUNC_FMC_NWAIT 0x260a +#define STM32H7_PC6_FUNC_SDMMC2_D6 0x260b +#define STM32H7_PC6_FUNC_SDMMC1_D6 0x260d +#define STM32H7_PC6_FUNC_DCMI_D0 0x260e +#define STM32H7_PC6_FUNC_LCD_HSYNC 0x260f +#define STM32H7_PC6_FUNC_EVENTOUT 0x2610 +#define STM32H7_PC6_FUNC_ANALOG 0x2611 + +#define STM32H7_PC7_FUNC_GPIO 0x2700 +#define STM32H7_PC7_FUNC_TRGIO 0x2701 +#define STM32H7_PC7_FUNC_HRTIM_CHA2 0x2702 +#define STM32H7_PC7_FUNC_TIM3_CH2 0x2703 +#define STM32H7_PC7_FUNC_TIM8_CH2 0x2704 +#define STM32H7_PC7_FUNC_DFSDM_DATIN3 0x2705 +#define STM32H7_PC7_FUNC_I2S3_MCK 0x2707 +#define STM32H7_PC7_FUNC_USART6_RX 0x2708 +#define STM32H7_PC7_FUNC_SDMMC1_D123DIR 0x2709 +#define STM32H7_PC7_FUNC_FMC_NE1 0x270a +#define STM32H7_PC7_FUNC_SDMMC2_D7 0x270b +#define STM32H7_PC7_FUNC_SWPMI_TX 0x270c +#define STM32H7_PC7_FUNC_SDMMC1_D7 0x270d +#define STM32H7_PC7_FUNC_DCMI_D1 0x270e +#define STM32H7_PC7_FUNC_LCD_G6 0x270f +#define STM32H7_PC7_FUNC_EVENTOUT 0x2710 +#define STM32H7_PC7_FUNC_ANALOG 0x2711 + +#define STM32H7_PC8_FUNC_GPIO 0x2800 +#define STM32H7_PC8_FUNC_TRACED1 0x2801 +#define STM32H7_PC8_FUNC_HRTIM_CHB1 0x2802 +#define STM32H7_PC8_FUNC_TIM3_CH3 0x2803 +#define STM32H7_PC8_FUNC_TIM8_CH3 0x2804 +#define STM32H7_PC8_FUNC_USART6_CK 0x2808 +#define STM32H7_PC8_FUNC_UART5_RTS 0x2809 +#define STM32H7_PC8_FUNC_FMC_NE2_FMC_NCE 0x280a +#define STM32H7_PC8_FUNC_SWPMI_RX 0x280c +#define STM32H7_PC8_FUNC_SDMMC1_D0 0x280d +#define STM32H7_PC8_FUNC_DCMI_D2 0x280e +#define STM32H7_PC8_FUNC_EVENTOUT 0x2810 +#define STM32H7_PC8_FUNC_ANALOG 0x2811 + +#define STM32H7_PC9_FUNC_GPIO 0x2900 +#define STM32H7_PC9_FUNC_MCO2 0x2901 +#define STM32H7_PC9_FUNC_TIM3_CH4 0x2903 +#define STM32H7_PC9_FUNC_TIM8_CH4 0x2904 +#define STM32H7_PC9_FUNC_I2C3_SDA 0x2905 +#define STM32H7_PC9_FUNC_I2S_CKIN 0x2906 +#define STM32H7_PC9_FUNC_UART5_CTS 0x2909 +#define STM32H7_PC9_FUNC_QUADSPI_BK1_IO0 0x290a +#define STM32H7_PC9_FUNC_LCD_G3 0x290b +#define STM32H7_PC9_FUNC_SWPMI_SUSPEND 0x290c +#define STM32H7_PC9_FUNC_SDMMC1_D1 0x290d +#define STM32H7_PC9_FUNC_DCMI_D3 0x290e +#define STM32H7_PC9_FUNC_LCD_B2 0x290f +#define STM32H7_PC9_FUNC_EVENTOUT 0x2910 +#define STM32H7_PC9_FUNC_ANALOG 0x2911 + +#define STM32H7_PC10_FUNC_GPIO 0x2a00 +#define STM32H7_PC10_FUNC_HRTIM_EEV1 0x2a03 +#define STM32H7_PC10_FUNC_DFSDM_CKIN5 0x2a04 +#define STM32H7_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07 +#define STM32H7_PC10_FUNC_USART3_TX 0x2a08 +#define STM32H7_PC10_FUNC_UART4_TX 0x2a09 +#define STM32H7_PC10_FUNC_QUADSPI_BK1_IO1 0x2a0a +#define STM32H7_PC10_FUNC_SDMMC1_D2 0x2a0d +#define STM32H7_PC10_FUNC_DCMI_D8 0x2a0e +#define STM32H7_PC10_FUNC_LCD_R2 0x2a0f +#define STM32H7_PC10_FUNC_EVENTOUT 0x2a10 +#define STM32H7_PC10_FUNC_ANALOG 0x2a11 + +#define STM32H7_PC11_FUNC_GPIO 0x2b00 +#define STM32H7_PC11_FUNC_HRTIM_FLT2 0x2b03 +#define STM32H7_PC11_FUNC_DFSDM_DATIN5 0x2b04 +#define STM32H7_PC11_FUNC_SPI3_MISO_I2S3_SDI 0x2b07 +#define STM32H7_PC11_FUNC_USART3_RX 0x2b08 +#define STM32H7_PC11_FUNC_UART4_RX 0x2b09 +#define STM32H7_PC11_FUNC_QUADSPI_BK2_NCS 0x2b0a +#define STM32H7_PC11_FUNC_SDMMC1_D3 0x2b0d +#define STM32H7_PC11_FUNC_DCMI_D4 0x2b0e +#define STM32H7_PC11_FUNC_EVENTOUT 0x2b10 +#define STM32H7_PC11_FUNC_ANALOG 0x2b11 + +#define STM32H7_PC12_FUNC_GPIO 0x2c00 +#define STM32H7_PC12_FUNC_TRACED3 0x2c01 +#define STM32H7_PC12_FUNC_HRTIM_EEV2 0x2c03 +#define STM32H7_PC12_FUNC_SPI3_MOSI_I2S3_SDO 0x2c07 +#define STM32H7_PC12_FUNC_USART3_CK 0x2c08 +#define STM32H7_PC12_FUNC_UART5_TX 0x2c09 +#define STM32H7_PC12_FUNC_SDMMC1_CK 0x2c0d +#define STM32H7_PC12_FUNC_DCMI_D9 0x2c0e +#define STM32H7_PC12_FUNC_EVENTOUT 0x2c10 +#define STM32H7_PC12_FUNC_ANALOG 0x2c11 + +#define STM32H7_PC13_FUNC_GPIO 0x2d00 +#define STM32H7_PC13_FUNC_EVENTOUT 0x2d10 +#define STM32H7_PC13_FUNC_ANALOG 0x2d11 + +#define STM32H7_PC14_FUNC_GPIO 0x2e00 +#define STM32H7_PC14_FUNC_EVENTOUT 0x2e10 +#define STM32H7_PC14_FUNC_ANALOG 0x2e11 + +#define STM32H7_PC15_FUNC_GPIO 0x2f00 +#define STM32H7_PC15_FUNC_EVENTOUT 0x2f10 +#define STM32H7_PC15_FUNC_ANALOG 0x2f11 + +#define STM32H7_PD0_FUNC_GPIO 0x3000 +#define STM32H7_PD0_FUNC_DFSDM_CKIN6 0x3004 +#define STM32H7_PD0_FUNC_SAI3_SCK_A 0x3007 +#define STM32H7_PD0_FUNC_UART4_RX 0x3009 +#define STM32H7_PD0_FUNC_CAN1_RX 0x300a +#define STM32H7_PD0_FUNC_FMC_D2_FMC_DA2 0x300d +#define STM32H7_PD0_FUNC_EVENTOUT 0x3010 +#define STM32H7_PD0_FUNC_ANALOG 0x3011 + +#define STM32H7_PD1_FUNC_GPIO 0x3100 +#define STM32H7_PD1_FUNC_DFSDM_DATIN6 0x3104 +#define STM32H7_PD1_FUNC_SAI3_SD_A 0x3107 +#define STM32H7_PD1_FUNC_UART4_TX 0x3109 +#define STM32H7_PD1_FUNC_CAN1_TX 0x310a +#define STM32H7_PD1_FUNC_FMC_D3_FMC_DA3 0x310d +#define STM32H7_PD1_FUNC_EVENTOUT 0x3110 +#define STM32H7_PD1_FUNC_ANALOG 0x3111 + +#define STM32H7_PD2_FUNC_GPIO 0x3200 +#define STM32H7_PD2_FUNC_TRACED2 0x3201 +#define STM32H7_PD2_FUNC_TIM3_ETR 0x3203 +#define STM32H7_PD2_FUNC_UART5_RX 0x3209 +#define STM32H7_PD2_FUNC_SDMMC1_CMD 0x320d +#define STM32H7_PD2_FUNC_DCMI_D11 0x320e +#define STM32H7_PD2_FUNC_EVENTOUT 0x3210 +#define STM32H7_PD2_FUNC_ANALOG 0x3211 + +#define STM32H7_PD3_FUNC_GPIO 0x3300 +#define STM32H7_PD3_FUNC_DFSDM_CKOUT 0x3304 +#define STM32H7_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306 +#define STM32H7_PD3_FUNC_USART2_CTS_NSS 0x3308 +#define STM32H7_PD3_FUNC_FMC_CLK 0x330d +#define STM32H7_PD3_FUNC_DCMI_D5 0x330e +#define STM32H7_PD3_FUNC_LCD_G7 0x330f +#define STM32H7_PD3_FUNC_EVENTOUT 0x3310 +#define STM32H7_PD3_FUNC_ANALOG 0x3311 + +#define STM32H7_PD4_FUNC_GPIO 0x3400 +#define STM32H7_PD4_FUNC_HRTIM_FLT3 0x3403 +#define STM32H7_PD4_FUNC_SAI3_FS_A 0x3407 +#define STM32H7_PD4_FUNC_USART2_RTS 0x3408 +#define STM32H7_PD4_FUNC_CAN1_RXFD 0x340a +#define STM32H7_PD4_FUNC_FMC_NOE 0x340d +#define STM32H7_PD4_FUNC_EVENTOUT 0x3410 +#define STM32H7_PD4_FUNC_ANALOG 0x3411 + +#define STM32H7_PD5_FUNC_GPIO 0x3500 +#define STM32H7_PD5_FUNC_HRTIM_EEV3 0x3503 +#define STM32H7_PD5_FUNC_USART2_TX 0x3508 +#define STM32H7_PD5_FUNC_CAN1_TXFD 0x350a +#define STM32H7_PD5_FUNC_FMC_NWE 0x350d +#define STM32H7_PD5_FUNC_EVENTOUT 0x3510 +#define STM32H7_PD5_FUNC_ANALOG 0x3511 + +#define STM32H7_PD6_FUNC_GPIO 0x3600 +#define STM32H7_PD6_FUNC_SAI1_D1 0x3603 +#define STM32H7_PD6_FUNC_DFSDM_CKIN4 0x3604 +#define STM32H7_PD6_FUNC_DFSDM_DATIN1 0x3605 +#define STM32H7_PD6_FUNC_SPI3_MOSI_I2S3_SDO 0x3606 +#define STM32H7_PD6_FUNC_SAI1_SD_A 0x3607 +#define STM32H7_PD6_FUNC_USART2_RX 0x3608 +#define STM32H7_PD6_FUNC_SAI4_SD_A 0x3609 +#define STM32H7_PD6_FUNC_CAN2_RXFD 0x360a +#define STM32H7_PD6_FUNC_SAI4_D1 0x360b +#define STM32H7_PD6_FUNC_SDMMC2_CK 0x360c +#define STM32H7_PD6_FUNC_FMC_NWAIT 0x360d +#define STM32H7_PD6_FUNC_DCMI_D10 0x360e +#define STM32H7_PD6_FUNC_LCD_B2 0x360f +#define STM32H7_PD6_FUNC_EVENTOUT 0x3610 +#define STM32H7_PD6_FUNC_ANALOG 0x3611 + +#define STM32H7_PD7_FUNC_GPIO 0x3700 +#define STM32H7_PD7_FUNC_DFSDM_DATIN4 0x3704 +#define STM32H7_PD7_FUNC_SPI1_MOSI_I2S1_SDO 0x3706 +#define STM32H7_PD7_FUNC_DFSDM_CKIN1 0x3707 +#define STM32H7_PD7_FUNC_USART2_CK 0x3708 +#define STM32H7_PD7_FUNC_SPDIFRX_IN0 0x370a +#define STM32H7_PD7_FUNC_SDMMC2_CMD 0x370c +#define STM32H7_PD7_FUNC_FMC_NE1 0x370d +#define STM32H7_PD7_FUNC_EVENTOUT 0x3710 +#define STM32H7_PD7_FUNC_ANALOG 0x3711 + +#define STM32H7_PD8_FUNC_GPIO 0x3800 +#define STM32H7_PD8_FUNC_DFSDM_CKIN3 0x3804 +#define STM32H7_PD8_FUNC_SAI3_SCK_B 0x3807 +#define STM32H7_PD8_FUNC_USART3_TX 0x3808 +#define STM32H7_PD8_FUNC_SPDIFRX_IN1 0x380a +#define STM32H7_PD8_FUNC_FMC_D13_FMC_DA13 0x380d +#define STM32H7_PD8_FUNC_EVENTOUT 0x3810 +#define STM32H7_PD8_FUNC_ANALOG 0x3811 + +#define STM32H7_PD9_FUNC_GPIO 0x3900 +#define STM32H7_PD9_FUNC_DFSDM_DATIN3 0x3904 +#define STM32H7_PD9_FUNC_SAI3_SD_B 0x3907 +#define STM32H7_PD9_FUNC_USART3_RX 0x3908 +#define STM32H7_PD9_FUNC_CAN2_RXFD 0x390a +#define STM32H7_PD9_FUNC_FMC_D14_FMC_DA14 0x390d +#define STM32H7_PD9_FUNC_EVENTOUT 0x3910 +#define STM32H7_PD9_FUNC_ANALOG 0x3911 + +#define STM32H7_PD10_FUNC_GPIO 0x3a00 +#define STM32H7_PD10_FUNC_DFSDM_CKOUT 0x3a04 +#define STM32H7_PD10_FUNC_SAI3_FS_B 0x3a07 +#define STM32H7_PD10_FUNC_USART3_CK 0x3a08 +#define STM32H7_PD10_FUNC_CAN2_TXFD 0x3a0a +#define STM32H7_PD10_FUNC_FMC_D15_FMC_DA15 0x3a0d +#define STM32H7_PD10_FUNC_LCD_B3 0x3a0f +#define STM32H7_PD10_FUNC_EVENTOUT 0x3a10 +#define STM32H7_PD10_FUNC_ANALOG 0x3a11 + +#define STM32H7_PD11_FUNC_GPIO 0x3b00 +#define STM32H7_PD11_FUNC_LPTIM2_IN2 0x3b04 +#define STM32H7_PD11_FUNC_I2C4_SMBA 0x3b05 +#define STM32H7_PD11_FUNC_USART3_CTS_NSS 0x3b08 +#define STM32H7_PD11_FUNC_QUADSPI_BK1_IO0 0x3b0a +#define STM32H7_PD11_FUNC_SAI2_SD_A 0x3b0b +#define STM32H7_PD11_FUNC_FMC_A16 0x3b0d +#define STM32H7_PD11_FUNC_EVENTOUT 0x3b10 +#define STM32H7_PD11_FUNC_ANALOG 0x3b11 + +#define STM32H7_PD12_FUNC_GPIO 0x3c00 +#define STM32H7_PD12_FUNC_LPTIM1_IN1 0x3c02 +#define STM32H7_PD12_FUNC_TIM4_CH1 0x3c03 +#define STM32H7_PD12_FUNC_LPTIM2_IN1 0x3c04 +#define STM32H7_PD12_FUNC_I2C4_SCL 0x3c05 +#define STM32H7_PD12_FUNC_USART3_RTS 0x3c08 +#define STM32H7_PD12_FUNC_QUADSPI_BK1_IO1 0x3c0a +#define STM32H7_PD12_FUNC_SAI2_FS_A 0x3c0b +#define STM32H7_PD12_FUNC_FMC_A17 0x3c0d +#define STM32H7_PD12_FUNC_EVENTOUT 0x3c10 +#define STM32H7_PD12_FUNC_ANALOG 0x3c11 + +#define STM32H7_PD13_FUNC_GPIO 0x3d00 +#define STM32H7_PD13_FUNC_LPTIM1_OUT 0x3d02 +#define STM32H7_PD13_FUNC_TIM4_CH2 0x3d03 +#define STM32H7_PD13_FUNC_I2C4_SDA 0x3d05 +#define STM32H7_PD13_FUNC_QUADSPI_BK1_IO3 0x3d0a +#define STM32H7_PD13_FUNC_SAI2_SCK_A 0x3d0b +#define STM32H7_PD13_FUNC_FMC_A18 0x3d0d +#define STM32H7_PD13_FUNC_EVENTOUT 0x3d10 +#define STM32H7_PD13_FUNC_ANALOG 0x3d11 + +#define STM32H7_PD14_FUNC_GPIO 0x3e00 +#define STM32H7_PD14_FUNC_TIM4_CH3 0x3e03 +#define STM32H7_PD14_FUNC_SAI3_MCLK_B 0x3e07 +#define STM32H7_PD14_FUNC_UART8_CTS 0x3e09 +#define STM32H7_PD14_FUNC_FMC_D0_FMC_DA0 0x3e0d +#define STM32H7_PD14_FUNC_EVENTOUT 0x3e10 +#define STM32H7_PD14_FUNC_ANALOG 0x3e11 + +#define STM32H7_PD15_FUNC_GPIO 0x3f00 +#define STM32H7_PD15_FUNC_TIM4_CH4 0x3f03 +#define STM32H7_PD15_FUNC_SAI3_MCLK_A 0x3f07 +#define STM32H7_PD15_FUNC_UART8_RTS 0x3f09 +#define STM32H7_PD15_FUNC_FMC_D1_FMC_DA1 0x3f0d +#define STM32H7_PD15_FUNC_EVENTOUT 0x3f10 +#define STM32H7_PD15_FUNC_ANALOG 0x3f11 + +#define STM32H7_PE0_FUNC_GPIO 0x4000 +#define STM32H7_PE0_FUNC_LPTIM1_ETR 0x4002 +#define STM32H7_PE0_FUNC_TIM4_ETR 0x4003 +#define STM32H7_PE0_FUNC_HRTIM_SCIN 0x4004 +#define STM32H7_PE0_FUNC_LPTIM2_ETR 0x4005 +#define STM32H7_PE0_FUNC_UART8_RX 0x4009 +#define STM32H7_PE0_FUNC_CAN1_RXFD 0x400a +#define STM32H7_PE0_FUNC_SAI2_MCK_A 0x400b +#define STM32H7_PE0_FUNC_FMC_NBL0 0x400d +#define STM32H7_PE0_FUNC_DCMI_D2 0x400e +#define STM32H7_PE0_FUNC_EVENTOUT 0x4010 +#define STM32H7_PE0_FUNC_ANALOG 0x4011 + +#define STM32H7_PE1_FUNC_GPIO 0x4100 +#define STM32H7_PE1_FUNC_LPTIM1_IN2 0x4102 +#define STM32H7_PE1_FUNC_HRTIM_SCOUT 0x4104 +#define STM32H7_PE1_FUNC_UART8_TX 0x4109 +#define STM32H7_PE1_FUNC_CAN1_TXFD 0x410a +#define STM32H7_PE1_FUNC_FMC_NBL1 0x410d +#define STM32H7_PE1_FUNC_DCMI_D3 0x410e +#define STM32H7_PE1_FUNC_EVENTOUT 0x4110 +#define STM32H7_PE1_FUNC_ANALOG 0x4111 + +#define STM32H7_PE2_FUNC_GPIO 0x4200 +#define STM32H7_PE2_FUNC_TRACECLK 0x4201 +#define STM32H7_PE2_FUNC_SAI1_CK1 0x4203 +#define STM32H7_PE2_FUNC_SPI4_SCK 0x4206 +#define STM32H7_PE2_FUNC_SAI1_MCLK_A 0x4207 +#define STM32H7_PE2_FUNC_SAI4_MCLK_A 0x4209 +#define STM32H7_PE2_FUNC_QUADSPI_BK1_IO2 0x420a +#define STM32H7_PE2_FUNC_SAI4_CK1 0x420b +#define STM32H7_PE2_FUNC_ETH_MII_TXD3 0x420c +#define STM32H7_PE2_FUNC_FMC_A23 0x420d +#define STM32H7_PE2_FUNC_EVENTOUT 0x4210 +#define STM32H7_PE2_FUNC_ANALOG 0x4211 + +#define STM32H7_PE3_FUNC_GPIO 0x4300 +#define STM32H7_PE3_FUNC_TRACED0 0x4301 +#define STM32H7_PE3_FUNC_TIM15_BKIN 0x4305 +#define STM32H7_PE3_FUNC_SAI1_SD_B 0x4307 +#define STM32H7_PE3_FUNC_SAI4_SD_B 0x4309 +#define STM32H7_PE3_FUNC_FMC_A19 0x430d +#define STM32H7_PE3_FUNC_EVENTOUT 0x4310 +#define STM32H7_PE3_FUNC_ANALOG 0x4311 + +#define STM32H7_PE4_FUNC_GPIO 0x4400 +#define STM32H7_PE4_FUNC_TRACED1 0x4401 +#define STM32H7_PE4_FUNC_SAI1_D2 0x4403 +#define STM32H7_PE4_FUNC_DFSDM_DATIN3 0x4404 +#define STM32H7_PE4_FUNC_TIM15_CH1N 0x4405 +#define STM32H7_PE4_FUNC_SPI4_NSS 0x4406 +#define STM32H7_PE4_FUNC_SAI1_FS_A 0x4407 +#define STM32H7_PE4_FUNC_SAI4_FS_A 0x4409 +#define STM32H7_PE4_FUNC_SAI4_D2 0x440b +#define STM32H7_PE4_FUNC_FMC_A20 0x440d +#define STM32H7_PE4_FUNC_DCMI_D4 0x440e +#define STM32H7_PE4_FUNC_LCD_B0 0x440f +#define STM32H7_PE4_FUNC_EVENTOUT 0x4410 +#define STM32H7_PE4_FUNC_ANALOG 0x4411 + +#define STM32H7_PE5_FUNC_GPIO 0x4500 +#define STM32H7_PE5_FUNC_TRACED2 0x4501 +#define STM32H7_PE5_FUNC_SAI1_CK2 0x4503 +#define STM32H7_PE5_FUNC_DFSDM_CKIN3 0x4504 +#define STM32H7_PE5_FUNC_TIM15_CH1 0x4505 +#define STM32H7_PE5_FUNC_SPI4_MISO 0x4506 +#define STM32H7_PE5_FUNC_SAI1_SCK_A 0x4507 +#define STM32H7_PE5_FUNC_SAI4_SCK_A 0x4509 +#define STM32H7_PE5_FUNC_SAI4_CK2 0x450b +#define STM32H7_PE5_FUNC_FMC_A21 0x450d +#define STM32H7_PE5_FUNC_DCMI_D6 0x450e +#define STM32H7_PE5_FUNC_LCD_G0 0x450f +#define STM32H7_PE5_FUNC_EVENTOUT 0x4510 +#define STM32H7_PE5_FUNC_ANALOG 0x4511 + +#define STM32H7_PE6_FUNC_GPIO 0x4600 +#define STM32H7_PE6_FUNC_TRACED3 0x4601 +#define STM32H7_PE6_FUNC_TIM1_BKIN2 0x4602 +#define STM32H7_PE6_FUNC_SAI1_D1 0x4603 +#define STM32H7_PE6_FUNC_TIM15_CH2 0x4605 +#define STM32H7_PE6_FUNC_SPI4_MOSI 0x4606 +#define STM32H7_PE6_FUNC_SAI1_SD_A 0x4607 +#define STM32H7_PE6_FUNC_SAI4_SD_A 0x4609 +#define STM32H7_PE6_FUNC_SAI4_D1 0x460a +#define STM32H7_PE6_FUNC_SAI2_MCK_B 0x460b +#define STM32H7_PE6_FUNC_TIM1_BKIN2_COMP12 0x460c +#define STM32H7_PE6_FUNC_FMC_A22 0x460d +#define STM32H7_PE6_FUNC_DCMI_D7 0x460e +#define STM32H7_PE6_FUNC_LCD_G1 0x460f +#define STM32H7_PE6_FUNC_EVENTOUT 0x4610 +#define STM32H7_PE6_FUNC_ANALOG 0x4611 + +#define STM32H7_PE7_FUNC_GPIO 0x4700 +#define STM32H7_PE7_FUNC_TIM1_ETR 0x4702 +#define STM32H7_PE7_FUNC_DFSDM_DATIN2 0x4704 +#define STM32H7_PE7_FUNC_UART7_RX 0x4708 +#define STM32H7_PE7_FUNC_QUADSPI_BK2_IO0 0x470b +#define STM32H7_PE7_FUNC_FMC_D4_FMC_DA4 0x470d +#define STM32H7_PE7_FUNC_EVENTOUT 0x4710 +#define STM32H7_PE7_FUNC_ANALOG 0x4711 + +#define STM32H7_PE8_FUNC_GPIO 0x4800 +#define STM32H7_PE8_FUNC_TIM1_CH1N 0x4802 +#define STM32H7_PE8_FUNC_DFSDM_CKIN2 0x4804 +#define STM32H7_PE8_FUNC_UART7_TX 0x4808 +#define STM32H7_PE8_FUNC_QUADSPI_BK2_IO1 0x480b +#define STM32H7_PE8_FUNC_FMC_D5_FMC_DA5 0x480d +#define STM32H7_PE8_FUNC_COMP_2_OUT 0x480e +#define STM32H7_PE8_FUNC_EVENTOUT 0x4810 +#define STM32H7_PE8_FUNC_ANALOG 0x4811 + +#define STM32H7_PE9_FUNC_GPIO 0x4900 +#define STM32H7_PE9_FUNC_TIM1_CH1 0x4902 +#define STM32H7_PE9_FUNC_DFSDM_CKOUT 0x4904 +#define STM32H7_PE9_FUNC_UART7_RTS 0x4908 +#define STM32H7_PE9_FUNC_QUADSPI_BK2_IO2 0x490b +#define STM32H7_PE9_FUNC_FMC_D6_FMC_DA6 0x490d +#define STM32H7_PE9_FUNC_EVENTOUT 0x4910 +#define STM32H7_PE9_FUNC_ANALOG 0x4911 + +#define STM32H7_PE10_FUNC_GPIO 0x4a00 +#define STM32H7_PE10_FUNC_TIM1_CH2N 0x4a02 +#define STM32H7_PE10_FUNC_DFSDM_DATIN4 0x4a04 +#define STM32H7_PE10_FUNC_UART7_CTS 0x4a08 +#define STM32H7_PE10_FUNC_QUADSPI_BK2_IO3 0x4a0b +#define STM32H7_PE10_FUNC_FMC_D7_FMC_DA7 0x4a0d +#define STM32H7_PE10_FUNC_EVENTOUT 0x4a10 +#define STM32H7_PE10_FUNC_ANALOG 0x4a11 + +#define STM32H7_PE11_FUNC_GPIO 0x4b00 +#define STM32H7_PE11_FUNC_TIM1_CH2 0x4b02 +#define STM32H7_PE11_FUNC_DFSDM_CKIN4 0x4b04 +#define STM32H7_PE11_FUNC_SPI4_NSS 0x4b06 +#define STM32H7_PE11_FUNC_SAI2_SD_B 0x4b0b +#define STM32H7_PE11_FUNC_FMC_D8_FMC_DA8 0x4b0d +#define STM32H7_PE11_FUNC_LCD_G3 0x4b0f +#define STM32H7_PE11_FUNC_EVENTOUT 0x4b10 +#define STM32H7_PE11_FUNC_ANALOG 0x4b11 + +#define STM32H7_PE12_FUNC_GPIO 0x4c00 +#define STM32H7_PE12_FUNC_TIM1_CH3N 0x4c02 +#define STM32H7_PE12_FUNC_DFSDM_DATIN5 0x4c04 +#define STM32H7_PE12_FUNC_SPI4_SCK 0x4c06 +#define STM32H7_PE12_FUNC_SAI2_SCK_B 0x4c0b +#define STM32H7_PE12_FUNC_FMC_D9_FMC_DA9 0x4c0d +#define STM32H7_PE12_FUNC_COMP_1_OUT 0x4c0e +#define STM32H7_PE12_FUNC_LCD_B4 0x4c0f +#define STM32H7_PE12_FUNC_EVENTOUT 0x4c10 +#define STM32H7_PE12_FUNC_ANALOG 0x4c11 + +#define STM32H7_PE13_FUNC_GPIO 0x4d00 +#define STM32H7_PE13_FUNC_TIM1_CH3 0x4d02 +#define STM32H7_PE13_FUNC_DFSDM_CKIN5 0x4d04 +#define STM32H7_PE13_FUNC_SPI4_MISO 0x4d06 +#define STM32H7_PE13_FUNC_SAI2_FS_B 0x4d0b +#define STM32H7_PE13_FUNC_FMC_D10_FMC_DA10 0x4d0d +#define STM32H7_PE13_FUNC_COMP_2_OUT 0x4d0e +#define STM32H7_PE13_FUNC_LCD_DE 0x4d0f +#define STM32H7_PE13_FUNC_EVENTOUT 0x4d10 +#define STM32H7_PE13_FUNC_ANALOG 0x4d11 + +#define STM32H7_PE14_FUNC_GPIO 0x4e00 +#define STM32H7_PE14_FUNC_TIM1_CH4 0x4e02 +#define STM32H7_PE14_FUNC_SPI4_MOSI 0x4e06 +#define STM32H7_PE14_FUNC_SAI2_MCK_B 0x4e0b +#define STM32H7_PE14_FUNC_FMC_D11_FMC_DA11 0x4e0d +#define STM32H7_PE14_FUNC_LCD_CLK 0x4e0f +#define STM32H7_PE14_FUNC_EVENTOUT 0x4e10 +#define STM32H7_PE14_FUNC_ANALOG 0x4e11 + +#define STM32H7_PE15_FUNC_GPIO 0x4f00 +#define STM32H7_PE15_FUNC_TIM1_BKIN 0x4f02 +#define STM32H7_PE15_FUNC_HDMI__TIM1_BKIN 0x4f06 +#define STM32H7_PE15_FUNC_FMC_D12_FMC_DA12 0x4f0d +#define STM32H7_PE15_FUNC_TIM1_BKIN_COMP12 0x4f0e +#define STM32H7_PE15_FUNC_LCD_R7 0x4f0f +#define STM32H7_PE15_FUNC_EVENTOUT 0x4f10 +#define STM32H7_PE15_FUNC_ANALOG 0x4f11 + +#define STM32H7_PF0_FUNC_GPIO 0x5000 +#define STM32H7_PF0_FUNC_I2C2_SDA 0x5005 +#define STM32H7_PF0_FUNC_FMC_A0 0x500d +#define STM32H7_PF0_FUNC_EVENTOUT 0x5010 +#define STM32H7_PF0_FUNC_ANALOG 0x5011 + +#define STM32H7_PF1_FUNC_GPIO 0x5100 +#define STM32H7_PF1_FUNC_I2C2_SCL 0x5105 +#define STM32H7_PF1_FUNC_FMC_A1 0x510d +#define STM32H7_PF1_FUNC_EVENTOUT 0x5110 +#define STM32H7_PF1_FUNC_ANALOG 0x5111 + +#define STM32H7_PF2_FUNC_GPIO 0x5200 +#define STM32H7_PF2_FUNC_I2C2_SMBA 0x5205 +#define STM32H7_PF2_FUNC_FMC_A2 0x520d +#define STM32H7_PF2_FUNC_EVENTOUT 0x5210 +#define STM32H7_PF2_FUNC_ANALOG 0x5211 + +#define STM32H7_PF3_FUNC_GPIO 0x5300 +#define STM32H7_PF3_FUNC_FMC_A3 0x530d +#define STM32H7_PF3_FUNC_EVENTOUT 0x5310 +#define STM32H7_PF3_FUNC_ANALOG 0x5311 + +#define STM32H7_PF4_FUNC_GPIO 0x5400 +#define STM32H7_PF4_FUNC_FMC_A4 0x540d +#define STM32H7_PF4_FUNC_EVENTOUT 0x5410 +#define STM32H7_PF4_FUNC_ANALOG 0x5411 + +#define STM32H7_PF5_FUNC_GPIO 0x5500 +#define STM32H7_PF5_FUNC_FMC_A5 0x550d +#define STM32H7_PF5_FUNC_EVENTOUT 0x5510 +#define STM32H7_PF5_FUNC_ANALOG 0x5511 + +#define STM32H7_PF6_FUNC_GPIO 0x5600 +#define STM32H7_PF6_FUNC_TIM16_CH1 0x5602 +#define STM32H7_PF6_FUNC_SPI5_NSS 0x5606 +#define STM32H7_PF6_FUNC_SAI1_SD_B 0x5607 +#define STM32H7_PF6_FUNC_UART7_RX 0x5608 +#define STM32H7_PF6_FUNC_SAI4_SD_B 0x5609 +#define STM32H7_PF6_FUNC_QUADSPI_BK1_IO3 0x560a +#define STM32H7_PF6_FUNC_EVENTOUT 0x5610 +#define STM32H7_PF6_FUNC_ANALOG 0x5611 + +#define STM32H7_PF7_FUNC_GPIO 0x5700 +#define STM32H7_PF7_FUNC_TIM17_CH1 0x5702 +#define STM32H7_PF7_FUNC_SPI5_SCK 0x5706 +#define STM32H7_PF7_FUNC_SAI1_MCLK_B 0x5707 +#define STM32H7_PF7_FUNC_UART7_TX 0x5708 +#define STM32H7_PF7_FUNC_SAI4_MCLK_B 0x5709 +#define STM32H7_PF7_FUNC_QUADSPI_BK1_IO2 0x570a +#define STM32H7_PF7_FUNC_EVENTOUT 0x5710 +#define STM32H7_PF7_FUNC_ANALOG 0x5711 + +#define STM32H7_PF8_FUNC_GPIO 0x5800 +#define STM32H7_PF8_FUNC_TIM16_CH1N 0x5802 +#define STM32H7_PF8_FUNC_SPI5_MISO 0x5806 +#define STM32H7_PF8_FUNC_SAI1_SCK_B 0x5807 +#define STM32H7_PF8_FUNC_UART7_RTS 0x5808 +#define STM32H7_PF8_FUNC_SAI4_SCK_B 0x5809 +#define STM32H7_PF8_FUNC_TIM13_CH1 0x580a +#define STM32H7_PF8_FUNC_QUADSPI_BK1_IO0 0x580b +#define STM32H7_PF8_FUNC_EVENTOUT 0x5810 +#define STM32H7_PF8_FUNC_ANALOG 0x5811 + +#define STM32H7_PF9_FUNC_GPIO 0x5900 +#define STM32H7_PF9_FUNC_TIM17_CH1N 0x5902 +#define STM32H7_PF9_FUNC_SPI5_MOSI 0x5906 +#define STM32H7_PF9_FUNC_SAI1_FS_B 0x5907 +#define STM32H7_PF9_FUNC_UART7_CTS 0x5908 +#define STM32H7_PF9_FUNC_SAI4_FS_B 0x5909 +#define STM32H7_PF9_FUNC_TIM14_CH1 0x590a +#define STM32H7_PF9_FUNC_QUADSPI_BK1_IO1 0x590b +#define STM32H7_PF9_FUNC_EVENTOUT 0x5910 +#define STM32H7_PF9_FUNC_ANALOG 0x5911 + +#define STM32H7_PF10_FUNC_GPIO 0x5a00 +#define STM32H7_PF10_FUNC_TIM16_BKIN 0x5a02 +#define STM32H7_PF10_FUNC_SAI1_D3 0x5a03 +#define STM32H7_PF10_FUNC_QUADSPI_CLK 0x5a0a +#define STM32H7_PF10_FUNC_SAI4_D3 0x5a0b +#define STM32H7_PF10_FUNC_DCMI_D11 0x5a0e +#define STM32H7_PF10_FUNC_LCD_DE 0x5a0f +#define STM32H7_PF10_FUNC_EVENTOUT 0x5a10 +#define STM32H7_PF10_FUNC_ANALOG 0x5a11 + +#define STM32H7_PF11_FUNC_GPIO 0x5b00 +#define STM32H7_PF11_FUNC_SPI5_MOSI 0x5b06 +#define STM32H7_PF11_FUNC_SAI2_SD_B 0x5b0b +#define STM32H7_PF11_FUNC_FMC_SDNRAS 0x5b0d +#define STM32H7_PF11_FUNC_DCMI_D12 0x5b0e +#define STM32H7_PF11_FUNC_EVENTOUT 0x5b10 +#define STM32H7_PF11_FUNC_ANALOG 0x5b11 + +#define STM32H7_PF12_FUNC_GPIO 0x5c00 +#define STM32H7_PF12_FUNC_FMC_A6 0x5c0d +#define STM32H7_PF12_FUNC_EVENTOUT 0x5c10 +#define STM32H7_PF12_FUNC_ANALOG 0x5c11 + +#define STM32H7_PF13_FUNC_GPIO 0x5d00 +#define STM32H7_PF13_FUNC_DFSDM_DATIN6 0x5d04 +#define STM32H7_PF13_FUNC_I2C4_SMBA 0x5d05 +#define STM32H7_PF13_FUNC_FMC_A7 0x5d0d +#define STM32H7_PF13_FUNC_EVENTOUT 0x5d10 +#define STM32H7_PF13_FUNC_ANALOG 0x5d11 + +#define STM32H7_PF14_FUNC_GPIO 0x5e00 +#define STM32H7_PF14_FUNC_DFSDM_CKIN6 0x5e04 +#define STM32H7_PF14_FUNC_I2C4_SCL 0x5e05 +#define STM32H7_PF14_FUNC_FMC_A8 0x5e0d +#define STM32H7_PF14_FUNC_EVENTOUT 0x5e10 +#define STM32H7_PF14_FUNC_ANALOG 0x5e11 + +#define STM32H7_PF15_FUNC_GPIO 0x5f00 +#define STM32H7_PF15_FUNC_I2C4_SDA 0x5f05 +#define STM32H7_PF15_FUNC_FMC_A9 0x5f0d +#define STM32H7_PF15_FUNC_EVENTOUT 0x5f10 +#define STM32H7_PF15_FUNC_ANALOG 0x5f11 + +#define STM32H7_PG0_FUNC_GPIO 0x6000 +#define STM32H7_PG0_FUNC_FMC_A10 0x600d +#define STM32H7_PG0_FUNC_EVENTOUT 0x6010 +#define STM32H7_PG0_FUNC_ANALOG 0x6011 + +#define STM32H7_PG1_FUNC_GPIO 0x6100 +#define STM32H7_PG1_FUNC_FMC_A11 0x610d +#define STM32H7_PG1_FUNC_EVENTOUT 0x6110 +#define STM32H7_PG1_FUNC_ANALOG 0x6111 + +#define STM32H7_PG2_FUNC_GPIO 0x6200 +#define STM32H7_PG2_FUNC_TIM8_BKIN 0x6204 +#define STM32H7_PG2_FUNC_TIM8_BKIN_COMP12 0x620c +#define STM32H7_PG2_FUNC_FMC_A12 0x620d +#define STM32H7_PG2_FUNC_EVENTOUT 0x6210 +#define STM32H7_PG2_FUNC_ANALOG 0x6211 + +#define STM32H7_PG3_FUNC_GPIO 0x6300 +#define STM32H7_PG3_FUNC_TIM8_BKIN2 0x6304 +#define STM32H7_PG3_FUNC_TIM8_BKIN2_COMP12 0x630c +#define STM32H7_PG3_FUNC_FMC_A13 0x630d +#define STM32H7_PG3_FUNC_EVENTOUT 0x6310 +#define STM32H7_PG3_FUNC_ANALOG 0x6311 + +#define STM32H7_PG4_FUNC_GPIO 0x6400 +#define STM32H7_PG4_FUNC_TIM1_BKIN2 0x6402 +#define STM32H7_PG4_FUNC_TIM1_BKIN2_COMP12 0x640c +#define STM32H7_PG4_FUNC_FMC_A14_FMC_BA0 0x640d +#define STM32H7_PG4_FUNC_EVENTOUT 0x6410 +#define STM32H7_PG4_FUNC_ANALOG 0x6411 + +#define STM32H7_PG5_FUNC_GPIO 0x6500 +#define STM32H7_PG5_FUNC_TIM1_ETR 0x6502 +#define STM32H7_PG5_FUNC_FMC_A15_FMC_BA1 0x650d +#define STM32H7_PG5_FUNC_EVENTOUT 0x6510 +#define STM32H7_PG5_FUNC_ANALOG 0x6511 + +#define STM32H7_PG6_FUNC_GPIO 0x6600 +#define STM32H7_PG6_FUNC_TIM17_BKIN 0x6602 +#define STM32H7_PG6_FUNC_HRTIM_CHE1 0x6603 +#define STM32H7_PG6_FUNC_QUADSPI_BK1_NCS 0x660b +#define STM32H7_PG6_FUNC_FMC_NE3 0x660d +#define STM32H7_PG6_FUNC_DCMI_D12 0x660e +#define STM32H7_PG6_FUNC_LCD_R7 0x660f +#define STM32H7_PG6_FUNC_EVENTOUT 0x6610 +#define STM32H7_PG6_FUNC_ANALOG 0x6611 + +#define STM32H7_PG7_FUNC_GPIO 0x6700 +#define STM32H7_PG7_FUNC_HRTIM_CHE2 0x6703 +#define STM32H7_PG7_FUNC_SAI1_MCLK_A 0x6707 +#define STM32H7_PG7_FUNC_USART6_CK 0x6708 +#define STM32H7_PG7_FUNC_FMC_INT 0x670d +#define STM32H7_PG7_FUNC_DCMI_D13 0x670e +#define STM32H7_PG7_FUNC_LCD_CLK 0x670f +#define STM32H7_PG7_FUNC_EVENTOUT 0x6710 +#define STM32H7_PG7_FUNC_ANALOG 0x6711 + +#define STM32H7_PG8_FUNC_GPIO 0x6800 +#define STM32H7_PG8_FUNC_TIM8_ETR 0x6804 +#define STM32H7_PG8_FUNC_SPI6_NSS 0x6806 +#define STM32H7_PG8_FUNC_USART6_RTS 0x6808 +#define STM32H7_PG8_FUNC_SPDIFRX_IN2 0x6809 +#define STM32H7_PG8_FUNC_ETH_PPS_OUT 0x680c +#define STM32H7_PG8_FUNC_FMC_SDCLK 0x680d +#define STM32H7_PG8_FUNC_LCD_G7 0x680f +#define STM32H7_PG8_FUNC_EVENTOUT 0x6810 +#define STM32H7_PG8_FUNC_ANALOG 0x6811 + +#define STM32H7_PG9_FUNC_GPIO 0x6900 +#define STM32H7_PG9_FUNC_SPI1_MISO_I2S1_SDI 0x6906 +#define STM32H7_PG9_FUNC_USART6_RX 0x6908 +#define STM32H7_PG9_FUNC_SPDIFRX_IN3 0x6909 +#define STM32H7_PG9_FUNC_QUADSPI_BK2_IO2 0x690a +#define STM32H7_PG9_FUNC_SAI2_FS_B 0x690b +#define STM32H7_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d +#define STM32H7_PG9_FUNC_DCMI_VSYNC 0x690e +#define STM32H7_PG9_FUNC_EVENTOUT 0x6910 +#define STM32H7_PG9_FUNC_ANALOG 0x6911 + +#define STM32H7_PG10_FUNC_GPIO 0x6a00 +#define STM32H7_PG10_FUNC_HRTIM_FLT5 0x6a03 +#define STM32H7_PG10_FUNC_SPI1_NSS_I2S1_WS 0x6a06 +#define STM32H7_PG10_FUNC_LCD_G3 0x6a0a +#define STM32H7_PG10_FUNC_SAI2_SD_B 0x6a0b +#define STM32H7_PG10_FUNC_FMC_NE3 0x6a0d +#define STM32H7_PG10_FUNC_DCMI_D2 0x6a0e +#define STM32H7_PG10_FUNC_LCD_B2 0x6a0f +#define STM32H7_PG10_FUNC_EVENTOUT 0x6a10 +#define STM32H7_PG10_FUNC_ANALOG 0x6a11 + +#define STM32H7_PG11_FUNC_GPIO 0x6b00 +#define STM32H7_PG11_FUNC_HRTIM_EEV4 0x6b03 +#define STM32H7_PG11_FUNC_SPI1_SCK_I2S1_CK 0x6b06 +#define STM32H7_PG11_FUNC_SPDIFRX_IN0 0x6b09 +#define STM32H7_PG11_FUNC_SDMMC2_D2 0x6b0b +#define STM32H7_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c +#define STM32H7_PG11_FUNC_DCMI_D3 0x6b0e +#define STM32H7_PG11_FUNC_LCD_B3 0x6b0f +#define STM32H7_PG11_FUNC_EVENTOUT 0x6b10 +#define STM32H7_PG11_FUNC_ANALOG 0x6b11 + +#define STM32H7_PG12_FUNC_GPIO 0x6c00 +#define STM32H7_PG12_FUNC_LPTIM1_IN1 0x6c02 +#define STM32H7_PG12_FUNC_HRTIM_EEV5 0x6c03 +#define STM32H7_PG12_FUNC_SPI6_MISO 0x6c06 +#define STM32H7_PG12_FUNC_USART6_RTS 0x6c08 +#define STM32H7_PG12_FUNC_SPDIFRX_IN1 0x6c09 +#define STM32H7_PG12_FUNC_LCD_B4 0x6c0a +#define STM32H7_PG12_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6c0c +#define STM32H7_PG12_FUNC_FMC_NE4 0x6c0d +#define STM32H7_PG12_FUNC_LCD_B1 0x6c0f +#define STM32H7_PG12_FUNC_EVENTOUT 0x6c10 +#define STM32H7_PG12_FUNC_ANALOG 0x6c11 + +#define STM32H7_PG13_FUNC_GPIO 0x6d00 +#define STM32H7_PG13_FUNC_TRACED0 0x6d01 +#define STM32H7_PG13_FUNC_LPTIM1_OUT 0x6d02 +#define STM32H7_PG13_FUNC_HRTIM_EEV10 0x6d03 +#define STM32H7_PG13_FUNC_SPI6_SCK 0x6d06 +#define STM32H7_PG13_FUNC_USART6_CTS_NSS 0x6d08 +#define STM32H7_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c +#define STM32H7_PG13_FUNC_FMC_A24 0x6d0d +#define STM32H7_PG13_FUNC_LCD_R0 0x6d0f +#define STM32H7_PG13_FUNC_EVENTOUT 0x6d10 +#define STM32H7_PG13_FUNC_ANALOG 0x6d11 + +#define STM32H7_PG14_FUNC_GPIO 0x6e00 +#define STM32H7_PG14_FUNC_TRACED1 0x6e01 +#define STM32H7_PG14_FUNC_LPTIM1_ETR 0x6e02 +#define STM32H7_PG14_FUNC_SPI6_MOSI 0x6e06 +#define STM32H7_PG14_FUNC_USART6_TX 0x6e08 +#define STM32H7_PG14_FUNC_QUADSPI_BK2_IO3 0x6e0a +#define STM32H7_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c +#define STM32H7_PG14_FUNC_FMC_A25 0x6e0d +#define STM32H7_PG14_FUNC_LCD_B0 0x6e0f +#define STM32H7_PG14_FUNC_EVENTOUT 0x6e10 +#define STM32H7_PG14_FUNC_ANALOG 0x6e11 + +#define STM32H7_PG15_FUNC_GPIO 0x6f00 +#define STM32H7_PG15_FUNC_USART6_CTS_NSS 0x6f08 +#define STM32H7_PG15_FUNC_FMC_SDNCAS 0x6f0d +#define STM32H7_PG15_FUNC_DCMI_D13 0x6f0e +#define STM32H7_PG15_FUNC_EVENTOUT 0x6f10 +#define STM32H7_PG15_FUNC_ANALOG 0x6f11 + +#define STM32H7_PH0_FUNC_GPIO 0x7000 +#define STM32H7_PH0_FUNC_EVENTOUT 0x7010 +#define STM32H7_PH0_FUNC_ANALOG 0x7011 + +#define STM32H7_PH1_FUNC_GPIO 0x7100 +#define STM32H7_PH1_FUNC_EVENTOUT 0x7110 +#define STM32H7_PH1_FUNC_ANALOG 0x7111 + +#define STM32H7_PH2_FUNC_GPIO 0x7200 +#define STM32H7_PH2_FUNC_LPTIM1_IN2 0x7202 +#define STM32H7_PH2_FUNC_QUADSPI_BK2_IO0 0x720a +#define STM32H7_PH2_FUNC_SAI2_SCK_B 0x720b +#define STM32H7_PH2_FUNC_ETH_MII_CRS 0x720c +#define STM32H7_PH2_FUNC_FMC_SDCKE0 0x720d +#define STM32H7_PH2_FUNC_LCD_R0 0x720f +#define STM32H7_PH2_FUNC_EVENTOUT 0x7210 +#define STM32H7_PH2_FUNC_ANALOG 0x7211 + +#define STM32H7_PH3_FUNC_GPIO 0x7300 +#define STM32H7_PH3_FUNC_QUADSPI_BK2_IO1 0x730a +#define STM32H7_PH3_FUNC_SAI2_MCK_B 0x730b +#define STM32H7_PH3_FUNC_ETH_MII_COL 0x730c +#define STM32H7_PH3_FUNC_FMC_SDNE0 0x730d +#define STM32H7_PH3_FUNC_LCD_R1 0x730f +#define STM32H7_PH3_FUNC_EVENTOUT 0x7310 +#define STM32H7_PH3_FUNC_ANALOG 0x7311 + +#define STM32H7_PH4_FUNC_GPIO 0x7400 +#define STM32H7_PH4_FUNC_I2C2_SCL 0x7405 +#define STM32H7_PH4_FUNC_LCD_G5 0x740a +#define STM32H7_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b +#define STM32H7_PH4_FUNC_LCD_G4 0x740f +#define STM32H7_PH4_FUNC_EVENTOUT 0x7410 +#define STM32H7_PH4_FUNC_ANALOG 0x7411 + +#define STM32H7_PH5_FUNC_GPIO 0x7500 +#define STM32H7_PH5_FUNC_I2C2_SDA 0x7505 +#define STM32H7_PH5_FUNC_SPI5_NSS 0x7506 +#define STM32H7_PH5_FUNC_FMC_SDNWE 0x750d +#define STM32H7_PH5_FUNC_EVENTOUT 0x7510 +#define STM32H7_PH5_FUNC_ANALOG 0x7511 + +#define STM32H7_PH6_FUNC_GPIO 0x7600 +#define STM32H7_PH6_FUNC_I2C2_SMBA 0x7605 +#define STM32H7_PH6_FUNC_SPI5_SCK 0x7606 +#define STM32H7_PH6_FUNC_ETH_MII_RXD2 0x760c +#define STM32H7_PH6_FUNC_FMC_SDNE1 0x760d +#define STM32H7_PH6_FUNC_DCMI_D8 0x760e +#define STM32H7_PH6_FUNC_EVENTOUT 0x7610 +#define STM32H7_PH6_FUNC_ANALOG 0x7611 + +#define STM32H7_PH7_FUNC_GPIO 0x7700 +#define STM32H7_PH7_FUNC_I2C3_SCL 0x7705 +#define STM32H7_PH7_FUNC_SPI5_MISO 0x7706 +#define STM32H7_PH7_FUNC_ETH_MII_RXD3 0x770c +#define STM32H7_PH7_FUNC_FMC_SDCKE1 0x770d +#define STM32H7_PH7_FUNC_DCMI_D9 0x770e +#define STM32H7_PH7_FUNC_EVENTOUT 0x7710 +#define STM32H7_PH7_FUNC_ANALOG 0x7711 + +#define STM32H7_PH8_FUNC_GPIO 0x7800 +#define STM32H7_PH8_FUNC_TIM5_ETR 0x7803 +#define STM32H7_PH8_FUNC_I2C3_SDA 0x7805 +#define STM32H7_PH8_FUNC_FMC_D16 0x780d +#define STM32H7_PH8_FUNC_DCMI_HSYNC 0x780e +#define STM32H7_PH8_FUNC_LCD_R2 0x780f +#define STM32H7_PH8_FUNC_EVENTOUT 0x7810 +#define STM32H7_PH8_FUNC_ANALOG 0x7811 + +#define STM32H7_PH9_FUNC_GPIO 0x7900 +#define STM32H7_PH9_FUNC_I2C3_SMBA 0x7905 +#define STM32H7_PH9_FUNC_FMC_D17 0x790d +#define STM32H7_PH9_FUNC_DCMI_D0 0x790e +#define STM32H7_PH9_FUNC_LCD_R3 0x790f +#define STM32H7_PH9_FUNC_EVENTOUT 0x7910 +#define STM32H7_PH9_FUNC_ANALOG 0x7911 + +#define STM32H7_PH10_FUNC_GPIO 0x7a00 +#define STM32H7_PH10_FUNC_TIM5_CH1 0x7a03 +#define STM32H7_PH10_FUNC_I2C4_SMBA 0x7a05 +#define STM32H7_PH10_FUNC_FMC_D18 0x7a0d +#define STM32H7_PH10_FUNC_DCMI_D1 0x7a0e +#define STM32H7_PH10_FUNC_LCD_R4 0x7a0f +#define STM32H7_PH10_FUNC_EVENTOUT 0x7a10 +#define STM32H7_PH10_FUNC_ANALOG 0x7a11 + +#define STM32H7_PH11_FUNC_GPIO 0x7b00 +#define STM32H7_PH11_FUNC_TIM5_CH2 0x7b03 +#define STM32H7_PH11_FUNC_I2C4_SCL 0x7b05 +#define STM32H7_PH11_FUNC_FMC_D19 0x7b0d +#define STM32H7_PH11_FUNC_DCMI_D2 0x7b0e +#define STM32H7_PH11_FUNC_LCD_R5 0x7b0f +#define STM32H7_PH11_FUNC_EVENTOUT 0x7b10 +#define STM32H7_PH11_FUNC_ANALOG 0x7b11 + +#define STM32H7_PH12_FUNC_GPIO 0x7c00 +#define STM32H7_PH12_FUNC_TIM5_CH3 0x7c03 +#define STM32H7_PH12_FUNC_I2C4_SDA 0x7c05 +#define STM32H7_PH12_FUNC_FMC_D20 0x7c0d +#define STM32H7_PH12_FUNC_DCMI_D3 0x7c0e +#define STM32H7_PH12_FUNC_LCD_R6 0x7c0f +#define STM32H7_PH12_FUNC_EVENTOUT 0x7c10 +#define STM32H7_PH12_FUNC_ANALOG 0x7c11 + +#define STM32H7_PH13_FUNC_GPIO 0x7d00 +#define STM32H7_PH13_FUNC_TIM8_CH1N 0x7d04 +#define STM32H7_PH13_FUNC_UART4_TX 0x7d09 +#define STM32H7_PH13_FUNC_CAN1_TX 0x7d0a +#define STM32H7_PH13_FUNC_FMC_D21 0x7d0d +#define STM32H7_PH13_FUNC_LCD_G2 0x7d0f +#define STM32H7_PH13_FUNC_EVENTOUT 0x7d10 +#define STM32H7_PH13_FUNC_ANALOG 0x7d11 + +#define STM32H7_PH14_FUNC_GPIO 0x7e00 +#define STM32H7_PH14_FUNC_TIM8_CH2N 0x7e04 +#define STM32H7_PH14_FUNC_UART4_RX 0x7e09 +#define STM32H7_PH14_FUNC_CAN1_RX 0x7e0a +#define STM32H7_PH14_FUNC_FMC_D22 0x7e0d +#define STM32H7_PH14_FUNC_DCMI_D4 0x7e0e +#define STM32H7_PH14_FUNC_LCD_G3 0x7e0f +#define STM32H7_PH14_FUNC_EVENTOUT 0x7e10 +#define STM32H7_PH14_FUNC_ANALOG 0x7e11 + +#define STM32H7_PH15_FUNC_GPIO 0x7f00 +#define STM32H7_PH15_FUNC_TIM8_CH3N 0x7f04 +#define STM32H7_PH15_FUNC_CAN1_TXFD 0x7f0a +#define STM32H7_PH15_FUNC_FMC_D23 0x7f0d +#define STM32H7_PH15_FUNC_DCMI_D11 0x7f0e +#define STM32H7_PH15_FUNC_LCD_G4 0x7f0f +#define STM32H7_PH15_FUNC_EVENTOUT 0x7f10 +#define STM32H7_PH15_FUNC_ANALOG 0x7f11 + +#define STM32H7_PI0_FUNC_GPIO 0x8000 +#define STM32H7_PI0_FUNC_TIM5_CH4 0x8003 +#define STM32H7_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006 +#define STM32H7_PI0_FUNC_CAN1_RXFD 0x800a +#define STM32H7_PI0_FUNC_FMC_D24 0x800d +#define STM32H7_PI0_FUNC_DCMI_D13 0x800e +#define STM32H7_PI0_FUNC_LCD_G5 0x800f +#define STM32H7_PI0_FUNC_EVENTOUT 0x8010 +#define STM32H7_PI0_FUNC_ANALOG 0x8011 + +#define STM32H7_PI1_FUNC_GPIO 0x8100 +#define STM32H7_PI1_FUNC_TIM8_BKIN2 0x8104 +#define STM32H7_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106 +#define STM32H7_PI1_FUNC_TIM8_BKIN2_COMP12 0x810c +#define STM32H7_PI1_FUNC_FMC_D25 0x810d +#define STM32H7_PI1_FUNC_DCMI_D8 0x810e +#define STM32H7_PI1_FUNC_LCD_G6 0x810f +#define STM32H7_PI1_FUNC_EVENTOUT 0x8110 +#define STM32H7_PI1_FUNC_ANALOG 0x8111 + +#define STM32H7_PI2_FUNC_GPIO 0x8200 +#define STM32H7_PI2_FUNC_TIM8_CH4 0x8204 +#define STM32H7_PI2_FUNC_SPI2_MISO_I2S2_SDI 0x8206 +#define STM32H7_PI2_FUNC_FMC_D26 0x820d +#define STM32H7_PI2_FUNC_DCMI_D9 0x820e +#define STM32H7_PI2_FUNC_LCD_G7 0x820f +#define STM32H7_PI2_FUNC_EVENTOUT 0x8210 +#define STM32H7_PI2_FUNC_ANALOG 0x8211 + +#define STM32H7_PI3_FUNC_GPIO 0x8300 +#define STM32H7_PI3_FUNC_TIM8_ETR 0x8304 +#define STM32H7_PI3_FUNC_SPI2_MOSI_I2S2_SDO 0x8306 +#define STM32H7_PI3_FUNC_FMC_D27 0x830d +#define STM32H7_PI3_FUNC_DCMI_D10 0x830e +#define STM32H7_PI3_FUNC_EVENTOUT 0x8310 +#define STM32H7_PI3_FUNC_ANALOG 0x8311 + +#define STM32H7_PI4_FUNC_GPIO 0x8400 +#define STM32H7_PI4_FUNC_TIM8_BKIN 0x8404 +#define STM32H7_PI4_FUNC_SAI2_MCK_A 0x840b +#define STM32H7_PI4_FUNC_TIM8_BKIN_COMP12 0x840c +#define STM32H7_PI4_FUNC_FMC_NBL2 0x840d +#define STM32H7_PI4_FUNC_DCMI_D5 0x840e +#define STM32H7_PI4_FUNC_LCD_B4 0x840f +#define STM32H7_PI4_FUNC_EVENTOUT 0x8410 +#define STM32H7_PI4_FUNC_ANALOG 0x8411 + +#define STM32H7_PI5_FUNC_GPIO 0x8500 +#define STM32H7_PI5_FUNC_TIM8_CH1 0x8504 +#define STM32H7_PI5_FUNC_SAI2_SCK_A 0x850b +#define STM32H7_PI5_FUNC_FMC_NBL3 0x850d +#define STM32H7_PI5_FUNC_DCMI_VSYNC 0x850e +#define STM32H7_PI5_FUNC_LCD_B5 0x850f +#define STM32H7_PI5_FUNC_EVENTOUT 0x8510 +#define STM32H7_PI5_FUNC_ANALOG 0x8511 + +#define STM32H7_PI6_FUNC_GPIO 0x8600 +#define STM32H7_PI6_FUNC_TIM8_CH2 0x8604 +#define STM32H7_PI6_FUNC_SAI2_SD_A 0x860b +#define STM32H7_PI6_FUNC_FMC_D28 0x860d +#define STM32H7_PI6_FUNC_DCMI_D6 0x860e +#define STM32H7_PI6_FUNC_LCD_B6 0x860f +#define STM32H7_PI6_FUNC_EVENTOUT 0x8610 +#define STM32H7_PI6_FUNC_ANALOG 0x8611 + +#define STM32H7_PI7_FUNC_GPIO 0x8700 +#define STM32H7_PI7_FUNC_TIM8_CH3 0x8704 +#define STM32H7_PI7_FUNC_SAI2_FS_A 0x870b +#define STM32H7_PI7_FUNC_FMC_D29 0x870d +#define STM32H7_PI7_FUNC_DCMI_D7 0x870e +#define STM32H7_PI7_FUNC_LCD_B7 0x870f +#define STM32H7_PI7_FUNC_EVENTOUT 0x8710 +#define STM32H7_PI7_FUNC_ANALOG 0x8711 + +#define STM32H7_PI8_FUNC_GPIO 0x8800 +#define STM32H7_PI8_FUNC_EVENTOUT 0x8810 +#define STM32H7_PI8_FUNC_ANALOG 0x8811 + +#define STM32H7_PI9_FUNC_GPIO 0x8900 +#define STM32H7_PI9_FUNC_UART4_RX 0x8909 +#define STM32H7_PI9_FUNC_CAN1_RX 0x890a +#define STM32H7_PI9_FUNC_FMC_D30 0x890d +#define STM32H7_PI9_FUNC_LCD_VSYNC 0x890f +#define STM32H7_PI9_FUNC_EVENTOUT 0x8910 +#define STM32H7_PI9_FUNC_ANALOG 0x8911 + +#define STM32H7_PI10_FUNC_GPIO 0x8a00 +#define STM32H7_PI10_FUNC_CAN1_RXFD 0x8a0a +#define STM32H7_PI10_FUNC_ETH_MII_RX_ER 0x8a0c +#define STM32H7_PI10_FUNC_FMC_D31 0x8a0d +#define STM32H7_PI10_FUNC_LCD_HSYNC 0x8a0f +#define STM32H7_PI10_FUNC_EVENTOUT 0x8a10 +#define STM32H7_PI10_FUNC_ANALOG 0x8a11 + +#define STM32H7_PI11_FUNC_GPIO 0x8b00 +#define STM32H7_PI11_FUNC_LCD_G6 0x8b0a +#define STM32H7_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b +#define STM32H7_PI11_FUNC_EVENTOUT 0x8b10 +#define STM32H7_PI11_FUNC_ANALOG 0x8b11 + +#define STM32H7_PI12_FUNC_GPIO 0x8c00 +#define STM32H7_PI12_FUNC_ETH_TX_ER 0x8c0c +#define STM32H7_PI12_FUNC_LCD_HSYNC 0x8c0f +#define STM32H7_PI12_FUNC_EVENTOUT 0x8c10 +#define STM32H7_PI12_FUNC_ANALOG 0x8c11 + +#define STM32H7_PI13_FUNC_GPIO 0x8d00 +#define STM32H7_PI13_FUNC_LCD_VSYNC 0x8d0f +#define STM32H7_PI13_FUNC_EVENTOUT 0x8d10 +#define STM32H7_PI13_FUNC_ANALOG 0x8d11 + +#define STM32H7_PI14_FUNC_GPIO 0x8e00 +#define STM32H7_PI14_FUNC_LCD_CLK 0x8e0f +#define STM32H7_PI14_FUNC_EVENTOUT 0x8e10 +#define STM32H7_PI14_FUNC_ANALOG 0x8e11 + +#define STM32H7_PI15_FUNC_GPIO 0x8f00 +#define STM32H7_PI15_FUNC_LCD_G2 0x8f0a +#define STM32H7_PI15_FUNC_LCD_R0 0x8f0f +#define STM32H7_PI15_FUNC_EVENTOUT 0x8f10 +#define STM32H7_PI15_FUNC_ANALOG 0x8f11 + +#define STM32H7_PJ0_FUNC_GPIO 0x9000 +#define STM32H7_PJ0_FUNC_LCD_R7 0x900a +#define STM32H7_PJ0_FUNC_LCD_R1 0x900f +#define STM32H7_PJ0_FUNC_EVENTOUT 0x9010 +#define STM32H7_PJ0_FUNC_ANALOG 0x9011 + +#define STM32H7_PJ1_FUNC_GPIO 0x9100 +#define STM32H7_PJ1_FUNC_LCD_R2 0x910f +#define STM32H7_PJ1_FUNC_EVENTOUT 0x9110 +#define STM32H7_PJ1_FUNC_ANALOG 0x9111 + +#define STM32H7_PJ2_FUNC_GPIO 0x9200 +#define STM32H7_PJ2_FUNC_DSI_TE 0x920e +#define STM32H7_PJ2_FUNC_LCD_R3 0x920f +#define STM32H7_PJ2_FUNC_EVENTOUT 0x9210 +#define STM32H7_PJ2_FUNC_ANALOG 0x9211 + +#define STM32H7_PJ3_FUNC_GPIO 0x9300 +#define STM32H7_PJ3_FUNC_LCD_R4 0x930f +#define STM32H7_PJ3_FUNC_EVENTOUT 0x9310 +#define STM32H7_PJ3_FUNC_ANALOG 0x9311 + +#define STM32H7_PJ4_FUNC_GPIO 0x9400 +#define STM32H7_PJ4_FUNC_LCD_R5 0x940f +#define STM32H7_PJ4_FUNC_EVENTOUT 0x9410 +#define STM32H7_PJ4_FUNC_ANALOG 0x9411 + +#define STM32H7_PJ5_FUNC_GPIO 0x9500 +#define STM32H7_PJ5_FUNC_LCD_R6 0x950f +#define STM32H7_PJ5_FUNC_EVENTOUT 0x9510 +#define STM32H7_PJ5_FUNC_ANALOG 0x9511 + +#define STM32H7_PJ6_FUNC_GPIO 0x9600 +#define STM32H7_PJ6_FUNC_TIM8_CH2 0x9604 +#define STM32H7_PJ6_FUNC_LCD_R7 0x960f +#define STM32H7_PJ6_FUNC_EVENTOUT 0x9610 +#define STM32H7_PJ6_FUNC_ANALOG 0x9611 + +#define STM32H7_PJ7_FUNC_GPIO 0x9700 +#define STM32H7_PJ7_FUNC_TRGIN 0x9701 +#define STM32H7_PJ7_FUNC_TIM8_CH2N 0x9704 +#define STM32H7_PJ7_FUNC_LCD_G0 0x970f +#define STM32H7_PJ7_FUNC_EVENTOUT 0x9710 +#define STM32H7_PJ7_FUNC_ANALOG 0x9711 + +#define STM32H7_PJ8_FUNC_GPIO 0x9800 +#define STM32H7_PJ8_FUNC_TIM1_CH3N 0x9802 +#define STM32H7_PJ8_FUNC_TIM8_CH1 0x9804 +#define STM32H7_PJ8_FUNC_UART8_TX 0x9809 +#define STM32H7_PJ8_FUNC_LCD_G1 0x980f +#define STM32H7_PJ8_FUNC_EVENTOUT 0x9810 +#define STM32H7_PJ8_FUNC_ANALOG 0x9811 + +#define STM32H7_PJ9_FUNC_GPIO 0x9900 +#define STM32H7_PJ9_FUNC_TIM1_CH3 0x9902 +#define STM32H7_PJ9_FUNC_TIM8_CH1N 0x9904 +#define STM32H7_PJ9_FUNC_UART8_RX 0x9909 +#define STM32H7_PJ9_FUNC_LCD_G2 0x990f +#define STM32H7_PJ9_FUNC_EVENTOUT 0x9910 +#define STM32H7_PJ9_FUNC_ANALOG 0x9911 + +#define STM32H7_PJ10_FUNC_GPIO 0x9a00 +#define STM32H7_PJ10_FUNC_TIM1_CH2N 0x9a02 +#define STM32H7_PJ10_FUNC_TIM8_CH2 0x9a04 +#define STM32H7_PJ10_FUNC_SPI5_MOSI 0x9a06 +#define STM32H7_PJ10_FUNC_LCD_G3 0x9a0f +#define STM32H7_PJ10_FUNC_EVENTOUT 0x9a10 +#define STM32H7_PJ10_FUNC_ANALOG 0x9a11 + +#define STM32H7_PJ11_FUNC_GPIO 0x9b00 +#define STM32H7_PJ11_FUNC_TIM1_CH2 0x9b02 +#define STM32H7_PJ11_FUNC_TIM8_CH2N 0x9b04 +#define STM32H7_PJ11_FUNC_SPI5_MISO 0x9b06 +#define STM32H7_PJ11_FUNC_LCD_G4 0x9b0f +#define STM32H7_PJ11_FUNC_EVENTOUT 0x9b10 +#define STM32H7_PJ11_FUNC_ANALOG 0x9b11 + +#define STM32H7_PJ12_FUNC_GPIO 0x9c00 +#define STM32H7_PJ12_FUNC_TRGOUT 0x9c01 +#define STM32H7_PJ12_FUNC_LCD_G3 0x9c0a +#define STM32H7_PJ12_FUNC_LCD_B0 0x9c0f +#define STM32H7_PJ12_FUNC_EVENTOUT 0x9c10 +#define STM32H7_PJ12_FUNC_ANALOG 0x9c11 + +#define STM32H7_PJ13_FUNC_GPIO 0x9d00 +#define STM32H7_PJ13_FUNC_LCD_B4 0x9d0a +#define STM32H7_PJ13_FUNC_LCD_B1 0x9d0f +#define STM32H7_PJ13_FUNC_EVENTOUT 0x9d10 +#define STM32H7_PJ13_FUNC_ANALOG 0x9d11 + +#define STM32H7_PJ14_FUNC_GPIO 0x9e00 +#define STM32H7_PJ14_FUNC_LCD_B2 0x9e0f +#define STM32H7_PJ14_FUNC_EVENTOUT 0x9e10 +#define STM32H7_PJ14_FUNC_ANALOG 0x9e11 + +#define STM32H7_PJ15_FUNC_GPIO 0x9f00 +#define STM32H7_PJ15_FUNC_LCD_B3 0x9f0f +#define STM32H7_PJ15_FUNC_EVENTOUT 0x9f10 +#define STM32H7_PJ15_FUNC_ANALOG 0x9f11 + +#define STM32H7_PK0_FUNC_GPIO 0xa000 +#define STM32H7_PK0_FUNC_TIM1_CH1N 0xa002 +#define STM32H7_PK0_FUNC_TIM8_CH3 0xa004 +#define STM32H7_PK0_FUNC_SPI5_SCK 0xa006 +#define STM32H7_PK0_FUNC_LCD_G5 0xa00f +#define STM32H7_PK0_FUNC_EVENTOUT 0xa010 +#define STM32H7_PK0_FUNC_ANALOG 0xa011 + +#define STM32H7_PK1_FUNC_GPIO 0xa100 +#define STM32H7_PK1_FUNC_TIM1_CH1 0xa102 +#define STM32H7_PK1_FUNC_TIM8_CH3N 0xa104 +#define STM32H7_PK1_FUNC_SPI5_NSS 0xa106 +#define STM32H7_PK1_FUNC_LCD_G6 0xa10f +#define STM32H7_PK1_FUNC_EVENTOUT 0xa110 +#define STM32H7_PK1_FUNC_ANALOG 0xa111 + +#define STM32H7_PK2_FUNC_GPIO 0xa200 +#define STM32H7_PK2_FUNC_TIM1_BKIN 0xa202 +#define STM32H7_PK2_FUNC_TIM8_BKIN 0xa204 +#define STM32H7_PK2_FUNC_TIM8_BKIN_COMP12 0xa20b +#define STM32H7_PK2_FUNC_TIM1_BKIN_COMP12 0xa20c +#define STM32H7_PK2_FUNC_LCD_G7 0xa20f +#define STM32H7_PK2_FUNC_EVENTOUT 0xa210 +#define STM32H7_PK2_FUNC_ANALOG 0xa211 + +#define STM32H7_PK3_FUNC_GPIO 0xa300 +#define STM32H7_PK3_FUNC_LCD_B4 0xa30f +#define STM32H7_PK3_FUNC_EVENTOUT 0xa310 +#define STM32H7_PK3_FUNC_ANALOG 0xa311 + +#define STM32H7_PK4_FUNC_GPIO 0xa400 +#define STM32H7_PK4_FUNC_LCD_B5 0xa40f +#define STM32H7_PK4_FUNC_EVENTOUT 0xa410 +#define STM32H7_PK4_FUNC_ANALOG 0xa411 + +#define STM32H7_PK5_FUNC_GPIO 0xa500 +#define STM32H7_PK5_FUNC_LCD_B6 0xa50f +#define STM32H7_PK5_FUNC_EVENTOUT 0xa510 +#define STM32H7_PK5_FUNC_ANALOG 0xa511 + +#define STM32H7_PK6_FUNC_GPIO 0xa600 +#define STM32H7_PK6_FUNC_LCD_B7 0xa60f +#define STM32H7_PK6_FUNC_EVENTOUT 0xa610 +#define STM32H7_PK6_FUNC_ANALOG 0xa611 + +#define STM32H7_PK7_FUNC_GPIO 0xa700 +#define STM32H7_PK7_FUNC_LCD_DE 0xa70f +#define STM32H7_PK7_FUNC_EVENTOUT 0xa710 +#define STM32H7_PK7_FUNC_ANALOG 0xa711 + +#endif /* _DT_BINDINGS_STM32H7_PINFUNC_H */ diff --git a/include/dwc3-sti-glue.h b/include/dwc3-sti-glue.h new file mode 100644 index 00000000000..98e76961b65 --- /dev/null +++ b/include/dwc3-sti-glue.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2017 + * Patrice Chotard <patrice.chotard@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DWC3_STI_UBOOT_H_ +#define __DWC3_STI_UBOOT_H_ + +/* glue registers */ +#define CLKRST_CTRL 0x00 +#define AUX_CLK_EN BIT(0) +#define SW_PIPEW_RESET_N BIT(4) +#define EXT_CFG_RESET_N BIT(8) + +#define XHCI_REVISION BIT(12) + +#define USB2_VBUS_MNGMNT_SEL1 0x2C +#define USB2_VBUS_UTMIOTG 0x1 + +#define SEL_OVERRIDE_VBUSVALID(n) ((n) << 0) +#define SEL_OVERRIDE_POWERPRESENT(n) ((n) << 4) +#define SEL_OVERRIDE_BVALID(n) ((n) << 8) + +/* Static DRD configuration */ +#define USB3_CONTROL_MASK 0xf77 + +#define USB3_DEVICE_NOT_HOST BIT(0) +#define USB3_FORCE_VBUSVALID BIT(1) +#define USB3_DELAY_VBUSVALID BIT(2) +#define USB3_SEL_FORCE_OPMODE BIT(4) +#define USB3_FORCE_OPMODE(n) ((n) << 5) +#define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8) +#define USB3_FORCE_DPPULLDOWN2 BIT(9) +#define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10) +#define USB3_FORCE_DMPULLDOWN2 BIT(11) + +int sti_dwc3_init(enum usb_dr_mode mode); + +#endif /* __DWC3_STI_UBOOT_H_ */ diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index cd3eb47da4a..59bfc14df68 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -156,7 +156,7 @@ #elif defined(CONFIG_MPC85xx) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR -#elif defined(CONFIG_LS102XA) || defined(CONFIG_ARCH_LS1012A) +#elif defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR 0 #endif |