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2016-07-26defconfig: am43xx_hs_evm: enable i2c driver modelMugunthan V N
Enable i2c driver model for am43xx_hs_evm as omap i2c supports driver model. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-26defconfig: am43xx_evm: enable i2c driver modelMugunthan V N
Enable i2c driver model for am43xx_evm as omap i2c supports driver model. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-26defconfig: am335x_evm: enable i2c driver modelMugunthan V N
Enable i2c driver model for am335x_evm as omap i2c supports driver model. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-26defconfig: am335x_boneblack_vboot: enable i2c driver modelMugunthan V N
Enable i2c driver model for am335x_boneblack_vboot as omap i2c supports driver model. Also enable CONFIG_DM_I2C_COMPAT for legacy drivers of i2c devices. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-26drivers: i2c: omap24xx_i2c: adopt omap_i2c driver to driver modelMugunthan V N
Convert omap i2c driver to adopt i2c driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-26drivers: i2c: omap24xx_i2c: prepare driver for DM conversionMugunthan V N
Prepare the driver for DM conversion. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-26ti_armv7_common: i2c: do not define DM_I2C for splMugunthan V N
Since omap's spl doesn't support DM currently, do not define DM_I2C for spl build. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-26drivers: i2c: uclass: parse dt parameters only when CONFIG_OF_CONTROL is enableMugunthan V N
parse dt parameter of i2c devices only when CONFIG_OF_CONTROL is enabled. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-26omap5/dra7: i2c: correct register offset for sync registerMugunthan V N
The register offset of i2c_sysc offset is not correct as per omap5[1]/dra7[2] TRM, correct the offsets as per the documentation. [1] - http://www.ti.com/lit/pdf/swpu249 [2] - http://www.ti.com/lit/pdf/spruhz6 Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-26omap4: i2c: correct register offset for sync registerMugunthan V N
The register offset of i2c_sysc offset is not correct as per omap4 TRM [1], correct the offsets as per the documentation. [1] - http://www.ti.com/lit/ug/swpu235ab/swpu235ab.pdf Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-26tools: env: Fix format warnings in debugMarcin Niestroj
Format warnings (-Wformat) were shown in printf() calls after defining DEBUG macro. Update format string and explicitly cast variables to suppress all warnings. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2016-07-25rockchip: sdram: Fix register layout for LinuxJohn Keeping
The ChromeOS kernel reads the RAM settings from PMU_SYS_REG2 and expects the bootloader to store the necessary information there. We're using the same register to pass the same information between the SPL and U-Boot but in a slightly different format. Change this to use the format expected by the Linux DMC driver so that the system doesn't hang in Linux by misconfiguring the RAM. This is almost the same as commit b5788dc ("rockchip: rk3288: correct sdram setting") which was reverted in commit b525556 ("Revert "rockchip: rk3288: correct sdram setting"") but parenthese have been added to apply the mask correctly when reading the "bw" setting and a couple of minor style issues have been fixed to keep check_patch.pl happy. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25mmc: rockchip: add SDHCI driver support for rockchip socKever Yang
Rockchip rk3399 using arasan sdhci-5.1 controller. This patch add the controller support to enable mmc device with full driver-model support, tested on rk3399 evb board. According to my test result, this driver should be OK, the command "part list mmc 0" can result in a right output, but all the mmc command failed like this: => mmc info No MMC device available Command failed, result=1 The result of get_mmc_num in cmd/mmc.c is always 0? Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25ARM64: evb-rk3399: add a README for this board setupKever Yang
Add a README to guide people flash the ATF and U-Boot with Rockchip tools to bring up to board. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25config: add config file for evb-rk3399Kever Yang
This patch add basic config option for evb-rk3399 board. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25ARM64: rockchip: add support for rk3399 SoC based evbKever Yang
RK3399 is a SoC from Rockchip with dual-core Cortex-A72 and quad-core Cortex-A53 CPU. It supports two USB3.0 type-C ports and two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-128MB range. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25dts: add support for Rockchip rk3399 socKever Yang
These files are from kernel upstream: "649a371 Add linux-next specific files for 20160616" with some modification need by U-Boot: - chosen with stdout-path to uart2. - add clock-frequency for uart2 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25rockchip: update fastboot usageXu Ziyuan
Introduce how to use fastboot feature on rk3288. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25mkimage: rockchip: add suport for rk33 serialKever Yang
Add support for rockchip rk33 series Soc like rk3368 and rk3399 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25rockchip: Use rockchip_get_clk() to obtain the SoC clockSimon Glass
The current code picks the first available clock. In U-Boot proper this is the oscillator device, not the SoC clock device. As a result the HDMI display does not work. Fix this by calling rockchip_get_clk() instead. Fixes: 135aa950 (clk: convert API to match reset/mailbox style) Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
2016-07-25rockchip: Add a way to obtain the main clock deviceSimon Glass
On Rockchip SoCs we typically have a main clock device that uses the Soc clock driver. There is also a fixed clock for the oscillator. Add a function to obtain the core clock. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-25dm: core: Add a way to find a device by its driverSimon Glass
Some SoCs have a single clock device. Provide a way to find it given its driver name. This is handled by the linker so will fail if the name is not found, avoiding strange errors when names change and do not match. It is also faster than a string comparison. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-25rockchip: rk3288: fix FREF_MIN_HZ constantHeiko Stübner
According to the TRM the minimum FREF frequency is 269kHz not MHz. Adapt the constant accordingly. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25cosmetic: rockchip: rk3288: rename rkclk_configure_cpuHeiko Stübner
The function is very specific to the rk3288 in its arguments referencing the rk3288 cru and grf and every other rockchip soc has differing cru and grf registers. So make that function naming explicit. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25cosmetic: rockchip: sort socs according to numbersHeiko Stübner
Having some sort of ordering proofed helpful in a lot of other places already. So for a larger number of rockchip socs it might be helpful as well instead of an ever increasing unsorted list. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25cosmetic: rockchip: rk3036: pinctrl: fix config symbol namingHeiko Stübner
Rockchip socs are always named rkxxxx in all places, as also shown by the naming of the rk3036 pinctrl file itself. Therefore also name the config symbol according to this scheme. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25cosmetic: rockchip: rk3288: pinctrl: fix config symbol namingHeiko Stübner
The rk3288 pinctrl is very specific to this soc, so should not hog the generic rockchip naming. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25rockchip: rk3288: add fastboot supportXu Ziyuan
Enable fastboot feature on rk3288. This path doesn't support the fastboot flash function command entirely. We will hit "cannot find partition" assertion without specified partition environment. Define gpt partition layout in specified board such as firefly-rk3288, then enjoy it! Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25usb: dwc2 : invalidate dcache before starting DMAXu Ziyuan
Invalidate dcache before starting the DMA to ensure coherency. In case there are any dirty lines from the DMA buffer in the cache, subsequent cache-line replacements may corrupt the buffer in memory while the DMA is still going on. Cache-line replacement can happen if the CPU tries to bring some other memory locations into the cache while the DMA is going on. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25usb: dwc2-otg: adjust fifo size via platform dataXu Ziyuan
The total FIFO size of some SoCs may be different from the existen, this patch supports fifo size setting from platform data. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25usb: rockchip-phy: implement USB2.0 phy controlXu Ziyuan
So far, Rockchip SoCs have two kinds of USB2.0 phy, such as Synopsys and Innosilicon. This patch applys dwc2 usb driver framework to implement phy_init() and phy_off() methods for Synopsys phy on Rockchip platform. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25rockchip: Exclude rk_timer for ARM64Andreas Färber
It conflicts with the generic_timer. Cc: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25mkimage: rockchip: add suport for rk33 serialKever Yang
Add support for rockchip rk33 series Soc like rk3368 and rk3399 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25rockchip: Clean up CPU selectionAndreas Färber
In preparation for RK3368 and RK3399, which need to select ARM64, don't select CPU_V7 at the ARCH_ROCKCHIP level but at the SoC level instead. Cc: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25board: move all the rockchip board in one folderKever Yang
The 'evb_rk3036' and 'kylin' is not a vendor name, let's replace them to 'rockchip' which is a real _vendor_ name, and meet the architecure 'board/<vendor>/<board-name>/'. More boards from rockchip like evb_rk3288, evb_rk3399 will comes later. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Eddie Cai <eddie.cai.kernel@gmail.com>
2016-07-25rockchip: add basic support for evb-rk3288 boardXu Ziyuan
evb-3288 board RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet. It also includes on-board 8G eMMC and 2GB of SDRAM. Expansion connector provide access to display pins, I2C, SPI, UART and GPIOs. This add some basic files required to allow the board to output serial messaged and can run command(mmc info etc). evb-rk3288 also supports booting from eMMC or SD card, the default is eMMC. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-25rockchip: add option to change method of loading u-bootXu Ziyuan
If we would like to boot from SD card, we have to implement mmc driver in SPL stage, and get a slightly large SPL binary. Rockchip SoC's bootrom code has the ability to load spl and u-boot, then boot. If CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is enabled, the spl will return to bootrom in board_init_f(), then bootrom loads u-boot binary. Loading sequence after rework: bootrom ==> spl ==> bootrom ==> u-boot Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed up spelling of U-Boot, boorom, opinion->option, Rochchip: Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-25Prepare v2016.09-rc1Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-07-25sandbox: Migrate CONFIG_I2C_EEPROMTom Rini
Most users of CONFIG_I2C_EEPROM were migrated to defconfig a while ago, but sandbox was skipped. Leave it off for sandbox_spl where it does not build, but does not need to be either. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2016-07-25powerpc/86xx: Pass -mcpu=7400 to GCCScott Wood
Without this, GCC uses the toolchain default, which may be incompatible with -maltivec. Signed-off-by: Scott Wood <oss@buserror.net> Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-25Merge git://git.denx.de/u-boot-nand-flashTom Rini
2016-07-25arm64: thunderx_88xx_defconfig: remove unneeded CONFIG_SYS_EXTRA_OPTIONSMasahiro Yamada
ARM64 is correctly select'ed in arch/arm/Kconfig, so this line in the defconfig is unneeded. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-25dtoc: Correct the type widening code in fdt_fallbackSimon Glass
This code does not match the fdt version in fdt.py. When dtoc is unable to use the Python libfdt library, it uses the fallback version, which does not widen arrays correctly. Fix this to avoid a warning 'excess elements in array initialize' in dt-platdata.c which happens on some platforms. Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com>
2016-07-25hashtable: Fix compiler warning on 32-bit sandboxSimon Glass
This fixes a mismatch between the %zu format and the type used on sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-25part_efi: Fix compiler warning on 32-bit sandboxSimon Glass
This fixes a mismatch between the %zu format and the type used on sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-25lzmadec: Use the same type as the lzma callSimon Glass
With sandbox on 32-bit the size_t type can be a little inconsistent. Use the same type as the caller expects to avoid a compiler warning. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-25sandbox: Add instructions about building on 32-bit machinesSimon Glass
Sandbox is built with 64-bit ints by default. This doesn't work properly on 32-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-25tools, rsa: Further minor cleanups on top of c236ebd and 2b9ec7mario.six@gdsys.cc
[NOTE: I took v1 of these patches in, and then v2 came out, this commit is squashing the minor deltas from v1 -> v2 of updates to c236ebd and 2b9ec76 into this commit - trini] - Added an additional NULL check, as suggested by Simon Glass to fit_image_process_sig - Re-formatted the comment blocks Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> [For merging the chnages from v2 back onto v1] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-07-25ARM: am33xx: Always inhibit init/refresh during DDR phy initRuss Dill
A couple of commits have modified the am33xx/am437x ddr2/ddr3 initialization path to fix certain issues, but have had the side effect of causing L3 noc errors during initialization. The two commits are: 69b918 "am33xx,ddr3: fix ddr3 sdram configuration" fc46ba "arm: am437x: Enable hardware leveling for EMIF" The EMIF_REG_INITREF_DIS_MASK bit still needs to be set for all platforms. This delays initialization and refresh until a later stage. The 500us timer can be programmed for platforms that require it and for platforms that don't require it. It is currently hardcoded for 400MHz systems. For systems with a higher memory frequency this needs to be a larger value, and for systems with a lower memory frequency this can be a lower value. This can be considered a separate issue and corrected in a later commit. Signed-off-by: Russ Dill <Russ.Dill@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-25ARM: am33xx: Fix DDR init delay placementRuss Dill
The delay needs to be before the write to ref_ctrl register which initiates refreshes. An improper initialization sequence generates an L3 noc error. Signed-off-by: Russ Dill <Russ.Dill@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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